Initial checkin

component/soc/realtek/8195a/fwlib/src/hal_32k.c

@@ -0,0 +1,293 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h"
+
+#ifdef CONFIG_TIMER_MODULE
+
+VOID
+En32KCalibration(
+    VOID
+)
+{
+    u32 Rtemp;
+    u32 Ttemp = 0;
+
+    //DiagPrintf("32K clock source calibration\n");
+
+    //set parameter
+    HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+    //offset 1 = 0x1500
+    Rtemp = 0x811500;
+    HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+    HalDelayUs(40);
+    HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+
+    //offset 2 = 0x01c0
+    Rtemp = 0x8201c0;
+    HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+    HalDelayUs(40);
+        HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+    
+    //offset 4 = 0x0100
+    Rtemp = 0x840100;
+        HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+    HalDelayUs(40);
+    HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+
+    //offset 0 = 0xf980
+    Rtemp = 0x80f980;
+    HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+    HalDelayUs(40);
+    HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
+
+    while(1) {
+        //Polling LOCK
+        Rtemp = 0x110000;
+        HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
+        //DiagPrintf("Polling lock\n");
+        HalDelayUs(40);
+
+        Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL1);
+        if ((Rtemp & 0x3000) != 0x0){
+            //DiagPrintf("32.768 Calibration Success\n", Ttemp);
+            break;
+        }
+        else {
+            Ttemp++;
+            HalDelayUs(30);
+            //DiagPrintf("Check lock: %d\n", Ttemp);
+            //DiagPrintf("0x278: %x\n", Rtemp);
+            if (Ttemp > 100000) { /*Delay 100ms*/            
+                DiagPrintf("32K Calibration Fail!!\n", Ttemp);
+                break;
+            }
+        }
+    }
+}
+
+#if CONFIG_WDG
+WDG_ADAPTER          WDGAdapter;
+extern HAL_TIMER_OP HalTimerOp;
+
+#ifdef CONFIG_WDG_NORMAL
+VOID
+WDGInitial(
+    IN  u32 Period
+)
+{
+    u8 CountId;
+    u16 DivFactor;
+    u32 CountTemp; 
+    u32 CountProcess = 0;
+    u32 DivFacProcess = 0;
+    u32 PeriodProcess = 100*Period;
+    u32 MinPeriodTemp = 0xFFFFFFFF;
+    u32 PeriodTemp = 0;
+    u32 *Reg = (u32*)&(WDGAdapter.Ctrl);
+    
+    DBG_8195A(" Period = 0x%08x\n", Period);
+
+    for (CountId = 0; CountId < 12; CountId++) {
+        CountTemp = ((0x00000001 << (CountId+1))-1);
+        DivFactor = (u16)((PeriodProcess)/(CountTemp*3));
+        
+        if (DivFactor > 0) {
+            PeriodTemp = 3*(DivFactor+1)*CountTemp;
+            if (PeriodProcess < PeriodTemp) {
+                if (MinPeriodTemp > PeriodTemp) {
+                    MinPeriodTemp = PeriodTemp;
+                    CountProcess = CountId;
+                    DivFacProcess = DivFactor;
+                }
+            }
+        }
+    }
+
+    DBG_8195A("WdgScalar = 0x%08x\n", DivFacProcess);
+    DBG_8195A("WdgCunLimit = 0x%08x\n", CountProcess);
+
+    WDGAdapter.Ctrl.WdgScalar   = DivFacProcess;
+    WDGAdapter.Ctrl.WdgEnByte   = 0;
+    WDGAdapter.Ctrl.WdgClear    = 1;
+    WDGAdapter.Ctrl.WdgCunLimit = CountProcess;
+    WDGAdapter.Ctrl.WdgMode     = RESET_MODE;
+    WDGAdapter.Ctrl.WdgToISR    = 0;
+
+    HAL_WRITE32(VENDOR_REG_BASE, 0, (*Reg));
+    
+}
+
+VOID
+WDGIrqHandle
+(
+    IN  VOID        *Data
+)
+{
+    u32 temp;
+    WDG_REG *CtrlReg;
+
+    if (NULL != WDGAdapter.UserCallback) {
+        WDGAdapter.UserCallback(WDGAdapter.callback_id);
+    }
+
+    // Clear ISR
+    temp = HAL_READ32(VENDOR_REG_BASE, 0);
+    CtrlReg = (WDG_REG*)&temp;
+    CtrlReg->WdgToISR    = 1;    // write 1 clear
+    HAL_WRITE32(VENDOR_REG_BASE, 0, (temp));
+}
+
+VOID
+WDGIrqInitial(
+    VOID
+)
+{
+    u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
+    
+    WDGAdapter.IrqHandle.Data = (u32)&WDGAdapter;
+    WDGAdapter.IrqHandle.IrqFun = (IRQ_FUN)WDGIrqHandle;
+    WDGAdapter.IrqHandle.IrqNum = WDG_IRQ;
+    WDGAdapter.IrqHandle.Priority = 0;
+         
+    InterruptRegister(&(WDGAdapter.IrqHandle));
+    InterruptEn(&(WDGAdapter.IrqHandle));
+
+    WDGAdapter.Ctrl.WdgToISR    = 1;    // clear ISR first
+    WDGAdapter.Ctrl.WdgMode     = INT_MODE;
+    HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
+    WDGAdapter.Ctrl.WdgToISR    = 0;
+}
+
+VOID
+WDGStart(
+    VOID
+)
+{
+    u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
+    WDGAdapter.Ctrl.WdgEnByte    = 0xA5;
+    HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
+}
+
+VOID
+WDGStop(
+    VOID
+)
+{
+    u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
+    WDGAdapter.Ctrl.WdgEnByte    = 0;
+    HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
+}
+
+VOID
+WDGRefresh(
+    VOID
+)
+{
+    u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
+    WDGAdapter.Ctrl.WdgClear    = 1;
+    HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
+} 
+
+VOID
+WDGIrqCallBackReg(
+    IN VOID *CallBack,
+    IN u32   Id
+)
+{
+    WDGAdapter.UserCallback = (VOID (*)(u32))CallBack;
+    WDGAdapter.callback_id = Id;
+} 
+
+#endif
+
+#ifdef CONFIG_WDG_TEST
+VOID
+WDGIrqHandle
+(
+    IN  VOID        *Data
+)
+{
+}
+
+
+VOID
+WDGGtimerHandle
+(
+    IN  VOID        *Data
+)
+{
+    u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
+    WDGAdapter.Ctrl.WdgClear    = 1;
+    DBG_8195A("reset WDG\n");
+    if (HAL_READ32(SYSTEM_CTRL_BASE,REG_SYS_DSTBY_INFO2) == 0) {
+        HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
+    }
+}
+
+
+VOID
+InitWDGIRQ(VOID)
+{
+    u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
+    
+    WDGAdapter.Ctrl.WdgScalar   = 0x96;
+    WDGAdapter.Ctrl.WdgEnByte   = 0xA5;
+    WDGAdapter.Ctrl.WdgClear    = 1;
+    WDGAdapter.Ctrl.WdgCunLimit = CNTFFFH;
+    WDGAdapter.Ctrl.WdgMode     = RESET_MODE;
+    WDGAdapter.Ctrl.WdgToISR    = 0;
+
+    if (WDGAdapter.Ctrl.WdgMode == INT_MODE) {
+        
+        WDGAdapter.IrqHandle.Data = NULL;
+        WDGAdapter.IrqHandle.IrqFun = (IRQ_FUN)WDGIrqHandle;
+        WDGAdapter.IrqHandle.IrqNum = WDG_IRQ;
+        WDGAdapter.IrqHandle.Priority = 5;
+             
+        InterruptRegister(&(WDGAdapter.IrqHandle));
+        InterruptEn(&(WDGAdapter.IrqHandle));
+    }
+    else {
+        
+        WDGAdapter.WdgGTimer.TimerIrqPriority   = 0;
+        WDGAdapter.WdgGTimer.TimerMode          = USER_DEFINED;
+        WDGAdapter.WdgGTimer.IrqDis             = OFF;
+        WDGAdapter.WdgGTimer.TimerId            = 2;//
+        WDGAdapter.WdgGTimer.IrqHandle.IrqFun   = (IRQ_FUN)WDGGtimerHandle;
+        WDGAdapter.WdgGTimer.IrqHandle.IrqNum   = TIMER2_7_IRQ;
+        WDGAdapter.WdgGTimer.IrqHandle.Priority = 5;
+        WDGAdapter.WdgGTimer.IrqHandle.Data     = NULL;
+        
+        if ((WDGAdapter.Ctrl.WdgCunLimit == CNTFFFH)&&(WDGAdapter.Ctrl.WdgScalar >= 0x8429)){
+            WDGAdapter.WdgGTimer.TimerLoadValueUs = 0xFFFFFFFF - WDGTIMERELY;
+        }
+        else {
+            WDGAdapter.WdgGTimer.TimerLoadValueUs   = (BIT0 << (WDGAdapter.Ctrl.WdgCunLimit+1))
+                *WDGAdapter.Ctrl.WdgScalar*TIMER_TICK_US - WDGTIMERELY;
+        }
+
+        HalTimerOp.HalTimerInit((VOID*) &(WDGAdapter.WdgGTimer));
+    }
+    //fill reg
+    HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
+}
+
+
+//WDG
+VOID HalWdgInit(
+    VOID
+)
+{
+        
+}
+#endif  //CONFIG_WDG_TEST
+#endif  //CONFIG_WDG
+#endif  //#ifdef CONFIG_TIMER_MODULE

component/soc/realtek/8195a/fwlib/src/hal_common.c

@@ -0,0 +1,23 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#include "rtl8195a.h"
+#include "hal_common.h"
+
+extern HAL_TIMER_OP        HalTimerOp;
+
+HAL_Status 
+HalCommonInit(void){
+
+#ifdef CONFIG_TIMER_MODULE
+    HalTimerOpInit_Patch((VOID*)(&HalTimerOp));
+#endif
+
+    return HAL_OK;
+}

component/soc/realtek/8195a/fwlib/src/hal_gdma.c

@@ -0,0 +1,574 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h"
+#include "hal_gdma.h"
+
+#define MAX_GDMA_INDX       1
+#define MAX_GDMA_CHNL       6
+
+static u8 HalGdmaReg[MAX_GDMA_INDX+1];
+
+const HAL_GDMA_CHNL GDMA_Chnl_Option[] = { 
+        {0,0,GDMA0_CHANNEL0_IRQ,0},
+        {1,0,GDMA1_CHANNEL0_IRQ,0},
+        {0,1,GDMA0_CHANNEL1_IRQ,0},
+        {1,1,GDMA1_CHANNEL1_IRQ,0},
+        {0,2,GDMA0_CHANNEL2_IRQ,0},
+        {1,2,GDMA1_CHANNEL2_IRQ,0},
+        {0,3,GDMA0_CHANNEL3_IRQ,0},
+        {1,3,GDMA1_CHANNEL3_IRQ,0},
+        {0,4,GDMA0_CHANNEL4_IRQ,0},
+        {1,4,GDMA1_CHANNEL4_IRQ,0},
+        {0,5,GDMA0_CHANNEL5_IRQ,0},
+        {1,5,GDMA1_CHANNEL5_IRQ,0},
+        
+        {0xff,0,0,0}    // end
+};
+
+const HAL_GDMA_CHNL GDMA_Multi_Block_Chnl_Option[] = { 
+        {0,4,GDMA0_CHANNEL4_IRQ,0},
+        {1,4,GDMA1_CHANNEL4_IRQ,0},
+        {0,5,GDMA0_CHANNEL5_IRQ,0},
+        {1,5,GDMA1_CHANNEL5_IRQ,0},
+        
+        {0xff,0,0,0}    // end
+};
+
+
+const u16 HalGdmaChnlEn[6] = {
+    GdmaCh0, GdmaCh1, GdmaCh2, GdmaCh3,
+    GdmaCh4, GdmaCh5
+};
+
+
+    
+VOID HalGdmaOpInit(
+    IN  VOID *Data
+)
+{
+    PHAL_GDMA_OP pHalGdmaOp = (PHAL_GDMA_OP) Data;
+
+    pHalGdmaOp->HalGdmaOnOff = HalGdmaOnOffRtl8195a;
+    pHalGdmaOp->HalGdamChInit = HalGdamChInitRtl8195a;
+    pHalGdmaOp->HalGdmaChDis = HalGdmaChDisRtl8195a;
+    pHalGdmaOp->HalGdmaChEn = HalGdmaChEnRtl8195a;
+    pHalGdmaOp->HalGdmaChSeting = HalGdmaChSetingRtl8195a;
+#ifndef CONFIG_CHIP_E_CUT
+    pHalGdmaOp->HalGdmaChBlockSeting = HalGdmaChBlockSetingRtl8195a_Patch;
+#else
+    pHalGdmaOp->HalGdmaChBlockSeting = HalGdmaChBlockSetingRtl8195a_V04;
+#endif
+    pHalGdmaOp->HalGdmaChIsrEnAndDis = HalGdmaChIsrEnAndDisRtl8195a;
+    pHalGdmaOp->HalGdmaChIsrClean = HalGdmaChIsrCleanRtl8195a;
+    pHalGdmaOp->HalGdmaChCleanAutoSrc = HalGdmaChCleanAutoSrcRtl8195a;
+    pHalGdmaOp->HalGdmaChCleanAutoDst = HalGdmaChCleanAutoDstRtl8195a;
+}
+
+VOID HalGdmaOn(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    pHalGdmaAdapter->GdmaOnOff = ON;
+    HalGdmaOnOffRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+VOID HalGdmaOff(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    pHalGdmaAdapter->GdmaOnOff = OFF;
+    HalGdmaOnOffRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+BOOL HalGdmaChInit(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    return (HalGdamChInitRtl8195a((VOID*)pHalGdmaAdapter));
+}
+
+VOID HalGdmaChDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    HalGdmaChDisRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+VOID HalGdmaChEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    HalGdmaChEnRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+BOOL HalGdmaChSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    return (HalGdmaChSetingRtl8195a((VOID*)pHalGdmaAdapter));
+}
+
+BOOL HalGdmaChBlockSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+#ifndef CONFIG_CHIP_E_CUT
+    return (HalGdmaChBlockSetingRtl8195a_Patch((VOID*)pHalGdmaAdapter));
+#else
+    return (HalGdmaChBlockSetingRtl8195a_V04((VOID*)pHalGdmaAdapter));
+#endif
+}
+
+VOID HalGdmaChIsrEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    pHalGdmaAdapter->IsrCtrl = ENABLE;
+    HalGdmaChIsrEnAndDisRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+VOID HalGdmaChIsrDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    pHalGdmaAdapter->IsrCtrl = DISABLE;
+    HalGdmaChIsrEnAndDisRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+u8 HalGdmaChIsrClean(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    return (HalGdmaChIsrCleanRtl8195a((VOID*)pHalGdmaAdapter));
+}
+
+VOID HalGdmaChCleanAutoSrc(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    HalGdmaChCleanAutoSrcRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+VOID HalGdmaChCleanAutoDst(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
+{
+    HalGdmaChCleanAutoDstRtl8195a((VOID*)pHalGdmaAdapter);
+}
+
+HAL_Status HalGdmaChnlRegister (u8 GdmaIdx, u8 ChnlNum)
+{
+    u32 mask;
+
+    if ((GdmaIdx > MAX_GDMA_INDX) || (ChnlNum > MAX_GDMA_CHNL)) {
+        // Invalid GDMA Index or Channel Number
+        return HAL_ERR_PARA;
+    }
+
+    mask = 1 << ChnlNum;
+
+    if ((HalGdmaReg[GdmaIdx] & mask) != 0) {
+        return HAL_BUSY;
+    }
+    else {
+#if 1
+        if (HalGdmaReg[GdmaIdx] == 0) {
+            if (GdmaIdx == 0) {
+                ACTCK_GDMA0_CCTRL(ON);
+                GDMA0_FCTRL(ON);
+            }
+            else {
+                ACTCK_GDMA1_CCTRL(ON);
+                GDMA1_FCTRL(ON);
+            }
+        }
+#endif    
+        HalGdmaReg[GdmaIdx] |= mask;
+        return HAL_OK;
+    }
+}
+
+VOID HalGdmaChnlUnRegister (u8 GdmaIdx, u8 ChnlNum)
+{
+    u32 mask;
+
+    if ((GdmaIdx > MAX_GDMA_INDX) || (ChnlNum > MAX_GDMA_CHNL)) {
+        // Invalid GDMA Index or Channel Number
+        return;
+    }
+    
+    mask = 1 << ChnlNum;
+
+    HalGdmaReg[GdmaIdx] &= ~mask;
+#if 1
+    if (HalGdmaReg[GdmaIdx] == 0) {
+        if (GdmaIdx == 0) {
+            ACTCK_GDMA0_CCTRL(OFF);
+            GDMA0_FCTRL(OFF);
+        }
+        else {
+            ACTCK_GDMA1_CCTRL(OFF);
+            GDMA1_FCTRL(OFF);
+        }
+    }
+#endif    
+}
+
+PHAL_GDMA_CHNL HalGdmaChnlAlloc (HAL_GDMA_CHNL *pChnlOption)
+{
+    HAL_GDMA_CHNL *pgdma_chnl;
+
+    pgdma_chnl = pChnlOption;
+    if (pChnlOption == NULL) {
+        // Use default GDMA Channel Option table
+        pgdma_chnl = (HAL_GDMA_CHNL*)&GDMA_Chnl_Option[0];
+    }
+    else{
+        pgdma_chnl = (HAL_GDMA_CHNL*) pgdma_chnl;
+    }
+
+    while (pgdma_chnl->GdmaIndx <= MAX_GDMA_INDX) {
+        if (HalGdmaChnlRegister(pgdma_chnl->GdmaIndx, pgdma_chnl->GdmaChnl) == HAL_OK) {
+            // This GDMA Channel is available
+            break;
+        }
+        pgdma_chnl += 1;
+    }
+
+    if (pgdma_chnl->GdmaIndx > MAX_GDMA_INDX) {
+        pgdma_chnl = NULL;
+    }
+    
+    return pgdma_chnl;
+}
+
+VOID HalGdmaChnlFree (HAL_GDMA_CHNL *pChnl)
+{
+    IRQ_HANDLE IrqHandle;
+
+    IrqHandle.IrqNum = pChnl->IrqNum;
+    InterruptDis(&IrqHandle);
+    InterruptUnRegister(&IrqHandle);
+    HalGdmaChnlUnRegister(pChnl->GdmaIndx, pChnl->GdmaChnl);
+}
+
+VOID HalGdmaMemIrqHandler(VOID *pData)
+{
+    PHAL_GDMA_OBJ pHalGdmaObj=(PHAL_GDMA_OBJ)pData;
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PIRQ_HANDLE pGdmaIrqHandle;
+    
+    pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
+    pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle);
+    // Clean Auto Reload Bit
+    HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter);
+
+    // Clear Pending ISR
+    HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
+
+    HalGdmaChDis((VOID*)(pHalGdmaAdapter));
+    pHalGdmaObj->Busy = 0;
+
+    if (pGdmaIrqHandle->IrqFun != NULL) {
+        pGdmaIrqHandle->IrqFun((VOID*)pGdmaIrqHandle->Data);
+    }
+}
+
+BOOL HalGdmaMemCpyAggrInit(PHAL_GDMA_OBJ pHalGdmaObj)
+{
+    HAL_GDMA_CHNL *pgdma_chnl;
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PIRQ_HANDLE pGdmaIrqHandle;
+    IRQ_HANDLE IrqHandle;
+
+    pgdma_chnl = HalGdmaChnlAlloc((PHAL_GDMA_CHNL) &GDMA_Multi_Block_Chnl_Option[0]);    // get a whatever GDMA channel
+    if (NULL == pgdma_chnl) {        
+        DBG_GDMA_ERR("%s: Cannot allocate a GDMA Channel\n", __FUNCTION__);
+        return _FALSE;
+    }
+
+    pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
+    pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle);
+    
+    DBG_GDMA_INFO("%s: Use GDMA%d CH%d\n", __FUNCTION__, pgdma_chnl->GdmaIndx, pgdma_chnl->GdmaChnl);
+
+    _memset((void *)pHalGdmaAdapter, 0, sizeof(HAL_GDMA_ADAPTER));
+
+    pHalGdmaAdapter->GdmaCtl.TtFc = TTFCMemToMem;
+    pHalGdmaAdapter->GdmaCtl.Done = 1;
+    pHalGdmaAdapter->MuliBlockCunt = 0;
+    pHalGdmaAdapter->MaxMuliBlock = 1;
+    pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl;
+    pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx;
+    pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl;
+    pHalGdmaAdapter->GdmaIsrType = (TransferType|ErrType);
+    pHalGdmaAdapter->IsrCtrl = ENABLE;
+    pHalGdmaAdapter->GdmaOnOff = ON;
+    pHalGdmaAdapter->GdmaCtl.IntEn      = 1;
+    pHalGdmaAdapter->Rsvd4to7 = 1;
+    pHalGdmaAdapter->Llpctrl = 1;
+    pGdmaIrqHandle->IrqNum = pgdma_chnl->IrqNum;
+    pGdmaIrqHandle->Priority = 10;
+
+    IrqHandle.IrqFun = (IRQ_FUN) HalGdmaMemIrqHandler;
+    IrqHandle.Data = (u32) pHalGdmaObj;
+    IrqHandle.IrqNum = pGdmaIrqHandle->IrqNum;
+    IrqHandle.Priority = pGdmaIrqHandle->Priority;
+
+    InterruptRegister(&IrqHandle);
+    InterruptEn(&IrqHandle);
+    pHalGdmaObj->Busy = 0;
+    
+    return _TRUE;
+}
+
+
+VOID HalGdmaMultiBlockSetting(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    u8 BlockNumber;
+    u8 BlockIndex;
+    u8 FourBytesAlign;
+
+    BlockNumber = pHalGdmaObj->BlockNum;
+    pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
+
+    pHalGdmaAdapter->GdmaCtl.LlpSrcEn = 1;
+    pHalGdmaAdapter->GdmaCtl.LlpDstEn = 1;
+
+    if(((pHalGdmaBlock[0].SrcAddr & 0x03) == 0) &&((pHalGdmaBlock[0].DstAddr & 0x03) == 0) 
+        && ((pHalGdmaBlock[0].BlockLength & 0X03) == 0)){   
+        pHalGdmaAdapter->GdmaCtl.SrcMsize   = MsizeEight;
+        pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes;
+        pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
+        pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes; 
+        FourBytesAlign = 1;
+    }
+    else{
+        pHalGdmaAdapter->GdmaCtl.SrcMsize   = MsizeEight;
+        pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte;
+        pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
+        pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte;
+        FourBytesAlign = 0;
+    }
+    
+    for(BlockIndex = 0; BlockIndex < BlockNumber; BlockIndex++){
+       
+        pHalGdmaObj->GdmaChLli[BlockIndex].Sarx = pHalGdmaBlock[BlockIndex].SrcAddr;
+        pHalGdmaObj->GdmaChLli[BlockIndex].Darx = pHalGdmaBlock[BlockIndex].DstAddr;
+        pHalGdmaObj->BlockSizeList[BlockIndex].pNextBlockSiz = &pHalGdmaObj->BlockSizeList[BlockIndex + 1];
+
+        if(FourBytesAlign){
+            pHalGdmaObj->BlockSizeList[BlockIndex].BlockSize = pHalGdmaBlock[BlockIndex].BlockLength >> 2;
+        }
+        else{
+            pHalGdmaObj->BlockSizeList[BlockIndex].BlockSize = pHalGdmaBlock[BlockIndex].BlockLength;
+        }
+        
+        pHalGdmaObj->Lli[BlockIndex].pLliEle = (GDMA_CH_LLI_ELE*) &pHalGdmaObj->GdmaChLli[BlockIndex];
+        pHalGdmaObj->Lli[BlockIndex].pNextLli = &pHalGdmaObj->Lli[BlockIndex + 1];
+
+
+        if(BlockIndex == BlockNumber - 1){
+            pHalGdmaObj->BlockSizeList[BlockIndex].pNextBlockSiz = NULL;
+            pHalGdmaObj->Lli[BlockIndex].pNextLli = NULL;
+        }
+        //DBG_GDMA_INFO("Lli[%d].pLiEle = %x\r\n", BlockIndex,Lli[BlockIndex].pLliEle);
+        //DBG_GDMA_INFO("Lli[%d].pNextLli = %x\r\n", BlockIndex,Lli[BlockIndex].pNextLli);
+    }
+
+    pHalGdmaAdapter->pBlockSizeList = (struct BLOCK_SIZE_LIST*) &pHalGdmaObj->BlockSizeList;
+    pHalGdmaAdapter->pLlix = (struct GDMA_CH_LLI*) &pHalGdmaObj->Lli;
+    //DBG_GDMA_INFO("pHalGdmaAdapter->pBlockSizeList = %x\r\n", pHalGdmaAdapter->pBlockSizeList);
+    //DBG_GDMA_INFO("pHalGdmaAdapter->pLlix  = %x\r\n", pHalGdmaAdapter->pLlix );
+}
+
+VOID HalGdmaLLPMemAlign(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PGDMA_CH_LLI_ELE pLliEle;
+    struct GDMA_CH_LLI *pGdmaChLli;
+    struct BLOCK_SIZE_LIST *pGdmaChBkLi;
+    u32 CtlxLow;
+    u32 CtlxUp;
+    u8 BlockNumber;
+    u8 BlockIndex;
+    
+    pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
+    BlockNumber = pHalGdmaObj->BlockNum;
+    
+    pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
+    pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
+    pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
+    
+    //4 Move to the second block to configure Memory Alginment setting
+    pLliEle->Llpx = (u32) pGdmaChLli->pLliEle;
+    pGdmaChBkLi = pGdmaChBkLi ->pNextBlockSiz;
+    
+    for(BlockIndex = 1; BlockIndex < BlockNumber; BlockIndex++){
+        pLliEle = pGdmaChLli->pLliEle;
+        CtlxLow = pLliEle->CtlxLow;
+        CtlxLow &= (BIT_INVC_CTLX_LO_DST_TR_WIDTH & BIT_INVC_CTLX_LO_SRC_TR_WIDTH);
+        CtlxUp = pLliEle->CtlxUp;    
+        CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
+
+        if(((pHalGdmaBlock[BlockIndex].SrcAddr & 0x03) == 0) &&((pHalGdmaBlock[BlockIndex].DstAddr & 0x03) == 0) 
+            && ((pHalGdmaBlock[BlockIndex].BlockLength & 0X03) == 0)){
+            pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes;
+            pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes;
+            pGdmaChBkLi->BlockSize = pHalGdmaBlock[BlockIndex].BlockLength>> 2;
+
+        }
+        else{
+            pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte;
+            pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte;
+            pGdmaChBkLi->BlockSize = pHalGdmaBlock[BlockIndex].BlockLength;
+        }
+
+        CtlxLow |= (BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
+              BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth));
+        CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);  
+
+        pGdmaChLli = pGdmaChLli->pNextLli;
+        pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;    
+        pLliEle->CtlxLow = CtlxLow;
+        pLliEle->CtlxUp = CtlxUp;
+        pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle);
+
+    }
+}
+
+VOID HalGdmaMemAggr(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    
+    u8 BlockNumber;
+
+    BlockNumber = pHalGdmaObj->BlockNum;
+    pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
+
+    if (pHalGdmaObj->Busy) {
+        DBG_GDMA_ERR("%s: ==> GDMA is Busy\r\n", __FUNCTION__);
+        return;
+    }
+    pHalGdmaObj->Busy = 1;
+
+    pHalGdmaAdapter->MaxMuliBlock = BlockNumber;
+    pHalGdmaAdapter->ChSar = pHalGdmaBlock[0].SrcAddr;
+    pHalGdmaAdapter->ChDar = pHalGdmaBlock[0].DstAddr;
+    
+    HalGdmaMultiBlockSetting(pHalGdmaObj, pHalGdmaBlock);    
+    HalGdmaOn((pHalGdmaAdapter));
+    HalGdmaChIsrEn((pHalGdmaAdapter));
+    HalGdmaChBlockSeting((pHalGdmaAdapter));
+    HalGdmaLLPMemAlign(pHalGdmaObj, pHalGdmaBlock);
+    HalGdmaChEn((pHalGdmaAdapter));
+
+}
+
+
+
+BOOL HalGdmaMemCpyInit(PHAL_GDMA_OBJ pHalGdmaObj)
+{
+    HAL_GDMA_CHNL *pgdma_chnl;
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PIRQ_HANDLE pGdmaIrqHandle;
+    IRQ_HANDLE IrqHandle;
+
+    pgdma_chnl = HalGdmaChnlAlloc(NULL);    // get a whatever GDMA channel
+    if (NULL == pgdma_chnl) {        
+        DBG_GDMA_ERR("%s: Cannot allocate a GDMA Channel\n", __FUNCTION__);
+        return _FALSE;
+    }
+
+    pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
+    pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle);
+    
+    DBG_GDMA_INFO("%s: Use GDMA%d CH%d\n", __FUNCTION__, pgdma_chnl->GdmaIndx, pgdma_chnl->GdmaChnl);
+#if 0
+    if (pgdma_chnl->GdmaIndx == 0) {
+        ACTCK_GDMA0_CCTRL(ON);
+        GDMA0_FCTRL(ON);
+    }
+    else if (pgdma_chnl->GdmaIndx == 1) {
+        ACTCK_GDMA1_CCTRL(ON);
+        GDMA1_FCTRL(ON);
+    }
+#endif    
+    _memset((void *)pHalGdmaAdapter, 0, sizeof(HAL_GDMA_ADAPTER));
+
+//    pHalGdmaAdapter->GdmaCtl.TtFc = TTFCMemToMem;
+    pHalGdmaAdapter->GdmaCtl.Done = 1;
+//    pHalGdmaAdapter->MuliBlockCunt = 0;
+//    pHalGdmaAdapter->MaxMuliBlock = 1;
+    pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl;
+    pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx;
+    pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl;
+    pHalGdmaAdapter->GdmaIsrType = (TransferType|ErrType);
+    pHalGdmaAdapter->IsrCtrl = ENABLE;
+    pHalGdmaAdapter->GdmaOnOff = ON;
+
+    pHalGdmaAdapter->GdmaCtl.IntEn      = 1;
+//    pHalGdmaAdapter->GdmaCtl.SrcMsize   = MsizeEight;
+//    pHalGdmaAdapter->GdmaCtl.DestMsize  = MsizeEight;
+//    pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes;
+//    pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes;
+//    pHalGdmaAdapter->GdmaCtl.Dinc = IncType;
+//    pHalGdmaAdapter->GdmaCtl.Sinc = IncType;
+
+    pGdmaIrqHandle->IrqNum = pgdma_chnl->IrqNum;
+    pGdmaIrqHandle->Priority = 10;
+
+    IrqHandle.IrqFun = (IRQ_FUN) HalGdmaMemIrqHandler;
+    IrqHandle.Data = (u32) pHalGdmaObj;
+    IrqHandle.IrqNum = pGdmaIrqHandle->IrqNum;
+    IrqHandle.Priority = pGdmaIrqHandle->Priority;
+
+    InterruptRegister(&IrqHandle);
+    InterruptEn(&IrqHandle);
+    pHalGdmaObj->Busy = 0;
+    
+    return _TRUE;
+}
+
+VOID HalGdmaMemCpyDeInit(PHAL_GDMA_OBJ pHalGdmaObj)
+{
+    HAL_GDMA_CHNL GdmaChnl;
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PIRQ_HANDLE pGdmaIrqHandle;
+
+    pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
+    pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle);
+
+    GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
+    GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
+    GdmaChnl.IrqNum = pGdmaIrqHandle->IrqNum;
+    HalGdmaChnlFree(&GdmaChnl);
+}
+
+// If multi-task using the same GDMA Object, then it needs a mutex to protect this procedure
+VOID* HalGdmaMemCpy(PHAL_GDMA_OBJ pHalGdmaObj, void* pDest, void* pSrc, u32 len)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+
+    if (pHalGdmaObj->Busy) {
+        DBG_GDMA_ERR("%s: ==> GDMA is Busy\r\n", __FUNCTION__);
+        return 0;
+    }
+    pHalGdmaObj->Busy = 1;
+    pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
+
+    DBG_GDMA_INFO("%s: ==> Src=0x%x Dst=0x%x Len=%d\r\n", __FUNCTION__, pSrc, pDest, len);
+    if ((((u32)pSrc & 0x03)==0) &&
+        (((u32)pDest & 0x03)==0) &&        
+        ((len & 0x03)== 0)) {
+        // 4-bytes aligned, move 4 bytes each transfer
+        pHalGdmaAdapter->GdmaCtl.SrcMsize   = MsizeEight;
+        pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes;
+        pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
+        pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes;
+        pHalGdmaAdapter->GdmaCtl.BlockSize = len >> 2;
+    }
+    else {
+        pHalGdmaAdapter->GdmaCtl.SrcMsize   = MsizeEight;
+        pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte;
+        pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
+        pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte;
+        pHalGdmaAdapter->GdmaCtl.BlockSize = len;
+    }
+
+    pHalGdmaAdapter->ChSar = (u32)pSrc;
+    pHalGdmaAdapter->ChDar = (u32)pDest;                
+    pHalGdmaAdapter->PacketLen = len;
+
+    HalGdmaOn((pHalGdmaAdapter));
+    HalGdmaChIsrEn((pHalGdmaAdapter));
+    HalGdmaChSeting((pHalGdmaAdapter));
+    HalGdmaChEn((pHalGdmaAdapter));
+
+    return (pDest);
+}

component/soc/realtek/8195a/fwlib/src/hal_gpio.c

@@ -0,0 +1,204 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#include "rtl8195a.h"
+
+#ifdef CONFIG_GPIO_EN
+
+HAL_GPIO_ADAPTER gHAL_Gpio_Adapter;
+extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
+
+extern VOID GPIO_PullCtrl_8195a(u32 chip_pin, u8 pull_type);
+
+/**
+  * @brief  To get the GPIO IP Pin name for the given chip pin name
+  *
+  * @param  chip_pin: The chip pin name.
+  *
+  * @retval The gotten GPIO IP pin name
+  */
+u32 
+HAL_GPIO_GetPinName(
+    u32 chip_pin
+)
+{
+    return HAL_GPIO_GetIPPinName_8195a((u32)chip_pin);
+}
+
+/**
+  * @brief  Set the GPIO pad Pull type
+  *
+  *  @param    pin: The pin for pull type control.
+  *  @param    mode: the pull type for the pin.
+  *  @return   None
+  */
+VOID 
+HAL_GPIO_PullCtrl(
+    u32 pin,
+    u32 mode    
+)
+{
+    u8 pull_type;
+
+    switch (mode) {
+        case hal_PullNone:
+            pull_type = DIN_PULL_NONE;
+            break;
+            
+        case hal_PullDown:
+            pull_type = DIN_PULL_LOW;
+            break;
+            
+        case hal_PullUp:
+            pull_type = DIN_PULL_HIGH;
+            break;
+            
+        case hal_OpenDrain:
+        default:
+            pull_type = DIN_PULL_NONE;
+            break;
+    }
+
+//    HAL_GPIO_PullCtrl_8195a (pin, pull_type);
+    GPIO_PullCtrl_8195a (pin, pull_type);
+}
+
+
+/**
+  * @brief  Initializes a GPIO Pin by the GPIO_Pin parameters.
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
+  *
+  * @retval HAL_Status
+  */
+VOID 
+HAL_GPIO_Init(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    u8 port_num;
+    u8 pin_num;
+    u32 chip_pin;
+    HAL_Status ret;
+
+    if (_pHAL_Gpio_Adapter == NULL) {
+        _pHAL_Gpio_Adapter = &gHAL_Gpio_Adapter;
+//        DBG_GPIO_INFO("HAL_GPIO_Init: Initial GPIO Adapter\n ");
+    }
+
+    port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
+    pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
+    chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num);
+    if (GpioFunctionChk(chip_pin, ENABLE) == _FALSE) {
+        DBG_GPIO_ERR("HAL_GPIO_Init: GPIO Pin(%x) Unavailable\n ", chip_pin);
+        return;
+    }
+
+    // Make the pin pull control default as High-Z
+    GPIO_PullCtrl_8195a(chip_pin, HAL_GPIO_HIGHZ);
+
+    ret = HAL_GPIO_Init_8195a(GPIO_Pin);
+    
+    if (ret != HAL_OK) {
+        GpioFunctionChk(chip_pin, DISABLE);
+    }
+}
+
+/**
+  * @brief  Initializes a GPIO Pin as a interrupt signal
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
+  *
+  * @retval HAL_Status
+  */
+VOID 
+HAL_GPIO_Irq_Init(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    u8 port_num;
+    u8 pin_num;
+    u32 chip_pin;
+    HAL_Status ret;
+    
+    if (_pHAL_Gpio_Adapter == NULL) {
+        _pHAL_Gpio_Adapter = &gHAL_Gpio_Adapter;
+//        DBG_GPIO_INFO("%s: Initial GPIO Adapter\n ", __FUNCTION__);
+    }
+
+    if (_pHAL_Gpio_Adapter->IrqHandle.IrqFun == NULL) {
+        _pHAL_Gpio_Adapter->IrqHandle.IrqFun = (IRQ_FUN)HAL_GPIO_MbedIrqHandler_8195a;
+        _pHAL_Gpio_Adapter->IrqHandle.Priority = 6;
+        HAL_GPIO_RegIrq_8195a(&_pHAL_Gpio_Adapter->IrqHandle);        
+        InterruptEn(&_pHAL_Gpio_Adapter->IrqHandle);
+//        DBG_GPIO_INFO("%s: Initial GPIO IRQ Adapter\n ", __FUNCTION__);
+    }
+
+    port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
+    pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
+    chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num);
+    if (GpioFunctionChk(chip_pin, ENABLE) == _FALSE) {
+        DBG_GPIO_ERR("HAL_GPIO_Irq_Init: GPIO Pin(%x) Unavailable\n ", chip_pin);
+        return;
+    }
+
+    DBG_GPIO_INFO("HAL_GPIO_Irq_Init: GPIO(name=0x%x)(mode=%d)\n ", GPIO_Pin->pin_name, 
+        GPIO_Pin->pin_mode);
+    HAL_GPIO_MaskIrq_8195a(GPIO_Pin);
+    ret = HAL_GPIO_Init_8195a(GPIO_Pin);
+    if (ret != HAL_OK) {
+        GpioFunctionChk(chip_pin, DISABLE);
+    }    
+}
+
+/**
+  * @brief  UnInitial GPIO Adapter
+  *
+  *
+  * @retval HAL_Status
+  */
+VOID
+HAL_GPIO_IP_DeInit(
+    VOID
+)
+{
+    if (_pHAL_Gpio_Adapter != NULL) {
+        InterruptDis(&_pHAL_Gpio_Adapter->IrqHandle);
+        HAL_GPIO_UnRegIrq_8195a(&_pHAL_Gpio_Adapter->IrqHandle);                
+        _pHAL_Gpio_Adapter = NULL;
+    }
+    
+}
+
+/**
+  * @brief  De-Initializes a GPIO Pin, reset it as default setting.
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @retval HAL_Status
+  */
+VOID 
+HAL_GPIO_DeInit(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    u8 port_num;
+    u8 pin_num;
+    u32 chip_pin;
+    
+    port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
+    pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
+    chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num);
+    HAL_GPIO_DeInit_8195a(GPIO_Pin);
+
+    GpioFunctionChk(chip_pin, DISABLE);
+}
+
+
+#endif // CONFIG_GPIO_EN

component/soc/realtek/8195a/fwlib/src/hal_i2s.c

@@ -0,0 +1,560 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h"
+#include "hal_i2s.h"
+#include "rand.h"
+#include "rtl_utility.h"
+
+
+//1 need to be modified 
+
+
+/*======================================================
+    Local used variables
+*/
+SRAM_BF_DATA_SECTION
+HAL_I2S_OP HalI2SOpSAL={0};
+
+
+VOID
+I2SISRHandle(
+    IN  VOID *Data
+)
+{
+    PHAL_I2S_ADAPTER pI2SAdp = (PHAL_I2S_ADAPTER) Data;
+    PHAL_I2S_OP     pHalI2SOP = &HalI2SOpSAL;
+    PHAL_I2S_INIT_DAT pI2SCfg = pI2SAdp->pInitDat;
+    u32 I2STxIsr, I2SRxIsr;
+    u8  I2SPageNum = pI2SCfg->I2SPageNum+1;
+//    u32 I2SPageSize = (pI2SAdp->I2SPageSize+1)<<2;
+    u32 i;
+    u32 pbuf;
+
+    I2STxIsr = pHalI2SOP->HalI2SReadReg(pI2SCfg, REG_I2S_TX_STATUS_INT);
+    I2SRxIsr = pHalI2SOP->HalI2SReadReg(pI2SCfg, REG_I2S_RX_STATUS_INT);
+
+    pI2SCfg->I2STxIntrClr = I2STxIsr;
+    pI2SCfg->I2SRxIntrClr = I2SRxIsr;
+    pHalI2SOP->HalI2SClrIntr(pI2SCfg);
+
+    for (i=0 ; i<I2SPageNum ; i++) { // page 0, 1, 2, 3
+        if (I2STxIsr & (1<<pI2SCfg->I2SHWTxIdx)) {
+//            pbuf = ((u32)(pI2SCfg->I2STxData)) + (I2SPageSize*pI2SCfg->I2SHWTxIdx);
+            pbuf = (u32)pI2SAdp->TxPageList[pI2SCfg->I2SHWTxIdx];
+            pI2SAdp->UserCB.TxCCB(pI2SAdp->UserCB.TxCBId, (char*)pbuf);
+            I2STxIsr &= ~(1<<pI2SCfg->I2SHWTxIdx);
+            pI2SCfg->I2SHWTxIdx += 1;
+            if (pI2SCfg->I2SHWTxIdx == I2SPageNum) {
+                pI2SCfg->I2SHWTxIdx = 0;
+            }
+        }
+        
+        if (I2SRxIsr & (1<<pI2SCfg->I2SHWRxIdx)) {
+//            pbuf = ((u32)(pI2SCfg->I2SRxData)) + (I2SPageSize*pI2SCfg->I2SHWRxIdx);
+            pbuf = (u32)pI2SAdp->RxPageList[pI2SCfg->I2SHWRxIdx];
+            pI2SAdp->UserCB.RxCCB(pI2SAdp->UserCB.RxCBId, (char*)pbuf);
+            I2SRxIsr &= ~(1<<pI2SCfg->I2SHWRxIdx);
+            pI2SCfg->I2SHWRxIdx += 1;
+            if (pI2SCfg->I2SHWRxIdx == I2SPageNum) {
+                pI2SCfg->I2SHWRxIdx = 0;
+            }
+        }
+    }
+}
+
+
+static HAL_Status
+RtkI2SIrqInit(
+    IN  PHAL_I2S_ADAPTER pI2SAdapter
+)
+{
+    PIRQ_HANDLE pIrqHandle;
+
+    if (pI2SAdapter->DevNum > I2S_MAX_ID) {
+        DBG_I2S_ERR("RtkI2SIrqInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
+        return HAL_ERR_PARA;
+    }
+    
+    pIrqHandle = &pI2SAdapter->IrqHandle;
+    
+    switch (pI2SAdapter->DevNum){
+        case I2S0_SEL:
+            pIrqHandle->IrqNum = I2S0_PCM0_IRQ;
+            break;
+            
+        case I2S1_SEL:
+            pIrqHandle->IrqNum = I2S1_PCM1_IRQ;
+            break;
+            
+        default:
+            return HAL_ERR_PARA;
+    }
+
+    pIrqHandle->Data = (u32) (pI2SAdapter);
+    pIrqHandle->IrqFun = (IRQ_FUN) I2SISRHandle;
+    pIrqHandle->Priority = 6;
+    InterruptRegister(pIrqHandle);
+    InterruptEn(pIrqHandle);
+    
+    return HAL_OK;
+}
+
+static HAL_Status
+RtkI2SIrqDeInit(
+    IN  PHAL_I2S_ADAPTER pI2SAdapter
+)
+{
+    if (pI2SAdapter->DevNum > I2S_MAX_ID) {
+        DBG_I2S_ERR("RtkI2SIrqDeInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
+        return HAL_ERR_PARA;
+    }
+
+    InterruptDis(&pI2SAdapter->IrqHandle);
+    InterruptUnRegister(&pI2SAdapter->IrqHandle);  
+
+    return HAL_OK;
+}
+
+static HAL_Status
+RtkI2SPinMuxInit(
+    IN  PHAL_I2S_ADAPTER pI2SAdapter
+)
+{
+    u32 I2Stemp;
+
+    if (pI2SAdapter->DevNum > I2S_MAX_ID) {
+        DBG_I2S_ERR("RtkI2SPinMuxInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
+        return HAL_ERR_PARA;
+    }
+
+    // enable system pll
+    I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) | (1<<9) | (1<<10);
+    HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);
+
+    switch (pI2SAdapter->DevNum){
+        case I2S0_SEL:
+            ACTCK_I2S_CCTRL(ON);
+            SLPCK_I2S_CCTRL(ON);
+            LXBUS_FCTRL(ON); // enable lx bus for i2s
+            
+            /*I2S0 Pin Mux Setting*/
+            PinCtrl(I2S0, pI2SAdapter->PinMux, ON);
+            if (pI2SAdapter->PinMux == I2S_S0) {
+                DBG_I2S_WARN(ANSI_COLOR_MAGENTA"I2S0 Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET);
+            }
+            I2S0_MCK_CTRL(ON);
+            I2S0_PIN_CTRL(ON);
+            I2S0_FCTRL(ON);
+            
+            break;
+        case I2S1_SEL:
+            ACTCK_I2S_CCTRL(ON);
+            SLPCK_I2S_CCTRL(ON);
+            LXBUS_FCTRL(ON); // enable lx bus for i2s
+            
+            /*I2S1 Pin Mux Setting*/
+            PinCtrl(I2S1, pI2SAdapter->PinMux, ON);
+            if (pI2SAdapter->PinMux == I2S_S2) {
+                DBG_I2S_WARN(ANSI_COLOR_MAGENTA"I2S1 Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET);
+            }
+            I2S1_MCK_CTRL(ON);
+            I2S1_PIN_CTRL(ON);
+            I2S0_FCTRL(ON); //i2s 1 is control by bit 24 BIT_PERI_I2S0_EN
+            I2S1_FCTRL(ON);
+            break;
+        default:
+            return HAL_ERR_PARA;
+    }
+    
+    return HAL_OK;
+}
+
+
+static HAL_Status
+RtkI2SPinMuxDeInit(
+    IN  PHAL_I2S_ADAPTER pI2SAdapter
+)
+{
+    if (pI2SAdapter->DevNum > I2S_MAX_ID) {
+        DBG_I2S_ERR("RtkI2SPinMuxDeInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
+        return HAL_ERR_PARA;
+    }
+
+    switch (pI2SAdapter->DevNum){
+        case I2S0_SEL:
+            /*I2S0 Pin Mux Setting*/
+            //ACTCK_I2C0_CCTRL(OFF);
+            PinCtrl(I2S0, pI2SAdapter->PinMux, OFF);
+            I2S0_MCK_CTRL(OFF);
+            I2S0_PIN_CTRL(OFF);
+            //I2S0_FCTRL(OFF);
+            
+            break;
+        case I2S1_SEL:
+            /*I2S1 Pin Mux Setting*/
+            //ACTCK_I2C1_CCTRL(OFF);
+            PinCtrl(I2S1, pI2SAdapter->PinMux, OFF);
+            I2S1_MCK_CTRL(OFF);
+            I2S1_PIN_CTRL(OFF);
+            //I2S1_FCTRL(OFF);
+            break;
+        default:
+            return HAL_ERR_PARA;
+    }
+    
+    return HAL_OK;
+}
+
+
+HAL_Status
+RtkI2SInit(
+    IN  VOID *Data
+)
+{
+    PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
+    PHAL_I2S_OP     pHalI2SOP  = &HalI2SOpSAL;
+    PHAL_I2S_INIT_DAT pI2SCfg;
+
+    if (pI2SAdapter == 0) {
+        DBG_I2S_ERR("RtkI2SInit: Null Pointer\r\n");
+        return HAL_ERR_PARA;
+    }
+    
+    if (pI2SAdapter->DevNum > I2S_MAX_ID) {
+        DBG_I2S_ERR("RtkI2SInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
+        return HAL_ERR_PARA;
+    }
+
+    pI2SCfg = pI2SAdapter->pInitDat;
+
+    /*I2S Initialize HAL Operations*/
+    HalI2SOpInit(pHalI2SOP);
+    
+    /*I2S Interrupt Initialization*/
+    RtkI2SIrqInit(pI2SAdapter);
+
+    /*I2S Pin Mux Initialization*/
+    RtkI2SPinMuxInit(pI2SAdapter);
+
+    /*I2S Load User Setting*/
+    pI2SCfg->I2SIdx = pI2SAdapter->DevNum;
+
+    /*I2S HAL Initialization*/
+    pHalI2SOP->HalI2SInit(pI2SCfg);
+
+    /*I2S Device Status Update*/
+    pI2SAdapter->DevSts  = I2S_STS_INITIALIZED;
+    
+    /*I2S Enable Module*/
+    pI2SCfg->I2SEn = I2S_ENABLE;
+    pHalI2SOP->HalI2SEnable(pI2SCfg);
+
+    /*I2S Device Status Update*/
+    pI2SAdapter->DevSts  = I2S_STS_IDLE;    
+    
+    return HAL_OK;
+}
+
+HAL_Status
+RtkI2SDeInit(
+    IN  VOID *Data
+)
+{
+    PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
+    PHAL_I2S_OP     pHalI2SOP  = &HalI2SOpSAL;
+    PHAL_I2S_INIT_DAT pI2SCfg;
+    u32 I2Stemp;
+
+    if (pI2SAdapter == 0) {
+        DBG_I2S_ERR("RtkI2SDeInit: Null Pointer\r\n");
+        return HAL_ERR_PARA;
+    }
+
+    pI2SCfg = pI2SAdapter->pInitDat;
+
+    /*I2S Disable Module*/
+    pI2SCfg->I2SEn = I2S_DISABLE;
+    pHalI2SOP->HalI2SEnable(pI2SCfg);
+    HalI2SClearAllOwnBit((VOID*)pI2SCfg);
+
+    /*I2C HAL DeInitialization*/
+    //pHalI2SOP->HalI2SDeInit(pI2SCfg);
+    
+    /*I2S Interrupt DeInitialization*/
+    RtkI2SIrqDeInit(pI2SAdapter);
+
+    /*I2S Pin Mux DeInitialization*/
+    RtkI2SPinMuxDeInit(pI2SAdapter);
+    
+    /*I2S HAL DeInitialization*/
+    pHalI2SOP->HalI2SDeInit(pI2SCfg);
+
+    /*I2S CLK Source Close*/
+    I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) & (~((1<<9) | (1<<10)));
+    HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);     
+
+    /*I2S Device Status Update*/
+    pI2SAdapter->DevSts  = I2S_STS_UNINITIAL;
+    
+    return HAL_OK;
+}
+
+HAL_Status
+RtkI2SEnable(
+    IN  VOID *Data
+)
+{
+    PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
+    PHAL_I2S_OP     pHalI2SOP  = &HalI2SOpSAL;
+    PHAL_I2S_INIT_DAT pI2SCfg;
+    u32 I2Stemp;
+
+    // Enable IP Clock
+    I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) | (1<<9) | (1<<10);
+    HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);  
+    ACTCK_I2S_CCTRL(ON);
+    SLPCK_I2S_CCTRL(ON);
+
+    pI2SCfg = pI2SAdapter->pInitDat;
+    pI2SCfg->I2SEn = I2S_ENABLE;
+    pHalI2SOP->HalI2SEnable(pI2SCfg);
+
+    return HAL_OK;
+}
+
+HAL_Status
+RtkI2SDisable(
+    IN  VOID *Data
+)
+{
+    PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
+    PHAL_I2S_OP     pHalI2SOP  = &HalI2SOpSAL;
+    PHAL_I2S_INIT_DAT pI2SCfg;
+    u32 I2Stemp;
+
+    pI2SCfg = pI2SAdapter->pInitDat;
+    pI2SCfg->I2SEn = I2S_DISABLE;
+    pHalI2SOP->HalI2SEnable(pI2SCfg);
+
+    // Gate IP Clock
+    ACTCK_I2S_CCTRL(OFF);
+    SLPCK_I2S_CCTRL(OFF);
+
+    // Close I2S bus clock(WS,SCLK,MCLK). If needs that clock, mark this. 
+    I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) & (~((1<<9) | (1<<10)));
+    HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);    
+   
+    return HAL_OK;
+}
+
+RTK_STATUS
+RtkI2SIoCtrl(
+    IN  VOID *Data
+)
+{
+    return _EXIT_SUCCESS;
+}
+
+RTK_STATUS
+RtkI2SPowerCtrl(
+    IN  VOID *Data
+)
+{
+    return _EXIT_SUCCESS;
+}
+
+HAL_Status
+RtkI2SLoadDefault( 
+    IN  VOID *Adapter,
+    IN  VOID *Setting
+)
+{
+    PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Adapter;
+    PHAL_I2S_INIT_DAT pI2SCfg = pI2SAdapter->pInitDat;
+    PHAL_I2S_DEF_SETTING pLoadSetting = (PHAL_I2S_DEF_SETTING)Setting;
+
+    if (pI2SAdapter == 0) {
+        DBG_I2S_ERR("RtkI2SLoadDefault: Null Pointer\r\n");
+        return HAL_ERR_PARA;
+    }
+
+    if (pI2SAdapter->pInitDat == NULL) {
+        DBG_I2S_ERR("RtkI2SLoadDefault: pInitDat is NULL!\r\n", pI2SAdapter->DevNum);
+        return HAL_ERR_PARA;
+    }
+
+    pI2SAdapter->DevSts          = pLoadSetting->DevSts;
+    pI2SAdapter->ErrType         = 0;
+    pI2SAdapter->TimeOut         = 0;
+    
+    pI2SCfg->I2SIdx        = pI2SAdapter->DevNum;
+    pI2SCfg->I2SEn         = I2S_DISABLE;
+    pI2SCfg->I2SMaster     = pLoadSetting->I2SMaster;
+    pI2SCfg->I2SWordLen    = pLoadSetting->I2SWordLen;
+    pI2SCfg->I2SChNum      = pLoadSetting->I2SChNum;
+    pI2SCfg->I2SPageNum    = pLoadSetting->I2SPageNum;
+    pI2SCfg->I2SPageSize   = pLoadSetting->I2SPageSize;
+    pI2SCfg->I2SRate       = pLoadSetting->I2SRate;
+    pI2SCfg->I2STRxAct     = pLoadSetting->I2STRxAct;
+    pI2SCfg->I2STxIntrMSK  = pLoadSetting->I2STxIntrMSK;
+    pI2SCfg->I2SRxIntrMSK  = pLoadSetting->I2SRxIntrMSK;
+
+    return HAL_OK;
+}
+
+VOID HalI2SOpInit(
+    IN  VOID *Data
+)
+{
+    PHAL_I2S_OP pHalI2SOp = (PHAL_I2S_OP) Data;
+
+    pHalI2SOp->HalI2SDeInit      = HalI2SDeInitRtl8195a;
+    pHalI2SOp->HalI2STx          = HalI2STxRtl8195a;
+    pHalI2SOp->HalI2SRx          = HalI2SRxRtl8195a;
+    pHalI2SOp->HalI2SEnable      = HalI2SEnableRtl8195a;
+    pHalI2SOp->HalI2SIntrCtrl    = HalI2SIntrCtrlRtl8195a;
+    pHalI2SOp->HalI2SReadReg     = HalI2SReadRegRtl8195a;
+    pHalI2SOp->HalI2SClrIntr     = HalI2SClrIntrRtl8195a;
+    pHalI2SOp->HalI2SClrAllIntr  = HalI2SClrAllIntrRtl8195a;
+    pHalI2SOp->HalI2SDMACtrl     = HalI2SDMACtrlRtl8195a;
+
+#ifndef CONFIG_CHIP_E_CUT
+    pHalI2SOp->HalI2SInit        = HalI2SInitRtl8195a_Patch;
+    pHalI2SOp->HalI2SSetRate     = HalI2SSetRateRtl8195a;
+    pHalI2SOp->HalI2SSetWordLen  = HalI2SSetWordLenRtl8195a;
+    pHalI2SOp->HalI2SSetChNum    = HalI2SSetChNumRtl8195a;
+    pHalI2SOp->HalI2SSetPageNum  = HalI2SSetPageNumRtl8195a;
+    pHalI2SOp->HalI2SSetPageSize = HalI2SSetPageSizeRtl8195a;
+#else
+    pHalI2SOp->HalI2SInit        = HalI2SInitRtl8195a_V04;
+    pHalI2SOp->HalI2SSetRate     = HalI2SSetRateRtl8195a_V04;
+    pHalI2SOp->HalI2SSetWordLen  = HalI2SSetWordLenRtl8195a_V04;
+    pHalI2SOp->HalI2SSetChNum    = HalI2SSetChNumRtl8195a_V04;
+    pHalI2SOp->HalI2SSetPageNum  = HalI2SSetPageNumRtl8195a_V04;
+    pHalI2SOp->HalI2SSetPageSize = HalI2SSetPageSizeRtl8195a_V04;
+#endif  // #ifndef CONFIG_CHIP_E_CUT
+}
+
+HAL_Status 
+HalI2SInit(
+    IN VOID *Data
+)
+{
+    HAL_Status ret;
+    PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
+    u32 Function;
+    u8 funret;    
+    
+#ifdef CONFIG_SOC_PS_MODULE
+    REG_POWER_STATE I2sPwrState;
+#endif
+
+    if(pI2SAdapter->DevNum == 0){
+        Function = I2S0;
+    }
+    else {
+        Function = I2S1;
+    }
+        
+    funret = FunctionChk(Function, (u32)pI2SAdapter->PinMux);
+
+    if (funret == _FALSE){
+        return HAL_ERR_HW;
+    }
+
+    ret = RtkI2SInit(Data);
+#ifdef CONFIG_SOC_PS_MODULE
+    if(ret == HAL_OK) {
+        // To register a new peripheral device power state
+        I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum;
+        I2sPwrState.PwrState = ACT;
+        RegPowerState(I2sPwrState);
+    }
+#endif
+
+    return ret;
+
+}
+
+VOID 
+HalI2SDeInit(
+    IN VOID *Data
+)
+{
+#ifdef CONFIG_SOC_PS_MODULE
+    REG_POWER_STATE I2sPwrState;
+    PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
+    u8 HwState;
+
+    I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum;
+    QueryRegPwrState(I2sPwrState.FuncIdx, &(I2sPwrState.PwrState), &HwState);
+
+    // if the power state isn't ACT, then switch the power state back to ACT first
+    if ((I2sPwrState.PwrState != ACT) && (I2sPwrState.PwrState != INACT)) {
+        HalI2SEnable(Data);
+        QueryRegPwrState(I2sPwrState.FuncIdx, &(I2sPwrState.PwrState), &HwState);
+    }
+
+    if (I2sPwrState.PwrState == ACT) {
+        I2sPwrState.PwrState = INACT;
+        RegPowerState(I2sPwrState);
+    }   
+#endif
+
+    RtkI2SDeInit(Data);  
+
+}
+
+
+HAL_Status 
+HalI2SDisable(
+    IN VOID *Data
+)
+{
+    HAL_Status ret;
+#ifdef CONFIG_SOC_PS_MODULE
+    REG_POWER_STATE I2sPwrState;
+    PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
+#endif
+
+    ret = RtkI2SDisable(Data);
+#ifdef CONFIG_SOC_PS_MODULE
+    if (ret == HAL_OK) {
+        I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum;
+        I2sPwrState.PwrState = SLPCG;
+        RegPowerState(I2sPwrState);
+    }
+#endif
+    return ret;
+}
+
+HAL_Status 
+HalI2SEnable(
+    IN VOID *Data
+)
+{
+    HAL_Status ret;
+#ifdef CONFIG_SOC_PS_MODULE
+    REG_POWER_STATE I2sPwrState;
+    PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
+#endif
+
+    ret = RtkI2SEnable(Data);
+#ifdef CONFIG_SOC_PS_MODULE
+    if (ret == HAL_OK) {
+        I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum;
+        I2sPwrState.PwrState = ACT;
+        RegPowerState(I2sPwrState);
+    }
+#endif
+    return ret;
+}
+

component/soc/realtek/8195a/fwlib/src/hal_mii.c

@@ -0,0 +1,134 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#include "rtl8195a.h"
+
+#ifdef CONFIG_MII_EN
+
+#include "hal_mii.h"
+
+HAL_ETHER_ADAPTER HalEtherAdp;
+
+
+
+s32
+HalMiiInit(
+	IN VOID
+)
+{
+	if (FunctionChk(MII, S0) == _FALSE)
+		return HAL_ERR_UNKNOWN;
+	else
+		return HalMiiInitRtl8195a();
+}
+
+
+VOID
+HalMiiDeInit(
+	IN VOID
+)
+{
+	HalMiiDeInitRtl8195a();
+}
+
+
+s32
+HalMiiWriteData(
+	IN const char *Data,
+	IN u32 Size
+)
+{
+	return HalMiiWriteDataRtl8195a(Data, Size);
+}
+
+
+u32
+HalMiiSendPacket(
+	IN VOID
+)
+{
+	return HalMiiSendPacketRtl8195a();
+}
+
+
+u32
+HalMiiReceivePacket(
+	IN VOID
+)
+{
+	return HalMiiReceivePacketRtl8195a();
+}
+
+
+u32
+HalMiiReadData(
+	IN u8 *Data,
+	IN u32 Size
+)
+{
+	return HalMiiReadDataRtl8195a(Data, Size);
+}
+
+
+VOID
+HalMiiGetMacAddress(
+	IN u8 *Addr
+)
+{
+	HalMiiGetMacAddressRtl8195a(Addr);
+}
+
+
+u32
+HalMiiGetLinkStatus(
+	IN VOID
+)
+{
+	return HalMiiGetLinkStatusRtl8195a();
+}
+
+
+VOID
+HalMiiForceLink(
+	IN s32 Speed,
+	IN s32 Duplex
+)
+{
+	HalMiiForceLinkRtl8195a(Speed, Duplex);
+}
+
+
+#ifdef CONFIG_MII_VERIFY
+VOID
+HalMiiOpInit(
+    IN VOID *Data
+)
+{
+    PHAL_MII_OP pHalMiiOp = (PHAL_MII_OP) Data;
+
+
+    pHalMiiOp->HalMiiGmacInit          = HalMiiGmacInitRtl8195a;
+    pHalMiiOp->HalMiiGmacReset         = HalMiiGmacResetRtl8195a;
+    pHalMiiOp->HalMiiGmacEnablePhyMode = HalMiiGmacEnablePhyModeRtl8195a;
+    pHalMiiOp->HalMiiGmacXmit          = HalMiiGmacXmitRtl8195a;
+    pHalMiiOp->HalMiiGmacCleanTxRing   = HalMiiGmacCleanTxRingRtl8195a;
+    pHalMiiOp->HalMiiGmacFillTxInfo    = HalMiiGmacFillTxInfoRtl8195a;
+    pHalMiiOp->HalMiiGmacFillRxInfo    = HalMiiGmacFillRxInfoRtl8195a;
+    pHalMiiOp->HalMiiGmacTx            = HalMiiGmacTxRtl8195a;
+    pHalMiiOp->HalMiiGmacRx            = HalMiiGmacRxRtl8195a;
+    pHalMiiOp->HalMiiGmacSetDefaultEthIoCmd   = HalMiiGmacSetDefaultEthIoCmdRtl8195a;
+    pHalMiiOp->HalMiiGmacInitIrq       = HalMiiGmacInitIrqRtl8195a;
+    pHalMiiOp->HalMiiGmacGetInterruptStatus   = HalMiiGmacGetInterruptStatusRtl8195a;
+    pHalMiiOp->HalMiiGmacClearInterruptStatus = HalMiiGmacClearInterruptStatusRtl8195a;
+}
+#endif  // #ifdef CONFIG_MII_VERIFY
+
+#endif  // #ifdef CONFIG_MII_EN
+
+

component/soc/realtek/8195a/fwlib/src/hal_nfc.c

@@ -0,0 +1,20 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h"
+#include "hal_nfc.h"
+
+VOID HalNFCOpInit(
+    IN  VOID *Data
+)
+{
+
+}
+

component/soc/realtek/8195a/fwlib/src/hal_pcm.c

@@ -0,0 +1,28 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "hal_pcm.h"
+
+VOID HalPcmOpInit(
+    IN  VOID *Data
+)
+{
+    PHAL_PCM_OP pHalPcmOp = (PHAL_PCM_OP) Data;
+
+    pHalPcmOp->HalPcmOnOff = HalPcmOnOffRtl8195a;
+    pHalPcmOp->HalPcmInit = HalPcmInitRtl8195a;
+    pHalPcmOp->HalPcmSetting = HalPcmSettingRtl8195a;
+    pHalPcmOp->HalPcmEn = HalPcmEnRtl8195a;
+    pHalPcmOp->HalPcmIsrEnAndDis= HalPcmIsrEnAndDisRtl8195a;
+    pHalPcmOp->HalPcmDumpReg= HalPcmDumpRegRtl8195a;
+    pHalPcmOp->HalPcm= HalPcmRtl8195a;
+}
+
+

component/soc/realtek/8195a/fwlib/src/hal_pwm.c

@@ -0,0 +1,141 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+ 
+
+#include "rtl8195a.h"
+
+#ifdef CONFIG_PWM_EN
+#include "hal_pwm.h"
+#include "hal_timer.h"
+
+const u8 PWMTimerIdx[MAX_PWM_CTRL_PIN]= {3,4,5,2};  // the G-timer ID used for PWM pin 0~3
+
+/**
+  * @brief  Initializes and enable a PWM control pin.
+  *
+  * @param  pwm_id: the PWM pin index
+  * @param  sel: pin mux selection
+  *
+  * @retval HAL_Status
+  */
+HAL_Status 
+HAL_Pwm_Init(
+    HAL_PWM_ADAPTER *pPwmAdapt,
+    u32 pwm_id,
+    u32 sel
+)
+{
+    u32 timer_id;
+
+    if (NULL == pPwmAdapt) {
+        DBG_PWM_ERR ("HAL_Pwm_Init: NULL adapter\n");
+        return HAL_ERR_PARA;
+    }
+
+    if ((pwm_id >= MAX_PWM_CTRL_PIN) || (sel > 3)) {
+        DBG_PWM_ERR ("HAL_Pwm_Init: Invalid PWM index(%d), sel(%d)\n", pwm_id, sel);
+        return HAL_ERR_PARA;
+    }
+    
+    pPwmAdapt->pwm_id = pwm_id;
+    pPwmAdapt->sel = sel;
+    timer_id = PWMTimerIdx[pwm_id];
+    pPwmAdapt->gtimer_id = timer_id;
+
+    if (_FALSE == FunctionChk((pPwmAdapt->pwm_id+PWM0), pPwmAdapt->sel)) {
+        return HAL_ERR_HW;
+    }
+
+#ifndef CONFIG_CHIP_E_CUT
+    return HAL_Pwm_Init_8195a(pPwmAdapt);
+#else
+    return HAL_Pwm_Init_8195a_V04(pPwmAdapt);
+#endif
+}
+
+
+/**
+  * @brief  Disable a PWM control pin.
+  *
+  * @param  pwm_id: the PWM pin index
+  *
+  * @retval None
+  */
+void 
+HAL_Pwm_Enable(
+    HAL_PWM_ADAPTER *pPwmAdapt
+)
+{
+    if (NULL == pPwmAdapt) {
+        DBG_PWM_ERR ("HAL_Pwm_Enable: NULL adapter\n");
+        return;
+    }
+    
+#ifndef CONFIG_CHIP_E_CUT
+    HAL_Pwm_Enable_8195a(pPwmAdapt);
+#else
+    HAL_Pwm_Enable_8195a_V04(pPwmAdapt);
+#endif
+}
+
+
+/**
+  * @brief  Disable a PWM control pin.
+  *
+  * @param  pwm_id: the PWM pin index
+  *
+  * @retval None
+  */
+void 
+HAL_Pwm_Disable(
+    HAL_PWM_ADAPTER *pPwmAdapt
+)
+{
+    if (NULL == pPwmAdapt) {
+        DBG_PWM_ERR ("HAL_Pwm_Disable: NULL adapter\n");
+        return;
+    }
+    
+#ifndef CONFIG_CHIP_E_CUT
+    HAL_Pwm_Disable_8195a(pPwmAdapt);
+#else
+    HAL_Pwm_Disable_8195a_V04(pPwmAdapt);
+#endif
+}
+
+/**
+  * @brief  Set the duty ratio of the PWM pin.
+  *
+  * @param  pwm_id: the PWM pin index
+  * @param  period: the period time, in micro-second.
+  * @param  pulse_width: the pulse width time, in micro-second.
+  *
+  * @retval None
+  */
+void
+HAL_Pwm_SetDuty(
+    HAL_PWM_ADAPTER *pPwmAdapt,
+    u32 period,
+    u32 pulse_width
+)
+{
+    if (NULL == pPwmAdapt) {
+        DBG_PWM_ERR ("HAL_Pwm_SetDuty: NULL adapter\n");
+        return;
+    }
+    
+#ifndef CONFIG_CHIP_E_CUT
+    HAL_Pwm_SetDuty_8195a(pPwmAdapt, period, pulse_width);
+#else
+    HAL_Pwm_SetDuty_8195a_V04(pPwmAdapt, period, pulse_width);
+#endif
+}
+
+
+#endif  // end of "#ifdef CONFIG_PWM_EN"

component/soc/realtek/8195a/fwlib/src/hal_ssi.c

@@ -0,0 +1,685 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#include "rtl8195a.h"
+#include "hal_ssi.h"
+
+const HAL_GDMA_CHNL Ssi2_TX_GDMA_Chnl_Option[] = { 
+    {0,4,GDMA0_CHANNEL4_IRQ,0},
+    {0,5,GDMA0_CHANNEL5_IRQ,0},
+    {0,3,GDMA0_CHANNEL3_IRQ,0},
+    {0,0,GDMA0_CHANNEL0_IRQ,0},
+    {0,1,GDMA0_CHANNEL1_IRQ,0},
+    {0,2,GDMA0_CHANNEL2_IRQ,0},
+    
+    {0xff,0,0,0}    // end
+};
+
+const HAL_GDMA_CHNL Ssi2_RX_GDMA_Chnl_Option[] = { 
+    {1,4,GDMA1_CHANNEL4_IRQ,0},
+    {1,5,GDMA1_CHANNEL5_IRQ,0},
+    {1,3,GDMA1_CHANNEL3_IRQ,0},
+    {1,0,GDMA1_CHANNEL0_IRQ,0},
+    {1,1,GDMA1_CHANNEL1_IRQ,0},
+    {1,2,GDMA1_CHANNEL2_IRQ,0},
+    
+    {0xff,0,0,0}    // end
+};
+
+const HAL_GDMA_CHNL Ssi_MultiBlk_GDMA_Chnl_Option[] = {
+    {0,4,GDMA0_CHANNEL4_IRQ,0},
+    {0,5,GDMA0_CHANNEL5_IRQ,0},
+    {1,4,GDMA1_CHANNEL4_IRQ,0},
+    {1,5,GDMA1_CHANNEL5_IRQ,0},
+    {0xff,0,0,0}    // end
+};
+
+//TODO: Load default Setting: It should be loaded from external setting file.
+const DW_SSI_DEFAULT_SETTING SpiDefaultSetting =
+{
+    .RxCompCallback    = NULL,
+    .RxCompCbPara      = NULL,
+    .RxData            = NULL,
+    .TxCompCallback    = NULL,
+    .TxCompCbPara      = NULL,
+    .TxData            = NULL,
+    .DmaRxDataLevel    =    7,  // RX FIFO stored bytes > (DMARDLR(7) + 1) then trigger DMA transfer
+    .DmaTxDataLevel    =   48,  // TX FIFO free space > (FIFO_SPACE(64)-DMATDLR(48)) then trigger DMA transfer
+    .InterruptPriority = 10,
+    .RxLength          =    0,
+    .RxLengthRemainder =    0,
+    .RxThresholdLevel  =    7,  // if number of entries in th RX FIFO >= (RxThresholdLevel+1), RX interrupt asserted
+    .TxLength          =    0,
+    .TxThresholdLevel  =    8,  // if number of entries in th TX FIFO <= TxThresholdLevel, TX interrupt asserted
+    .SlaveSelectEnable =    0,
+    .ClockDivider      = SSI_CLK_SPI0_2/1000000,    // SCLK=1M
+    .DataFrameNumber   =    0,
+    .ControlFrameSize  = CFS_1_BIT,
+    .DataFrameFormat   = FRF_MOTOROLA_SPI,
+    .DataFrameSize     = DFS_8_BITS,
+    .DmaControl        = 0, // default DMA is disable
+    .InterruptMask     =  0x0,
+    .MicrowireDirection    = MW_DIRECTION_MASTER_TO_SLAVE,
+    .MicrowireHandshaking  = MW_HANDSHAKE_DISABLE,
+    .MicrowireTransferMode = MW_TMOD_NONSEQUENTIAL,
+    .SclkPhase             = SCPH_TOGGLES_AT_START,
+    .SclkPolarity          = SCPOL_INACTIVE_IS_HIGH,
+    .SlaveOutputEnable     = SLV_TXD_ENABLE,  // Slave
+    .TransferMode          = TMOD_TR,
+    .TransferMechanism     = SSI_DTM_INTERRUPT
+};
+
+extern HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor);
+extern HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor);
+extern HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor);
+extern HAL_Status HalSsiDeInitRtl8195a(VOID * Adapter);
+extern HAL_Status HalSsiClockOffRtl8195a(VOID * Adapter);
+extern HAL_Status HalSsiClockOnRtl8195a(VOID * Adapter);
+extern HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length);
+extern HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
+extern HAL_Status HalSsiEnterCriticalRtl8195a(VOID * Data);
+extern HAL_Status HalSsiExitCriticalRtl8195a(VOID * Data);
+extern HAL_Status HalSsiIsTimeoutRtl8195a(u32 StartCount, u32 TimeoutCnt);
+extern HAL_Status HalSsiStopRecvRtl8195a(VOID * Data);
+extern HAL_Status HalSsiSetFormatRtl8195a(VOID * Adaptor);
+extern VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate);
+#ifdef CONFIG_GDMA_EN
+extern VOID HalSsiDmaInitRtl8195a(VOID *Adapter);
+#endif
+
+VOID HalSsiOpInit(VOID *Adaptor)
+{
+    PHAL_SSI_OP pHalSsiOp = (PHAL_SSI_OP) Adaptor;
+
+//    pHalSsiOp->HalSsiPinmuxEnable            = HalSsiPinmuxEnableRtl8195a;
+#if CONFIG_CHIP_E_CUT
+    pHalSsiOp->HalSsiPinmuxEnable            = HalSsiPinmuxEnableRtl8195a_V04;
+    pHalSsiOp->HalSsiPinmuxDisable           = HalSsiPinmuxDisableRtl8195a_V04;
+#else
+    pHalSsiOp->HalSsiPinmuxEnable            = HalSsiPinmuxEnableRtl8195a_Patch;
+    pHalSsiOp->HalSsiPinmuxDisable           = HalSsiPinmuxDisableRtl8195a;
+#endif
+
+    pHalSsiOp->HalSsiEnable                  = HalSsiEnableRtl8195a;
+    pHalSsiOp->HalSsiDisable                 = HalSsiDisableRtl8195a;
+//    pHalSsiOp->HalSsiInit                    = HalSsiInitRtl8195a;
+#if CONFIG_CHIP_E_CUT
+    pHalSsiOp->HalSsiInit                    = HalSsiInitRtl8195a_V04;
+#else
+    pHalSsiOp->HalSsiInit                    = HalSsiInitRtl8195a_Patch;
+#endif
+    pHalSsiOp->HalSsiSetSclkPolarity         = HalSsiSetSclkPolarityRtl8195a;
+    pHalSsiOp->HalSsiSetSclkPhase            = HalSsiSetSclkPhaseRtl8195a;
+    pHalSsiOp->HalSsiWrite                   = HalSsiWriteRtl8195a;
+    pHalSsiOp->HalSsiRead                    = HalSsiReadRtl8195a;
+    pHalSsiOp->HalSsiGetRxFifoLevel          = HalSsiGetRxFifoLevelRtl8195a;
+    pHalSsiOp->HalSsiGetTxFifoLevel          = HalSsiGetTxFifoLevelRtl8195a;
+    pHalSsiOp->HalSsiGetStatus               = HalSsiGetStatusRtl8195a;
+    pHalSsiOp->HalSsiGetInterruptStatus      = HalSsiGetInterruptStatusRtl8195a;
+    pHalSsiOp->HalSsiLoadSetting             = HalSsiLoadSettingRtl8195a;
+    pHalSsiOp->HalSsiSetInterruptMask        = HalSsiSetInterruptMaskRtl8195a;
+    pHalSsiOp->HalSsiGetInterruptMask        = HalSsiGetInterruptMaskRtl8195a;
+    pHalSsiOp->HalSsiSetDeviceRole           = HalSsiSetDeviceRoleRtl8195a;
+    pHalSsiOp->HalSsiWriteable               = HalSsiWriteableRtl8195a;
+    pHalSsiOp->HalSsiReadable                = HalSsiReadableRtl8195a;
+    pHalSsiOp->HalSsiBusy                    = HalSsiBusyRtl8195a;
+    pHalSsiOp->HalSsiInterruptEnable         = HalSsiInterruptEnableRtl8195a;
+    pHalSsiOp->HalSsiInterruptDisable        = HalSsiInterruptDisableRtl8195a;
+//    pHalSsiOp->HalSsiReadInterrupt           = HalSsiReadInterruptRtl8195a;
+#if CONFIG_CHIP_E_CUT
+    pHalSsiOp->HalSsiReadInterrupt           = HalSsiIntReadRtl8195a_V04;
+#else
+    pHalSsiOp->HalSsiReadInterrupt           = HalSsiIntReadRtl8195a;
+#endif
+    pHalSsiOp->HalSsiSetRxFifoThresholdLevel = HalSsiSetRxFifoThresholdLevelRtl8195a;
+    pHalSsiOp->HalSsiSetTxFifoThresholdLevel = HalSsiSetTxFifoThresholdLevelRtl8195a;
+//    pHalSsiOp->HalSsiWriteInterrupt          = HalSsiWriteInterruptRtl8195a;
+#if CONFIG_CHIP_E_CUT
+    pHalSsiOp->HalSsiWriteInterrupt          = HalSsiIntWriteRtl8195a_V04;
+#else
+    pHalSsiOp->HalSsiWriteInterrupt          = HalSsiIntWriteRtl8195a;
+#endif
+    pHalSsiOp->HalSsiGetRawInterruptStatus   = HalSsiGetRawInterruptStatusRtl8195a;
+    pHalSsiOp->HalSsiGetSlaveEnableRegister  = HalSsiGetSlaveEnableRegisterRtl8195a;
+    pHalSsiOp->HalSsiSetSlaveEnableRegister  = HalSsiSetSlaveEnableRegisterRtl8195a;
+}
+
+
+#ifdef CONFIG_GDMA_EN    
+HAL_Status
+HalSsiTxMultiBlkChnl(
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter
+)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PSSI_DMA_CONFIG pDmaConfig;    
+    HAL_GDMA_CHNL *pgdma_chnl;
+
+    pDmaConfig = &pHalSsiAdapter->DmaConfig;
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter;
+
+    if((pHalSsiAdapter->HaveTxChannel == 1) && (pHalGdmaAdapter->ChNum != 4) && (pHalGdmaAdapter->ChNum != 5)){
+        HalSsiTxGdmaDeInit(pHalSsiAdapter);
+    }
+    if(pHalSsiAdapter->HaveTxChannel == 0){
+        pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Ssi_MultiBlk_GDMA_Chnl_Option);
+        if (pgdma_chnl == NULL) {
+            DBG_SSI_ERR("No Available DMA channel\n");
+            return HAL_BUSY;
+        }
+        else {
+            pHalGdmaAdapter->GdmaIndex   = pgdma_chnl->GdmaIndx;
+            pHalGdmaAdapter->ChNum       = pgdma_chnl->GdmaChnl;
+            pHalGdmaAdapter->ChEn        = 0x0101 << pgdma_chnl->GdmaChnl;
+            pDmaConfig->TxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum;       
+            pHalSsiAdapter->HaveTxChannel = 1;
+            InterruptRegister(&pDmaConfig->TxGdmaIrqHandle);
+            InterruptEn(&pDmaConfig->TxGdmaIrqHandle);    
+        }
+        HalSsiDmaInit(pHalSsiAdapter);  
+    }
+    DBG_SSI_INFO("TX GDMA Index = %x, Channel = %x\n",pHalGdmaAdapter->GdmaIndex,pHalGdmaAdapter->ChNum);
+    return HAL_OK;
+}
+
+HAL_Status
+HalSsiTxSingleBlkChnl(
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter
+)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PSSI_DMA_CONFIG pDmaConfig;    
+    HAL_GDMA_CHNL *pgdma_chnl;
+
+    pDmaConfig = &pHalSsiAdapter->DmaConfig;
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter;
+
+    if(pHalSsiAdapter->HaveTxChannel == 0){
+        if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) {
+            // The default GDMA Channel is not available, try others
+            if (pHalSsiAdapter->Index == 2) {
+                // SSI2 TX Only can use GDMA 0
+                pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Ssi2_TX_GDMA_Chnl_Option);
+            }
+            else {
+                pgdma_chnl = HalGdmaChnlAlloc(NULL);
+            }
+
+            if (pgdma_chnl == NULL) {
+                DBG_SSI_ERR("No Available DMA channel\n");
+                return HAL_BUSY;
+            }
+            else {
+                pHalGdmaAdapter->GdmaIndex   = pgdma_chnl->GdmaIndx;
+                pHalGdmaAdapter->ChNum       = pgdma_chnl->GdmaChnl;
+                pHalGdmaAdapter->ChEn        = 0x0101 << pgdma_chnl->GdmaChnl;
+                pDmaConfig->TxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum;
+                pHalSsiAdapter->HaveTxChannel = 1;
+            }
+        }
+        else{
+            pHalSsiAdapter->HaveTxChannel = 1;
+        }
+        InterruptRegister(&pDmaConfig->TxGdmaIrqHandle);
+        InterruptEn(&pDmaConfig->TxGdmaIrqHandle);            
+        DBG_SSI_INFO("TX GDMA Index = %x, Channle number = %x\n",pHalGdmaAdapter->GdmaIndex,pHalGdmaAdapter->ChNum);
+        HalSsiDmaInit(pHalSsiAdapter);  
+    }
+    
+    return HAL_OK;
+
+}
+
+HAL_Status
+HalSsiTxGdmaInit(
+    IN PHAL_SSI_OP pHalSsiOp,
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter
+)
+{
+    
+    if ((NULL == pHalSsiOp) || (NULL == pHalSsiAdapter)) {
+        return HAL_ERR_PARA;
+    }
+
+    // Load default setting
+    #if CONFIG_CHIP_E_CUT
+    HalSsiTxGdmaLoadDefRtl8195a_V04((void*)pHalSsiAdapter);
+    #else
+    HalSsiTxGdmaLoadDefRtl8195a((void*)pHalSsiAdapter);
+    #endif
+    return HAL_OK;
+}
+
+VOID
+HalSsiTxGdmaDeInit(
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter
+)
+{
+    PSSI_DMA_CONFIG pDmaConfig;    
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    HAL_GDMA_CHNL GdmaChnl;
+    
+    if (NULL == pHalSsiAdapter) {
+        return;
+    }
+
+    pDmaConfig = &pHalSsiAdapter->DmaConfig;
+
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter;
+    GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
+    GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
+    GdmaChnl.IrqNum = pDmaConfig->TxGdmaIrqHandle.IrqNum;
+    HalGdmaChnlFree(&GdmaChnl);
+    pHalSsiAdapter->HaveTxChannel = 0;
+}
+
+
+HAL_Status
+HalSsiDmaSend(
+    IN VOID *Adapter,      // PHAL_SSI_ADAPTOR
+    IN u8  *pTxData,  ///< Rx buffer
+    IN u32 Length      // buffer length
+)
+{
+    PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Adapter;
+    PSSI_DMA_CONFIG pDmaConfig;
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PHAL_GDMA_OP pHalGdmaOp;
+    
+    pDmaConfig = &pHalSsiAdapter->DmaConfig;    
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter;
+
+    #if CONFIG_CHIP_E_CUT
+    HalSsiDmaSendRtl8195a_V04(pHalSsiAdapter,pTxData,Length);
+    #else
+    HalSsiDmaSendRtl8195a(pHalSsiAdapter,pTxData,Length);
+    #endif
+    if (pHalGdmaAdapter->GdmaCtl.BlockSize > MAX_DMA_BLOCK_SIZE) {
+        // Maximum Data Length is 4092*16
+        #if CONFIG_CHIP_E_CUT
+        HalSsiDmaSendMultiBlockRtl8195a_V04(pHalSsiAdapter, pTxData, pHalGdmaAdapter->GdmaCtl.BlockSize);
+        #else
+        HalSsiDmaSendMultiBlockRtl8195a(pHalSsiAdapter, pTxData, pHalGdmaAdapter->GdmaCtl.BlockSize);
+        #endif
+        HalSsiTxMultiBlkChnl(pHalSsiAdapter);
+    }
+    else{
+        pHalGdmaAdapter->ChSar= (u32)pTxData;
+        HalSsiTxSingleBlkChnl(pHalSsiAdapter);
+        pHalGdmaAdapter->Rsvd4to7 = 0;
+        pHalGdmaAdapter->Llpctrl = 0;
+        pHalGdmaAdapter->GdmaCtl.LlpSrcEn = 0;
+        pHalGdmaAdapter->GdmaCtl.LlpDstEn = 0;
+        pHalGdmaAdapter->GdmaCfg.ReloadDst = 0;
+        pHalGdmaAdapter->GdmaCfg.ReloadSrc = 0;        
+    }
+
+    // Enable GDMA for TX
+    pHalGdmaOp = (PHAL_GDMA_OP)pDmaConfig->pHalGdmaOp;
+    pHalGdmaOp->HalGdmaOnOff((VOID*)(pHalGdmaAdapter));
+    pHalGdmaOp->HalGdmaChIsrEnAndDis((VOID*)(pHalGdmaAdapter));
+
+    if(pHalGdmaAdapter->Llpctrl)
+        pHalGdmaOp->HalGdmaChBlockSeting((VOID*)(pHalGdmaAdapter));
+    else
+        pHalGdmaOp->HalGdmaChSeting((VOID*)(pHalGdmaAdapter));
+    pHalGdmaOp->HalGdmaChEn((VOID*)(pHalGdmaAdapter));
+
+    return HAL_OK;
+}
+
+
+HAL_Status
+HalSsiRxMultiBlkChnl(
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter
+)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PSSI_DMA_CONFIG pDmaConfig;    
+    HAL_GDMA_CHNL *pgdma_chnl;
+
+    pDmaConfig = &pHalSsiAdapter->DmaConfig;
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter;
+    
+    if((pHalSsiAdapter->HaveRxChannel == 1) && (pHalGdmaAdapter->ChNum != 4) && (pHalGdmaAdapter->ChNum != 5)){
+        HalSsiRxGdmaDeInit(pHalSsiAdapter);
+    }
+    if(pHalSsiAdapter->HaveRxChannel == 0){
+        pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Ssi_MultiBlk_GDMA_Chnl_Option);
+        if (pgdma_chnl == NULL) {
+            DBG_SSI_ERR("No Available DMA channel\n");
+            return HAL_BUSY;
+        }
+        else {
+            pHalGdmaAdapter->GdmaIndex   = pgdma_chnl->GdmaIndx;
+            pHalGdmaAdapter->ChNum       = pgdma_chnl->GdmaChnl;
+            pHalGdmaAdapter->ChEn        = 0x0101 << pgdma_chnl->GdmaChnl;
+            pDmaConfig->RxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum; 
+            pHalSsiAdapter->HaveRxChannel = 1;
+            InterruptRegister(&pDmaConfig->RxGdmaIrqHandle);
+            InterruptEn(&pDmaConfig->RxGdmaIrqHandle);
+        }
+        HalSsiDmaInit(pHalSsiAdapter);  
+    }
+    DBG_SSI_INFO("RX GDMA index = %x, Channel = %x\n",pHalGdmaAdapter->GdmaIndex,pHalGdmaAdapter->ChNum);
+    return HAL_OK;
+}
+
+HAL_Status
+HalSsiRxSingleBlkChnl(
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter
+)
+{
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PSSI_DMA_CONFIG pDmaConfig;    
+    HAL_GDMA_CHNL *pgdma_chnl;
+
+    pDmaConfig = &pHalSsiAdapter->DmaConfig;
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter;
+
+    if(pHalSsiAdapter->HaveRxChannel == 0){    
+        if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) {
+            // The default GDMA Channel is not available, try others
+            if (pHalSsiAdapter->Index == 2) {
+                // SSI2 RX Only can use GDMA 1
+                pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Ssi2_RX_GDMA_Chnl_Option);
+            }
+            else {
+                pgdma_chnl = HalGdmaChnlAlloc(NULL);
+            }
+
+            if (pgdma_chnl == NULL) {
+                DBG_SSI_ERR("No Available DMA channel\n");
+                return HAL_BUSY;
+            }
+            else {
+                pHalGdmaAdapter->GdmaIndex   = pgdma_chnl->GdmaIndx;
+                pHalGdmaAdapter->ChNum       = pgdma_chnl->GdmaChnl;
+                pHalGdmaAdapter->ChEn        = 0x0101 << pgdma_chnl->GdmaChnl;
+                pDmaConfig->RxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum; 
+                pHalSsiAdapter->HaveRxChannel = 1;
+            }
+        }
+        else{
+            pHalSsiAdapter->HaveRxChannel = 1;
+        }
+        InterruptRegister(&pDmaConfig->RxGdmaIrqHandle);
+        InterruptEn(&pDmaConfig->RxGdmaIrqHandle);
+        DBG_SSI_INFO("RX GDMA Index = %x, Channle number = %x\n",pHalGdmaAdapter->GdmaIndex,pHalGdmaAdapter->ChNum);
+        HalSsiDmaInit(pHalSsiAdapter);  
+    }   
+    return HAL_OK;
+
+}
+
+HAL_Status
+HalSsiRxGdmaInit(
+    IN PHAL_SSI_OP pHalSsiOp,
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter
+)
+{
+    
+    if ((NULL == pHalSsiOp) || (NULL == pHalSsiAdapter)) {
+        return HAL_ERR_PARA;
+    }
+
+    // Load default setting
+    #if CONFIG_CHIP_E_CUT
+    HalSsiRxGdmaLoadDefRtl8195a_V04((void*)pHalSsiAdapter);
+    #else
+    HalSsiRxGdmaLoadDefRtl8195a((void*)pHalSsiAdapter);
+    #endif
+    return HAL_OK;
+}
+
+VOID
+HalSsiRxGdmaDeInit(
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter
+)
+{
+    PSSI_DMA_CONFIG pDmaConfig;    
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    HAL_GDMA_CHNL GdmaChnl;
+    
+    if (NULL == pHalSsiAdapter) {
+        return;
+    }
+
+    pDmaConfig = &pHalSsiAdapter->DmaConfig;
+
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter;
+    GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
+    GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
+    GdmaChnl.IrqNum = pDmaConfig->RxGdmaIrqHandle.IrqNum;
+    HalGdmaChnlFree(&GdmaChnl);
+    pHalSsiAdapter->HaveRxChannel = 0;
+}
+
+HAL_Status
+HalSsiDmaRecv(
+    IN VOID *Adapter,      // PHAL_SSI_ADAPTOR
+    IN u8  *pRxData,  ///< Rx buffer
+    IN u32 Length      // buffer length
+)
+{
+    PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Adapter;
+    PSSI_DMA_CONFIG pDmaConfig;
+    PHAL_GDMA_ADAPTER pHalGdmaAdapter;
+    PHAL_GDMA_OP pHalGdmaOp;
+    
+    pDmaConfig = &pHalSsiAdapter->DmaConfig;    
+    pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter;
+
+    #if CONFIG_CHIP_E_CUT
+    HalSsiDmaRecvRtl8195a_V04(pHalSsiAdapter,pRxData,Length);
+    #else
+    HalSsiDmaRecvRtl8195a(pHalSsiAdapter,pRxData,Length);
+    #endif
+    
+    if (pHalGdmaAdapter->GdmaCtl.BlockSize > MAX_DMA_BLOCK_SIZE) {
+        // Maximum Data Length is 4092*16
+        #if CONFIG_CHIP_E_CUT
+        HalSsiDmaRecvMultiBlockRtl8195a_V04(pHalSsiAdapter, pRxData, pHalGdmaAdapter->GdmaCtl.BlockSize);
+        #else
+        HalSsiDmaRecvMultiBlockRtl8195a(pHalSsiAdapter, pRxData, pHalGdmaAdapter->GdmaCtl.BlockSize);
+        #endif
+        HalSsiRxMultiBlkChnl(pHalSsiAdapter);
+    }
+    else{
+        pHalGdmaAdapter->ChDar = (u32)pRxData;
+        HalSsiRxSingleBlkChnl(pHalSsiAdapter);
+        pHalGdmaAdapter->Rsvd4to7 = 0;
+        pHalGdmaAdapter->Llpctrl = 0;
+        pHalGdmaAdapter->GdmaCtl.LlpSrcEn = 0;
+        pHalGdmaAdapter->GdmaCtl.LlpDstEn = 0;
+        pHalGdmaAdapter->GdmaCfg.ReloadDst = 0;
+        pHalGdmaAdapter->GdmaCfg.ReloadSrc = 0;     
+
+    }
+
+    // Enable GDMA for RX
+    pHalGdmaOp = (PHAL_GDMA_OP)pDmaConfig->pHalGdmaOp;
+    pHalGdmaOp->HalGdmaOnOff((VOID*)(pHalGdmaAdapter));
+    pHalGdmaOp->HalGdmaChIsrEnAndDis((VOID*)(pHalGdmaAdapter));
+    
+    if(pHalGdmaAdapter->Llpctrl)
+        pHalGdmaOp->HalGdmaChBlockSeting((VOID*)(pHalGdmaAdapter));
+    else
+        pHalGdmaOp->HalGdmaChSeting((VOID*)(pHalGdmaAdapter));
+    pHalGdmaOp->HalGdmaChEn((VOID*)(pHalGdmaAdapter));
+    
+    return HAL_OK;
+
+}
+
+#endif  // end of "#ifdef CONFIG_GDMA_EN"
+
+HAL_Status
+HalSsiInit(VOID *Data)
+{
+    HAL_Status ret;
+    PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data;
+    u32 Function;
+    u8 PinmuxSelect;
+    u8 Index;
+
+    PinmuxSelect = pHalSsiAdapter->PinmuxSelect;
+    Index = pHalSsiAdapter->Index;
+    switch (Index){
+        case 0:
+            Function = SPI0;
+            break;
+        case 1:
+            Function = SPI1;
+            break;
+        case 2:
+            Function = SPI2;
+            break;
+        default:
+            DBG_SSI_ERR("Invalid SPI Index.\n");
+            break;
+    }
+
+    ret = FunctionChk(Function, (u32)PinmuxSelect);
+    if(ret == _FALSE){
+        DBG_SSI_ERR("Invalid Pinmux Setting.\n");
+        return HAL_ERR_PARA;
+    }
+
+#ifdef CONFIG_SOC_PS_MODULE
+        REG_POWER_STATE SsiPwrState;
+#endif
+#if CONFIG_CHIP_E_CUT
+    ret = HalSsiInitRtl8195a_V04(pHalSsiAdapter);    
+#else
+    ret = HalSsiInitRtl8195a_Patch(pHalSsiAdapter);
+#endif
+#ifdef CONFIG_SOC_PS_MODULE
+        if(ret == HAL_OK) {
+            // To register a new peripheral device power state
+            SsiPwrState.FuncIdx = SPI0+ pHalSsiAdapter->Index;
+            SsiPwrState.PwrState = ACT;
+            RegPowerState(SsiPwrState);
+        }
+#endif
+
+    return ret;   
+}
+
+HAL_Status
+HalSsiDeInit(VOID *Data)
+{
+    HAL_Status ret;
+    PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data;
+#ifdef CONFIG_SOC_PS_MODULE
+        REG_POWER_STATE SsiPwrState;
+        u8 HardwareState;
+
+        SsiPwrState.FuncIdx= SPI0+ pHalSsiAdapter->Index;
+        QueryRegPwrState(SsiPwrState.FuncIdx, &(SsiPwrState.PwrState), &HardwareState);
+
+        if(SsiPwrState.PwrState != HardwareState){
+            DBG_SSI_ERR("Registered State is not the Hardware State");
+            return HAL_ERR_UNKNOWN;
+        }
+        else{
+            if((SsiPwrState.PwrState != INACT) && (SsiPwrState.PwrState !=ACT)){
+                    DBG_SSI_INFO("Return to ACT state before DeInit");
+                    HalSsiEnable(pHalSsiAdapter);
+                    QueryRegPwrState(SsiPwrState.FuncIdx, &(SsiPwrState.PwrState), &HardwareState);
+            }
+            if(SsiPwrState.PwrState == ACT){
+                SsiPwrState.PwrState = INACT;
+                RegPowerState(SsiPwrState);
+            }          
+        }
+#endif
+#if CONFIG_CHIP_E_CUT
+    ret = HalSsiDeInitRtl8195a_V04(pHalSsiAdapter);
+#else
+    ret = HalSsiDeInitRtl8195a(pHalSsiAdapter);
+#endif
+    return ret;
+}
+
+
+HAL_Status
+HalSsiEnable(VOID *Data)
+{
+    HAL_Status ret;
+    PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data;
+#ifdef CONFIG_SOC_PS_MODULE
+        REG_POWER_STATE SsiPwrState;
+#endif
+#if CONFIG_CHIP_E_CUT
+    ret = HalSsiClockOnRtl8195a_V04(pHalSsiAdapter);
+#else
+    ret = HalSsiClockOnRtl8195a(pHalSsiAdapter);
+#endif
+#ifdef CONFIG_SOC_PS_MODULE
+        if(ret == HAL_OK) {
+            // To register a new peripheral device power state
+            SsiPwrState.FuncIdx = SPI0+ pHalSsiAdapter->Index;
+            SsiPwrState.PwrState = ACT;
+            RegPowerState(SsiPwrState);
+        }
+#endif
+
+    return ret;   
+}
+
+HAL_Status
+HalSsiDisable(VOID *Data)
+{
+    HAL_Status ret;
+    PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data;
+#ifdef CONFIG_SOC_PS_MODULE
+        REG_POWER_STATE SsiPwrState;
+#endif
+#if CONFIG_CHIP_E_CUT
+    ret = HalSsiClockOffRtl8195a_V04(pHalSsiAdapter);
+#else
+    ret = HalSsiClockOffRtl8195a(pHalSsiAdapter);
+#endif
+#ifdef CONFIG_SOC_PS_MODULE
+        if(ret == HAL_OK) {
+            // To register a new peripheral device power state
+            SsiPwrState.FuncIdx = SPI0+ pHalSsiAdapter->Index;
+            SsiPwrState.PwrState = SLPCG;
+            RegPowerState(SsiPwrState);
+        }
+#endif
+
+    return ret;   
+}
+
+HAL_Status HalSsiEnterCritical(VOID *Data)
+{
+    return HalSsiEnterCriticalRtl8195a(Data);
+}
+
+HAL_Status HalSsiExitCritical(VOID *Data)
+{
+    return HalSsiExitCriticalRtl8195a(Data);
+}
+
+HAL_Status HalSsiTimeout(u32 StartCount, u32 TimeoutCnt)
+{
+    return HalSsiIsTimeoutRtl8195a(StartCount,TimeoutCnt);
+}
+
+HAL_Status HalSsiStopRecv(VOID * Data)
+{
+    return HalSsiStopRecvRtl8195a(Data);
+}
+
+HAL_Status HalSsiSetFormat(VOID * Data)
+{
+    return HalSsiSetFormatRtl8195a(Data);
+}

component/soc/realtek/8195a/fwlib/src/hal_timer.c

@@ -0,0 +1,36 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#include "rtl8195a.h"
+
+VOID 
+HalTimerOpInit_Patch(
+    IN  VOID *Data
+)
+{
+    PHAL_TIMER_OP pHalTimerOp = (PHAL_TIMER_OP) Data;
+
+    pHalTimerOp->HalGetTimerId = HalGetTimerIdRtl8195a;    
+#ifdef CONFIG_CHIP_E_CUT
+    pHalTimerOp->HalTimerInit = (BOOL (*)(void*))HalTimerInitRtl8195a_V04;   
+#else
+    pHalTimerOp->HalTimerInit = (BOOL (*)(void*))HalTimerInitRtl8195a_Patch;   
+#endif
+#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
+    pHalTimerOp->HalTimerReadCount = HalTimerReadCountRtl8195aV02;    
+#else
+    pHalTimerOp->HalTimerReadCount = HalTimerReadCountRtl8195a_Patch;    
+#endif
+    pHalTimerOp->HalTimerIrqClear = HalTimerIrqClearRtl8195a;
+    pHalTimerOp->HalTimerDis = HalTimerDisRtl8195a_Patch;
+    pHalTimerOp->HalTimerEn = HalTimerEnRtl8195a_Patch;
+    pHalTimerOp->HalTimerDumpReg = HalTimerDumpRegRtl8195a;
+}
+