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622
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h
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622
component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef _RTL8195A_UART_H_
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#define _RTL8195A_UART_H_
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#define MAX_UART_INDEX 2
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#define RUART_DLL_OFF 0x00
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#define RUART_DLM_OFF 0x04 //RW, DLAB = 1
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#define RUART_INTERRUPT_EN_REG_OFF 0x04
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#define RUART_IER_ERBI 0x01 //BIT0, Enable Received Data Available Interrupt (rx trigger)
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#define RUART_IER_ETBEI (1<<1) //BIT1, Enable Transmitter FIFO Empty Interrupt (tx fifo empty)
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#define RUART_IER_ELSI (1<<2) //BIT2, Enable Receiver Line Status Interrupt (receiver line status)
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#define RUART_IER_EDSSI (1<<3) //BIT3, Enable Modem Status Interrupt (modem status transition)
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#define RUART_INT_ID_REG_OFF 0x08 //[R]
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#define RUART_IIR_INT_PEND 0x01
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#define RUART_IIR_INT_ID (0x07<<1) //011(3), 010(2), 110(6), 001(1), 000(0)
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#define RUART_FIFO_CTL_REG_OFF 0x08 //[W]
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#define RUART_FIFO_CTL_REG_FIFO_ENABLE 0x01 //BIT0
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#define RUART_FIFO_CTL_REG_CLEAR_RXFIFO (1<<1) //BIT1, 0x02, Write 1 clear
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#define RUART_FIFO_CTL_REG_CLEAR_TXFIFO (1<<2) //BIT2, 0x04, Write 1 clear
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#define RUART_FIFO_CTL_REG_DMA_ENABLE 0x08 //BIT3
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#define FIFO_CTL_DEFAULT_WITH_FIFO_DMA 0xC9
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#define FIFO_CTL_DEFAULT_WITH_FIFO 0xC1
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#define RUART_MODEM_CTL_REG_OFF 0x10
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#define RUART_MCR_RTS BIT1
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#define RUART_MCL_AUTOFLOW_ENABLE (1<<5) //BIT5, 0x20
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#define RUART_LINE_CTL_REG_OFF 0x0C
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#define RUART_LINE_CTL_REG_DLAB_ENABLE (1<<7) //BIT7, 0x80
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#define RUART_LINE_STATUS_REG_OFF 0x14
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#define RUART_LINE_STATUS_REG_DR 0x01 //BIT0, Data Ready indicator
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#define RUART_LINE_STATUS_ERR_OVERRUN (1<<1) //BIT1, Over Run
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#define RUART_LINE_STATUS_ERR_PARITY (1<<2) //BIT2, Parity error
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#define RUART_LINE_STATUS_ERR_FRAMING (1<<3) //BIT3, Framing error
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#define RUART_LINE_STATUS_ERR_BREAK (1<<4) //BIT4, Break interrupt error
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#define RUART_LINE_STATUS_REG_THRE (1<<5) //BIT5, 0x20, Transmit Holding Register Empty Interrupt enable
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#define RUART_LINE_STATUS_REG_TEMT (1<<6) //BIT6, 0x40, Transmitter Empty indicator(bit)
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#define RUART_LINE_STATUS_ERR_RXFIFO (1<<7) //BIT7, RX FIFO error
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#define RUART_LINE_STATUS_ERR (RUART_LINE_STATUS_ERR_OVERRUN|RUART_LINE_STATUS_ERR_PARITY| \
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RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \
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RUART_LINE_STATUS_ERR_RXFIFO) //Line status error
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#define RUART_MODEM_STATUS_REG_OFF 0x18 //Modem Status Register
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#define RUART_SCRATCH_PAD_REG_OFF 0x1C //Scratch Pad Register
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#define RUART_SP_REG_RXBREAK_INT_STATUS (1<<7) //BIT7, 0x80, Write 1 clear
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#define RUART_SP_REG_DBG_SEL (0x0F<<8) //[11:8], Debug port selection
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#define RUART_SP_REG_XFACTOR_ADJ (0x7FF<<16) //[26:16]
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#define RUART_STS_REG_OFF 0x20
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#define RUART_STS_REG_RESET_RCV (1<<3) //BIT3, 0x08, Reset Uart Receiver
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#define RUART_STS_REG_XFACTOR 0xF<<4
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#define RUART_REV_BUF_REG_OFF 0x24 //Receiver Buffer Register
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#define RUART_TRAN_HOLD_REG_OFF 0x24 //Transmitter Holding Register
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#define RUART_MISC_CTL_REG_OFF 0x28
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#define RUART_TXDMA_BURSTSIZE_MASK 0xF8 //7:3
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#define RUART_RXDMA_BURSTSIZE_MASK 0x1F00 //12:8
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#define RUART_DEBUG_REG_OFF 0x3C
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// RUART_LINE_CTL_REG_OFF (0x0C)
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#define BIT_SHIFT_LCR_WLS 0 // word length select: 0: 7 bits, 1: 8bits
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#define BIT_MASK_LCR_WLS_8BITS 0x1
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#define BIT_LCR_WLS(x)(((x) & BIT_MASK_LCR_WLS_8BITS) << BIT_SHIFT_LCR_WLS)
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#define BIT_CLR_LCR_WLS (~(BIT_MASK_LCR_WLS_8BITS << BIT_SHIFT_LCR_WLS))
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#define BIT_SHIFT_LCR_STB 2 // Stop bit select: 0: no stop bit, 1: 1 stop bit
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#define BIT_MASK_LCR_STB_EN 0x1
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#define BIT_LCR_STB_EN(x)(((x) & BIT_MASK_LCR_STB_EN) << BIT_SHIFT_LCR_STB)
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#define BIT_INVC_LCR_STB_EN (~(BIT_MASK_LCR_STB_EN << BIT_SHIFT_LCR_STB))
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#define BIT_SHIFT_LCR_PARITY_EN 3
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#define BIT_MASK_LCR_PARITY_EN 0x1
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#define BIT_LCR_PARITY_EN(x)(((x) & BIT_MASK_LCR_PARITY_EN) << BIT_SHIFT_LCR_PARITY_EN)
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#define BIT_INVC_LCR_PARITY_EN (~(BIT_MASK_LCR_PARITY_EN << BIT_SHIFT_LCR_PARITY_EN))
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#define BIT_SHIFT_LCR_PARITY_TYPE 4
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#define BIT_MASK_LCR_PARITY_TYPE 0x1
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#define BIT_LCR_PARITY_TYPE(x)(((x) & BIT_MASK_LCR_PARITY_TYPE) << BIT_SHIFT_LCR_PARITY_TYPE)
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#define BIT_INVC_LCR_PARITY_TYPE (~(BIT_MASK_LCR_PARITY_TYPE << BIT_SHIFT_LCR_PARITY_TYPE))
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#define BIT_SHIFT_LCR_STICK_PARITY_EN 5
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#define BIT_MASK_LCR_STICK_PARITY_EN 0x1
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#define BIT_LCR_STICK_PARITY_EN(x)(((x) & BIT_MASK_LCR_STICK_PARITY_EN) << BIT_SHIFT_LCR_STICK_PARITY_EN)
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#define BIT_INVC_LCR_STICK_PARITY_EN (~(BIT_MASK_LCR_STICK_PARITY_EN << BIT_SHIFT_LCR_STICK_PARITY_EN))
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#define BIT_SHIFT_LCR_BREAK_CTRL 6
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#define BIT_MASK_LCR_BREAK_CTRL 0x1
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#define BIT_UART_LCR_BREAK_CTRL ((BIT_MASK_LCR_BREAK_CTRL) << BIT_SHIFT_LCR_BREAK_CTRL)
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#define RUART_BAUD_RATE_2400 2400
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#define RUART_BAUD_RATE_4800 4800
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#define RUART_BAUD_RATE_9600 9600
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#define RUART_BAUD_RATE_19200 19200
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#define RUART_BAUD_RATE_38400 38400
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#define RUART_BAUD_RATE_57600 57600
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#define RUART_BAUD_RATE_115200 115200
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#define RUART_BAUD_RATE_921600 921600
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#define RUART_BAUD_RATE_1152000 1152000
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#define HAL_RUART_READ32(UartIndex, addr) \
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HAL_READ32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
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#define HAL_RUART_WRITE32(UartIndex, addr, value) \
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HAL_WRITE32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
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#define HAL_RUART_READ16(UartIndex, addr) \
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HAL_READ16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
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#define HAL_RUART_WRITE16(UartIndex, addr, value) \
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HAL_WRITE16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
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#define HAL_RUART_READ8(UartIndex, addr) \
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HAL_READ8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
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#define HAL_RUART_WRITE8(UartIndex, addr, value) \
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HAL_WRITE8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
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#define UART_OVSR_POOL_MIN 1000
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#define UART_OVSR_POOL_MAX 2090
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#define DIVISOR_RESOLUTION 10
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#define JITTER_LIMIT 100
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#define UART_SCLK (200000000*5/12)
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typedef struct _RUART_SPEED_SETTING_ {
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u32 BaudRate;
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u32 Ovsr;
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u32 Div;
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u32 Ovsr_adj;
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#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
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u8 Ovsr_adj_max_bits; // 9: No parity, 10: with Parity
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u8 Ovsr_adj_bits;
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u16 *Ovsr_adj_map;
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u32 max_err; // 10 ~ 100: 30
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u32 Ovsr_min; // 10 ~ 20: 1000
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u32 Ovsr_max; // 10 ~ 20: 2000
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u32 divisor_resolution; // 1 ~ 20: 10
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u32 jitter_lim; // 50 ~ 100: 100
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u32 sclk; // 83.33333 MHz
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#endif
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}RUART_SPEED_SETTING, *PRUART_SPEED_SETTING;
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typedef enum _UART_RXFIFO_TRIGGER_LEVEL_ {
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OneByte = 0x00,
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FourBytes = 0x01,
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EightBytes = 0x10,
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FourteenBytes = 0x11
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}UART_RXFIFO_TRIGGER_LEVEL, *PUART_RXFIFO_TRIGGER_LEVEL;
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typedef enum _RUART0_PINMUX_SELECT_ {
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RUART0_MUX_TO_GPIOC = S0,
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RUART0_MUX_TO_GPIOE = S1,
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RUART0_MUX_TO_GPIOA = S2
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}RUART0_PINMUX_SELECT, *PRUART0_PINMUX_SELECT;
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typedef enum _RUART1_PINMUX_SELECT_ {
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RUART1_MUX_TO_GPIOD = S0,
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RUART1_MUX_TO_GPIOE = S1,
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RUART1_MUX_TO_GPIOB = S2
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}RUART1_PINMUX_SELECT, *PRUART1_PINMUX_SELECT;
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typedef enum _RUART2_PINMUX_SELECT_ {
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RUART2_MUX_TO_GPIOA = S0,
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RUART2_MUX_TO_GPIOC = S1,
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RUART2_MUX_TO_GPIOD = S2
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}RUART2_PINMUX_SELECT, *PRUART2_PINMUX_SELECT;
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typedef enum _RUART_FLOW_CONTROL_ {
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AUTOFLOW_DISABLE = 0,
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AUTOFLOW_ENABLE = 1
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}RUART_FLOW_CONTROL, *PRUART_FLOW_CONTROL;
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typedef enum _RUART_WORD_LEN_SEL_ {
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RUART_WLS_7BITS = 0,
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RUART_WLS_8BITS = 1
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}RUART_WORD_LEN_SEL, *PRUART_WORD_LEN_SEL;
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typedef enum _RUART_STOP_BITS_ {
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RUART_STOP_BIT_1 = 0,
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RUART_STOP_BIT_2 = 1
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}RUART_STOP_BITS, *PRUART_STOP_BITS;
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typedef enum _RUART_PARITY_CONTROL_ {
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RUART_PARITY_DISABLE = 0,
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RUART_PARITY_ENABLE = 1
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}RUART_PARITY_CONTROL, *PRUART_PARITY_CONTROL;
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typedef enum _RUART_PARITY_TYPE_ {
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RUART_ODD_PARITY = 0,
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RUART_EVEN_PARITY = 1
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}RUART_PARITY_TYPE, *PRUART_PARITY_TYPE;
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typedef enum _RUART_STICK_PARITY_CONTROL_ {
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RUART_STICK_PARITY_DISABLE = 0,
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RUART_STICK_PARITY_ENABLE = 1
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}RUART_STICK_PARITY_CONTROL, *PRUART_STICK_PARITY_CONTROL;
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typedef enum _UART_INT_ID_ {
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ModemStatus = 0,
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TxFifoEmpty = 1,
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ReceiverDataAvailable = 2,
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ReceivLineStatus = 3,
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TimeoutIndication = 6
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}UART_INT_ID, *PUART_INT_ID;
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typedef enum _HAL_UART_State_
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{
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HAL_UART_STATE_NULL = 0x00, // UART hardware not been initial yet
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HAL_UART_STATE_READY = 0x10, // UART is initialed, ready to use
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HAL_UART_STATE_BUSY = 0x20, // UART hardware is busy on configuration
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HAL_UART_STATE_BUSY_TX = 0x21, // UART is buzy on TX
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HAL_UART_STATE_BUSY_RX = 0x22, // UART is busy on RX
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HAL_UART_STATE_BUSY_TX_RX = 0x23, // UART is busy on TX an RX
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HAL_UART_STATE_TIMEOUT = 0x30, // Transfer timeout
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HAL_UART_STATE_ERROR = 0x40 // UART Error
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}HAL_UART_State, *PHAL_UART_State;
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typedef enum _HAL_UART_Status_
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{
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HAL_UART_STATUS_OK = 0x00, // Transfer OK
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HAL_UART_STATUS_TIMEOUT = 0x01, // Transfer Timeout
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HAL_UART_STATUS_ERR_OVERRUN = 0x02, // RX Over run
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HAL_UART_STATUS_ERR_PARITY = 0x04, // Parity error
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HAL_UART_STATUS_ERR_FRAM = 0x08, // Framing Error
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HAL_UART_STATUS_ERR_BREAK = 0x10, // Break Interrupt
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HAL_UART_STATUS_ERR_PARA = 0x20, // Parameter error
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HAL_UART_STATUS_ERR_RXFIFO = 0x80, // RX FIFO error
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}HAL_UART_Status, *PHAL_UART_Status;
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u32
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HalRuartGetDebugValueRtl8195a(
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IN VOID* Data,
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IN u32 DbgSel
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);
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#if 0
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u32
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FindElementIndex(
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u32 Element,
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u32* Array
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);
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#endif
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VOID
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RuartResetRxFifoRtl8195a(
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IN u8 UartIndex
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);
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#if 0
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VOID
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RuartBusDomainEnableRtl8195a(
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IN u8 UartIndex
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);
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#endif
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HAL_Status
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HalRuartResetRxFifoRtl8195a(
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IN VOID *Data
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);
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HAL_Status
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HalRuartInitRtl8195a(
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IN VOID *Data
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);
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VOID
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HalRuartDeInitRtl8195a(
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IN VOID *Data ///< RUART Adapter
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);
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HAL_Status
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HalRuartPutCRtl8195a(
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IN VOID *Data,
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IN u8 TxData
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);
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u32
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HalRuartSendRtl8195a(
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IN VOID *Data,
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IN u8 *pTxData,
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IN u32 Length,
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IN u32 Timeout
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);
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HAL_Status
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HalRuartIntSendRtl8195a(
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IN VOID *Data, // PHAL_RUART_ADAPTER
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IN u8 *pTxData, // the Buffer to be send
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IN u32 Length // the length of data to be send
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);
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HAL_Status
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HalRuartDmaSendRtl8195a(
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IN VOID *Data, // PHAL_RUART_ADAPTER
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IN u8 *pTxData, // the Buffer to be send
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IN u32 Length // the length of data to be send
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);
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HAL_Status
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HalRuartStopSendRtl8195a(
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IN VOID *Data // PHAL_RUART_ADAPTER
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);
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HAL_Status
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HalRuartGetCRtl8195a(
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IN VOID *Data,
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OUT u8 *pRxByte
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);
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u32
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HalRuartRecvRtl8195a(
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IN VOID *Data,
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IN u8 *pRxData,
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IN u32 Length,
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IN u32 Timeout
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);
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HAL_Status
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HalRuartIntRecvRtl8195a(
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IN VOID *Data, ///< RUART Adapter
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IN u8 *pRxData, ///< Rx buffer
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IN u32 Length // buffer length
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);
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HAL_Status
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HalRuartDmaRecvRtl8195a(
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IN VOID *Data, ///< RUART Adapter
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IN u8 *pRxData, ///< Rx buffer
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IN u32 Length // buffer length
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||||
);
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HAL_Status
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HalRuartStopRecvRtl8195a(
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IN VOID *Data // PHAL_RUART_ADAPTER
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);
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u8
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HalRuartGetIMRRtl8195a(
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IN VOID *Data
|
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);
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_LONG_CALL_ROM_ VOID
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HalRuartSetIMRRtl8195a(
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IN VOID *Data
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);
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VOID
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HalRuartDmaInitRtl8195a(
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IN VOID *Data
|
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);
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VOID
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||||
HalRuartRTSCtrlRtl8195a(
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IN VOID *Data,
|
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IN BOOLEAN RtsCtrl
|
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);
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VOID
|
||||
HalRuartRegIrqRtl8195a(
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IN VOID *Data
|
||||
);
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VOID
|
||||
HalRuartIntEnableRtl8195a(
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IN VOID *Data
|
||||
);
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||||
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||||
VOID
|
||||
HalRuartIntDisableRtl8195a(
|
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IN VOID *Data
|
||||
);
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||||
|
||||
VOID
|
||||
HalRuartAdapterLoadDefRtl8195a(
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IN VOID *pAdp,
|
||||
IN u8 UartIdx
|
||||
);
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||||
|
||||
VOID
|
||||
HalRuartTxGdmaLoadDefRtl8195a(
|
||||
IN VOID *pAdp,
|
||||
IN VOID *pCfg
|
||||
);
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||||
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||||
VOID
|
||||
HalRuartRxGdmaLoadDefRtl8195a(
|
||||
IN VOID *pAdp,
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||||
IN VOID *pCfg
|
||||
);
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||||
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||||
_LONG_CALL_ HAL_Status HalRuartIntSendRtl8195aV02(
|
||||
IN VOID *Data, // PHAL_RUART_ADAPTER
|
||||
IN u8 *pTxData, // the Buffer to be send
|
||||
IN u32 Length // the length of data to be send
|
||||
);
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||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartIntRecvRtl8195aV02(
|
||||
IN VOID *Data, ///< RUART Adapter
|
||||
IN u8 *pRxData, ///< Rx buffer
|
||||
IN u32 Length // buffer length
|
||||
);
|
||||
|
||||
_LONG_CALL_ s32
|
||||
FindElementIndex_v02(
|
||||
u32 Element, ///< RUART Baudrate
|
||||
u32* Array, ///< Pre-defined Baudrate Array
|
||||
u32 ElementNo
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status HalRuartInitRtl8195a_v02(IN VOID *Data);
|
||||
|
||||
// New added function 2015/04/20
|
||||
HAL_Status
|
||||
HalRuartResetTxFifoRtl8195a(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartResetRxFifoRtl8195a_Patch(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartResetTRxFifoRtl8195a(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartSetBaudRateRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartEnableRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartDisableRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartFlowCtrlRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
u32
|
||||
_UartTxDmaIrqHandle_Patch(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
u32
|
||||
_UartRxDmaIrqHandle_Patch(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartDmaSendRtl8195a_Patch(
|
||||
IN VOID *Data,
|
||||
IN u8 *pTxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartDmaRecvRtl8195a_Patch(
|
||||
IN VOID *Data,
|
||||
IN u8 *pRxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartMultiBlkDmaSendRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 *pTxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartMultiBlkDmaRecvRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 *pRxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
RuartIsTimeout (
|
||||
u32 StartCount,
|
||||
u32 TimeoutCnt
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartStopRecvRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartStopSendRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalRuartEnterCriticalRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalRuartExitCriticalRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
#if CONFIG_CHIP_E_CUT
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartResetTxFifoRtl8195a_V04(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartResetRxFifoRtl8195a_V04(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartResetTRxFifoRtl8195a_V04(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartSetBaudRateRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartInitRtl8195a_V04(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartEnableRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartDisableRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartFlowCtrlRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ u32
|
||||
_UartTxDmaIrqHandle_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ u32
|
||||
_UartRxDmaIrqHandle_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartDmaSendRtl8195a_V04(
|
||||
IN VOID *Data,
|
||||
IN u8 *pTxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartDmaRecvRtl8195a_V04(
|
||||
IN VOID *Data,
|
||||
IN u8 *pRxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartMultiBlkDmaSendRtl8195a_V04(
|
||||
IN VOID *Data,
|
||||
IN u8 *pTxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartMultiBlkDmaRecvRtl8195a_V04(
|
||||
IN VOID *Data,
|
||||
IN u8 *pRxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartStopRecvRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartStopSendRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ VOID
|
||||
HalRuartEnterCriticalRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ VOID
|
||||
HalRuartExitCriticalRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
#endif // #if CONFIG_CHIP_E_CUT
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue