rtl8710 testing

.gitignore

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+blink.bin
+blink.elf

Makefile

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+FILENAME_PREFIX = blink
+ADDRESS = 0x10000bc8
+
+CC_PARAMS = -Wall -g -Os -mlittle-endian -mlong-calls -mthumb -mcpu=cortex-m3 -mfloat-abi=soft -mthumb-interwork -ffunction-sections -ffreestanding -fsingle-precision-constant -Ddouble=float -Wstrict-aliasing=0 -Wl,-T,rtl8710.ld -nostartfiles -nostdlib -u cortex_vectors -Wl,--gc-sections
+
+BASE_PARAMS = -DCORTEX_INTERRUPT_MAX=2 -Icortex cortex/cortex.c -Wl,--section-start=.text=$(ADDRESS)
+
+FIRMWARE_PARAMS = main.c
+
+CC = arm-none-eabi-gcc
+
+all: firmware
+
+firmware:
+	$(CC) $(CC_PARAMS) $(BASE_PARAMS) $(FIRMWARE_PARAMS) -lgcc -o $(FILENAME_PREFIX).elf
+	arm-none-eabi-strip $(FILENAME_PREFIX).elf
+	arm-none-eabi-objcopy -O binary $(FILENAME_PREFIX).elf $(FILENAME_PREFIX).bin
+	chmod 755 $(FILENAME_PREFIX).bin
+
+size:
+	arm-none-eabi-size -A -x $(FILENAME_PREFIX).elf
+
+clean:
+	rm -rf $(FILENAME_PREFIX).bin $(FILENAME_PREFIX).elf
+
+install:
+	openocd -f interface/stlink-v2-1.cfg -f rtl8710.ocd -c "init" -c "reset halt" -c "load_image $(FILENAME_PREFIX).bin $(ADDRESS) bin" -c "cortex_start $(ADDRESS)"
+
+reset:
+	openocd -f interface/stlink-v2-1.cfg -f rtl8710.ocd -c "init" -c "reset halt" -c "reset run"
+

README.md

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+RTL-00 blink test using openocd and stm32f3348-discovery
+
+pins:
+
+LED:   GC4
+SWDIO: GE3
+SWCLK: GE4
+
+building:
+
+make
+
+testing:
+
+make install
+

cortex/cortex.h

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+#ifndef _CORTEX_H_
+#define _CORTEX_H_
+
+#include <stdint.h>
+
+typedef struct{
+	volatile uint32_t ISER[8];
+	uint32_t RESERVED1[24];
+	volatile uint32_t ICER[8];
+	uint32_t RESERVED2[24];
+	volatile uint32_t ISPR[8];
+	uint32_t RESERVED3[24];
+	volatile uint32_t ICPR[8];
+	uint32_t RESERVED4[24];
+	volatile uint32_t IABR[8];
+	uint32_t RESERVED5[56];
+	volatile uint32_t IPR[32];
+}NVIC_TypeDef;
+
+typedef struct{
+	uint32_t RESERVED1[2];
+	volatile uint32_t ACTLR;
+	uint32_t RESERVED2[829];
+	volatile const uint32_t CPUID;
+	volatile uint32_t ICSR;
+	volatile uint32_t VTOR;
+	volatile uint32_t AIRCR;
+	volatile uint32_t SCR;
+	volatile uint32_t CCR;
+	volatile uint32_t SHPR[3];
+	volatile uint32_t SHCSR;
+	volatile uint32_t CFSR;
+	volatile uint32_t HFSR;
+	volatile uint32_t DFSR;
+	volatile uint32_t MMFAR;
+	volatile uint32_t BFAR;
+	volatile uint32_t AFSR;
+	volatile const uint32_t PFR[2];
+	volatile const uint32_t DFR;
+	volatile const uint32_t AFR;
+	volatile const uint32_t MMFR[4];
+	volatile const uint32_t ISAR[5];
+	uint32_t RESERVED3[5];
+	volatile uint32_t CPACR;
+}SCB_TypeDef;
+
+#define NVIC                                ((NVIC_TypeDef *)0xE000E100)
+#define SCB                                 ((SCB_TypeDef *)0xE000E000)
+
+// SCB_AIRCR
+#define SCB_AIRCR_VECTRESET                 (((uint32_t)0x0001) << 0)
+#define SCB_AIRCR_VECTCLRACTIVE             (((uint32_t)0x0001) << 1)
+#define SCB_AIRCR_SYSRESETREQ               (((uint32_t)0x0001) << 2)
+#define SCB_AIRCR_PRIGROUP                  (((uint32_t)0x0007) << 8)
+#define SCB_AIRCR_VECTKEY                   (((uint32_t)0xFFFF) << 16)
+#define SCB_AIRCR_VECTKEYSTAT               (((uint32_t)0xFFFF) << 16)
+
+// SCB_CPACR
+#define SCB_CPACR_CP10                      (((uint32_t)0x03) << 20)
+#define SCB_CPACR_CP11                      (((uint32_t)0x03) << 22)
+
+#define cortex_interrupt_set_priority(i, p) (NVIC->IPR[(i) >> 2] = ((NVIC->IPR[(i) >> 2] & ~(((uint32_t)0xFF) << (((i) & 0x03) << 3))) | (((uint32_t)p) << (((i) & 0x03) << 3))))
+#define cortex_interrupt_enable(i)          (NVIC->ISER[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F)))
+#define cortex_interrupt_disable(i)         (NVIC->ICER[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F)))
+#define cortex_interrupt_clear(i)           (NVIC->ICPR[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F)))
+#define cortex_interrupts_disable()         __asm__("cpsid f")
+#define cortex_interrupts_enable()          __asm__("cpsie f")
+
+#define interrupts_disable()                __asm__("cpsid f")
+#define interrupts_enable()                 __asm__("cpsie f")
+
+#define CORTEX_ISR(n)                       _CORTEX_ISR(n)
+#define _CORTEX_ISR(n)                      void __attribute__((interrupt)) CORTEX_INTERRUPT_##n##_Handler()
+
+void cortex_bootstrap(void *start) __attribute__ ((noreturn));
+void cortex_reboot() __attribute__ ((noreturn));
+
+#endif
+

main.c

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+#include <stdint.h>
+
+void delay(uint32_t delay){
+	volatile uint32_t i;
+	for(i = 0; i < delay; i++)__asm__("nop");
+}
+
+int main(){
+	*(volatile uint32_t *)0x4000021C |= (((uint32_t)1) << 8); // REG_SOC_PERI_FUNC1_EN |= BIT_PERI_GPIO_EN; (enable gpio peripheral)
+
+	*(volatile uint32_t *)0x40001004 |= (((uint32_t)1) << 8); // GPIO_PORTA_DDR |= ...???; (set gpio to output, GC4 on B&T RTL-00)
+
+	while(1){
+		*(volatile uint32_t *)0x40001000 |= (((uint32_t)1) << 8); // GPIO_PORTA_DR |= ...???;   (pin high)
+		delay(1000000);
+		*(volatile uint32_t *)0x40001000 &= ~(((uint32_t)1) << 8); // GPIO_PORTA_DR &= ~...???; (pin low)
+		delay(1000000);
+	}
+}
+

rtl8710.ld

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+MEMORY{
+	tcm (rx)     : ORIGIN = 0x1FFF0000, LENGTH = 64k
+	ram (rwx)    : ORIGIN = 0x10000000, LENGTH = 458751
+}
+
+PROVIDE(STACK_TOP = 0x1FFF0000 + 64k);
+
+SECTIONS{
+	.text : { __text_beg__ = . ; *(.vectors*) *(.header) *(.text) *(.text*) *(.rodata) *(.rodata*) *(.glue_7) *(.glue_7t) *(.eh_frame) *(.ARM.extab*) . = ALIGN(4); __text_end__ = . ; } >ram
+	.data : { . = ALIGN(4); __data_beg__ = . ; *(.ram_vectors) *(.data) *(.data*) *(.ram_func) . = ALIGN(4); __data_end__ = . ; } >ram
+	.bss : { . = ALIGN(4); __bss_beg__ = . ; *(.bss) *(COMMON) . = ALIGN(4); __bss_end__ = . ; } >ram
+	__exidx_start = .;
+	.ARM.exidx : { ___exidx_start = . ; *(.ARM.exidx*) ; ___exidx_end = . ; } >ram
+	__exidx_end = .;
+	.ARM.extab : { *(.ARM.extab*) } >ram
+	. = ALIGN(4);
+	end = .; PROVIDE (end = .);
+}
+

rtl8710.ocd

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+#
+# script for RTL8710
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME rtl8710
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 2kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x800
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x2ba01477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x10000C00 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+adapter_khz 500
+adapter_nsrst_delay 100
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+# halt
+# load_image $firmware 0x20000000 bin
+
+proc cortex_start {address} {
+	reg faultmask 0x01
+	set vectors ""
+	mem2array vectors 32 $address 2
+	reg sp $vectors(0)
+	reg pc $vectors(1)
+	resume
+}
+