j3d1/rtl8710-sdk
1
0
Fork 0
mirror of https://github.com/dgoodlad/rtl8710-sdk.git synced 2025-07-31 12:41:06 +00:00
Code Issues Projects Releases Packages Wiki Activity

Import required parts of ameba sdk 4.0b

Browse source
This commit is contained in:
David Goodlad 2019-04-23 21:10:24 +10:00
parent 2d21e45bba
commit 7319ca1482
737 changed files with 304718 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

181
vendor/sdk/component/common/drivers/i2s/alc5640.c vendored Normal file
View file

@ -0,0 +1,181 @@
#include <stdio.h>
#include "FreeRTOS.h"
#include "PinNames.h"
#include "basic_types.h"
#include "diag.h"
#include <osdep_api.h>
#include "i2c_api.h"
#include "pinmap.h"
//#define I2C_MTR_SDA PC_4//PB_3
//#define I2C_MTR_SCL PC_5//PB_2
#if defined(CONFIG_PLATFORM_8195A)
#define I2C_MTR_SDA PB_3
#define I2C_MTR_SCL PB_2
#elif defined(CONFIG_PLATFORM_8711B)
#define I2C_MTR_SDA PA_30
#define I2C_MTR_SCL PA_29
#endif
#define I2C_BUS_CLK 100000 //hz
#define I2C_ALC5640_ADDR (0x38/2)
#define RT5640_PRIV_INDEX 0x6a
#define RT5640_PRIV_DATA 0x6c
#if defined (__ICCARM__)
i2c_t alc5640_i2c;
#else
volatile i2c_t alc5640_i2c;
#endif
static void alc5640_delay(void)
{
int i;
i=10000;
while (i) {
i--;
asm volatile ("nop\n\t");
}
}
void alc5640_reg_write(unsigned int reg, unsigned int value)
{
char buf[4];
buf[0] = (char)reg;
buf[1] = (char)(value>>8);
buf[2] = (char)(value&0xff);
i2c_write(&alc5640_i2c, I2C_ALC5640_ADDR, &buf[0], 3, 1);
alc5640_delay();
}
void alc5640_reg_read(unsigned int reg, unsigned int *value)
{
int tmp;
char *buf = (char*)&tmp;
buf[0] = (char)reg;
i2c_write(&alc5640_i2c, I2C_ALC5640_ADDR, &buf[0], 1, 1);
alc5640_delay();
buf[0] = 0xaa;
buf[1] = 0xaa;
i2c_read(&alc5640_i2c, I2C_ALC5640_ADDR, &buf[0], 2, 1);
alc5640_delay();
*value= ((buf[0]&0xFF)<<8)|(buf[1]&0xFF);
}
void alc5640_index_write(unsigned int reg, unsigned int value)
{
alc5640_reg_write(RT5640_PRIV_INDEX, reg);
alc5640_reg_write(RT5640_PRIV_DATA, value);
}
void alc5640_index_read(unsigned int reg, unsigned int *value)
{
alc5640_reg_write(RT5640_PRIV_INDEX, reg);
alc5640_reg_read(RT5640_PRIV_DATA, value);
}
void alc5640_reg_dump(void)
{
int i;
unsigned int value;
printf("alc5640 codec reg dump\n\r");
printf("------------------------\n\r");
for(i=0;i<=0xff;i++){
alc5640_reg_read(i, &value);
printf("%02x : %04x\n\r", i, (unsigned short)value);
}
printf("------------------------\n\r");
}
void alc5640_index_dump(void)
{
int i;
unsigned int value;
printf("alc5640 codec index dump\n\r");
printf("------------------------\n\r");
for(i=0;i<=0xff;i++){
alc5640_index_read(i, &value);
printf("%02x : %04x\n\r", i, (unsigned short)value);
}
printf("------------------------\n\r");
}
void alc5640_init(void)
{
i2c_init(&alc5640_i2c, I2C_MTR_SDA, I2C_MTR_SCL);
i2c_frequency(&alc5640_i2c, I2C_BUS_CLK);
}
void alc5640_set_word_len(int len_idx) // interface2
{
// 0: 16 1: 20 2: 24 3: 8
unsigned int val;
alc5640_reg_read(0x71,&val);
val &= (~(0x3<<2));
val |= (len_idx<<2);
alc5640_reg_write(0x71,val);
alc5640_reg_read(0x70,&val);
val &= (~(0x3<<2));
val |= (len_idx<<2);
alc5640_reg_write(0x70,val);
}
void alc5640_init_interface1(void)
{
// I2S1 -> DAC -> SPK R/L
alc5640_reg_write(0x00,0x0021);
alc5640_reg_write(0xD9,0x0009);
alc5640_reg_write(0x73,0x0014);
alc5640_reg_write(0xFA,0x3401);
alc5640_index_write(0x1C,0x0D21);
alc5640_reg_write(0x63,0xA8F0);
wait_ms(100); // delay 100 ms.
alc5640_reg_write(0x63,0xE8F8);
alc5640_reg_write(0x61,0x9801);
alc5640_index_write(0x3D,0x2600);
alc5640_index_write(0x1C,0xFD21);
alc5640_reg_write(0x2A,0x1414);
alc5640_reg_write(0x48,0xB800);
alc5640_reg_write(0x49,0x1800);
alc5640_reg_write(0x01,0x4848);
alc5640_reg_write(0xD9,0x0809);
}
void alc5640_init_interface2(void)
{
alc5640_reg_write(0x00,0x0021);
alc5640_reg_write(0x63,0xE8FE);
alc5640_reg_write(0x61,0x5800);
alc5640_reg_write(0x62,0x0C00);
alc5640_reg_write(0x73,0x0000);
alc5640_reg_write(0x2A,0x4242);
alc5640_reg_write(0x45,0x2000);
alc5640_reg_write(0x02,0x4848);
alc5640_reg_write(0x8E,0x0019);
alc5640_reg_write(0x8F,0x3100);
alc5640_reg_write(0x91,0x0E00);
alc5640_index_write(0x3D,0x3E00);
alc5640_reg_write(0xFA,0x0011);
alc5640_reg_write(0x83,0x0800);
alc5640_reg_write(0x84,0xA000);
alc5640_reg_write(0xFA,0x0C11);
alc5640_reg_write(0x64,0x4010);
alc5640_reg_write(0x65,0x0C00);
alc5640_reg_write(0x61,0x5806);
alc5640_reg_write(0x62,0xCC00);
alc5640_reg_write(0x3C,0x004F);
alc5640_reg_write(0x3E,0x004F);
alc5640_reg_write(0x28,0x3030);
alc5640_reg_write(0x2F,0x0080);
}

9
vendor/sdk/component/common/drivers/i2s/alc5640.h vendored Normal file
View file

@ -0,0 +1,9 @@
#ifndef _ALC5640_H_
#define _ALC5640_H_
void alc5640_reg_dump(void);
void alc5640_index_dump(void);
void alc5640_init(void);
void alc5640_set_word_len(int len_idx);
void alc5640_init_interface1(void);
void alc5640_init_interface2(void);
#endif

201
vendor/sdk/component/common/drivers/i2s/alc5651.c vendored Normal file
View file

@ -0,0 +1,201 @@
#include <stdio.h>
#include "PinNames.h"
#include "basic_types.h"
#include "diag.h"
#include <osdep_api.h>
#include "i2c_api.h"
#include "pinmap.h"
//#define I2C_MTR_SDA PC_4//PB_3
//#define I2C_MTR_SCL PC_5//PB_2
#if defined(CONFIG_PLATFORM_8195A)
#define I2C_MTR_SDA PB_3
#define I2C_MTR_SCL PB_2
#elif defined(CONFIG_PLATFORM_8711B)
#define I2C_MTR_SDA PA_30
#define I2C_MTR_SCL PA_29
#endif
#define I2C_BUS_CLK 100000 //hz
#define I2C_ALC5651_ADDR (0x34/2)
#define RT5651_PRIV_INDEX 0x6a
#define RT5651_PRIV_DATA 0x6c
#if defined (__ICCARM__)
i2c_t alc5651_i2c;
#else
volatile i2c_t alc5651_i2c;
#define printf DBG_8195A
#endif
static void alc5651_delay(void)
{
int i;
i=10000;
while (i) {
i--;
asm volatile ("nop\n\t");
}
}
void alc5651_reg_write(unsigned int reg, unsigned int value)
{
char buf[4];
buf[0] = (char)reg;
buf[1] = (char)(value>>8);
buf[2] = (char)(value&0xff);
i2c_write(&alc5651_i2c, I2C_ALC5651_ADDR, &buf[0], 3, 1);
alc5651_delay();
}
void alc5651_reg_read(unsigned int reg, unsigned int *value)
{
int tmp;
char *buf = (char*)&tmp;
buf[0] = (char)reg;
i2c_write(&alc5651_i2c, I2C_ALC5651_ADDR, &buf[0], 1, 1);
alc5651_delay();
buf[0] = 0xaa;
buf[1] = 0xaa;
i2c_read(&alc5651_i2c, I2C_ALC5651_ADDR, &buf[0], 2, 1);
alc5651_delay();
*value= ((buf[0]&0xFF)<<8)|(buf[1]&0xFF);
}
void alc5651_index_write(unsigned int reg, unsigned int value)
{
alc5651_reg_write(RT5651_PRIV_INDEX, reg);
alc5651_reg_write(RT5651_PRIV_DATA, value);
}
void alc5651_index_read(unsigned int reg, unsigned int *value)
{
alc5651_reg_write(RT5651_PRIV_INDEX, reg);
alc5651_reg_read(RT5651_PRIV_DATA, value);
}
void alc5651_reg_dump(void)
{
int i;
unsigned int value;
printf("alc5651 codec reg dump\n\r");
printf("------------------------\n\r");
for(i=0;i<=0xff;i++){
alc5651_reg_read(i, &value);
printf("%02x : %04x\n\r", i, (unsigned short)value);
}
printf("------------------------\n\r");
}
void alc5651_index_dump(void)
{
int i;
unsigned int value;
printf("alc5651 codec index dump\n\r");
printf("------------------------\n\r");
for(i=0;i<=0xff;i++){
alc5651_index_read(i, &value);
printf("%02x : %04x\n\r", i, (unsigned short)value);
}
printf("------------------------\n\r");
}
void alc5651_init(void)
{
i2c_init(&alc5651_i2c, I2C_MTR_SDA, I2C_MTR_SCL);
i2c_frequency(&alc5651_i2c, I2C_BUS_CLK);
}
void alc5651_set_word_len(int len_idx) // interface2
{
// 0: 16 1: 20 2: 24 3: 8
unsigned int val;
alc5651_reg_read(0x71,&val);
val &= (~(0x3<<2));
val |= (len_idx<<2);
alc5651_reg_write(0x71,val);
alc5651_reg_read(0x70,&val);
val &= (~(0x3<<2));
val |= (len_idx<<2);
alc5651_reg_write(0x70,val);
}
void alc5651_init_interface1(void)
{
alc5651_reg_write(0x00,0x0021);
alc5651_reg_write(0x63,0xE8FE);
alc5651_reg_write(0x61,0x5800);
alc5651_reg_write(0x62,0x0C00);
alc5651_reg_write(0x73,0x0000);
alc5651_reg_write(0x2A,0x4242);
alc5651_reg_write(0x45,0x2000);
alc5651_reg_write(0x02,0x4848);
alc5651_reg_write(0x8E,0x0019);
alc5651_reg_write(0x8F,0x3100);
alc5651_reg_write(0x91,0x0E00);
alc5651_index_write(0x3D,0x3E00);
alc5651_reg_write(0xFA,0x0011);
alc5651_reg_write(0x83,0x0800);
alc5651_reg_write(0x84,0xA000);
alc5651_reg_write(0xFA,0x0C11);
alc5651_reg_write(0x64,0x4010);
alc5651_reg_write(0x65,0x0C00);
alc5651_reg_write(0x61,0x5806);
alc5651_reg_write(0x62,0xCC00);
alc5651_reg_write(0x3C,0x004F);
alc5651_reg_write(0x3E,0x004F);
alc5651_reg_write(0x27,0x3820);
alc5651_reg_write(0x77,0x0000);
}
void alc5651_init_interface2(void)
{
int reg_value=0;
alc5651_reg_write(0x00,0x0021);//reset all, device id 1
alc5651_reg_write(0x63,0xE8FE);//Power managerment control 3:
//VREF1&2 on, both slow VREF, MBIAS on, MBIAS bandcap power on, L & R HP Amp on, improve HP Amp driving enabled
alc5651_reg_write(0x61,0x5800);//power managerment control 1:
//I2S2 digital interface on, Analog DACL1 & DACR1 on.
alc5651_reg_write(0x62,0x0C00);//stereo1 & 2 DAC filter power on
alc5651_reg_write(0x73,0x0000);//ADC/DAC Clock control 1:
//I2S Clock Pre-Divider 1 & 2: /1. Stereo DAC Over Sample Rate : 128Fs
alc5651_reg_write(0x2A,0x4242);//Stereo DAC digital mixer control
//Un-mute DACL2 to Stereo DAC Left & Right Mixer
alc5651_reg_write(0x45,0x2000);//HPOMIX: Un-mute DAC1 to HPOMIX
alc5651_reg_write(0x02,0x4848);//HP Output Control:
//Unmute HPOL, HPOR
// alc5651_reg_write(0x0F,0x1F1F);//INL & INR Volume Control
// alc5651_reg_write(0x0D,0x0800);//IN1/2 Input Control
// alc5651_reg_write(0x1C,0x7F7F);//Stereo1 ADC Digital Volume Control
// alc5651_reg_write(0x1E,0xF000);// ADC Digital Boost Gain Control
alc5651_reg_write(0x8E,0x0019);//HP Amp Control 1
// Enable HP Output, Charge Pump Power On, HP Amp All Power On
alc5651_reg_write(0x8F,0x3100);//HP Amp Control 2, HP Depop Mode 2
alc5651_reg_write(0x91,0x0E00);//HP Amp Control 3, select HP capless power mode
alc5651_index_write(0x3D,0x3E00);//unknown
alc5651_reg_write(0xFA,0x0011);//enable input clock
alc5651_reg_write(0x83,0x0800);//default ASRC control 1
alc5651_reg_write(0x84,0xA000);//ASRC control 2: I2S1 enable ASRC mode, Sterol1 DAC filter ASRC mode.
// alc5651_reg_write(0xFA,0x0C11);//? ? ? MX-FAh[15:4]reserved
alc5651_reg_write(0x64,0x4010);//power managerment control 4:
//MIC BST2 Power On; MIC2 SE Mode single-end mode or line-input mode
alc5651_reg_write(0x65,0x0C00);//power managerment control 5: RECMIX L & R power on
alc5651_reg_write(0x61,0x5806);//power managerment control 1:
// I2S2 Digital Interface On, Analog DACL1, DACR1 power on; Analog ADCL, ADCR power on
alc5651_reg_write(0x62,0xCC00);//power managerment control 2: Stereo1&2 ADC/DAC digital filter power on
alc5651_reg_write(0x3C,0x004F);//RECMIXL
alc5651_reg_write(0x3E,0x004F);//RECMIXR
alc5651_reg_write(0x28,0x3030);//stereo2 ADC digital mixer control : Mute Stereo2 ADC L&R channel, ADCR
alc5651_reg_write(0x2F,0x0080); //Interface DAC/ADC Data control: Select IF2 ADCDAT Data Source IF1_ADC2
}

9
vendor/sdk/component/common/drivers/i2s/alc5651.h vendored Normal file
View file

@ -0,0 +1,9 @@
#ifndef _ALC5651_H_
#define _ALC5651_H_
void alc5651_reg_dump(void);
void alc5651_index_dump(void);
void alc5651_init(void);
void alc5651_set_word_len(int len_idx);
void alc5651_init_interface1(void);
void alc5651_init_interface2(void);
#endif

227
vendor/sdk/component/common/drivers/i2s/alc5679.c vendored Normal file
View file

@ -0,0 +1,227 @@
#include "PinNames.h"
#include "basic_types.h"
#include <osdep_api.h>
#include "i2c_api.h"
#include "i2c_ex_api.h"
#include "pinmap.h"
#include "wait_api.h"
#include "alc5679.h"
#define I2C_ALC5679_ADDR (0X5A/2)//(0x58/2)
#if defined(CONFIG_PLATFORM_8195A)
#define I2C_MTR_SDA PB_3
#define I2C_MTR_SCL PB_2
#elif defined(CONFIG_PLATFORM_8711B)
#define I2C_MTR_SDA PA_30
#define I2C_MTR_SCL PA_29
#endif
#define I2C_BUS_CLK 100000 //100K HZ
//i2c_t rt5679_i2c;
#if defined (__ICCARM__)
i2c_t rt5679_i2c;
#else
volatile i2c_t rt5679_i2c;
#define printf DBG_8195A
#endif
static void rt5679_delay(void)
{
int i;
i=10000;
while (i) {
i--;
asm volatile ("nop\n\t");
}
}
u8 rt5679_reg_write(u16 reg, u16 val)
{
int length = 0;
char buf[4];
buf[0] = (char)(reg >> 8);
buf[1] = (char)(reg&0xff);
buf[2] = (char)(val>>8);
buf[3] = (char)(val&0xff);
length = i2c_write(&rt5679_i2c, I2C_ALC5679_ADDR, &buf[0], 4, 1);
rt5679_delay();
return (length==4)?0:1;
}
u8 rt5679_reg_read(u16 reg, u16* val)
{
int tmp;
char *buf = (char*)&tmp;
u8 ret = 0;
buf[0] = (char)(reg >> 8);
buf[1] = (char)(reg&0xff);
if(i2c_write(&rt5679_i2c, I2C_ALC5679_ADDR, &buf[0], 2, 1) != 2){
DBG_8195A("rt5679_reg_read(): write register addr fail\n");
ret = 1;
}
rt5679_delay();
buf[0] = 0xaa;
buf[1] = 0xaa;
if(i2c_read(&rt5679_i2c, I2C_ALC5679_ADDR, &buf[0], 2, 1) < 2){
DBG_8195A("rt5679_reg_read(): read register value fail\n");
ret = 1;
}else
*val = ((buf[0]&0xFF)<<8)|(buf[1]&0xFF);
rt5679_delay();
return ret;
}
u16 rt5679_reg_modify(u16 reg, u16 val, u16 iMask)
{
u16 val1;
rt5679_reg_read(reg, &val1);
u16 val2 = (val1 &(~iMask))|val;
if(!rt5679_reg_write(reg, val2)) return 0;
return val2;
}
void rt5679_i2c_init(void)
{
i2c_init(&rt5679_i2c, I2C_MTR_SDA, I2C_MTR_SCL);
i2c_frequency(&rt5679_i2c, I2C_BUS_CLK);
}
int rt5679_check_id(void)
{
unsigned short ret = 0;
rt5679_reg_read(RT5679_VENDOR_ID2, &ret);
printf("Device with ID register is %x \n", ret);
if (ret != RT5679_DEVICE_ID) {
printf("Device with ID register %x is not rt5679\n", ret);
return 1;
}else{
return 0;
}
}
void rt5679_reg_dump(void)
{
int i;
unsigned short value;
printf("rt5679 codec reg dump\n\r");
printf("------------------------\n\r");
for(i=0;i<=0xff;i++){
rt5679_reg_read(i, &value);
printf("%02x : %04x\n\r", i, value);
}
printf("------------------------\n\r");
}
void rt5679_mic_to_i2s(void)
{
rt5679_reg_write(0x0000,0x10EC);
rt5679_reg_write(0x00FA,0x0001);
rt5679_reg_write(0x0076,0x0777);
rt5679_reg_write(0x0078,0x0000);
rt5679_reg_write(0x004A,0x8080);
rt5679_reg_write(0x0050,0x8553);
rt5679_reg_write(0x0061,0x8000);
rt5679_reg_write(0x0062,0x8000);
rt5679_reg_write(0x00C2,0x5000);
}
void rt5679_linein_to_i2s(void)
{
rt5679_reg_write(0x0000,0x10EC);
rt5679_reg_write(0x061D,0x04DF);
rt5679_reg_write(0x0007,0x1010);
rt5679_reg_write(0x004A,0x4040);
rt5679_reg_write(0x0060,0x0060);
rt5679_reg_write(0x0061,0x8000);
rt5679_reg_write(0x0062,0x8000);
rt5679_reg_write(0x0063,0xE340);
rt5679_reg_write(0x0064,0xC000);
rt5679_reg_write(0x0066,0x2000);
//rt5679_reg_write(0x0070,0x8020);//32 bit
rt5679_reg_write(0x0070,0x8000);//16bit
//rt5679_reg_write(0x0070,0x8040);//enable mono mode
rt5679_reg_write(0x0076,0x0777);
rt5679_reg_write(0x0078,0x0000);
rt5679_reg_write(0x00FA,0x0001);
rt5679_reg_write(0x0610,0xB490);
}
void rt5679_i2s_to_hp(void)
{
rt5679_reg_write(0x0000,0x10EC);
rt5679_reg_write(0x0609,0x1122);
rt5679_reg_write(0x060A,0x3622);
rt5679_reg_write(0x060B,0x1022);
rt5679_reg_write(0x060C,0x3622);
rt5679_reg_write(0x0671,0xC0D0);
rt5679_reg_write(0x0603,0x0444);
rt5679_reg_write(0x068F,0x0007);
rt5679_reg_write(0x0690,0x0007);
rt5679_reg_write(0x0684,0x0217);
rt5679_reg_write(0x0122,0x0000);
rt5679_reg_write(0x0121,0x0000);
rt5679_reg_write(0x0014,0x5454);
rt5679_reg_write(0x0673,0xAEAA);
rt5679_reg_write(0x0660,0x3840);
///////////////////////////////
rt5679_reg_write(0x0661,0x3840);
rt5679_reg_write(0x0665,0x0101);
rt5679_reg_write(0x0681,0x0118);
rt5679_reg_write(0x0682,0x0118);
rt5679_reg_write(0x07F3,0x0008);
rt5679_reg_write(0x061D,0xE4CF);
rt5679_reg_write(0x00FA,0x0001);
rt5679_reg_write(0x0076,0x0777);
rt5679_reg_write(0x0078,0x0000);
rt5679_reg_write(0x0660,0x3840);
rt5679_reg_write(0x0661,0x3840);
rt5679_reg_write(0x0070,0x8000);//16bit 8000 32bit 8020
rt5679_reg_write(0x0040,0xF0AA);
rt5679_reg_write(0x0046,0x8080);
////////////////////////////////
rt5679_reg_write(0x0061,0x8000);
rt5679_reg_write(0x0062,0x0400);
rt5679_reg_write(0x061D,0xE4CF);
rt5679_reg_write(0x0063,0xA240);
rt5679_reg_write(0x0066,0x1680);
wait_ms(20);
rt5679_reg_write(0x0063,0xE340);
rt5679_reg_write(0x0066,0x1F80);
rt5679_reg_write(0x0066,0xDF80);
rt5679_reg_write(0x0080,0x6000);
rt5679_reg_write(0x0063,0xE342);
rt5679_reg_write(0x0076,0x1777);
rt5679_reg_write(0x0066,0xFF80);
rt5679_reg_write(0x000A,0x5353);
rt5679_reg_write(0x0614,0xB490);
rt5679_reg_write(0x0060,0x0003);
rt5679_reg_write(0x0401,0x0630);
////////////////////////////////
rt5679_reg_write(0x0403,0x0267);
rt5679_reg_write(0x0404,0x9ECD);
rt5679_reg_write(0x0400,0x7D00);
rt5679_reg_write(0x0400,0xFD00);
wait_ms(650);
rt5679_reg_write(0x0080,0x0000);
rt5679_reg_write(0x0063,0xE340);
rt5679_reg_write(0x0076,0x0777);
rt5679_reg_write(0x019B,0x0003);
rt5679_reg_write(0x0003,0x8080);
rt5679_reg_write(0x0066,0xDF80);
rt5679_reg_write(0x000A,0x5455);
rt5679_reg_write(0x0614,0xA490);
rt5679_reg_write(0x0060,0x0000);
rt5679_reg_write(0x0404,0x9E0C);
}

13
vendor/sdk/component/common/drivers/i2s/alc5679.h vendored Normal file
View file

@ -0,0 +1,13 @@
#ifndef _ALC5679_H_
#define _ALC5679_H_
#define RT5679_DEVICE_ID 0x6385
#define RT5679_VENDOR_ID2 0x00ff
/////////////////////////////////////////////////////
void rt5679_i2c_init(void);
int check_id();
void rt5679_linein_to_i2s(void);
void rt5679_i2s_to_hp(void);
void rt5679_mic_to_i2s(void);
#endif

200
vendor/sdk/component/common/drivers/i2s/sgtl5000.c vendored Normal file
View file

@ -0,0 +1,200 @@
#include "sgtl5000.h"
#include "PinNames.h"
#include "basic_types.h"
#include "i2c_api.h"
#include "i2c_ex_api.h"
#include "pinmap.h"
#include "wait_api.h"
//#define I2C_MTR_SDA PC_4//PB_3
//#define I2C_MTR_SCL PC_5//PB_2
#define I2C_MTR_SDA PB_3
#define I2C_MTR_SCL PB_2
#define I2C_BUS_CLK 100000 //100K HZ
i2c_t sgtl5000_i2c;
uint16_t ana_ctrl;
uint8_t i2c_addr;
bool muted;
u8 sgtl5000_reg_write(u16 reg, u16 val)
{
int length = 0;
char buf[4];
buf[0] = (char)(reg >> 8);
buf[1] = (char)(reg&0xff);
buf[2] = (char)(val>>8);
buf[3] = (char)(val&0xff);
length = i2c_write(&sgtl5000_i2c, i2c_addr, &buf[0], 4, 1);
return (length==4)?0:1;
}
u8 sgtl5000_reg_read(u16 reg, u16* val)
{
int tmp;
char *buf = (char*)&tmp;
u8 ret = 0;
buf[0] = (char)(reg >> 8);
buf[1] = (char)(reg&0xff);
if(i2c_write(&sgtl5000_i2c, i2c_addr, &buf[0], 2, 1) != 2){
DBG_8195A("sgtl5000_reg_read(): write register addr fail\n");
ret = 1;
}
buf[0] = 0xaa;
buf[1] = 0xaa;
if(i2c_read(&sgtl5000_i2c, i2c_addr, &buf[0], 2, 1) < 2){
DBG_8195A("sgtl5000_reg_read(): read register value fail\n");
ret = 1;
}else
*val = ((buf[0]&0xFF)<<8)|(buf[1]&0xFF);
return ret;
}
u16 sgtl5000_reg_modify(u16 reg, u16 val, u16 iMask)
{
u16 val1;
sgtl5000_reg_read(reg, &val1);
u16 val2 = (val1 &(~iMask))|val;
if(!sgtl5000_reg_write(reg, val2)) return 0;
return val2;
}
void sgtl5000_setAddress(uint8_t level)
{
if (level == 0) {
i2c_addr = SGTL5000_I2C_ADDR_CS_LOW;
} else {
i2c_addr = SGTL5000_I2C_ADDR_CS_HIGH;
}
}
void sgtl5000_i2c_master_txc_callback(void *userdata)
{
}
void sgtl5000_i2c_master_rxc_callback(void *userdata)
{
}
void sgtl5000_i2c_master_err_callback(void *userdata)
{
//DBG_8195A("I2C Ack address:%d", (sgtl5000_i2c.I2Cx->IC_TAR)& BIT_CTRL_IC_TAR);//sgtl5000_i2c.SalI2CHndPriv.SalI2CHndPriv.I2CAckAddr);
//DBG_8195A("I2C Error:%x\n", sgtl5000_i2c.I2Cx->IC_TX_ABRT_SOURCE);//sgtl5000_i2c.SalI2CHndPriv.SalI2CHndPriv.ErrType);
}
void sgtl5000_reg_dump(void);
u8 sgtl5000_enable(void){
u16 temp = 0;
u8 ret = 0;
muted = 1;
memset(&sgtl5000_i2c, 0x00, sizeof(sgtl5000_i2c));
i2c_init(&sgtl5000_i2c, I2C_MTR_SDA, I2C_MTR_SCL);
i2c_frequency(&sgtl5000_i2c, I2C_BUS_CLK);
i2c_set_user_callback(&sgtl5000_i2c, I2C_ERR_OCCURRED, sgtl5000_i2c_master_err_callback);
// set I2C address
sgtl5000_setAddress(0); // CTRL_ADR0_CS is tied to GND
wait_ms(5);
ret = sgtl5000_reg_read(CHIP_ID, &temp);
if(ret == 0)
DBG_8195A("SGTL5000 CHIP ID:0x%04X\n", temp);
else
DBG_8195A("Get SGTL5000 CHIP ID fail\n");
sgtl5000_reg_write(CHIP_ANA_POWER, 0x4060); // VDDD is externally driven with 1.8V
sgtl5000_reg_write(CHIP_LINREG_CTRL, 0x006C); // VDDA & VDDIO both over 3.1V
sgtl5000_reg_write(CHIP_REF_CTRL, 0x01F2); // VAG=1.575, normal ramp, +12.5% bias current
sgtl5000_reg_write(CHIP_LINE_OUT_CTRL, 0x0F22); // LO_VAGCNTRL=1.65V, OUT_CURRENT=0.54mA
sgtl5000_reg_write(CHIP_SHORT_CTRL, 0x4446); // allow up to 125mA
sgtl5000_reg_write(CHIP_ANA_CTRL, 0x0137); // enable zero cross detectors
sgtl5000_reg_write(CHIP_ANA_POWER, 0x40FF); // power up: lineout, hp, adc, dac
sgtl5000_reg_write(CHIP_DIG_POWER, 0x0073); // power up all digital stuff
wait_ms(400);
sgtl5000_reg_write(CHIP_LINE_OUT_VOL, 0x1D1D); // default approx 1.3 volts peak-to-peak
sgtl5000_reg_write(CHIP_CLK_CTRL, 0x0004); // 44.1 kHz, 256*Fs
sgtl5000_reg_write(CHIP_I2S_CTRL, 0x0130); // SCLK=32*Fs, 16bit, I2S format
// default signal routing is ok?
sgtl5000_reg_write(CHIP_SSS_CTRL, 0x0010); // ADC->I2S, I2S->DAC
sgtl5000_reg_write(CHIP_ADCDAC_CTRL, 0x0000); // disable dac mute
sgtl5000_reg_write(CHIP_DAC_VOL, 0x3C3C); // digital gain, 0dB
sgtl5000_reg_write(CHIP_ANA_HP_CTRL, 0x7F7F); // set volume (lowest level)
sgtl5000_reg_write(CHIP_ANA_CTRL, 0x0036); // enable zero cross detectors
//semi_automated = true;
//sgtl5000_reg_dump();
return 0;
}
bool sgtl5000_muteHeadphone(void) {
return sgtl5000_reg_write(CHIP_ANA_CTRL, ana_ctrl | (1<<4));
}
bool sgtl5000_unmuteHeadphone(void) {
return sgtl5000_reg_write(CHIP_ANA_CTRL, ana_ctrl & ~(1<<4));
}
bool sgtl5000_muteLineout(void) {
return sgtl5000_reg_write(CHIP_ANA_CTRL, ana_ctrl | (1<<8));
}
bool sgtl5000_unmuteLineout(void) {
return sgtl5000_reg_write(CHIP_ANA_CTRL, ana_ctrl & ~(1<<8));
}
u8 sgtl5000_setVolume(float val){
int volumeInt = 0;
volumeInt = (int)(val * 129 + 0.499);
if (volumeInt == 0) {
muted = 1;
sgtl5000_reg_write(CHIP_ANA_HP_CTRL, 0x7F7F);
return sgtl5000_muteHeadphone();
} else if (volumeInt > 0x80) {
volumeInt = 0;
} else {
volumeInt = 0x80 - volumeInt;
}
if (muted) {
muted = 0;
sgtl5000_unmuteHeadphone();
}
volumeInt = volumeInt | (volumeInt << 8);
return sgtl5000_reg_write(CHIP_ANA_HP_CTRL, volumeInt); // set volume
}
void sgtl5000_reg_dump(void)
{
u16 reg;
u8 ret = 0;
u16 value;
DBG_8195A("SGTL5000 codec reg dump\n\r");
DBG_8195A("------------------------\n\r");
for(reg = 0; reg <= 0x013A; ){
ret = sgtl5000_reg_read(reg, &value);
if(ret == 0)
DBG_8195A("0x%04X : 0x%04X\n\r", reg, value);
reg += 0x02;
}
DBG_8195A("------------------------\n\r");
}

479
vendor/sdk/component/common/drivers/i2s/sgtl5000.h vendored Normal file
View file

@ -0,0 +1,479 @@
#ifndef _SGTL5000_H_
#define _SGTL5000_H_
#define CHIP_ID 0x0000
// 15:8 PARTID 0xA0 - 8 bit identifier for SGTL5000
// 7:0 REVID 0x00 - revision number for SGTL5000.
#define CHIP_DIG_POWER 0x0002
// 6 ADC_POWERUP 1=Enable, 0=disable the ADC block, both digital & analog,
// 5 DAC_POWERUP 1=Enable, 0=disable the DAC block, both analog and digital
// 4 DAP_POWERUP 1=Enable, 0=disable the DAP block
// 1 I2S_OUT_POWERUP 1=Enable, 0=disable the I2S data output
// 0 I2S_IN_POWERUP 1=Enable, 0=disable the I2S data input
#define CHIP_CLK_CTRL 0x0004
// 5:4 RATE_MODE Sets the sample rate mode. MCLK_FREQ is still specified
// relative to the rate in SYS_FS
// 0x0 = SYS_FS specifies the rate
// 0x1 = Rate is 1/2 of the SYS_FS rate
// 0x2 = Rate is 1/4 of the SYS_FS rate
// 0x3 = Rate is 1/6 of the SYS_FS rate
// 3:2 SYS_FS Sets the internal system sample rate (default=2)
// 0x0 = 32 kHz
// 0x1 = 44.1 kHz
// 0x2 = 48 kHz
// 0x3 = 96 kHz
// 1:0 MCLK_FREQ Identifies incoming SYS_MCLK frequency and if the PLL should be used
// 0x0 = 256*Fs
// 0x1 = 384*Fs
// 0x2 = 512*Fs
// 0x3 = Use PLL
// The 0x3 (Use PLL) setting must be used if the SYS_MCLK is not
// a standard multiple of Fs (256, 384, or 512). This setting can
// also be used if SYS_MCLK is a standard multiple of Fs.
// Before this field is set to 0x3 (Use PLL), the PLL must be
// powered up by setting CHIP_ANA_POWER->PLL_POWERUP and
// CHIP_ANA_POWER->VCOAMP_POWERUP. Also, the PLL dividers must
// be calculated based on the external MCLK rate and
// CHIP_PLL_CTRL register must be set (see CHIP_PLL_CTRL register
// description details on how to calculate the divisors).
#define CHIP_I2S_CTRL 0x0006
// 8 SCLKFREQ Sets frequency of I2S_SCLK when in master mode (MS=1). When in slave
// mode (MS=0), this field must be set appropriately to match SCLK input
// rate.
// 0x0 = 64Fs
// 0x1 = 32Fs - Not supported for RJ mode (I2S_MODE = 1)
// 7 MS Configures master or slave of I2S_LRCLK and I2S_SCLK.
// 0x0 = Slave: I2S_LRCLK an I2S_SCLK are inputs
// 0x1 = Master: I2S_LRCLK and I2S_SCLK are outputs
// NOTE: If the PLL is used (CHIP_CLK_CTRL->MCLK_FREQ==0x3),
// the SGTL5000 must be a master of the I2S port (MS==1)
// 6 SCLK_INV Sets the edge that data (input and output) is clocked in on for I2S_SCLK
// 0x0 = data is valid on rising edge of I2S_SCLK
// 0x1 = data is valid on falling edge of I2S_SCLK
// 5:4 DLEN I2S data length (default=1)
// 0x0 = 32 bits (only valid when SCLKFREQ=0),
// not valid for Right Justified Mode
// 0x1 = 24 bits (only valid when SCLKFREQ=0)
// 0x2 = 20 bits
// 0x3 = 16 bits
// 3:2 I2S_MODE Sets the mode for the I2S port
// 0x0 = I2S mode or Left Justified (Use LRALIGN to select)
// 0x1 = Right Justified Mode
// 0x2 = PCM Format A/B
// 0x3 = RESERVED
// 1 LRALIGN I2S_LRCLK Alignment to data word. Not used for Right Justified mode
// 0x0 = Data word starts 1 I2S_SCLK delay after I2S_LRCLK
// transition (I2S format, PCM format A)
// 0x1 = Data word starts after I2S_LRCLK transition (left
// justified format, PCM format B)
// 0 LRPOL I2S_LRCLK Polarity when data is presented.
// 0x0 = I2S_LRCLK = 0 - Left, 1 - Right
// 1x0 = I2S_LRCLK = 0 - Right, 1 - Left
// The left subframe should be presented first regardless of
// the setting of LRPOL.
#define CHIP_SSS_CTRL 0x000A
// 14 DAP_MIX_LRSWAP DAP Mixer Input Swap
// 0x0 = Normal Operation
// 0x1 = Left and Right channels for the DAP MIXER Input are swapped.
// 13 DAP_LRSWAP DAP Mixer Input Swap
// 0x0 = Normal Operation
// 0x1 = Left and Right channels for the DAP Input are swapped
// 12 DAC_LRSWAP DAC Input Swap
// 0x0 = Normal Operation
// 0x1 = Left and Right channels for the DAC are swapped
// 10 I2S_LRSWAP I2S_DOUT Swap
// 0x0 = Normal Operation
// 0x1 = Left and Right channels for the I2S_DOUT are swapped
// 9:8 DAP_MIX_SELECT Select data source for DAP mixer
// 0x0 = ADC
// 0x1 = I2S_IN
// 0x2 = Reserved
// 0x3 = Reserved
// 7:6 DAP_SELECT Select data source for DAP
// 0x0 = ADC
// 0x1 = I2S_IN
// 0x2 = Reserved
// 0x3 = Reserved
// 5:4 DAC_SELECT Select data source for DAC (default=1)
// 0x0 = ADC
// 0x1 = I2S_IN
// 0x2 = Reserved
// 0x3 = DAP
// 1:0 I2S_SELECT Select data source for I2S_DOUT
// 0x0 = ADC
// 0x1 = I2S_IN
// 0x2 = Reserved
// 0x3 = DAP
#define CHIP_ADCDAC_CTRL 0x000E
// 13 VOL_BUSY_DAC_RIGHT Volume Busy DAC Right
// 0x0 = Ready
// 0x1 = Busy - This indicates the channel has not reached its
// programmed volume/mute level
// 12 VOL_BUSY_DAC_LEFT Volume Busy DAC Left
// 0x0 = Ready
// 0x1 = Busy - This indicates the channel has not reached its
// programmed volume/mute level
// 9 VOL_RAMP_EN Volume Ramp Enable (default=1)
// 0x0 = Disables volume ramp. New volume settings take immediate
// effect without a ramp
// 0x1 = Enables volume ramp
// This field affects DAC_VOL. The volume ramp effects both
// volume settings and mute When set to 1 a soft mute is enabled.
// 8 VOL_EXPO_RAMP Exponential Volume Ramp Enable
// 0x0 = Linear ramp over top 4 volume octaves
// 0x1 = Exponential ramp over full volume range
// This bit only takes effect if VOL_RAMP_EN is 1.
// 3 DAC_MUTE_RIGHT DAC Right Mute (default=1)
// 0x0 = Unmute
// 0x1 = Muted
// If VOL_RAMP_EN = 1, this is a soft mute.
// 2 DAC_MUTE_LEFT DAC Left Mute (default=1)
// 0x0 = Unmute
// 0x1 = Muted
// If VOL_RAMP_EN = 1, this is a soft mute.
// 1 ADC_HPF_FREEZE ADC High Pass Filter Freeze
// 0x0 = Normal operation
// 0x1 = Freeze the ADC high-pass filter offset register. The
// offset continues to be subtracted from the ADC data stream.
// 0 ADC_HPF_BYPASS ADC High Pass Filter Bypass
// 0x0 = Normal operation
// 0x1 = Bypassed and offset not updated
#define CHIP_DAC_VOL 0x0010
// 15:8 DAC_VOL_RIGHT DAC Right Channel Volume. Set the Right channel DAC volume
// with 0.5017 dB steps from 0 to -90 dB
// 0x3B and less = Reserved
// 0x3C = 0 dB
// 0x3D = -0.5 dB
// 0xF0 = -90 dB
// 0xFC and greater = Muted
// If VOL_RAMP_EN = 1, there is an automatic ramp to the
// new volume setting.
// 7:0 DAC_VOL_LEFT DAC Left Channel Volume. Set the Left channel DAC volume
// with 0.5017 dB steps from 0 to -90 dB
// 0x3B and less = Reserved
// 0x3C = 0 dB
// 0x3D = -0.5 dB
// 0xF0 = -90 dB
// 0xFC and greater = Muted
// If VOL_RAMP_EN = 1, there is an automatic ramp to the
// new volume setting.
#define CHIP_PAD_STRENGTH 0x0014
// 9:8 I2S_LRCLK I2S LRCLK Pad Drive Strength (default=1)
// Sets drive strength for output pads per the table below.
// VDDIO 1.8 V 2.5 V 3.3 V
// 0x0 = Disable
// 0x1 = 1.66 mA 2.87 mA 4.02 mA
// 0x2 = 3.33 mA 5.74 mA 8.03 mA
// 0x3 = 4.99 mA 8.61 mA 12.05 mA
// 7:6 I2S_SCLK I2S SCLK Pad Drive Strength (default=1)
// 5:4 I2S_DOUT I2S DOUT Pad Drive Strength (default=1)
// 3:2 CTRL_DATA I2C DATA Pad Drive Strength (default=3)
// 1:0 CTRL_CLK I2C CLK Pad Drive Strength (default=3)
// (all use same table as I2S_LRCLK)
#define CHIP_ANA_ADC_CTRL 0x0020
// 8 ADC_VOL_M6DB ADC Volume Range Reduction
// This bit shifts both right and left analog ADC volume
// range down by 6.0 dB.
// 0x0 = No change in ADC range
// 0x1 = ADC range reduced by 6.0 dB
// 7:4 ADC_VOL_RIGHT ADC Right Channel Volume
// Right channel analog ADC volume control in 1.5 dB steps.
// 0x0 = 0 dB
// 0x1 = +1.5 dB
// ...
// 0xF = +22.5 dB
// This range is -6.0 dB to +16.5 dB if ADC_VOL_M6DB is set to 1.
// 3:0 ADC_VOL_LEFT ADC Left Channel Volume
// (same scale as ADC_VOL_RIGHT)
#define CHIP_ANA_HP_CTRL 0x0022
// 14:8 HP_VOL_RIGHT Headphone Right Channel Volume (default 0x18)
// Right channel headphone volume control with 0.5 dB steps.
// 0x00 = +12 dB
// 0x01 = +11.5 dB
// 0x18 = 0 dB
// ...
// 0x7F = -51.5 dB
// 6:0 HP_VOL_LEFT Headphone Left Channel Volume (default 0x18)
// (same scale as HP_VOL_RIGHT)
#define CHIP_ANA_CTRL 0x0024
// 8 MUTE_LO LINEOUT Mute, 0 = Unmute, 1 = Mute (default 1)
// 6 SELECT_HP Select the headphone input, 0 = DAC, 1 = LINEIN
// 5 EN_ZCD_HP Enable the headphone zero cross detector (ZCD)
// 0x0 = HP ZCD disabled
// 0x1 = HP ZCD enabled
// 4 MUTE_HP Mute the headphone outputs, 0 = Unmute, 1 = Mute (default)
// 2 SELECT_ADC Select the ADC input, 0 = Microphone, 1 = LINEIN
// 1 EN_ZCD_ADC Enable the ADC analog zero cross detector (ZCD)
// 0x0 = ADC ZCD disabled
// 0x1 = ADC ZCD enabled
// 0 MUTE_ADC Mute the ADC analog volume, 0 = Unmute, 1 = Mute (default)
#define CHIP_LINREG_CTRL 0x0026
// 6 VDDC_MAN_ASSN Determines chargepump source when VDDC_ASSN_OVRD is set.
// 0x0 = VDDA
// 0x1 = VDDIO
// 5 VDDC_ASSN_OVRD Charge pump Source Assignment Override
// 0x0 = Charge pump source is automatically assigned based
// on higher of VDDA and VDDIO
// 0x1 = the source of charge pump is manually assigned by
// VDDC_MAN_ASSN If VDDIO and VDDA are both the same
// and greater than 3.1 V, VDDC_ASSN_OVRD and
// VDDC_MAN_ASSN should be used to manually assign
// VDDIO as the source for charge pump.
// 3:0 D_PROGRAMMING Sets the VDDD linear regulator output voltage in 50 mV steps.
// Must clear the LINREG_SIMPLE_POWERUP and STARTUP_POWERUP bits
// in the 0x0030 (CHIP_ANA_POWER) register after power-up, for
// this setting to produce the proper VDDD voltage.
// 0x0 = 1.60
// 0xF = 0.85
#define CHIP_REF_CTRL 0x0028 // bandgap reference bias voltage and currents
// 8:4 VAG_VAL Analog Ground Voltage Control
// These bits control the analog ground voltage in 25 mV steps.
// This should usually be set to VDDA/2 or lower for best
// performance (maximum output swing at minimum THD). This VAG
// reference is also used for the DAC and ADC voltage reference.
// So changing this voltage scales the output swing of the DAC
// and the output signal of the ADC.
// 0x00 = 0.800 V
// 0x1F = 1.575 V
// 3:1 BIAS_CTRL Bias control
// These bits adjust the bias currents for all of the analog
// blocks. By lowering the bias current a lower quiescent power
// is achieved. It should be noted that this mode can affect
// performance by 3-4 dB.
// 0x0 = Nominal
// 0x1-0x3=+12.5%
// 0x4=-12.5%
// 0x5=-25%
// 0x6=-37.5%
// 0x7=-50%
// 0 SMALL_POP VAG Ramp Control
// Setting this bit slows down the VAG ramp from ~200 to ~400 ms
// to reduce the startup pop, but increases the turn on/off time.
// 0x0 = Normal VAG ramp
// 0x1 = Slow down VAG ramp
#define CHIP_MIC_CTRL 0x002A // microphone gain & internal microphone bias
// 9:8 BIAS_RESISTOR MIC Bias Output Impedance Adjustment
// Controls an adjustable output impedance for the microphone bias.
// If this is set to zero the micbias block is powered off and
// the output is highZ.
// 0x0 = Powered off
// 0x1 = 2.0 kohm
// 0x2 = 4.0 kohm
// 0x3 = 8.0 kohm
// 6:4 BIAS_VOLT MIC Bias Voltage Adjustment
// Controls an adjustable bias voltage for the microphone bias
// amp in 250 mV steps. This bias voltage setting should be no
// more than VDDA-200 mV for adequate power supply rejection.
// 0x0 = 1.25 V
// ...
// 0x7 = 3.00 V
// 1:0 GAIN MIC Amplifier Gain
// Sets the microphone amplifier gain. At 0 dB setting the THD
// can be slightly higher than other paths- typically around
// ~65 dB. At other gain settings the THD are better.
// 0x0 = 0 dB
// 0x1 = +20 dB
// 0x2 = +30 dB
// 0x3 = +40 dB
#define CHIP_LINE_OUT_CTRL 0x002C
// 11:8 OUT_CURRENT Controls the output bias current for the LINEOUT amplifiers. The
// nominal recommended setting for a 10 kohm load with 1.0 nF load cap
// is 0x3. There are only 5 valid settings.
// 0x0=0.18 mA
// 0x1=0.27 mA
// 0x3=0.36 mA
// 0x7=0.45 mA
// 0xF=0.54 mA
// 5:0 LO_VAGCNTRL LINEOUT Amplifier Analog Ground Voltage
// Controls the analog ground voltage for the LINEOUT amplifiers
// in 25 mV steps. This should usually be set to VDDIO/2.
// 0x00 = 0.800 V
// ...
// 0x1F = 1.575 V
// ...
// 0x23 = 1.675 V
// 0x24-0x3F are invalid
#define CHIP_LINE_OUT_VOL 0x002E
// 12:8 LO_VOL_RIGHT LINEOUT Right Channel Volume (default=4)
// Controls the right channel LINEOUT volume in 0.5 dB steps.
// Higher codes have more attenuation.
// 4:0 LO_VOL_LEFT LINEOUT Left Channel Output Level (default=4)
// Used to normalize the output level of the left line output
// to full scale based on the values used to set
// LINE_OUT_CTRL->LO_VAGCNTRL and CHIP_REF_CTRL->VAG_VAL.
// In general this field should be set to:
// 40*log((VAG_VAL)/(LO_VAGCNTRL)) + 15
// Suggested values based on typical VDDIO and VDDA voltages.
// VDDA VAG_VAL VDDIO LO_VAGCNTRL LO_VOL_*
// 1.8 V 0.9 3.3 V 1.55 0x06
// 1.8 V 0.9 1.8 V 0.9 0x0F
// 3.3 V 1.55 1.8 V 0.9 0x19
// 3.3 V 1.55 3.3 V 1.55 0x0F
// After setting to the nominal voltage, this field can be used
// to adjust the output level in +/-0.5 dB increments by using
// values higher or lower than the nominal setting.
#define CHIP_ANA_POWER 0x0030 // power down controls for the analog blocks.
// The only other power-down controls are BIAS_RESISTOR in the MIC_CTRL register
// and the EN_ZCD control bits in ANA_CTRL.
// 14 DAC_MONO While DAC_POWERUP is set, this allows the DAC to be put into left only
// mono operation for power savings. 0=mono, 1=stereo (default)
// 13 LINREG_SIMPLE_POWERUP Power up the simple (low power) digital supply regulator.
// After reset, this bit can be cleared IF VDDD is driven
// externally OR the primary digital linreg is enabled with
// LINREG_D_POWERUP
// 12 STARTUP_POWERUP Power up the circuitry needed during the power up ramp and reset.
// After reset this bit can be cleared if VDDD is coming from
// an external source.
// 11 VDDC_CHRGPMP_POWERUP Power up the VDDC charge pump block. If neither VDDA or VDDIO
// is 3.0 V or larger this bit should be cleared before analog
// blocks are powered up.
// 10 PLL_POWERUP PLL Power Up, 0 = Power down, 1 = Power up
// When cleared, the PLL is turned off. This must be set before
// CHIP_CLK_CTRL->MCLK_FREQ is programmed to 0x3. The
// CHIP_PLL_CTRL register must be configured correctly before
// setting this bit.
// 9 LINREG_D_POWERUP Power up the primary VDDD linear regulator, 0 = Power down, 1 = Power up
// 8 VCOAMP_POWERUP Power up the PLL VCO amplifier, 0 = Power down, 1 = Power up
// 7 VAG_POWERUP Power up the VAG reference buffer.
// Setting this bit starts the power up ramp for the headphone
// and LINEOUT. The headphone (and/or LINEOUT) powerup should
// be set BEFORE clearing this bit. When this bit is cleared
// the power-down ramp is started. The headphone (and/or LINEOUT)
// powerup should stay set until the VAG is fully ramped down
// (200 to 400 ms after clearing this bit).
// 0x0 = Power down, 0x1 = Power up
// 6 ADC_MONO While ADC_POWERUP is set, this allows the ADC to be put into left only
// mono operation for power savings. This mode is useful when
// only using the microphone input.
// 0x0 = Mono (left only), 0x1 = Stereo
// 5 REFTOP_POWERUP Power up the reference bias currents
// 0x0 = Power down, 0x1 = Power up
// This bit can be cleared when the part is a sleep state
// to minimize analog power.
// 4 HEADPHONE_POWERUP Power up the headphone amplifiers
// 0x0 = Power down, 0x1 = Power up
// 3 DAC_POWERUP Power up the DACs
// 0x0 = Power down, 0x1 = Power up
// 2 CAPLESS_HEADPHONE_POWERUP Power up the capless headphone mode
// 0x0 = Power down, 0x1 = Power up
// 1 ADC_POWERUP Power up the ADCs
// 0x0 = Power down, 0x1 = Power up
// 0 LINEOUT_POWERUP Power up the LINEOUT amplifiers
// 0x0 = Power down, 0x1 = Power up
#define CHIP_PLL_CTRL 0x0032
// 15:11 INT_DIVISOR
// 10:0 FRAC_DIVISOR
#define CHIP_CLK_TOP_CTRL 0x0034
// 11 ENABLE_INT_OSC Setting this bit enables an internal oscillator to be used for the
// zero cross detectors, the short detect recovery, and the
// charge pump. This allows the I2S clock to be shut off while
// still operating an analog signal path. This bit can be kept
// on when the I2S clock is enabled, but the I2S clock is more
// accurate so it is preferred to clear this bit when I2S is present.
// 3 INPUT_FREQ_DIV2 SYS_MCLK divider before PLL input
// 0x0 = pass through
// 0x1 = SYS_MCLK is divided by 2 before entering PLL
// This must be set when the input clock is above 17 Mhz. This
// has no effect when the PLL is powered down.
#define CHIP_ANA_STATUS 0x0036
// 9 LRSHORT_STS This bit is high whenever a short is detected on the left or right
// channel headphone drivers.
// 8 CSHORT_STS This bit is high whenever a short is detected on the capless headphone
// common/center channel driver.
// 4 PLL_IS_LOCKED This bit goes high after the PLL is locked.
#define CHIP_ANA_TEST1 0x0038 // intended only for debug.
#define CHIP_ANA_TEST2 0x003A // intended only for debug.
#define CHIP_SHORT_CTRL 0x003C
// 14:12 LVLADJR Right channel headphone short detector in 25 mA steps.
// 0x3=25 mA
// 0x2=50 mA
// 0x1=75 mA
// 0x0=100 mA
// 0x4=125 mA
// 0x5=150 mA
// 0x6=175 mA
// 0x7=200 mA
// This trip point can vary by ~30% over process so leave plenty
// of guard band to avoid false trips. This short detect trip
// point is also effected by the bias current adjustments made
// by CHIP_REF_CTRL->BIAS_CTRL and by CHIP_ANA_TEST1->HP_IALL_ADJ.
// 10:8 LVLADJL Left channel headphone short detector in 25 mA steps.
// (same scale as LVLADJR)
// 6:4 LVLADJC Capless headphone center channel short detector in 50 mA steps.
// 0x3=50 mA
// 0x2=100 mA
// 0x1=150 mA
// 0x0=200 mA
// 0x4=250 mA
// 0x5=300 mA
// 0x6=350 mA
// 0x7=400 mA
// 3:2 MODE_LR Behavior of left/right short detection
// 0x0 = Disable short detector, reset short detect latch,
// software view non-latched short signal
// 0x1 = Enable short detector and reset the latch at timeout
// (every ~50 ms)
// 0x2 = This mode is not used/invalid
// 0x3 = Enable short detector with only manual reset (have
// to return to 0x0 to reset the latch)
// 1:0 MODE_CM Behavior of capless headphone central short detection
// (same settings as MODE_LR)
#define DAP_CONTROL 0x0100
#define DAP_PEQ 0x0102
#define DAP_BASS_ENHANCE 0x0104
#define DAP_BASS_ENHANCE_CTRL 0x0106
#define DAP_AUDIO_EQ 0x0108
#define DAP_SGTL_SURROUND 0x010A
#define DAP_FILTER_COEF_ACCESS 0x010C
#define DAP_COEF_WR_B0_MSB 0x010E
#define DAP_COEF_WR_B0_LSB 0x0110
#define DAP_AUDIO_EQ_BASS_BAND0 0x0116 // 115 Hz
#define DAP_AUDIO_EQ_BAND1 0x0118 // 330 Hz
#define DAP_AUDIO_EQ_BAND2 0x011A // 990 Hz
#define DAP_AUDIO_EQ_BAND3 0x011C // 3000 Hz
#define DAP_AUDIO_EQ_TREBLE_BAND4 0x011E // 9900 Hz
#define DAP_MAIN_CHAN 0x0120
#define DAP_MIX_CHAN 0x0122
#define DAP_AVC_CTRL 0x0124
#define DAP_AVC_THRESHOLD 0x0126
#define DAP_AVC_ATTACK 0x0128
#define DAP_AVC_DECAY 0x012A
#define DAP_COEF_WR_B1_MSB 0x012C
#define DAP_COEF_WR_B1_LSB 0x012E
#define DAP_COEF_WR_B2_MSB 0x0130
#define DAP_COEF_WR_B2_LSB 0x0132
#define DAP_COEF_WR_A1_MSB 0x0134
#define DAP_COEF_WR_A1_LSB 0x0136
#define DAP_COEF_WR_A2_MSB 0x0138
#define DAP_COEF_WR_A2_LSB 0x013A
#define SGTL5000_I2C_ADDR_CS_LOW 0x0A // CTRL_ADR0_CS pin low (normal configuration)
#define SGTL5000_I2C_ADDR_CS_HIGH 0x2A // CTRL_ADR0_CS pin high
unsigned char sgtl5000_enable(void);
unsigned char sgtl5000_setVolume(float val);
#endif