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xidameng 2020-07-31 22:16:12 +08:00
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21
sdk/component/soc/realtek/amebad/app/monitor/include/monitor_rom.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _MONITOR_LIB_H_
#define _MONITOR_LIB_H_
_LONG_CALL_ extern u32 cmd_dump_word(u16 argc, u8 *argv[]);
_LONG_CALL_ extern u32 cmd_write_word(u16 argc, u8 *argv[]);
_LONG_CALL_ extern u32 cmd_flash(u16 argc, u8 *argv[]);
_LONG_CALL_ extern u32 cmd_efuse(u16 argc, u8 *argv[]);
_LONG_CALL_ u32 cmd_rom_table(void** PTable);
#define CmdDumpWord cmd_dump_word
#define CmdWriteWord cmd_write_word
#endif

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sdk/component/soc/realtek/amebad/app/monitor/include/rtl_trace.h Normal file
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/**
******************************************************************************
* @file rtl_trace.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions for log print and mask.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
u32 LOG_PRINTF_BUFFER(const char *fmt);
u32 LOG_PRINTF_BUFFER_INIT(u32 thread_init);
u32 LOG_BUFF_SUSPEND(void);
u32 LOG_BUFF_RESUME(void);
#define LOG_BUFFER_NUM 6
#define LOG_BUFFER_SIZE 512
typedef struct {
char buffer[LOG_BUFFER_SIZE];
/* please define member after buffer */
} log_buffer_t;
extern log_buffer_t log_buffer[];
typedef u32 (*DIAG_PRINT_BUF_FUNC)(const char *fmt);
extern DIAG_PRINT_BUF_FUNC ConfigDebugBufferGet;
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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sdk/component/soc/realtek/amebad/app/monitor/include/shell.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTK_CONSOL_H_
#define _RTK_CONSOL_H_
//Log UART
//UART_LOG_CMD_BUFLEN: only 126 bytes could be used for keeping input
// cmd, the last byte is for string end ('\0').
#define UART_LOG_CMD_BUFLEN 127
#define MAX_ARGV 16
typedef u32 (*ECHOFUNC)(IN u8*,...); //UART LOG echo-function type.
typedef u32 (*monitor_cmd_handler)(u16 argc, u8* argv[]);
typedef struct {
u8 BufCount; //record the input cmd char number.
u8 UARTLogBuf[UART_LOG_CMD_BUFLEN]; //record the input command.
} UART_LOG_BUF, *PUART_LOG_BUF;
typedef struct _COMMAND_TABLE_ {
const u8* cmd;
u16 ArgvCnt;
u32 (*func)(u16 argc, u8* argv[]);
const u8* msg;
}COMMAND_TABLE, *PCOMMAND_TABLE;
typedef struct {
u8 NewIdx;
u8 SeeIdx;
u8 RevdNo;
u8 EscSTS;
u8 ExecuteCmd;
u8 ExecuteEsc;
u8 BootRdy;
u8 Resvd;
PUART_LOG_BUF pTmpLogBuf;
VOID *pfINPUT;
PCOMMAND_TABLE pCmdTbl;
u32 CmdTblSz;
u32 CRSTS;
#ifdef CONFIG_UART_LOG_HISTORY
u8 (*pHistoryBuf)[UART_LOG_CMD_BUFLEN];
#endif
void (*GiveSema)(void);
u32 shell_task_rdy;
} UART_LOG_CTL, *PUART_LOG_CTL;
#define KB_ASCII_NUL 0x00
#define KB_ASCII_BS 0x08
#define KB_ASCII_TAB 0x09
#define KB_ASCII_LF 0x0A
#define KB_ASCII_CR 0x0D
#define KB_ASCII_ESC 0x1B
#define KB_ASCII_SP 0x20
#define KB_ASCII_BS_7F 0x7F
#define KB_ASCII_LBRKT 0x5B //[
#define KB_SPACENO_TAB 1
#ifdef CONFIG_UART_LOG_HISTORY
#define UART_LOG_HISTORY_LEN 5
#endif
//#ifdef CONFIG_DEBUG_LOG
#define _ConsolePrint DiagPrintf
//#else
//#define _ConsolePrint
//#endif
#define AMEBA_CONSOLE_PREFIX "#"
#define CONSOLE_AMEBA(...) do {\
_ConsolePrint("\r" AMEBA_CONSOLE_PREFIX __VA_ARGS__);\
}while(0)
_LONG_CALL_ VOID shell_init_rom(u32 TBLSz, VOID *pTBL);
_LONG_CALL_ VOID shell_task_rom(VOID *Data);
_LONG_CALL_ VOID shell_rom(u32 MaxWaitCount);
_LONG_CALL_ void shell_uart_irq_rom(void * Data);
_LONG_CALL_
extern VOID
shell_cmd_history(
IN u8 RevData,
IN UART_LOG_CTL *prvUartLogCtl,
IN u8 EchoFlag
);
_LONG_CALL_
extern u8
shell_cmd_chk(
IN u8 RevData,
IN UART_LOG_CTL *prvUartLogCtl,
IN u8 EchoFlag
);
_LONG_CALL_
extern VOID
shell_array_init(
IN u8 *pArrayToInit,
IN u8 ArrayLen,
IN u8 InitValue
);
extern u8** shell_get_argv(const u8 *string);
extern u8 shell_get_argc(const u8 *string);
VOID shell_init_ram(VOID);
void shell_switch_ipc_int(VOID *Data, u32 IrqStatus, u32 ChanNum);
#define RtlConsolTaskRom shell_task_rom
extern u32 shell_recv_all_data_onetime;
extern u32 shell_interrupt_on;
#endif //_RTK_CONSOL_H_

18
sdk/component/soc/realtek/amebad/app/touch_key/touch_key.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _TOUCH_KEY_H_
#define _TOUCH_KEY_H_
void app_hp_jack_init(void);
void app_captouch_init(void);
void app_keyscan_init(u8 reset_status);
#endif /* _RCU_STIMULI_H_ */

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sdk/component/soc/realtek/amebad/app/xmodem/xmodem_rom.h Normal file
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/*
X-Modem Header File
1999/09/03 sprite, support Xmode Tx & Rx
*/
#ifndef _XMODE_H_
#define _XMODE_H_
#include <basic_types.h>
/*****************
* X-Modem status
*****************/
#define XMODEM_OK 1
#define XMODEM_CANCEL 2
#define XMODEM_ACK 3
#define XMODEM_NAK 4
#define XMODEM_COMPLETE 5
#define XMODEM_NO_SESSION 6
#define XMODEM_ABORT 7
#define XMODEM_TIMEOUT 8
/****************************
* flow control character
****************************/
#define SOH 0x01 /* Start of header */
#define STX 0x02 /* Start of header XModem-1K */
#define EOT 0x04 /* End of transmission */
#define ACK 0x06 /* Acknowledge */
#define NAK 0x15 /* Not acknowledge */
#define CAN 0x18 /* Cancel */
#define ESC 0x1b /* User Break */
#define BAUDSET 0x05 /* Part of shakehands, added by Realtek*/
#define BAUDCHK 0x07 /* Part of shakehands, added by Realtek*/
#define XMERASE 0x17 /* Erase Flash, added by Realtek*/
#define XMREAD 0x19 /* Read Flash, added by Realtek*/
#define XMREADV2 0x20 /* Read Flash, added by Realtek*/
#define RXSTATUS 0x21 /* Read Status Register, added by Realtek*/
#define TXSTATUS 0x26 /* Write Status Register, added by Realtek, AZ ACUT ROM not support*/
#define XM_CHECKSUM 0x27 /* check flash write checksum: AZ ACUT ROM not support */
#define XM_TXREG 0x29 /* Write REG or RAM, AZ ACUT ROM not support */
#define XM_RXREG 0x31 /* Read REG or RAM, AZ ACUT ROM not support */
#define XM_ROMVER 0x33 /* read rom code version(02/03/04...): AZ ACUT ROM not support */
/****************************
* Xmode paramters
****************************/
#define FRAME_SIZE 132 /* X-modem structure */
#define FRAME_SIZE_1K 1028 /* X-modem structure */
#define XM_BUFFER_SIZE 1024 /* X-modem buffer */
#define WAIT_FRAME_TIME (830 * 1000) /* 1 sec, wait frame timeout, AmebaZ SMIC: (2500 * 10000), AmebaZ UMC: (2500 * 1000)*/
#define WAIT_CHAR_TIME (415 * 1000) /* 0.5 sec, wait char timeout AmebaZ SMIC: (1250 * 10000), AmebaZ UMC: (1250 * 1000)*/
#define WAIT_HANDSHAKE_TIME (1660 * 1000) /* 2 sec, handshake timeout AmebaZ SMIC: (2500 * 10000), AmebaZ UMC: (1250 * 1000)*/
#define XMODEM_READ_MAXRETRANS 25
/***********************
* frame structure
***********************/
typedef struct
{
unsigned char soh;
unsigned char recordNo;
unsigned char recordNoInverted;
unsigned char buffer[XM_BUFFER_SIZE];
unsigned char CRC;
} XMODEM_FRAME;
typedef struct _XMODEM_CTRL_ {
u16 currentFrame; /* current frame number */
u16 expected;
s32 rFinish;
u32 total_frame;
}XMODEM_CTRL, *PXMODEM_CTRL;
u32 xmodem_img_rxbuffer(u32 baud_rate);
/* wll define in section header later */
#define FWU_DATA_SECTION
#endif /* _XMODE_H_ */

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sdk/component/soc/realtek/amebad/app/xmodem/xmodem_uart_rom.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _XMPORT_UART_H_
#define _XMPORT_UART_H_
struct _xmodem_uart_map {
void (*xmodem_uart_init)(u8 uart_idx, u8 pin_mux, u32 baud_rate);
void (*xmodem_uart_deinit)(void);
void (*xmodem_uart_port_init)(u8 uart_idx, u8 pin_mux, u32 baud_rate);
void (*xmodem_uart_port_deinit)(u8 uart_idx);
char (*xmodem_uart_readable)(void);
char (*xmodem_uart_writable)(void);
char (*xmodem_uart_getc)(void);
void (*xmodem_uart_putc)(char c);
void (*xmodem_uart_putdata)(u8* buf, u32 cnt);
char (*xmodem_uart_getc_to)(char *pch, u32 timeout);
void (*xmodem_uart_clean_rx)(void);
};
extern UART_TypeDef* xmodem_uartx;
_LONG_CALL_ void xmodem_uart_init(u8 uart_idx, u8 pin_mux, u32 baud_rate);
_LONG_CALL_ void xmodem_uart_deinit(void) ;
_LONG_CALL_ void xmodem_uart_port_init(u8 uart_idx, u8 pin_mux, u32 baud_rate);
_LONG_CALL_ void xmodem_uart_port_deinit(u8 uart_idx);
_LONG_CALL_ char xmodem_uart_readable(void) ;
_LONG_CALL_ char xmodem_uart_writable(void) ;
_LONG_CALL_ char xmodem_uart_getc(void) ;
_LONG_CALL_ void xmodem_uart_putc(char c) ;
_LONG_CALL_ void xmodem_uart_putdata(u8* buf, u32 cnt) ;
_LONG_CALL_ char xmodem_uart_getc_to(char *pch, u32 timeout);
_LONG_CALL_ void xmodem_uart_clean_rx(void);
#endif // end of "#define _XMPORT_UART_H_"

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sdk/component/soc/realtek/amebad/app/xmodem/xmodem_update_rom.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _FW_UPDATE_ROM_H_
#define _FW_UPDATE_ROM_H_
#include "ameba_soc.h"
#define BOOT_UART_IDX 0
#define BOOT_UART_PIN_MUX 1
#define BOOT_UART_BAUD_RATE 38400
#define BOOT_UART_MAX_IMG_SZ (32*1024*1024) // 32M
extern VOID xmodem_img_write(char *ptr, unsigned int wr_offset, unsigned int frame_size);
extern VOID xmodem_img_download(u8 uart_idx);
#endif // end of "#define _FW_UPDATE_ROM_H_"

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sdk/component/soc/realtek/amebad/cmsis/arm_common_tables.h Normal file
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/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
* Description: Extern declaration for common tables
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

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sdk/component/soc/realtek/amebad/cmsis/arm_const_structs.h Normal file
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/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
* Description: Constant structs that are initialized for user convenience.
* For example, some can be given as arguments to the arm_cfft_f32() function.
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

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sdk/component/soc/realtek/amebad/cmsis/arm_math.h Normal file
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38
sdk/component/soc/realtek/amebad/cmsis/cmsis.h Normal file
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/* mbed Microcontroller Library
* A generic CMSIS include header
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "ameba_soc.h"
#include "cmsis_nvic.h"
#endif

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V5.00
* @date 09. November 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* ARM Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* ARM Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#include <cmsis_iar.h>
#ifndef __NO_RETURN
#define __NO_RETURN __noreturn
#endif
#ifndef __USED
#define __USED __root
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __UNALIGNED_UINT32
__packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
/*
* TI ARM Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __UNALIGNED_UINT32
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
// CORE: 64 vectors = 64 bytes from 0x00 to 0x3F
// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to ...
// Total: 128 vectors = 512 bytes (0x200) to be reserved in RAM
#define NVIC_NUM_VECTORS 128
#define NVIC_USER_IRQ_OFFSET 16
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

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/**************************************************************************//**
* @file core_cache.h
* @brief Realtek TM4 TM0 CMSIS Core Peripheral Access Layer Header File
* @version V5.0.1
* @date 25. November 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CORE_CACHE_H
#define __CORE_CACHE_H
#ifdef __cplusplus
extern "C" {
#endif
#define __ICACHE_PRESENT 1U
#define __DCACHE_PRESENT 1U
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 0U
#warning "__ICACHE_PRESENT not defined in device header file; using default!"
#endif
#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 0U
#warning "__DCACHE_PRESENT not defined in device header file; using default!"
#endif
#endif
/* ########################## Cache functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/* Cache Size ID Register Macros */
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_INLINE void SCB_EnableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_INLINE void SCB_DisableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_INLINE void SCB_InvalidateICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->ICIALLU = 0UL;
__DSB();
__ISB();
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
*/
__STATIC_INLINE void SCB_EnableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
*/
__STATIC_INLINE void SCB_DisableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
register uint32_t ccsidr;
register uint32_t sets;
register uint32_t ways;
SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
__DSB();
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
*/
__STATIC_INLINE void SCB_InvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
*/
__STATIC_INLINE void SCB_CleanDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
*/
__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize;
uint32_t op_addr = (uint32_t)addr;
int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
__DSB();
while (op_size > 0) {
SCB->DCIMVAC = op_addr;
op_addr += (uint32_t)linesize;
op_size -= linesize;
}
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize;
uint32_t op_addr = (uint32_t) addr;
int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
__DSB();
while (op_size > 0) {
SCB->DCCMVAC = op_addr;
op_addr += (uint32_t)linesize;
op_size -= linesize;
}
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize;
uint32_t op_addr = (uint32_t) addr;
int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
__DSB();
while (op_size > 0) {
SCB->DCCIMVAC = op_addr;
op_addr += (uint32_t)linesize;
op_size -= linesize;
}
__DSB();
__ISB();
#endif
}
/*@} end of CMSIS_Core_CacheFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CACHE_H */

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

793
sdk/component/soc/realtek/amebad/cmsis/core_cm0plus.h Normal file
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@ -0,0 +1,793 @@
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex-M0+
@{
*/
/* CMSIS CM0P definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
__CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1)
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/** \brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file core_cm4_simd.h
* @brief CMSIS Cortex-M4 SIMD Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM4_SIMD_H
#define __CORE_CM4_SIMD_H
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32) ) >> 32))
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#include <cmsis_iar.h>
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#include <cmsis_ccs.h>
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SMLALD(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
#define __SMLALDX(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SMLSLD(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
#define __SMLSLDX(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
/* not yet supported */
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CORE_CM4_SIMD_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.20
* @date 05. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/**************************************************************************//**
* @file mpu.h
* @brief Defines macros for the MPU registers seting.
*
* @version V1.00
* @date 2017-03-21
*
* @note
*
******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef _MPU_H_
#define _MPU_H_
/**
\brief The data structure for a MPU region configuration
*/
typedef struct {
uint32_t region_base; /*!< MPU region base, 32 bytes aligned. */
uint32_t region_size; /*!< MPU region size, 32 bytes aligned. */
uint8_t xn; /*!< eXecute Never attribute. This parameter can be a value of @ref mpu_region_config_xn_define. */
uint8_t ap; /*!< Access permissions. This parameter can be a value of @ref mpu_region_config_ap_define. */
uint8_t sh; /*!< Shareability for Normal memory. This parameter can be a value of @ref mpu_region_config_sh_define. */
uint8_t attr_idx; /*!< memory attribute indirect index. This parameter can be a value of 0~7. */
} mpu_region_config;
/** @defgroup mpu_region_config_xn_define
* @{
* note: eXecute Never attribute(MPU_RBAR[0]):
* 0: Allow program execution in this region.
* 1: Does not allow program execution in this region.
*/
#define MPU_EXEC_ALLOW 0
#define MPU_EXEC_NEVER 1
/**
* @}
*/
/** @defgroup mpu_region_config_ap_define
* @{
* note: Access permissions (MPU_RBAR[2:1]):
* 00: Read/write by privileged code only.
* 01: Read/write by any privilege level.
* 10: Read only by privileged code only.
* 11: Read only by any privilege level.
*/
#define MPU_PRIV_RW (0 << 1)
#define MPU_UN_PRIV_RW (1 << 1)
#define MPU_PRIV_R (2 << 1)
#define MPU_PRIV_W (3 << 1)
/**
* @}
*/
/** @defgroup mpu_region_config_sh_define
* @{
* note: Shareability for Normal memory(MPU_RBAR[4:3]):
* 00: Non-shareable.
* 01: Reserved.
* 10: Outer shareable.
* 11: Inner shareable.
*/
#define MPU_NON_SHAREABLE (0 << 3)
#define MPU_OUT_SHAREABLE (2 << 3)
#define MPU_INR_SHAREABLE (3 << 3)
/**
* @}
*/
#if defined (ARM_CORE_CM4)
#define MPU_MAX_REGION 8
#else
#define MPU_MAX_REGION 4
#endif
/** @defgroup mpu_region_memory_attribute_define
* @{
* note: Outer, bits [7:4]:
* 0b0000 Device memory.
* 0b00RW Normal memory, Outer write-through transient (RW!='00').
* 0b0100 Normal memory, Outer non-cacheable.
* 0b01RW Normal memory, Outer write-back transient (RW!='00').
* 0b10RW Normal memory, Outer write-through non-transient.
* 0b11RW Normal memory, Outer write-back non-transient.
* note: The transient attribute indicates that the benefit of caching is for a relatively short period,
* and that therefore it might be better to restrict allocation, to avoid possibly casting-out other,
* less transient, entries.
* note: Inner, bits [3:0], when Outer != '0000'
* 0b00RW Normal memory, Inner write-through transient (RW!='00').
* 0b0100 Normal memory, Inner non-cacheable.
* 0b01RW Normal memory, Inner write-back transient (RW!='00').
* 0b10RW Normal memory, Inner write-through non-transient.
* 0b11RW Normal memory, Inner write-back non-transient
*/
// define memory attribute of Normal memory with write-through transient, write allocation
#define NORMAL_WT_T_WA (0x01)
// define memory attribute of Normal memory with write-through transient, read allocation
#define NORMAL_WT_T_RA (0x02)
// define memory attribute of Normal memory with write-through transient, read & write allocation
#define NORMAL_WT_T_RWA (0x03)
// define memory attribute of Normal memory with non-cacheable
#define NORMAL_NC (0x04)
// define memory attribute of Normal memory with write-back transient, write allocation
#define NORMAL_WB_T_WA (0x05)
// define memory attribute of Normal memory with write-back transient, read allocation
#define NORMAL_WB_T_RA (0x06)
// define memory attribute of Normal memory with write-back transient, read and write allocation
#define NORMAL_WB_T_RWA (0x07)
// define memory attribute of Normal memory with write-through non-transient, no allocation
#define NORMAL_WT_NT (0x08)
// define memory attribute of Normal memory with write-through non-transient, write allocation
#define NORMAL_WT_NT_WA (0x09)
// define memory attribute of Normal memory with write-through non-transient, read allocation
#define NORMAL_WT_NT_RA (0x0A)
// define memory attribute of Normal memory with write-through non-transient, read and write allocation
#define NORMAL_WT_NT_RWA (0x0B)
// define memory attribute of Normal memory with write-back non-transient, no allocation
#define NORMAL_WB_NT (0x0C)
// define memory attribute of Normal memory with write-back non-transient, write allocation
#define NORMAL_WB_NT_WA (0x0D)
// define memory attribute of Normal memory with write-back non-transient, read allocation
#define NORMAL_WB_NT_RA (0x0E)
// define memory attribute of Normal memory with write-back non-transient, read and write allocation
#define NORMAL_WB_NT_RWA (0x0F)
/**
* @}
*/
/** @defgroup mpu_region_device_attribute_define
* @{
* note: Device, bits [3:2], when Outer == '0000':
* 0b00 Device-nGnRnE.
* 0b01 Device-nGnRE.
* 0b10 Device-nGRE.
* 0b11 Device-GRE.
*/
// define memory attribute of Device memory with non-gathering, non-reording, non-Early Write Acknowledge
#define DEVICE_NG_NR_NE ((0<<4)|(0<<2))
// define memory attribute of Device memory with non-gathering, non-reording, Early Write Acknowledge
#define DEVICE_NG_NR_E ((0<<4)|(1<<2))
// define memory attribute of Device memory with non-gathering, reording, Early Write Acknowledge
#define DEVICE_NG_R_E ((0<<4)|(2<<2))
// define memory attribute of Device memory with gathering, reording, Early Write Acknowledge
#define DEVICE_G_R_E ((0<<4)|(3<<2))
/**
* @}
*/
void mpu_init (void);
void mpu_set_mem_attr(uint8_t attr_idx, uint8_t mem_attr);
void mpu_region_cfg(uint8_t region_num, mpu_region_config *pmpu_cfg);
void mpu_enable(void);
void mpu_disable(void);
void mpu_entry_free(u32 entry_index);
char mpu_entry_alloc(void);
#endif //_MPU_H_

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/**************************************************************************//**
* @file mpu_config.c
* @brief Defines macros for the MPU configuration for the Secure region.
*
* @version V1.00
* @date 2017-03-21
*
* @note
*
******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef _MPU_CONFIG_S_H_
#define _MPU_CONFIG_S_H_
#include "mpu.h"
/** @defgroup mpu_config_define
* @{
* note: MPU_INIT_CTRL_ENABLE
* <q> Enable MPU
* <i> Value for MPU->CTRL register bit ENABLE
* <0=> MPU is disabled.
* <1=> MPU is enabled.
* note: MPU_INIT_CTRL_PRIVDEFENA
* <i> Value for MPU->CTRL register bit PRIVDEFENA
* Privileged background region enable:
* <0=> All accesses to unmapped addresses result in faults.
* <1=> Enables the default memory map for privilege code when the address accessed
* does not map into any MPU region. Unprivileged accesses to unmapped addresses
* result in faults.
* note: MPU_INIT_CTRL_HFNMIENA
* <i> Value for MPU->CTRL register bit HFNMIENA MPU Enable for HardFault and NMI (Non-Maskable Interrupt):
* <0=> HardFault and NMI handlers bypass MPU configuration as if MPU is disabled.
* <1=> MPU access rules apply to HardFault and NMI handlers.
*/
#define MPU_INIT_CTRL_ENABLE 1
#define MPU_INIT_CTRL_PRIVDEFENA 1
#define MPU_INIT_CTRL_HFNMIENA 0
/**
* @}
*/
/** @defgroup mpu_mem_attri_typical_define
* @{
* note: MPU_MEM_ATTR0~MPU_MEM_ATTR7
* no cache
* write-through + read allocation
* write-back + read allocation + write allocation
* <1=> MPU is enabled.
*/
#define MPU_MEM_ATTR0 ((NORMAL_NC << 4) | NORMAL_NC) // The memory attribute configuration of the MAIR[Attr0]
#define MPU_MEM_ATTR1 ((NORMAL_WT_T_RA << 4) | NORMAL_WT_T_RA) // The memory attribute configuration of the MAIR[Attr1]
#define MPU_MEM_ATTR2 ((NORMAL_WB_T_RWA << 4) | NORMAL_WB_T_RWA) // The memory attribute configuration of the MAIR[Attr2]
#define MPU_MEM_ATTR3 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr3]
#define MPU_MEM_ATTR4 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr4]
#define MPU_MEM_ATTR5 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr5]
#define MPU_MEM_ATTR6 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr6]
#define MPU_MEM_ATTR7 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr7]
#define MPU_MEM_ATTR_IDX_NC 0
#define MPU_MEM_ATTR_IDX_WT_T_RA 1
#define MPU_MEM_ATTR_IDX_WB_T_RWA 2
#define MPU_MEM_ATTR_IDX_DEVICE 3
/**
* @}
*/
#endif //_MPU_CONFIG_S_H_

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/**************************************************************************//**
* @file mpu_config.c
* @brief Defines macros for the MPU configuration for the Secure region.
*
* @version V1.00
* @date 2017-03-21
*
* @note
*
******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef _MPU_CONFIG_S_H_
#define _MPU_CONFIG_S_H_
#include "mpu.h"
/** @defgroup mpu_config_define
* @{
* note: MPU_INIT_CTRL_ENABLE
* <q> Enable MPU
* <i> Value for MPU->CTRL register bit ENABLE
* <0=> MPU is disabled.
* <1=> MPU is enabled.
* note: MPU_INIT_CTRL_PRIVDEFENA
* <i> Value for MPU->CTRL register bit PRIVDEFENA
* Privileged background region enable:
* <0=> All accesses to unmapped addresses result in faults.
* <1=> Enables the default memory map for privilege code when the address accessed
* does not map into any MPU region. Unprivileged accesses to unmapped addresses
* result in faults.
* note: MPU_INIT_CTRL_HFNMIENA
* <i> Value for MPU->CTRL register bit HFNMIENA MPU Enable for HardFault and NMI (Non-Maskable Interrupt):
* <0=> HardFault and NMI handlers bypass MPU configuration as if MPU is disabled.
* <1=> MPU access rules apply to HardFault and NMI handlers.
*/
#define MPU_INIT_CTRL_ENABLE 1
#define MPU_INIT_CTRL_PRIVDEFENA 1
#define MPU_INIT_CTRL_HFNMIENA 0
/**
* @}
*/
/** @defgroup mpu_mem_attri_typical_define
* @{
* note: MPU_MEM_ATTR0~MPU_MEM_ATTR7
* no cache
* write-through + read allocation
* write-back + read allocation + write allocation
* <1=> MPU is enabled.
*/
#define MPU_MEM_ATTR0 ((NORMAL_NC << 4) | NORMAL_NC) // The memory attribute configuration of the MAIR[Attr0]
#define MPU_MEM_ATTR1 ((NORMAL_WT_T_RA << 4) | NORMAL_WT_T_RA) // The memory attribute configuration of the MAIR[Attr1]
#define MPU_MEM_ATTR2 ((NORMAL_WB_T_RWA << 4) | NORMAL_WB_T_RWA) // The memory attribute configuration of the MAIR[Attr2]
#define MPU_MEM_ATTR3 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr3]
#define MPU_MEM_ATTR4 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr4]
#define MPU_MEM_ATTR5 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr5]
#define MPU_MEM_ATTR6 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr6]
#define MPU_MEM_ATTR7 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr7]
#define MPU_MEM_ATTR_IDX_NC 0
#define MPU_MEM_ATTR_IDX_WT_T_RA 1
#define MPU_MEM_ATTR_IDX_WB_T_RWA 2
#define MPU_MEM_ATTR_IDX_DEVICE 3
/**
* @}
*/
#endif //_MPU_CONFIG_S_H_

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/**************************************************************************//**
* @file mpu_config.c
* @brief Defines macros for the MPU configuration for the Secure region.
*
* @version V1.00
* @date 2017-03-21
*
* @note
*
******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef _MPU_CONFIG_S_H_
#define _MPU_CONFIG_S_H_
#include "mpu.h"
/** @defgroup mpu_config_define
* @{
* note: MPU_INIT_CTRL_ENABLE
* <q> Enable MPU
* <i> Value for MPU->CTRL register bit ENABLE
* <0=> MPU is disabled.
* <1=> MPU is enabled.
* note: MPU_INIT_CTRL_PRIVDEFENA
* <i> Value for MPU->CTRL register bit PRIVDEFENA
* Privileged background region enable:
* <0=> All accesses to unmapped addresses result in faults.
* <1=> Enables the default memory map for privilege code when the address accessed
* does not map into any MPU region. Unprivileged accesses to unmapped addresses
* result in faults.
* note: MPU_INIT_CTRL_HFNMIENA
* <i> Value for MPU->CTRL register bit HFNMIENA MPU Enable for HardFault and NMI (Non-Maskable Interrupt):
* <0=> HardFault and NMI handlers bypass MPU configuration as if MPU is disabled.
* <1=> MPU access rules apply to HardFault and NMI handlers.
*/
#define MPU_INIT_CTRL_ENABLE 1
#define MPU_INIT_CTRL_PRIVDEFENA 1
#define MPU_INIT_CTRL_HFNMIENA 0
/**
* @}
*/
/** @defgroup mpu_mem_attri_typical_define
* @{
* note: MPU_MEM_ATTR0~MPU_MEM_ATTR7
* no cache
* write-through + read allocation
* write-back + read allocation + write allocation
* <1=> MPU is enabled.
*/
#define MPU_MEM_ATTR0 ((NORMAL_NC << 4) | NORMAL_NC) // The memory attribute configuration of the MAIR[Attr0]
#define MPU_MEM_ATTR1 ((NORMAL_WT_T_RA << 4) | NORMAL_WT_T_RA) // The memory attribute configuration of the MAIR[Attr1]
#define MPU_MEM_ATTR2 ((NORMAL_WB_T_RWA << 4) | NORMAL_WB_T_RWA) // The memory attribute configuration of the MAIR[Attr2]
#define MPU_MEM_ATTR3 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr3]
#define MPU_MEM_ATTR4 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr4]
#define MPU_MEM_ATTR5 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr5]
#define MPU_MEM_ATTR6 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr6]
#define MPU_MEM_ATTR7 (DEVICE_NG_NR_NE) // The memory attribute configuration of the MAIR[Attr7]
#define MPU_MEM_ATTR_IDX_NC 0
#define MPU_MEM_ATTR_IDX_WT_T_RA 1
#define MPU_MEM_ATTR_IDX_WB_T_RWA 2
#define MPU_MEM_ATTR_IDX_DEVICE 3
/**
* @}
*/
#endif //_MPU_CONFIG_S_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _AMEBA_SOC_H_
#define _AMEBA_SOC_H_
/* rom headers */
#include "rtl8721d.h"
#include "rtl8721d_simulation.h"
#include "strproc.h"
#include "rtl8721dlp_km4.h"
#include "rtl8721d_captouch.h"
#ifndef CONFIG_BUILD_ROM
/* ram headers */
#include "platform_opts.h"
#include "rtl8721d_ota.h"
#ifdef PLATFORM_FREERTOS
#include "rtl8721d_freertos_pmu.h"
#include "freertos_pmu.h"
#include "FreeRTOS.h"
#include "task.h"
#if (tskKERNEL_VERSION_MAJOR>=10) && (tskKERNEL_VERSION_MINOR>=2)
#include "freertos_backtrace_ext.h"
#include "freertos_heap5_config.h"
#endif
#include "semphr.h"
#endif
#endif
#endif //_AMEBA_SOC_H_

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __BASIC_TYPES_H__
#define __BASIC_TYPES_H__
//#define PLATFORM_FREERTOS
#include <stdint.h>
#include <stddef.h> /* for size_t */
#define PLATFORM_LITTLE_ENDIAN 0
#define PLATFORM_BIG_ENDIAN 1
#define SYSTEM_ENDIAN PLATFORM_LITTLE_ENDIAN
#define SUCCESS 0
#define FAIL (-1)
#undef _SUCCESS
#define _SUCCESS 1
#undef _FAIL
#define _FAIL 0
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE (!FALSE)
#endif
#define _TRUE TRUE
#define _FALSE FALSE
#ifndef NULL
#define NULL 0
#endif
#ifdef __GNUC__
#define __weak __attribute__((weak))
#define likely(x) __builtin_expect ((x), 1)
#define unlikely(x) __builtin_expect ((x), 0)
#elif defined(__ICCARM__)
#define likely(x) (x)
#define unlikely(x) (x)
#endif
typedef unsigned int uint;
typedef signed int sint;
#ifdef __ICCARM__
#if (__VER__ < 8040000)
typedef signed long long __int64_t;
typedef unsigned long long __uint64_t;
#endif
#endif
#define s8 int8_t
#define u8 uint8_t
#define s16 int16_t
#define u16 uint16_t
#define s32 int32_t
#define u32 uint32_t
#define s64 int64_t
#define u64 uint64_t
#ifdef CONFIG_MBED_ENABLED
#ifndef BOOL
typedef unsigned char BOOL;
#endif
#ifndef bool
typedef unsigned char bool;
#endif
#else
#ifndef BOOL
typedef unsigned char BOOL;
#endif
#ifdef __cplusplus
#else
#ifndef bool
typedef unsigned char bool;
#endif
#endif
#endif
#define UCHAR uint8_t
#define USHORT uint16_t
#define UINT uint32_t
#define ULONG uint32_t
//typedef struct { volatile int counter; } atomic_t;
typedef enum _RTK_STATUS_ {
_EXIT_SUCCESS = 0,
_EXIT_FAILURE = 1
}RTK_STATUS, *PRTK_STATUS;
#define IN
#define OUT
#define VOID void
#define INOUT
#define NDIS_OID uint
#define NDIS_STATUS uint
#ifndef PVOID
typedef void * PVOID;
#endif
typedef u32 dma_addr_t;
typedef void (*proc_t)(void*);
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef __kernel_size_t SIZE_T;
typedef __kernel_ssize_t SSIZE_T;
#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field)
#define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T))
#define MEM_ALIGNMENT_PADDING (sizeof(SIZE_T) - 1)
#define SIZE_PTR SIZE_T
#define SSIZE_PTR SSIZE_T
#ifndef ON
#define ON 1
#endif
#ifndef OFF
#define OFF 0
#endif
#ifndef ENABLE
#define ENABLE 1
#endif
#ifndef DISABLE
#define DISABLE 0
#endif
#define BIT0 0x0001
#define BIT1 0x0002
#define BIT2 0x0004
#define BIT3 0x0008
#define BIT4 0x0010
#define BIT5 0x0020
#define BIT6 0x0040
#define BIT7 0x0080
#define BIT8 0x0100
#define BIT9 0x0200
#define BIT10 0x0400
#define BIT11 0x0800
#define BIT12 0x1000
#define BIT13 0x2000
#define BIT14 0x4000
#define BIT15 0x8000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#define BIT_(__n) (1U<<(__n))
#ifndef BIT
#define BIT(__n) (1U<<(__n))
#endif
#if defined (__ICCARM__)
#define STRINGIFY(s) #s
#define SECTION(_name) _Pragma( STRINGIFY(location=_name))
#define ALIGNMTO(_bound) _Pragma( STRINGIFY(data_alignment=_bound))
#define _PACKED_ __packed
#define _LONG_CALL_
#define _WEAK __weak
#define _OPTIMIZE_NONE_ _Pragma( STRINGIFY(optimize=none))
#define UNUSED_WARN_DIS
#else
#define SECTION(_name) __attribute__ ((__section__(_name)))
#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound)))
#define _PACKED_ __attribute__ ((packed))
#define _LONG_CALL_ __attribute__ ((long_call))
#define _WEAK __attribute__ ((weak))
#define _OPTIMIZE_NONE_ __attribute__ ((optimize("O0")))
#define UNUSED_WARN_DIS __attribute__((unused))
#endif
//port from fw by thomas
// TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness
#define SWAP32(x) ((u32)( \
(((u32)(x) & (u32)0x000000ff) << 24) | \
(((u32)(x) & (u32)0x0000ff00) << 8) | \
(((u32)(x) & (u32)0x00ff0000) >> 8) | \
(((u32)(x) & (u32)0xff000000) >> 24)))
#define WAP16(x) ((u16)( \
(((u16)(x) & (u16)0x00ff) << 8) | \
(((u16)(x) & (u16)0xff00) >> 8)))
#if SYSTEM_ENDIAN == PLATFORM_LITTLE_ENDIAN
#ifndef rtk_le16_to_cpu
#define rtk_cpu_to_le32(x) ((u32)(x))
#define rtk_le32_to_cpu(x) ((u32)(x))
#define rtk_cpu_to_le16(x) ((u16)(x))
#define rtk_le16_to_cpu(x) ((u16)(x))
#define rtk_cpu_to_be32(x) SWAP32((x))
#define rtk_be32_to_cpu(x) SWAP32((x))
#define rtk_cpu_to_be16(x) WAP16((x))
#define rtk_be16_to_cpu(x) WAP16((x))
#endif
#elif SYSTEM_ENDIAN == PLATFORM_BIG_ENDIAN
#ifndef rtk_le16_to_cpu
#define rtk_cpu_to_le32(x) SWAP32((x))
#define rtk_le32_to_cpu(x) SWAP32((x))
#define rtk_cpu_to_le16(x) WAP16((x))
#define rtk_le16_to_cpu(x) WAP16((x))
#define rtk_cpu_to_be32(x) ((__u32)(x))
#define rtk_be32_to_cpu(x) ((__u32)(x))
#define rtk_cpu_to_be16(x) ((__u16)(x))
#define rtk_be16_to_cpu(x) ((__u16)(x))
#endif
#endif
/*
* Call endian free function when
* 1. Read/write packet content.
* 2. Before write integer to IO.
* 3. After read integer from IO.
*/
//
// Byte Swapping routine.
//
#define EF1Byte (u8)
#define EF2Byte le16_to_cpu
#define EF4Byte le32_to_cpu
//
// Read LE format data from memory
//
#define ReadEF1Byte(_ptr) EF1Byte(*((u8 *)(_ptr)))
#define ReadEF2Byte(_ptr) EF2Byte(*((u16 *)(_ptr)))
#define ReadEF4Byte(_ptr) EF4Byte(*((u32 *)(_ptr)))
//
// Write LE data to memory
//
#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val)
#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val)
#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val)
//
// Example:
// BIT_LEN_MASK_32(0) => 0x00000000
// BIT_LEN_MASK_32(1) => 0x00000001
// BIT_LEN_MASK_32(2) => 0x00000003
// BIT_LEN_MASK_32(32) => 0xFFFFFFFF
//
#define BIT_LEN_MASK_32(__BitLen) \
(0xFFFFFFFF >> (32 - (__BitLen)))
//
// Example:
// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
//
#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \
(BIT_LEN_MASK_32(__BitLen) << (__BitOffset))
//
// Description:
// Return 4-byte value in host byte ordering from
// 4-byte pointer in litten-endian system.
//
#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
(EF4Byte(*((u32 *)(__pStart))))
//
// Description:
// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to
// 4-byte value in host byte ordering.
//
#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_32(__BitLen) \
)
//
// Description:
// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering
// and return the result in 4-byte value in host byte ordering.
//
#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
& \
( ~ BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \
)
//
// Description:
// Set subfield of little-endian 4-byte value to specified value.
//
#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u32 *)(__pStart)) = \
EF4Byte( \
LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
| \
( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \
);
#define BIT_LEN_MASK_16(__BitLen) \
(0xFFFF >> (16 - (__BitLen)))
#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \
(BIT_LEN_MASK_16(__BitLen) << (__BitOffset))
#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
(EF2Byte(*((u16 *)(__pStart))))
#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_16(__BitLen) \
)
#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
& \
( ~ BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \
)
#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u16 *)(__pStart)) = \
EF2Byte( \
LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
| \
( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \
);
#define BIT_LEN_MASK_8(__BitLen) \
(0xFF >> (8 - (__BitLen)))
#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \
(BIT_LEN_MASK_8(__BitLen) << (__BitOffset))
#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
(EF1Byte(*((u8 *)(__pStart))))
#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_8(__BitLen) \
)
#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
& \
( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \
)
#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u8 *)(__pStart)) = \
EF1Byte( \
LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
| \
( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \
);
//pclint
#define LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \
( \
LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
)
//pclint
#define SET_BITS_TO_LE_1BYTE_8BIT(__pStart, __BitOffset, __BitLen, __Value) \
{ \
*((pu1Byte)(__pStart)) = \
EF1Byte( \
LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \
| \
((u1Byte)__Value) \
); \
}
// Get the N-bytes aligment offset from the current length
#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment))
typedef unsigned char BOOLEAN,*PBOOLEAN;
#define TEST_FLAG(__Flag,__testFlag) (((__Flag) & (__testFlag)) != 0)
#define SET_FLAG(__Flag, __setFlag) ((__Flag) |= __setFlag)
#define CLEAR_FLAG(__Flag, __clearFlag) ((__Flag) &= ~(__clearFlag))
#define CLEAR_FLAGS(__Flag) ((__Flag) = 0)
#define TEST_FLAGS(__Flag, __testFlags) (((__Flag) & (__testFlags)) == (__testFlags))
/* Define compilor specific symbol */
//
// inline function
//
#if defined ( __ICCARM__ )
#define __inline__ inline
#define __inline inline
#define __inline_definition //In dialect C99, inline means that a function's definition is provided
//only for inlining, and that there is another definition
//(without inline) somewhere else in the program.
//That means that this program is incomplete, because if
//add isn't inlined (for example, when compiling without optimization),
//then main will have an unresolved reference to that other definition.
// Do not inline function is the function body is defined .c file and this
// function will be called somewhere else, otherwise there is compile error
#ifndef __STATIC_INLINE
#define __STATIC_INLINE _Pragma("inline=forced")
#endif
#elif defined ( __CC_ARM )
#define __inline__ __inline //__linine__ is not supported in keil compilor, use __inline instead
#define inline __inline
#define __inline_definition // for dialect C99
#elif defined ( __GNUC__ )
#define __inline__ inline
#define __inline inline
#define __inline_definition inline
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline __attribute__((always_inline))
#endif
#endif
//
// pack
//
#if defined (__ICCARM__)
#define RTW_PACK_STRUCT_BEGIN _Pragma( STRINGIFY(pack(1)))
#define RTW_PACK_STRUCT_STRUCT
#define RTW_PACK_STRUCT_END _Pragma( STRINGIFY(pack()))
//#define RTW_PACK_STRUCT_USE_INCLUDES
#elif defined (__CC_ARM)
#define RTW_PACK_STRUCT_BEGIN __packed
#define RTW_PACK_STRUCT_STRUCT
#define RTW_PACK_STRUCT_END
#elif defined (__GNUC__)
#define RTW_PACK_STRUCT_BEGIN
#define RTW_PACK_STRUCT_STRUCT __attribute__ ((__packed__))
#define RTW_PACK_STRUCT_END
#elif defined(PLATFORM_WINDOWS)
#define RTW_PACK_STRUCT_BEGIN
#define RTW_PACK_STRUCT_STRUCT
#define RTW_PACK_STRUCT_END
#define RTW_PACK_STRUCT_USE_INCLUDES
#endif
// for standard library
#ifdef __ICCARM__
#define __extension__ /* Ignore */
#define __restrict /* Ignore */
#endif
#if defined (__ARM_FEATURE_CMSE)
#ifdef __ICCARM__
#define NS_ENTRY __attribute__((cmse_nonsecure_entry))
#else
#define NS_ENTRY __attribute__((cmse_nonsecure_entry))
#endif
#if defined (ARM_CORE_CM4)
#ifdef __ICCARM__
typedef __cmse_nonsecure_call void nsfunc(void);
#else
typedef void __attribute__((cmse_nonsecure_call)) nsfunc(void);
#endif
#endif
#endif
typedef struct {
void (*rdp_decrypt_func)(u32 addr, u8 *key, u8 cnt, u8 *buf);
u32 psram_s_start_addr;
} BOOT_EXPORT_SYMB_TABLE;
typedef struct {
VOID (*RamStartFun) (VOID);
VOID (*RamWakeupFun) (VOID);
u32 VectorNS;
}RAM_START_FUNCTION, *PRAM_START_FUNCTION;
typedef struct _RAM_FUNCTION_START_TABLE_ {
VOID (*RamStartFun) (VOID);
VOID (*RamWakeupFun) (VOID);
VOID (*RamPatchFun0) (VOID);
VOID (*RamPatchFun1) (VOID);
VOID (*RamPatchFun2) (VOID);
VOID (*FlashStartFun) (VOID);
u32 Img1ValidCode;
BOOT_EXPORT_SYMB_TABLE *ExportTable;
}RAM_FUNCTION_START_TABLE, *PRAM_FUNCTION_START_TABLE;
typedef struct _DSLP_RETENTION_FUNC_TABLE_ {
VOID (*DSLPPatchFun0) (VOID);
u32 PatchLen;
}DSLP_RETENTION_FUNC_TABLE, *PDSLP_RETENTION_FUNC_TABLE;
struct _driver_call_os_func_map {
void (*driver_enter_critical)(void);
void (*driver_exit_critical)(void);
};
#endif// __BASIC_TYPES_H__

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef __HAL_CRYPTO_H__
#define __HAL_CRYPTO_H__
#include "ameba_soc.h"
#include "basic_types.h"
#endif /* __HAL_CRYPTO_H__ */

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SDIO_HOST_H_
#define _HAL_SDIO_HOST_H_
#include "rtl8721d_sdio_host.h"
#define SDIO_HOST_WAIT_FOREVER 0xFFFFFFFF
typedef struct _HAL_SDIO_HOST_OP_ {
HAL_Status (*HalSdioHostInitHost) (VOID *Data);
HAL_Status (*HalSdioHostInitCard) (VOID *Data);
HAL_Status (*HalSdioHostDeInit) (VOID *Data);
HAL_Status (*HalSdioHostRegIrq) (VOID *Data);
HAL_Status (*HalSdioHostReadBlocksDma) (VOID *Data, u64 ReadAddr, u32 BlockCnt);
HAL_Status (*HalSdioHostWriteBlocksDma) (VOID *Data, u64 WriteAddr, u32 BlockCnt);
HAL_Status (*HalSdioHostStopTransfer) (VOID *Data);
HAL_Status (*HalSdioHostGetCardStatus) (VOID *Data);
HAL_Status (*HalSdioHostGetSdStatus) (VOID *Data);
HAL_Status (*HalSdioHostChangeSdClock) (VOID *Data, u8 Frequency);
HAL_Status (*HalSdioHostErase) (VOID *Data, u64 StartAddr, u64 EndAddr);
HAL_Status (*HalSdioHostGetWriteProtect) (VOID *Data);
HAL_Status (*HalSdioHostSetWriteProtect) (VOID *Data, u8 Setting);
}HAL_SDIO_HOST_OP, *PHAL_SDIO_HOST_OP;
typedef struct _HAL_SDIO_HOST_ADAPTER_{
// IRQ_HANDLE IrqHandle; // Irq Handler
ADMA2_DESC_FMT *AdmaDescTbl;
u32 Response[4];
u32 CardOCR;
u32 CardStatus;
u32 IsWriteProtect;
u8 SdStatus[SD_STATUS_LEN];
u8 Csd[CSD_REG_LEN];
volatile u8 CmdCompleteFlg;
volatile u8 XferCompleteFlg;
volatile u8 ErrIntFlg;
volatile u8 CardCurState;
u8 IsSdhc;
u8 CurrSdClk;
u16 RCA;
u16 SdSpecVer;
VOID (*CardInsertCallBack)(VOID *pAdapter);
VOID (*CardRemoveCallBack)(VOID *pAdapter);
VOID *CardInsertCbPara;
VOID *CardRemoveCbPara;
}HAL_SDIO_HOST_ADAPTER, *PHAL_SDIO_HOST_ADAPTER;
extern HAL_Status
HalSdioHostInit(
IN VOID *Data
);
extern HAL_Status
HalSdioHostDeInit(
IN VOID *Data
);
extern HAL_Status
HalSdioHostEnable(
IN VOID *Data
);
extern HAL_Status
HalSdioHostDisable(
IN VOID *Data
);
extern VOID
HalSdioHostOpInit(
IN VOID *Data
);
#endif

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/**
******************************************************************************
* @file rom_map.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the definations of rom map.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _ROM_MAP_
#define _ROM_MAP_
#endif //_ROM_MAP_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_8721D_H_
#define _HAL_8721D_H_
#include "platform_autoconf.h"
#include "basic_types.h"
#include "section_config.h"
#include "memproc.h"
#include "rtl8721d_sys_on.h"
#include "rtl8721d_peri_on.h"
#include "hal_platform.h"
#include "rtl8721d_vector.h"
#include "rtl8721d_loguart.h"
#include "rtl8721d_soc_ps.h"
#include "diag.h"
#include "shell.h"
#include "rand.h"
#include "monitor_rom.h"
#include "rtl8721d_syscfg.h"
#include "rtl8721d_pmc.h"
#include "rtl8721d_clk.h"
#include "rtl8721d_bor.h"
#include "rtl8721d_crypto.h"
#include "rtl8721d_crypto_api.h"
#include "rtl8721d_boot.h"
#include "rtl8721d_wl_on.h"
#include "rtl8721d_otf.h"
#include "rtl8721d_flash.h"
#include "rtl8721d_backup_reg.h"
#include "rtl8721d_pinmap.h"
#include "rtl8721d_ipc.h"
#include "rtl8721dhp_sysreg.h"
#include "rtl8721dlp_sysreg.h"
#include "rtl8721d_pinmux.h"
#ifndef CONFIG_BUILD_ROM
#include "rtl8721d_ipc_api.h"
#endif
#include "xmodem_update_rom.h"
#if defined (ARM_CORE_CM4)
#include "rtl8721dhp_rcc.h"
#else
#include "rtl8721dlp_rcc.h"
#endif
/* =========================== Configuration of the ARM ARMV8MBL Processor and Core Peripherals ============================ */
#if defined (ARM_CORE_CM4)
#ifdef AMEBAD_TODO
#define __ARMV8MML_REV 0x0000U /*!< ARMV8MML Core Revision */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __FPU_DP 0 /*!< Double Precision FPU */
#endif
#define __CM3_REV 0x0200 /**< Core revision r0p0 */
#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 1 /**< Vendor specific implementation of SysTickConfig is defined *///see vPortSetupTimerInterrupt
#define __SAUREGION_PRESENT 1 /*!< SAU present or not */
#define __FPU_PRESENT 1 /*!< FPU present */
#define __VFP_FP__ 1
#ifndef __ARM_FEATURE_CMSE
#define __ARM_FEATURE_CMSE 3
#endif
#include <arm_cmse.h> /* Use CMSE intrinsics */
#include "core_armv8mml.h"
#include "core_cache.h"
#elif defined (ARM_CORE_CM0)
#define __ARMV8MBL_REV 0x0000U /*!< ARMV8MBL Core Revision */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __SAU_REGION_PRESENT 0 /*!< SAU present or not */
#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
#include "core_armv8mbl.h"
#include "core_cache.h"
#endif
#include "rtl8721d_trustzone.h"
#include "mpu_config.h"
#include "rtl8721d_gdma.h"
#include "rtl8721d_tim.h"
#include "rtl8721d_gpio.h"
#include "rtl8721d_ssi.h"
#include "rtl8721d_uart.h"
#include "rtl8721d_i2c.h"
#include "rtl8721d_i2s.h"
#include "rtl8721d_adc.h"
#include "rtl8721d_comparator.h"
#include "rtl8721d_sdio.h"
#include "rtl8721d_wdg.h"
#include "rtl8721d_rtc.h"
#include "rtl8721d_delay.h"
#include "rtl8721d_ir.h"
#include "rtl8721d_keyscan.h"
#include "rtl8721d_sgpio.h"
#include "rtl8721d_qdec.h"
#include "rtl8721d_usi.h"
#include "rtl8721d_usi_uart.h"
#include "rtl8721d_usi_ssi.h"
#include "rtl8721d_usi_i2c.h"
#include "rtl8721d_crc.h"
#include "rtl8721d_lcdc.h"
#include "rtl8721d_audio.h"
#include "rtl8721d_efuse.h"
#include "rtl8721d_cache.h"
#include "rtl8721d_psram.h"
#include "rtl8721d_sdioh.h"
#include "rtl8721dhp_sd.h"
// firmware information, located at the header of Image2
#define FW_VERSION (0x0100)
#define FW_SUBVERSION (0x0001)
#define FW_CHIP_ID (0x8195)
#define FW_CHIP_VER (0x01)
#define FW_BUS_TYPE (0x01) // the iNIC firmware type: USB/SDIO
#define FW_INFO_RSV1 (0x00) // the firmware information reserved
#define FW_INFO_RSV2 (0x00) // the firmware information reserved
#define FW_INFO_RSV3 (0x00) // the firmware information reserved
#define FW_INFO_RSV4 (0x00) // the firmware information reserved
#define FLASH_HS_BOOT_ADDR (SPI_FLASH_BASE + 0x4000)
#define FLASH_RESERVED_DATA_BASE 0x2000 // reserve 8K for Image1
#define FLASH_SYSTEM_DATA_ADDR 0x3000 // reserve 8K+4K for Image1 + Reserved data
#define FLASH_OTA1_CODE_ADDR 0x6020
#define FLASH_SECTOR_SIZE 0x1000
//BT calibration Data
#define FLASH_BT_PARA_ADDR 0x5FF0
/* Spic_Mode */
#define ReadQuadIOMode 0
#define ReadQuadOMode 1
#define ReadDualIOMode 2
#define ReadDualOMode 3
#define ReadOneMode 4
#define IMAGE_HEADER_LEN 0x20
typedef struct {
u32 signature[2];
u32 image_size;
u32 image_addr;
/* reserved for extention */
u32 sb_header;
u32 reserved[3];
} IMAGE_HEADER;
typedef struct {
/* 0x00 */
u32 Rsvd00;
u32 Valid_Image2;
u32 Rsvd01[2];
/* 0x10 */
u32 Rsvd10[4];
/* 0x20 */
u32 Rsvd20[2];
u32 BT_FW_DBG;
u32 FTL_GC_Status;
} SYSTEM_DATA;
typedef struct {
u32 reserved[12];
unsigned char sb_sig[64];
} SB_HEADER;
typedef enum _HAL_Status
{
HAL_OK = 0x00,
HAL_BUSY = 0x01,
HAL_TIMEOUT = 0x02,
HAL_ERR_PARA = 0x03, // error with invaild parameters
HAL_ERR_MEM = 0x04, // error with memory allocation failed
HAL_ERR_HW = 0x05, // error with hardware error
HAL_ERR_UNKNOWN = 0xee // unknown error
} HAL_Status;
#define USE_FULL_ASSERT
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function which reports
* the name of the source file and the source line number of the call
* that failed. If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : io_assert_failed((uint8_t *)__FUNCTION__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void io_assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#endif //_HAL_8721D_H_

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/**
******************************************************************************
* @file rtl8721d_adc.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_ADC_H_
#define _RTL8721D_ADC_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup ADC
* @brief ADC driver modules
* @{
*/
/** @addtogroup ADC
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* ADC:
* - Base Address: ADC
* - Channel number: 11
* - CH8~10: internal ADC channel
* - CH0~7: external ADC channel
* - Sample rate: configurable, frequency = CLK_ADC_CORE/divider, in which CLK_ADC_CORE is 2MHz, and can
* be divided by 12/16/32/64.
* - Resolution: 12 bit
* - Analog signal sampling: support 0 ~ 3.3V
* - IRQ: ADC_IRQ
* - Support Software-Trigger mode, Automatic mode, Timer-Trigger mode and Comparator-Assist mode.
* - GDMA source handshake interface: GDMA_HANDSHAKE_INTERFACE_ADC_RX
*
*****************************************************************************************
* How to use ADC in interrupt mode
*****************************************************************************************
* To use ADC in interrupt mode, the following steps are mandatory:
*
* 1. Enable the ADC interface clock:
* RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
*
* 2. Fill the ADC_InitStruct with the desired parameters.
*
* 3. Init Hardware with the parameters in ADC_InitStruct.
* ADC_Init(ADC_InitTypeDef* ADC_InitStruct)
*
* 4. Clear ADC interrupt:
* ADC_INTClear()
*
* 5. To configure interrupts:
* ADC_INTConfig(ADC_IT, ENABLE)
*
* 6. Enable the NVIC and the corresponding interrupt using following function.
* -InterruptRegister(): register the ADC irq handler
* -InterruptEn(): Enable the NVIC interrupt and set irq priority
*
* 7. Activate the ADC:
* ADC_Cmd(ENABLE).
*
* 8. Enbale specified mode:
* ADC_SWTrigCmd(ENABLE)/ADC_AutoCSwCmd(ENABLE)/ADC_TimerTrigCmd(Tim_Idx, PeriodMs, ENABLE)
*
* @note 1. If use ADC compare mode, call ADC_SetComp(ADC_channel, CompThresH, CompThresL, CompCtrl) to configure
* 2. If use ADC comparator-assist mode, you need to setup and enable comparator.
*
*****************************************************************************************
* How to use ADC in DMA mode
*****************************************************************************************
* To use ADC in DMA mode, the following steps are mandatory:
*
* 1. Enable the ADC interface clock:
* RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
*
* 2. Fill the ADC_InitStruct with the desired parameters.
*
* 3. Init Hardware use step2 parameters.
* ADC_Init(ADC_InitTypeDef* ADC_InitStruct).
*
* 4. Enable DMA read mode.
* ADC_SetDmaEnable().
*
* 5. Init and Enable ADC RX GDMA, configure GDMA related configurations(source address/destination address/block size etc.)
* ADC_RXGDMA_Init().
*
* 6. Activate the ADC peripheral:
* ADC_Cmd(ENABLE).
*
* 7. Enbale specified mode:
* ADC_SWTrigCmd(ENABLE)/ADC_AutoCSwCmd(ENABLE)/ \
* ADC_TimerTrigCmd(Tim_Idx, PeriodMs, ENABLE)
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Types ADC Exported Types
* @{
*/
/**
* @brief ADC Init structure definition
*/
typedef struct {
u8 ADC_OpMode; /*!< Specifies ADC operation mode.
This parameter can be a value of @ref ADC_Operation_Mode_Definitions */
u8 ADC_CvlistLen; /*!< The number of valid items in the ADC conversion channel list is (ADC_CvlistLen + 1).
This parameter can be set to 0~15 */
u8 ADC_Cvlist[16]; /*!< Specifies the ADC channel conversion order. Each member should be
the channel index */
u8 ADC_ClkDiv; /*!< Specifies ADC clock divider.
This parameter can be a value of @ref ADC_CLK_Divider_Definitions */
u8 ADC_RxThresholdLevel; /*!< Specifies the receive FIFO threshold level.
When the number of rx FIFO entries is greater than or equal to this
value +1, the receive FIFO full interrupt is triggered. */
u8 ADC_DMAThresholdLevel; /*!< Specifies ADC DMA operation threshold.
The dma_rx_req is generated when the number of valid data entries in the
receive FIFO is equal to or above this field value+1 and ADC_DMA_EN=1. */
u8 ADC_SpecialCh; /*!< Specifies ADC particular channel. This parameter defines that ADC module
should send interrupt signal to system when a conversion which of channel
number is the same as this parameter. Default 0xFF means there is no need
to set particular channel. */
u32 ADC_ChanInType; /*!< Specifies CH0~5 input type. Default all channels are in single-end mode.
If some channels need to be set to differential mode, use a value or
combination of @ref ADC_CH_Input_Type_Definitions. */
u8 ADC_ChIDEn; /*!< Specifies whether ADC enables BIT_ADC_DAT_CHID or not. */
} ADC_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_Exported_Constants ADC Exported Constants
* @{
*/
/** @defgroup ADC_Chn_Selection
* @{
*/
#define ADC_CH0 ((u8)0x00)
#define ADC_CH1 ((u8)0x01)
#define ADC_CH2 ((u8)0x02)
#define ADC_CH3 ((u8)0x03)
#define ADC_CH4 ((u8)0x04)
#define ADC_CH5 ((u8)0x05)
#define ADC_CH6 ((u8)0x06)
#define ADC_CH7 ((u8)0x07)
#define ADC_CH8 ((u8)0x08) /*!< ADC internal channel */
#define ADC_CH9 ((u8)0x09) /*!< ADC internal channel */
#define ADC_CH10 ((u8)0x0a) /*!< ADC internal channel */
#define ADC_CH_NUM (11)
#define ADC_GLOBAL ((u8)0xFF)
#define IS_ADC_CHN_SEL(SEL) (((SEL) == ADC_CH0) || \
((SEL) == ADC_CH1) || \
((SEL) == ADC_CH2) || \
((SEL) == ADC_CH3) || \
((SEL) == ADC_CH4) || \
((SEL) == ADC_CH5) || \
((SEL) == ADC_CH6) || \
((SEL) == ADC_CH7) || \
((SEL) == ADC_CH8) || \
((SEL) == ADC_CH9) || \
((SEL) == ADC_CH10))
/**
* @}
*/
/** @defgroup ADC_CLK_Divider_Definitions
* @{
*/
#define ADC_CLK_DIV_12 ((u8)0x00)
#define ADC_CLK_DIV_16 ((u8)0x01)
#define ADC_CLK_DIV_32 ((u8)0x02)
#define ADC_CLK_DIV_64 ((u8)0x03)
#define IS_ADC_SAMPLE_CLK(CLK) (((CLK) == ADC_CLK_DIV_12) || \
((CLK) == ADC_CLK_DIV_16) || \
((CLK) == ADC_CLK_DIV_32) || \
((CLK) == ADC_CLK_DIV_64))
/**
* @}
*/
/** @defgroup ADC_Operation_Mode_Definitions
* @{
*/
#define ADC_SW_TRI_MODE ((u8)0x00) /*!< ADC software-trigger mode */
#define ADC_AUTO_MODE ((u8)0x01) /*!< ADC automatic mode */
#define ADC_TIM_TRI_MODE ((u8)0x02) /*!< ADC timer-trigger mode */
#define ADC_COMP_ASSIST_MODE ((u8)0x03) /*!< ADC comparator-assist mode */
#define IS_ADC_MODE(mode) (((mode) == ADC_SW_TRI_MODE) || \
((mode) == ADC_AUTO_MODE) || \
((mode) == ADC_TIM_TRI_MODE) || \
((mode) == ADC_COMP_ASSIST_MODE))
/**
* @}
*/
/** @defgroup ADC_CH_Input_Type_Definitions
* @{
*/
#define ADC_DIFFERENTIAL_CH(x) BIT(x)
/**
* @}
*/
/** @defgroup ADC_Compare_Control_Definitions
* @{
*/
#define ADC_COMP_SMALLER_THAN_THL ((u8)0x00) /*!< Vin < ADC_COMP_TH_L */
#define ADC_COMP_GREATER_THAN_THH ((u8)0x01) /*!< Vin > ADC_COMP_TH_H */
#define ADC_COMP_WITHIN_THL_AND_THH ((u8)0x02) /*!< Vin >= ADC_COMP_TH_L && Vin <= ADC_COMP_TH_H */
#define ADC_COMP_OUTSIDE_THL_AND_THH ((u8)0x03) /*!< Vin < ADC_COMP_TH_L || Vin > ADC_COMP_TH_H */
#define IS_ADC_COMP_CRITERIA(rule) (((rule) == ADC_COMP_SMALLER_THAN_THL) || \
((rule) == ADC_COMP_GREATER_THAN_THH) || \
((rule) == ADC_COMP_WITHIN_THL_AND_THH) || \
((rule) == ADC_COMP_OUTSIDE_THL_AND_THH))
/**
* @}
*/
/** @defgroup ADC_Compare_Threshold_Definitions
* @{
*/
#define IS_ADC_VALID_COMP_TH(x) (x < 0x1000)
/**
* @}
*/
/** @defgroup ADC_Timer_Definitions
* @{
*/
#define IS_ADC_VALID_TIM(idx) (idx < 4)
/**
* @}
*/
/**
* @}
*/
/** @defgroup ADC_Exported_Functions ADC Exported Functions
* @{
*/
_LONG_CALL_ void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);
_LONG_CALL_ void ADC_Init(ADC_InitTypeDef* ADC_InitStruct);
_LONG_CALL_ void ADC_Cmd(u32 NewState);
_LONG_CALL_ void ADC_INTConfig(u32 ADC_IT, u32 NewState);
_LONG_CALL_ void ADC_INTClear(void);
_LONG_CALL_ void ADC_INTClearPendingBits(u32 ADC_IT);
_LONG_CALL_ u32 ADC_GetISR(void);
_LONG_CALL_ u32 ADC_GetRawISR(void);
_LONG_CALL_ u32 ADC_GetCompStatus(u8 ADC_Channel);
_LONG_CALL_ u32 ADC_GetRxCount(void);
_LONG_CALL_ u32 ADC_GetLastChan(void);
_LONG_CALL_ void ADC_SetComp(u8 ADC_channel, u16 CompThresH, u16 CompThresL, u8 CompCtrl);
_LONG_CALL_ void ADC_ResetCSwList(void);
_LONG_CALL_ u32 ADC_Readable(void);
_LONG_CALL_ u16 ADC_Read(void);
_LONG_CALL_ void ADC_ReceiveBuf(u16 *pBuf, u32 len);
_LONG_CALL_ void ADC_ClearFIFO(void);
_LONG_CALL_ u32 ADC_GetStatus(void);
_LONG_CALL_ void ADC_SWTrigCmd(u32 NewState);
_LONG_CALL_ void ADC_AutoCSwCmd(u32 NewState);
_LONG_CALL_ void ADC_TimerTrigCmd(u8 Tim_Idx, u32 PeriodMs, u32 NewState);
_LONG_CALL_ void ADC_SetDmaEnable(u32 newState);
_LONG_CALL_ u32 ADC_RXGDMA_Init(GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8* pDataBuf, u32 DataLen);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup ADC_Register_Definitions ADC Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup REG_ADC_CONF
* @{
*****************************************************************************/
#define BIT_ADC_ENABLE BIT(9)
#define BIT_SHIFT_CVLIST_LEN 4
#define BIT_MASK_CVLIST_LEN (u32)(0x0000000F << BIT_SHIFT_CVLIST_LEN)
#define BIT_SHIFT_OP_MODE 1
#define BIT_MASK_OP_MODE (u32)(0x00000007 << BIT_SHIFT_OP_MODE)
#define BIT_ADC_REF_IN_SEL BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_IN_TYPE
* @{
*****************************************************************************/
#define BIT_SHIFT_IN_TYPE_CH(x) (x)
#define BIT_ADC_IN_TYPE_CH(x) BIT(x)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_COMP_TH_CH
* @{
*****************************************************************************/
#define BIT_SHIFT_COMP_TH_H 16
#define BIT_MASK_COMP_TH_H (u32)(0x00000FFF << BIT_SHIFT_COMP_TH_H)
#define BIT_SHIFT_COMP_TH_L 0
#define BIT_MASK_COMP_TH_L (u32)(0x00000FFF << BIT_SHIFT_COMP_TH_L)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_COMP_CTRL
* @{
*****************************************************************************/
#define BIT_SHIFT_COMP_CTRL_CH(x) (2*x)
#define BIT_MASK_COMP_CTRL_CH(x) (u32)(0x00000003 << BIT_SHIFT_COMP_CTRL_CH(x))
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_COMP_STS
* @{
*****************************************************************************/
#define BIT_SHIFT_COMP_STS_CH(x) (2*x)
#define BIT_MASK_COMP_STS_CH(x) (u32)(0x00000003 << BIT_SHIFT_COMP_STS_CH(x))
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_CHSW_LIST0
* @{
*****************************************************************************/
#define BIT_SHIFT_CHSW0(x) (4*x)
#define BIT_MASK_CHSW0(x) (u32)(0x0000000F << BIT_SHIFT_CHSW0(x))
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_CHSW_LIST1
* @{
*****************************************************************************/
#define BIT_SHIFT_CHSW1(x) (4*(x - 8))
#define BIT_MASK_CHSW1(x) (u32)(0x0000000F << BIT_SHIFT_CHSW1)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_RST_LIST
* @{
*****************************************************************************/
#define BIT_ADC_RST_LIST BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_AUTO_CSW_CTRL
* @{
*****************************************************************************/
#define BIT_ADC_AUTO_CSW_EN BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_SW_TRIG
* @{
*****************************************************************************/
#define BIT_ADC_SW_TRIG BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_LAST_CH
* @{
*****************************************************************************/
#define BIT_ADC_LAST_CH (u32)(0x0000000F)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_BUSY_STS
* @{
*****************************************************************************/
#define BIT_ADC_FIFO_EMPTY BIT(2)
#define BIT_ADC_FIFO_FULL_REAL BIT(1)
#define BIT_ADC_BUSY_STS BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_INTR_CTRL
* @{
*****************************************************************************/
#define BIT_ADC_IT_COMP_CH_EN(x) BIT(8+x)
#define BIT_ADC_IT_COMP_CH10_EN BIT(18)
#define BIT_ADC_IT_COMP_CH9_EN BIT(17)
#define BIT_ADC_IT_COMP_CH8_EN BIT(16)
#define BIT_ADC_IT_COMP_CH7_EN BIT(15)
#define BIT_ADC_IT_COMP_CH6_EN BIT(14)
#define BIT_ADC_IT_COMP_CH5_EN BIT(13)
#define BIT_ADC_IT_COMP_CH4_EN BIT(12)
#define BIT_ADC_IT_COMP_CH3_EN BIT(11)
#define BIT_ADC_IT_COMP_CH2_EN BIT(10)
#define BIT_ADC_IT_COMP_CH1_EN BIT(9)
#define BIT_ADC_IT_COMP_CH0_EN BIT(8)
#define BIT_ADC_IT_ERR_EN BIT(7)
#define BIT_ADC_IT_DAT_OVW_EN BIT(6)
#define BIT_ADC_IT_FIFO_EMPTY_EN BIT(5)
#define BIT_ADC_IT_FIFO_OVER_EN BIT(4)
#define BIT_ADC_IT_FIFO_FULL_EN BIT(3)
#define BIT_ADC_IT_CHCV_END_EN BIT(2)
#define BIT_ADC_IT_CV_END_EN BIT(1)
#define BIT_ADC_IT_CVLIST_END_EN BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_INTR_STS
* @{
*****************************************************************************/
#define BIT_ADC_IT_COMP_CH10_STS BIT(18)
#define BIT_ADC_IT_COMP_CH9_STS BIT(17)
#define BIT_ADC_IT_COMP_CH8_STS BIT(16)
#define BIT_ADC_IT_COMP_CH7_STS BIT(15)
#define BIT_ADC_IT_COMP_CH6_STS BIT(14)
#define BIT_ADC_IT_COMP_CH5_STS BIT(13)
#define BIT_ADC_IT_COMP_CH4_STS BIT(12)
#define BIT_ADC_IT_COMP_CH3_STS BIT(11)
#define BIT_ADC_IT_COMP_CH2_STS BIT(10)
#define BIT_ADC_IT_COMP_CH1_STS BIT(9)
#define BIT_ADC_IT_COMP_CH0_STS BIT(8)
#define BIT_ADC_IT_ERR_STS BIT(7)
#define BIT_ADC_IT_DAT_OVW_STS BIT(6)
#define BIT_ADC_IT_FIFO_EMPTY_STS BIT(5)
#define BIT_ADC_IT_FIFO_OVER_STS BIT(4)
#define BIT_ADC_IT_FIFO_FULL_STS BIT(3)
#define BIT_ADC_IT_CHCV_END_STS BIT(2)
#define BIT_ADC_IT_CV_END_STS BIT(1)
#define BIT_ADC_IT_CVLIST_END_STS BIT(0)
#define BIT_ADC_IT_COMP_ALL_STS ( BIT_ADC_IT_COMP_CH0_STS | \
BIT_ADC_IT_COMP_CH1_STS | \
BIT_ADC_IT_COMP_CH2_STS | \
BIT_ADC_IT_COMP_CH3_STS | \
BIT_ADC_IT_COMP_CH4_STS | \
BIT_ADC_IT_COMP_CH5_STS | \
BIT_ADC_IT_COMP_CH6_STS | \
BIT_ADC_IT_COMP_CH7_STS | \
BIT_ADC_IT_COMP_CH8_STS | \
BIT_ADC_IT_COMP_CH9_STS | \
BIT_ADC_IT_COMP_CH10_STS )
#define BIT_ADC_IT_ALL_STS (BIT_ADC_IT_COMP_ALL_STS | \
BIT_ADC_IT_ERR_STS | \
BIT_ADC_IT_DAT_OVW_STS |\
BIT_ADC_IT_FIFO_EMPTY_STS |\
BIT_ADC_IT_FIFO_OVER_STS |\
BIT_ADC_IT_FIFO_FULL_STS |\
BIT_ADC_IT_CHCV_END_STS |\
BIT_ADC_IT_CV_END_STS |\
BIT_ADC_IT_CVLIST_END_STS)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_INTR_RAW_STS
* @{
*****************************************************************************/
#define BIT_ADC_IT_COMP_CH10_RAW_STS BIT(18)
#define BIT_ADC_IT_COMP_CH9_RAW_STS BIT(17)
#define BIT_ADC_IT_COMP_CH8_RAW_STS BIT(16)
#define BIT_ADC_IT_COMP_CH7_RAW_STS BIT(15)
#define BIT_ADC_IT_COMP_CH6_RAW_STS BIT(14)
#define BIT_ADC_IT_COMP_CH5_RAW_STS BIT(13)
#define BIT_ADC_IT_COMP_CH4_RAW_STS BIT(12)
#define BIT_ADC_IT_COMP_CH3_RAW_STS BIT(11)
#define BIT_ADC_IT_COMP_CH2_RAW_STS BIT(10)
#define BIT_ADC_IT_COMP_CH1_RAW_STS BIT(9)
#define BIT_ADC_IT_COMP_CH0_RAW_STS BIT(8)
#define BIT_ADC_IT_ERR_RAW_STS BIT(7)
#define BIT_ADC_IT_DAT_OVW_RAW_STS BIT(6)
#define BIT_ADC_IT_FIFO_EMPTY_RAW_STS BIT(5)
#define BIT_ADC_IT_FIFO_OVER_RAW_STS BIT(4)
#define BIT_ADC_IT_FIFO_FULL_RAW_STS BIT(3)
#define BIT_ADC_IT_CHCV_END_RAW_STS BIT(2)
#define BIT_ADC_IT_CV_END_RAW_STS BIT(1)
#define BIT_ADC_IT_CVLIST_END_RAW_STS BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_IT_CHNO_CON
* @{
*****************************************************************************/
#define BIT_MASK_IT_CHNO_CON (u32)(0x0000000F)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_FULL_LVL
* @{
*****************************************************************************/
#define BIT_MASK_FULL_LVL (u32)(0x0000003F)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_ADC_EXT_TRIG_TIMER_SEL
* @{
*****************************************************************************/
#define BIT_MASK_EXT_TRIG_TIMER_SEL (u32)(0x00000007)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_DATA_CH0_to_CH11
* @{
*****************************************************************************/
#define BIT_ADC_DAT_RDY BIT(17)
#define BIT_ADC_DAT_OVW BIT(16)
#define BIT_MASK_DATA_CH (u32)(0x00000FFF)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_DATA_GLOBAL
* @{
*****************************************************************************/
#define BIT_MASK_DAT_CH (u32)(0x0000000F << 18)
#define BIT_MASK_DAT_CHID (u32)(0x0000000F << 12)
#define BIT_MASK_DAT_GLOBAL (u32)(0x00000FFF)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_DMA_CON
* @{
*****************************************************************************/
#define BIT_SHIFT_DMA_LVL 8
#define BIT_MASK_DMA_LVL (u32)(0x0000000F << BIT_SHIFT_DMA_LVL)
#define BIT_ADC_DMA_EN BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_FLR
* @{
*****************************************************************************/
#define BIT_MASK_FLR (u32)(0x0000007F)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_CLR_FIFO
* @{
*****************************************************************************/
#define BIT_ADC_CLR_FIFO BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_CLK_DIV
* @{
*****************************************************************************/
#define BIT_MASK_CLK_DIV (u32)(0x00000007)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_DELAY_CNT
* @{
*****************************************************************************/
#define BIT_ADC_DAT_CHID BIT(31)
#define BIT_ADC_DAT_DELAY (u32)(0x00000003 << 2)
#define BIT_ADC_CTRL_DELAY (u32)(0x00000003)
/** @} */
/**************************************************************************//**
* @defgroup REG_ADC_PWR_CTRL
* @{
*****************************************************************************/
#define BIT_ADC_PWR_CTRL BIT(0)
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
#endif /* _RTL8721D_ADC_H_ */
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_audio.h
* @author
* @version V1.0.0
* @date 2017-12-13
* @brief This file contains all the functions prototypes for the audio codec firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_AUDIO_H_
#define _RTL8721D_AUDIO_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup audio
* @brief audio driver modules
* @{
*/
/** @addtogroup audio
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* audio sport:
* - Base Address: AUDIO_SPORT_DEV
* - Source clk: 40MHz or 45.1584MHz or 98.304MHz(default)
* - Sample rate: 8/16/32/44.1/48/88.2/96 /11.025/12/22.05 KHz
* - Sample bit: 16 bit, 24 bit, 8bit
* - Channel number: mono or stereo
* - Data format: I2S, Left justified, PCM mode A, PCM mode B, PCM mode A-N, PCM mode B-N
* - Use GDMA to move data
*
*****************************************************************************************
* How to use audio sport
*****************************************************************************************
* To use audio codec sport, the following steps are mandatory:
*
* 1. Open audio codec clock and function using
* PLLx_Set(0, ENABLE); (x is 0 or 1)
* RCC_PeriphClockCmd(APBPeriph_AUDIOC, APBPeriph_AUDIOC_CLOCK, ENABLE);
* RCC_PeriphClockCmd(APBPeriph_SPORT, APBPeriph_SPORT_CLOCK, ENABLE);
*
* 2. AUDIO SPORT pin setting:
* PAD_CMD(PinName, DISABLE).
*
* 3. Fill the AUDIO_SP_InitStruct with the desired parameters.
*
* 4. configure AUDIO SPORT with the corresponding configuration.
* AUDIO_SP_Init(AUDIO_SP_DEV, &SP_InitStruct)
*
* 5. According to audio codec transfer direction, start Tx or Rx or both path
* start Tx path:
* AUDIO_SP_TdmaCmd(AUDIO_SPORT_DEV, ENABLE);
* AUDIO_SP_TxStart(AUDIO_SPORT_DEV, ENABLE);
* start Rx path:
* AUDIO_SP_RdmaCmd(AUDIO_SPORT_DEV, ENABLE);
* AUDIO_SP_RxStart(AUDIO_SPORT_DEV, ENABLE);
*
* 6. Use AUDIO_SP_TXGDMA_Init or AUDIO_SP_RXGDMA_Init or both function to activate the GDMA according to transfer direction.
*
* @note All other functions can be used separately to modify, if needed,
* a specific feature of the AUDIO SPORT.
*****************************************************************************************
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup AUDIO_Exported_Types AUDIO Exported Types
* @{
*/
/**
* @brief AUDIO SPORT Init structure definition
*/
typedef struct {
u32 SP_WordLen; /*!< Specifies the AUDIO SPORT word length
This parameter can be a value of @ref SP_word_length */
u32 SP_DataFormat; /*!< Specifies the AUDIO SPORT data format
This parameter can be a value of @ref SP_data_format */
u32 SP_MonoStereo; /*!< Specifies the AUDIO SPORT channel number
This parameter can be a value of @ref SP_channel_number */
u32 SP_SelRxCh; /*!< Specifies the AUDIO SPORT selection of RX channel for ADC path
This parameter can be a value of @ref SP_SEL_RX_channel */
} SP_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup AUDIO_Exported_Constants AUDIO Exported Constants
* @{
*/
/** @defgroup SP_word_length AUDIO SPORT Word Length
* @{
*/
#define SP_WL_16 ((u32)0x00000000)
#define SP_WL_24 ((u32)0x00000002)
#define SP_WL_8 ((u32)0x00000003)
#define IS_SP_WORD_LEN(LEN) (((LEN) == SP_WL_16) || \
((LEN) == SP_WL_24) || \
((LEN) == SP_WL_8))
/**
* @}
*/
/** @defgroup SP_data_format AUDIO SPORT Interface Format
* @{
*/
#define SP_DF_I2S ((u32)0x00000000)
#define SP_DF_LEFT ((u32)0x00000001)
#define SP_DF_PCM_A ((u32)0x00000002)
#define SP_DF_PCM_B ((u32)0x00000003)
#define SP_DF_PCM_AN ((u32)0x00000006)
#define SP_DF_PCM_BN ((u32)0x00000007)
#define IS_SP_DATA_FMT(FORMAT) (((FORMAT) == SP_DF_I2S) || \
((FORMAT) == SP_DF_LEFT) || \
((FORMAT) == SP_DF_PCM_A) || \
((FORMAT) == SP_DF_PCM_B) || \
((FORMAT) == SP_DF_PCM_AN) || \
((FORMAT) == SP_DF_PCM_BN))
/**
* @}
*/
/** @defgroup SP_channel_number AUDIO SPORT Channel Number
* @{
*/
#define SP_CH_STEREO ((u32)0x00000000)
#define SP_CH_MONO ((u32)0x00000001)
#define IS_SP_CHN_NUM(NUM) (((NUM) == SP_CH_STEREO) || \
((NUM) == SP_CH_MONO))
/**
* @}
*/
/** @defgroup SP_SEL_RX_channel AUDIO SPORT Selection of RX Channel
* @{
*/
#define SP_RX_CH_LR ((u32)0x00000000)
#define SP_RX_CH_RL ((u32)0x00000001)
#define SP_RX_CH_LL ((u32)0x00000002)
#define SP_RX_CH_RR ((u32)0x00000003)
#define IS_SP_SEL_RX_CH(CH) (((CH) == SP_RX_CH_LR) || \
((CH) == SP_RX_CH_RL) || \
((CH) == SP_RX_CH_LL) || \
((CH) == SP_RX_CH_RR))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup AUDIO_Exported_Functions AUDIO Exported Functions
* @{
*/
/** @defgroup AUDIO_SPORT_functions
* @{
*/
_LONG_CALL_ void AUDIO_SP_StructInit(SP_InitTypeDef* SP_InitStruct);
_LONG_CALL_ void AUDIO_SP_Init(AUDIO_SPORT_TypeDef* SPORTx, SP_InitTypeDef* SP_InitStruct);
_LONG_CALL_ void AUDIO_SP_TxStart(AUDIO_SPORT_TypeDef* SPORTx, u32 NewState);
_LONG_CALL_ void AUDIO_SP_RxStart(AUDIO_SPORT_TypeDef* SPORTx, u32 NewState);
_LONG_CALL_ void AUDIO_SP_TdmaCmd(AUDIO_SPORT_TypeDef* SPORTx, u32 NewState);
_LONG_CALL_ void AUDIO_SP_RdmaCmd(AUDIO_SPORT_TypeDef* SPORTx, u32 NewState);
_LONG_CALL_ void AUDIO_SP_SetWordLen(AUDIO_SPORT_TypeDef* SPORTx, u32 SP_WordLen);
_LONG_CALL_ u32 AUDIO_SP_GetWordLen(AUDIO_SPORT_TypeDef* SPORTx);
_LONG_CALL_ void AUDIO_SP_SetMonoStereo(AUDIO_SPORT_TypeDef* SPORTx, u32 SP_MonoStereo);
_LONG_CALL_ BOOL AUDIO_SP_TXGDMA_Init(u32 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pTxData, u32 Length);
_LONG_CALL_ BOOL AUDIO_SP_RXGDMA_Init(u32 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pRxData, u32 Length);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup AUDIO_Register_Definitions AUDIO Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup AUDIO_SI_Register_Definitions AUDIO SI Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup SI_CTRLR
* @{
*****************************************************************************/
#define BIT_CTRLR_SI_WR_START ((u32)0x00000001 << 0)
#define BIT_CTRLR_SI_RD_START ((u32)0x00000001 << 4)
#define BIT_CTRLR_SI_DISABLE ((u32)0x00000001 << 7)
#define BIT_CTRLR_SI_ADDR ((u32)0x000000FF << 8)
#define BIT_CTRLR_SI_DATA ((u32)0x0000FFFF << 16)
/** @} */
/**************************************************************************//**
* @defgroup SI_CLK_EN
* @{
*****************************************************************************/
#define BIT_SI_CLK_EN ((u32)0x00000001 << 0)
/** @} */
/** @} */
/**************************************************************************//**
* @defgroup AUDIO_SPORT_Register_Definitions AUDIO SPORT Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup SP_CTRLR0
* @{
*****************************************************************************/
#define SP_CTRLR0_RST ((u32)0x00000001 << 0) /* Bit[0], reset SPORT1 module*/
#define SP_CTRLR0_TX_INV_I2S_SCLK ((u32)0x00000001 << 1) /* Bit[1], invert sclk to TX path (DAC path)*/
#define SP_CTRLR0_RX_INV_I2S_SCLK ((u32)0x00000001 << 2) /* Bit[2], invert sclk to RX path (ADC path)*/
#define SP_CTRLR0_SLAVE_CLK_SEL ((u32)0x00000001 << 3) /* Bit[3], To be an I2S or PCM slave (CLK path)*/
#define SP_CTRLR0_SLAVE_DATA_SEL ((u32)0x00000001 << 4) /* Bit[4], To be an I2S or PCM slave (data path)*/
#define SP_CTRLR0_WCLK_INV ((u32)0x00000001 << 5) /* Bit[5], invert I2S/PCM word clock*/
#define SP_CTRLR0_LOOPBACK ((u32)0x00000001 << 6) /* Bit[6], self loopback mode*/
#define SP_CTRLR0_DSP_CTL_MODE ((u32)0x00000001 << 7) /* Bit[7], 1: DSP and SPORT1 handshaking is enabled; 0: GDMA and SPORT1 handshaking is enabled*/
#define SP_CTRLR0_DATA_FORMAT_SEL ((u32)0x00000003 << 8) /* Bit[9:8], data format*/
#define SP_CTRLR0_EN_PCM_N_MODE_SEL ((u32)0x00000001 << 10)/* Bit[10], pcm n mode*/
#define SP_CTRLR0_EN_I2S_MONO ((u32)0x00000001 << 11)/* Bit[11], 1: mono; 0: stereo*/
#define SP_CTRLR0_DATA_LEN_SEL ((u32)0x00000003 << 12)/* Bit[13:12], data len*/
#define SP_CTRLR0_INV_I2S_SCLK ((u32)0x00000001 << 14)/* Bit[14], invert I2S/PCM bit clock*/
#define SP_CTRLR0_I2S_SELF_LPBK_EN ((u32)0x00000001 << 15)/* Bit[15], internal loopback mode*/
#define SP_CTRLR0_TX_DISABLE ((u32)0x00000001 << 16)/* Bit[16], disable or enable SPORT TX*/
#define SP_CTRLR0_START_TX ((u32)0x00000001 << 17)/* Bit[17], TX start*/
#define SP_CTRLR0_ADC_COMP ((u32)0x00000003 << 18)/* Bit[19:18], ADC compress*/
#define SP_CTRLR0_SEl_I2S_TX_CH ((u32)0x00000003 << 20)/* Bit[21:20], I2S TX channel select @ DAC path*/
#define SP_CTRLR0_TX_LSB_FIRST ((u32)0x00000001 << 22)/* Bit[22], TX MSB or LSB first select*/
#define SP_CTRLR0_RX_LSB_FIRST ((u32)0x00000001 << 23)/* Bit[23], RX MSB or LSB first select*/
#define SP_CTRLR0_RX_DISABLE ((u32)0x00000001 << 24)/* Bit[24], disable or enable SPORT RX*/
#define SP_CTRLR0_START_RX ((u32)0x00000001 << 25)/* Bit[25], RX start*/
#define SP_CTRLR0_DAC_COMP ((u32)0x00000003 << 26)/* Bit[27:26], DAC compress*/
#define SP_CTRLR0_SEL_I2S_RX_CH ((u32)0x00000003 << 28)/* Bit[29:28], I2S RX channel select @ ADC path*/
#define SP_CTRLR0_MCLK_SEL ((u32)0x00000001 << 30)/* Bit[30], MCLK output select*/
#define SP_CTRLR0_LONG_FRAME_SYNC ((u32)0x00000001 << 31)/* Bit[31], short frame sync or long frame sync select*/
/** @} */
/**************************************************************************//**
* @defgroup SP_CTRLR1
* @{
*****************************************************************************/
#define SP_CTRLR1_FRAME_SYNC_OFFSET ((u32)0x000000FF) /* Bit[7:0], To control the length of "long_frame_sync" signal when it is ON.*/
#define SP_CTRLR1_DEBUG_BUS_SEL ((u32)0x00000007 << 8) /* Bit[10:8], debug_bus*/
#define SP_CTRLR1_CLEAR_TX_ERR_CNT ((u32)0x00000001 << 12)/* Bit[12], clear TX error counter*/
#define SP_CTRLR1_CLEAR_RX_ERR_CNT ((u32)0x00000001 << 13)/* Bit[13], clear RX error counter*/
#define SP_CTRLR1_MODE_40MHZ ((u32)0x00000001 << 16)/* Bit[16], clock source is 40MHz or not*/
#define SP_CTRLR1_MODE_128FS ((u32)0x00000001 << 17)/* Bit[17], clock source is 128*fs or not*/
#define SP_CTRLR1_TDMA_REQ ((u32)0x00000001 << 18)/* Bit[18], Tx DAM request*/
#define SP_CTRLR1_RDMA_REQ ((u32)0x00000001 << 19)/* Bit[19], Rx DAM request*/
#define SP_CTRLR1_TX_SRC_BYTE_SWAP ((u32)0x00000001 << 20)/* Bit[20], swap H/L bytes read from the source memory*/
#define SP_CTRLR1_TX_SRC_LR_SWAP ((u32)0x00000001 << 21)/* Bit[21], swap L/R audio samples read from the source memory*/
#define SP_CTRLR1_RX_SNK_BYTE_SWAP ((u32)0x00000001 << 22)/* Bit[22], swap H/L bytes written to the sink memory*/
#define SP_CTRLR1_RX_SNK_LR_SWAP ((u32)0x00000001 << 23)/* Bit[23], swap L/R audio samples written to the sink memory*/
#define SP_CTRLR1_INT_ENABLE ((u32)0x000000FF << 24)/* Bit[31:24], for the interrupt of "sp_ready_to_tx"/"sp_ready_to_rx" */
/** @} */
/**************************************************************************//**
* @defgroup SP_DSP_INT_CR
* @{
*****************************************************************************/
#define SP_TX_DSP_CLEAR_INT ((u32)0x00000001<<0) /* Bit[0], clear TX interrupt (DSP mode) */
#define SP_RX_DSP_CLEAR_INT ((u32)0x00000001<<1) /* Bit[1], clear RX interrupt (DSP mode)*/
#define SP_TX_FIFO_DEPTH_HALF_SEL ((u32)0x00000001<<4) /* Bit[4], 1'b1 TX FIFO depth will reduce to half. It can reduce the data path latency*/
#define SP_RX_FIFO_DEPTH_HALF_SEL ((u32)0x00000001<<5) /* Bit[5], 1'b1 RX FIFO depth will reduce to half. It can reduce the data path latency*/
#define SP_TX_DMA_SINGLE_NO_REQ ((u32)0x00000001<<18) /* Bit[18], 1'b1 TX dma single no request*/
#define SP_RX_DMA_SINGLE_NO_REQ ((u32)0x00000001<<19) /* Bit[19], 1'b1 RX dma single no request*/
/** @} */
/**************************************************************************//**
* @defgroup SP_FIFO_SR
* @{
*****************************************************************************/
#define SP_TX0_WCNT_BUS ((u32)0x000000FF<<0) /* Bit[7:0],TX0 FIFO write counter status (SPK path)*/
#define SP_TX1_WCNT_BUS ((u32)0x000000FF<<8) /* Bit[15:8],TX1 FIFO write counter status (SPK path)*/
#define SP_RX0_RCNT_BUS ((u32)0x000000FF<<16) /* Bit[23:16],RX0 FIFO read counter status (MIC path)*/
#define SP_RX1_RCNT_BUS ((u32)0x000000FF<<24) /* Bit[31:24],RX1 FIFO read counter status (MIC path)*/
/** @} */
/**************************************************************************//**
* @defgroup SP_ERROR_CNT_SR
* @{
*****************************************************************************/
#define SP_TX_ERR_CNT ((u32)0x000000FF<<0) /* Bit[7:0],TX error counter (SPK path)*/
#define SP_RX_ERR_CNT ((u32)0x000000FF<<8) /* Bit[15:8],RX error counter (MIC path)*/
/** @} */
/**************************************************************************//**
* @defgroup SP_CLK_DIV
* @{
*****************************************************************************/
#define SP_CLK_MI ((u32)0x0000FFFF<<0) /* Bit[15:0],BCLK clock divider */
#define SP_CLK_NI ((u32)0x00007FFF<<16) /* Bit[30:16],BCLK clock divider */
#define SP_CLK_MI_NI_UPDATE ((u32)0x00000001<<31) /* Bit[31],update "mi" and "ni" to get the new clock rate */
/** @} */
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
typedef struct
{
AUDIO_SPORT_TypeDef* SPORTx;
u32 Tx_HandshakeInterface;
u32 Rx_HandshakeInterface;
} AUDIO_DevTable;
extern const AUDIO_DevTable AUDIO_DEV_TABLE[1];
#define AUDIO_BLOCK_SIZE 2048
#endif /* _RTL8721D_I2S_H_ */
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_backup_reg.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the 16bytes backup registers
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_BACKUP_REG_H_
#define _RTL8721D_BACKUP_REG_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup BKUP_REG
* @brief BKUP_REG driver modules
* @{
*/
/** @addtogroup BKUP_REG
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* backup register size:
* -32bytes (8 dwords)
*
* usage:
* - user can use this registers to save some data before reset happens
*
* backup register can not be reset by following functions:
* - cpu reset
* - system reset
* - soc sleep mode
*
* backup register will be reset by following functions:
* - soc deep sleep mode
* - soc power down reset
* - soc power off
*
* system defined bits (other bits are reserved for user):
* - dword0[0]: system reset
* - dword0[1]: watchdog reset
* - dword0[2]: BOR2 HW temp bit
* - dword0[3]: this is SW set bit before reboot, for uart download
* - dword0[4]: this is SW set bit before reboot, for uart download debug
* - dword0[5]: this is SW set bit before reboot, for rtc init indication, not used now
* - dword0[6]: BOR2 HW temp bit
* - dword0[7]: 1: enable bor2 detection; 0: disable
*
*****************************************************************************************
* how to use
*****************************************************************************************
* BKUP_Write: write a dword backup register
* BKUP_Read: read a dword backup register
* BKUP_Set: set 1 to some bits of backup register
* BKUP_Clear: set 0 to some bits of backup register
*****************************************************************************************
* @endverbatim
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup BKUP_REG_Exported_Constants BKUP_REG Exported Constants
* @{
*/
/** @defgroup BKUP_REG_Idx_definitions
* @{
*/
#define BKUP_REG0 ((u32)0x00000000) /*!< byte1 is used by system */
#define BKUP_REG1 ((u32)0x00000001) /*!< all bits can be used by user */
#define BKUP_REG2 ((u32)0x00000002) /*!< all bits can be used by user */
#define BKUP_REG3 ((u32)0x00000003) /*!< all bits can be used by user */
#define BKUP_REG4 ((u32)0x00000004) /*!< all bits can be used by user */
#define BKUP_REG5 ((u32)0x00000005) /*!< all bits can be used by user */
#define BKUP_REG6 ((u32)0x00000006) /*!< all bits can be used by user */
#define BKUP_REG7 ((u32)0x00000007) /*!< all bits can be used by user */
#define IS_BKUP_REG(IDX) (((IDX) == BKUP_REG0) || \
((IDX) == BKUP_REG1) ||\
((IDX) == BKUP_REG2) ||\
((IDX) == BKUP_REG3) ||\
((IDX) == BKUP_REG4) ||\
((IDX) == BKUP_REG5) ||\
((IDX) == BKUP_REG6) ||\
((IDX) == BKUP_REG7))
/**
* @}
*/
/**
* @}
*/
/** @defgroup BKUP_REG_Exported_Functions BKUP_REG Exported Functions
* @{
*/
_LONG_CALL_ void BKUP_Write(u32 DwordIdx, u32 WriteVal);
_LONG_CALL_ u32 BKUP_Read(u32 DwordIdx);
_LONG_CALL_ void BKUP_Set(u32 DwordIdx, u32 BitMask);
_LONG_CALL_ void BKUP_Clear(u32 DwordIdx, u32 BitMask);
_LONG_CALL_ u32 BOOT_Reason(void);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup BKUP_REG_Register_Definitions BKUP_REG Register Definitions
* @{
*****************************************************************************/
/* @defgroup BKUP_REG_WDORD7
* @{
*/
#define BIT_MASK_FLASH_STRUCT_ADDR ((u32)0xFFFFFFFF) /*!< used to backup address of flash_init_para*/
/** @} */
/**************************************************************************//**
* @defgroup BKUP_REG_WDORD0 REG_LP_BOOT_REASON0
* @{
*****************************************************************************/
#define BIT_CAPTOUCH_ENABLE BIT(15) /*!< KM4 captouch init controlled by this bit*/
#define BIT_KEY_ENABLE BIT(14) /*!< KM4 key init controlled by this bit*/
#define BIT_KM4_WAKE_DELAY BIT(13) /*!< km4 wakeup should be delayed if wakeup happend when km4 suspend */
//#define BIT_RTC_RESTORE BIT(12) /*!< this is SW set bit after rtc init, not used now */
#define BIT_WIFI_ENABLE BIT(11) /*!< KM0 WIFIFW INIT & KM4 WIFI Driver INIT Controlled by this bit */
#define BIT_UARTBURN_DEBUG BIT(10) /*!< this is SW set bit before reboot, for uart download debug */
#define BIT_UARTBURN_BOOT BIT(9) /*!< this is SW set bit before reboot, for uart download */
#define BIT_SW_SIM_RSVD BIT(8) /*!< 1: boot for simulation */
#define BIT_RESVED_BIT7 BIT(7) /*!< RESVED */
#define BIT_RESVED_BIT6 BIT(6) /*!< RESVED */
#define BIT_GPIO_ENABLE BIT(5) /*!< KM4 GPIO wake up controlled by this bit */
#define BIT_KM4WDG_RESET_HAPPEN BIT(4) /*!< km4 watchdog reset */
#define BIT_KM4SYS_RESET_HAPPEN BIT(3) /*!< km4 system reset */
#define BIT_RESVED_BIT2 BIT(2) /*!< RESVED */
#define BIT_WDG_RESET_HAPPEN BIT(1) /*!< km0 watchdog reset */
#define BIT_SYS_RESET_HAPPEN BIT(0) /*!< km0 system reset */
#define BIT_MASK_BOOT_REASON ((u32)0x0000001F)
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
#endif //_RTL8710B_BACKUP_REG_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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#ifndef _HAL_8710B_BOOT_
#define _HAL_8710B_BOOT_
#if defined ( __ICCARM__ )
extern u8* __image2_entry_func__;
extern u8* __image1_bss_start__;
extern u8* __image1_bss_end__;
extern u8* __bss_start__;
extern u8* __bss_end__;
extern u8* __cmd_table_start__;
extern u8* __cmd_table_end__;
extern u8* __psram_bss_start__;
extern u8* __psram_bss_end__;
extern u8* __ram_nocache_start__;
extern u8* __ram_nocache_end__;
extern u8* __image3_bss_start__;
extern u8* __image3_bss_end__;
#else
extern u8 __image1_validate_code__[];
extern u8 __image1_bss_start__[];
extern u8 __image1_bss_end__[];
extern u8 __image2_entry_func__[];
extern u8 __bss_start__[];
extern u8 __bss_end__[];
extern u8 __cmd_table_start__[];
extern u8 __cmd_table_end__[];
extern u8 __psram_bss_start__[];
extern u8 __psram_bss_end__[];
extern u8 __ram_nocache_start__[];
extern u8 __ram_nocache_end__[];
extern u8 __image3_bss_start__[];
extern u8 __image3_bss_end__[];
#endif
extern u8 __rom_bss_start__[];
extern u8 __rom_bss_end__[];
extern u8 __rom_bss_start_s__[];
extern u8 __rom_bss_end_s__[];
extern u8 __rom_bss_start_ns__[];
extern u8 __rom_bss_end_ns__[];
extern u8 __ram_image3_start__[];
extern u8 __ram_image3_end__[];
extern u8 __psram_image3_start__[];
extern u8 __psram_image3_end__[];
extern u8 __flash_text_start__[];
extern u8 __flash_img2_end__[];
extern u8 __flash_sec_text_start__[];
extern u8 __ram_start_table_start__[];
extern u8 __rom_top_4k_start_[];
extern u8 __rom_entry_ns_start__[];
extern u8 __retention_entry_func__[];
enum _BOOT_TYPE_ {
BOOT_FROM_FLASH = 0,
BOOT_FROM_SDIO = 1,
BOOT_FROM_USB = 2,
BOOT_FROM_UART0 = 3,
BOOT_FROM_UART1 = 4,
BOOT_FROM_SPI = 5,
BOOT_FROM_RSVD = 6,
};
/* security boot */
typedef struct {
int (*ed25519_verify_signature)(const unsigned char sig[],
const unsigned char *m, unsigned long long mlen,
const unsigned char pk[]);
void (*clear_ns_rom_bss)(void);
} ROM_SECURE_CALL_NS_ENTRY;
enum _CPU_PWRSEQ_ {
CPU_PWRSEQ_CMD_READ = 0xFFFFFF00,
CPU_PWRSEQ_CMD_WRITE = 0xFFFFFF01,
CPU_PWRSEQ_CMD_POLLING = 0xFFFFFF02,
CPU_PWRSEQ_CMD_DELAY = 0xFFFFFF03,
CPU_PWRSEQ_CMD_LOGE = 0xFFFFFF08,
CPU_PWRSEQ_CMD_END = 0xFFFFFFFF,
};
typedef struct {
u32 address;
u32 cmd; /* read/write/polling/delay/end */
u32 bitsc; /* bit mask clear or polling target */
u32 bitss; /* bit mask set or polling mask */
} CPU_PWR_SEQ;
typedef enum {
IMG_LS_BOOT = 0,
IMG_BACKUP = 1,
IMG_SYSDATA = 2,
IMG_HS_BOOT = 3,
IMG_LS_IMG2_OTA1 = 4,
IMG_HS_IMG_COMB_OTA1 = 5,
IMG_LS_IMG2_OTA2 = 6,
IMG_HS_IMG_COMB_OTA2 = 7,
} Image_Type;
typedef struct {
u32 VAddrStart;
u32 VAddrEnd;
u32 PAddrStart;
u32 PAddrEnd;
} MMU_ConfDef;
#define OTA_INDEX_1 0
#define OTA_INDEX_2 1
typedef struct {
u32 MaskAddr; /*start address for RSIP Mask, should be 4KB aligned*/
u16 MaskSize; /*size of the mask area, unit is 4KB */
} RSIP_MaskDef;
typedef u8 (*FuncPtr)(void);
extern void SysTick_Handler( void );
extern void SVC_Handler( void );
extern void PendSV_Handler( void );
extern u32 BOOT_ROM_CM4PON(u32 pwr_cmd_addr);
extern void BOOT_FLASH_Image1(void);
extern void BOOT_FLASH_WakeFromPG(void);
extern void BOOT_RAM_FuncEnable(void);
extern u32 BOOT_RAM_FLASH_Calibration(u8 read_mode);
extern PRAM_START_FUNCTION BOOT_RAM_SectionInit(void);
extern u32 ROM_SIM_ENABLE;
extern u32 IS_FPGA_VERIF; /* set in boot flash, based on MACRO, can not be used in ROM code */
extern RAM_START_FUNCTION Img2EntryFun0; //RamWakeupFun
#endif //_HAL_8710B_BOOT_

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/**
******************************************************************************
* @file rtl8721d_bor.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the bor.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_BOR_H_
#define _RTL8721D_BOR_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup BOR
* @brief BOR driver modules
* @{
*/
/** @addtogroup BOR
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* functions:
* - set bor mode
* - bor high and low threshold set for reset or interrupt mode
* - bor debounce timer set
* - bor interrupt clear
*
*****************************************************************************************
* How to use BOR
*****************************************************************************************
* To use the BOR mode, the following steps are mandatory:
*
* 1. Choose bor mode using the follwoing functions.
* BOR_ModeSet(u32 Option, u32 NewStatus);
*
* 2. If Choose bor Interrupt mode, register bor Interrupt handler using the follwoing functions.
* InterruptRegister() : register bor Interrupt handler
* InterruptEn() : enable bor Interrupt
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup BOR_Exported_Types BOR Exported Types
* @{
*/
/** @defgroup BOR_Exported_Constants BOR Exported Constants
* @{
*/
/* Exported constants ------------------------------------------------------------*/
/** @defgroup BOR_Mode_definitions
* @{
*/
#define BOR_RESET ((u32)(0x00000001 << 0))
#define BOR_INTR ((u32)(0x00000001 << 1))
/**
* @}
*/
/** @defgroup BOR_Debounce_Threshold_definitions
* @{
*/
#define IS_BOR_INTR_DBNC_THRES(DBNC) ((DBNC) <= 0x7FFF)
/**
* @}
*/
/** @defgroup BOR_Threshold_HIGH_definitions
* @{
*/
#define BOR_TH_HIGH0 ((u32)0x000000000)
#define BOR_TH_HIGH1 ((u32)0x000000001)
#define BOR_TH_HIGH2 ((u32)0x000000002)
#define BOR_TH_HIGH3 ((u32)0x000000003)
#define BOR_TH_HIGH4 ((u32)0x000000004)
#define BOR_TH_HIGH5 ((u32)0x000000005)
#define BOR_TH_HIGH6 ((u32)0x000000006)
#define BOR_TH_HIGH7 ((u32)0x000000007)
#define IS_BOR_TH_HIGH(TYPE) (((TYPE) == BOR_TH_HIGH0) || ((TYPE) == BOR_TH_HIGH1) || \
((TYPE) == BOR_TH_HIGH2) || ((TYPE) == BOR_TH_HIGH3) || \
((TYPE) == BOR_TH_HIGH4) || ((TYPE) == BOR_TH_HIGH5) || \
((TYPE) == BOR_TH_HIGH6) || ((TYPE) == BOR_TH_HIGH7))
/**
* @}
*/
/** @defgroup BOR_Threshold_LOW_definitions
* @{
*/
#define BOR_TH_LOW0 ((u32)0x000000000)
#define BOR_TH_LOW1 ((u32)0x000000001)
#define BOR_TH_LOW2 ((u32)0x000000002)
#define BOR_TH_LOW3 ((u32)0x000000003)
#define BOR_TH_LOW4 ((u32)0x000000004)
#define BOR_TH_LOW5 ((u32)0x000000005)
#define BOR_TH_LOW6 ((u32)0x000000006)
#define BOR_TH_LOW7 ((u32)0x000000007)
#define IS_BOR_TH_LOW(TYPE) (((TYPE) == BOR_TH_LOW0) || ((TYPE) == BOR_TH_LOW1) || \
((TYPE) == BOR_TH_LOW2) || ((TYPE) == BOR_TH_LOW3) || \
((TYPE) == BOR_TH_LOW4) || ((TYPE) == BOR_TH_LOW5) || \
((TYPE) == BOR_TH_LOW6) || ((TYPE) == BOR_TH_LOW7))
/**
* @}
*/
/**
* @}
*/
/** @defgroup BOR_Exported_Functions BOR Exported Functions
* @{
*/
VOID BOR_ThresholdSet(u32 Thres_Low, u32 Thres_High);
VOID BOR_DbncSet(u32 Option, u32 Dbnc_Value);
VOID BOR_ClearINT(void);
VOID BOR_ModeSet(u32 Option, u32 NewStatus);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif //_RTL8721D_BOR_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_cache.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the flash cache firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_CACHE_H_
#define _RTL8710B_CACHE_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup CACHE
* @brief CACHE modules
* @{
*/
/** @addtogroup CACHE
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* -just support read cache.
* -32K bytes.
* -used for flash read and XIP.
*
*****************************************************************************************
* how to use
*****************************************************************************************
* Cache_Enable: enable/disable cache
* Cache_Flush: flush cache, you should Cache_Flush after flash write or flash erase
*****************************************************************************************
* @endverbatim
*/
/** @defgroup CACHE_Type_define
* @{
*/
#define DATA_CACHE ((u32)0x00000000)
#define CODE_CACHE ((u32)0x00000001)
/**
* @}
*/
/** @defgroup CACHE_Line_Aligned_define
* @{
*/
#define CACHE_LINE_SIZE 32
#define CACHE_LINE_ADDR_MSK 0xFFFFFFE0
#define IS_CACHE_LINE_ALIGNED_SIZE(BYTES) ((BYTES & 0x1F) == 0)
#define IS_CACHE_LINE_ALIGNED_ADDR(ADDR) ((ADDR & 0x1F) == 0)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CACHE_Exported_Functions FLash Cache Exported Functions
* @{
*/
/**
* @brief Disable/Enable I/D cache.
* @param Enable
* This parameter can be any combination of the following values:
* @arg ENABLE cache enable & SPIC read 16bytes every read command
* @arg DISABLE cache disable & SPIC read 4bytes every read command
*/
__STATIC_INLINE
void Cache_Enable(u32 Enable)
{
if (Enable) {
SCB_EnableICache();
SCB_EnableDCache();
} else {
SCB_DisableICache();
SCB_DisableDCache();
}
}
/**
* @brief flush I/D cache.
*/
__STATIC_INLINE
void Cache_Flush(void)
{
SCB_InvalidateICache();
SCB_InvalidateDCache();
}
/**
* @brief Enable Icache.
*/
__STATIC_INLINE
void ICache_Enable(void)
{
SCB_EnableICache();
}
/**
* @brief Disable Icache.
*/
__STATIC_INLINE
void ICache_Disable(void)
{
SCB_DisableICache();
}
/**
* @brief Invalidate Icache.
*/
__STATIC_INLINE
void ICache_Invalidate(void)
{
SCB_InvalidateICache ();
}
/**
* @brief Check DCache Enabled or not.
*/
__STATIC_INLINE
u32 DCache_IsEnabled(void)
{
return ((SCB->CCR & (u32)SCB_CCR_DC_Msk)?1:0);
}
/**
* @brief Enable Dcache.
*/
__STATIC_INLINE
void DCache_Enable(void)
{
SCB_EnableDCache();
}
/**
* @brief Disable Dcache.
*/
__STATIC_INLINE
void DCache_Disable(void)
{
SCB_DisableDCache();
}
/**
* @brief D-Cache Invalidate by address.
* @details Invalidates D-Cache for the given address
* @param Address address (aligned to 32-byte boundary)
* @param Bytes size of memory block (in number of bytes)
*
* @note Dcache will be restored from memory.
* @note This can be used after DMA Rx, and CPU read DMA data from DMA buffer.
* @note if Address is 0xFFFFFFFF, it means dont care, it was used when all Dcache be Invalidated.
*/
__STATIC_INLINE
void DCache_Invalidate(u32 Address, u32 Bytes)
{
u32 addr = Address, len = Bytes;
if (DCache_IsEnabled() == 0)
return;
if ((Address == 0xFFFFFFFF) && (Bytes == 0xFFFFFFFF)) {
SCB_InvalidateDCache();
} else {
if ((addr & 0x1F) != 0) {
addr = (Address >> 5) << 5; //32-byte aligned
len = ((((Address + Bytes -1) >> 5) + 1) << 5) - addr; //next 32-byte aligned
}
SCB_InvalidateDCache_by_Addr((u32*)addr, len);
}
}
/**
* @brief D-Cache Clean by address
* @details Cleans D-Cache for the given address
* @param Address address (aligned to 32-byte boundary)
* @param Bytes size of memory block (in number of bytes)
*
* @note Dcache will be write back to memory.
* @note This can be used before DMA Tx, after CPU write data to DMA buffer.
* @note if Address is 0xFFFFFFFF, it means dont care, it was used when all Dcache be cleaned.
* @note AmebaD cache is default read allocation and write through, so clean is not needed.
*/
__STATIC_INLINE
void DCache_Clean(u32 Address, u32 Bytes)
{
u32 addr = Address, len = Bytes;
if (DCache_IsEnabled() == 0)
return;
if ((Address == 0xFFFFFFFF) && (Bytes == 0xFFFFFFFF)) {
SCB_CleanDCache();
} else {
if ((addr & 0x1F) != 0) {
addr = (Address >> 5) << 5; //32-byte aligned
len = ((((Address + Bytes -1) >> 5) + 1) << 5) - addr; //next 32-byte aligned
}
SCB_CleanDCache_by_Addr((u32*)addr, len);
}
}
/**
* @brief D-Cache Clean and Invalidate by address
* @details Cleans and invalidates D_Cache for the given address
* @param Address address (aligned to 32-byte boundary)
* @param Bytes size of memory block (in number of bytes)
*
* @note This can be used when you want to write back cache data and then Invalidate cache.
* @note if Address is 0xFFFFFFFF, it means dont care, it was used when all Dcache be cleaned.
*/
__STATIC_INLINE
void DCache_CleanInvalidate(u32 Address, u32 Bytes)
{
u32 addr = Address, len = Bytes;
if (DCache_IsEnabled() == 0)
return;
if ((Address == 0xFFFFFFFF) && (Bytes == 0xFFFFFFFF)) {
SCB_CleanInvalidateDCache();
} else {
if ((addr & 0x1F) != 0) {
addr = (Address >> 5) << 5; //32-byte aligned
len = ((((Address + Bytes -1) >> 5) + 1) << 5) - addr; //next 32-byte aligned
}
SCB_CleanInvalidateDCache_by_Addr((u32*)addr, len);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif //_RTL8710B_CACHE_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_captouch.h
* @author
* @version V1.0.0
* @date 2017-10-16
* @brief This file contains all the functions prototypes for the captouch.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_CAPTOUCH_H_
#define _RTL8721D_CAPTOUCH_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @addtogroup CapTouch CapTouch
* @{
*/
/** @addtogroup CapTouch
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* CAPTOUCH:
* - Base Address: CAPTOUCH_DEV
* - Clock source : 32.768KHz
* - Scan interval timer: 1.024KHz(32.768KHz/32)
* - Debounce Timer: Configurable
* - SocPs: Sleep Mode (clock gating & power gating)
* - IRQ: CapTouch_IRQ
*
*****************************************************************************************
* How to use Normal CapTouch
*****************************************************************************************
* To use the normal CapTouch mode, the following steps are mandatory:
*
* 1. Enable CapTouch peripheral clock
*
* 2. Configure the CapTouch pinmux.
*
* 3. Init Captouch parameters:
* CapTouch_StructInit(CapTouch_InitTypeDef* CapTouch_InitStruct)
*
* 4. Init Hardware use step3 parameters:
* CapTouch_Init(CAPTOUCH_TypeDef *CapTouch, CapTouch_InitTypeDef* CapTouch_InitStruct)
*
* 5. Enable the NVIC and the corresponding interrupt using following function if you need
* to use interrupt mode.
* CapTouch_INTConfig(): CapTouch IRQ Enable set
* CapTouch_INTMask(): CapTouch IRQ mask set
* InterruptRegister(): register the captouch irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 6. Enable CapTouch module using CapTouch_Cmd().
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types --------------------------------------------------------*/
/** @defgroup CapTouch_Exported_Types CapTouch Exported Types
* @{
*/
/**
* @brief CapTouch Channel Initialization structure definition
*/
typedef struct {
u16 CT_DiffThrehold; /*!< Difference threshold data of touch judgement for channelx :
1. Configured during development; (0x0~0xFFF) (0~4095)
2. Init number=0x0, need to be configured
3. recommend data=80%*(signal-baseline); */
u8 CT_MbiasCurrent; /*!< Channelx mbias current tuning(sensitivity tuning).
Touch bias current BIT[5] ~ BIT[0]: 8uA/4uA/2uA/1uA/0.5uA/0.25uA.
The sensitivity parameter is used to increase or decrease the strength
of the sensor signal (difference count). A higher value of sensitivity (bias current)
setting leads to a stronger signal from the sensors (more difference
count for the same capacitance change), but also increases the response
time and average power consumption.*/
u8 CT_ETCNNoiseThr; /*!< Specifies negetive noise threshold of ETC.
This parameter must be set to a value in the 0x1-0xff range.
The noise threshold indicates the raw data of the maximum capacitance change
caused by environmental change. The CTC system provides configurable
positive noise threshold and negative noise threshold for optimal calibration.
The recommend value of noise threshold is 40%* touch threshold. Users need
tune the two noise thresholds for different applications and noise environment.*/
u8 CT_ETCPNoiseThr; /*!< Specifies positive threshold of ETC.
This parameter must be set to a value in the 0x1-0xff range. */
u8 CT_CHEnable; /*!< Specifies this channel is enable or not */
} CapTouch_CHInitTypeDef;
/**
* @brief CapTouch Initialization structure definition
*/
typedef struct {
u32 CT_DebounceEn; /*!< Specifies CapTouch press event Debounce Enable.
This parameter must be set to a value in the 0x0-1 range. The de-bounce
parameter can be configured by register CTC_CTRL.
For example, when de-bounce is enabled and configured as 00 (2 times scan),
finger touch interrupt will not be sent to the host until 2 times continue
finger touch event is detected. Sensor de-bounce function is suitable for
both button application and proximity detection.*/
u32 CT_SampleCnt; /*!< Specifies sample cnt for average function,sample cnt = 2*exp(CT_SampleCnt+2).
This parameter can be a value of 0x0-0x7*/
u32 CT_ScanInterval; /*!< Specifies scan interval of every key.
This parameter must be set to a value in the 0x1-0xfff range. */
u32 CT_ETCStep; /*!< Specifies baseline update setp of ETC.
This parameter must be set to a value in the 0x0-0xfff range. */
u32 CT_ETCFactor; /*!< Specifies CapTouch ETC Factor.
This parameter must be set to a value in the 0x0-0xf range. */
u32 CT_ETCScanInterval; /*!< Specifies ETC scan interval
This parameter can be set to a value in the 0x1-0x7f range*/
CapTouch_CHInitTypeDef CT_Channel[5]; /*!< Specifies the initialization parameters for each channel */
}CapTouch_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CapTouch_Exported_Constants CapTouch Exported Constants
* @{
*/
/** @defgroup CapTouch_Peripheral_definitions
* @{
*/
#define IS_CAPTOUCH_ALL_PERIPH(PERIPH) ((PERIPH) == CAPTOUCH_DEV)
/**
* @}
*/
/** @defgroup CapTouch_INT_Related_definitions
* @{
*/
#define CT_CHX_PRESS_INT(x) (0x00000001 << (x))
#define CT_CHX_RELEASE_INT(x) (0x00000001 << ((x) + 8))
#define IS_CT_INT_EN(IT) (((IT) & ~BIT_CT_ALL_INT_EN) == 0)
#define IS_CT_INT_CLR(IT) (((IT) & ~BIT_CT_ALL_INT_CLR_MASK) == 0)
/**
* @}
*/
/** @defgroup CapTouch_Channel_Related_definitions
* @{
*/
#define CT_CHANNEL_NUM 4
#define IS_CT_CHANNEL(CHANNEL_NUM) (CHANNEL_NUM < CT_CHANNEL_NUM)
/**
* @}
*/
/** @defgroup CapTouch_Noise_Threshold_Type_definitions
* @{
*/
#define P_NOISE_THRES 0
#define N_NOISE_THRES 1
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CapTouch_Exported_Functions CapTouch Exported Functions
* @{
*/
/** @defgroup CapTouch_Exported_Normal_Functions CapTouch Normal Functions
* @{
*/
void CapTouch_StructInit(CapTouch_InitTypeDef* CapTouch_InitStruct);
void CapTouch_Init(CAPTOUCH_TypeDef *CapTouch, CapTouch_InitTypeDef* CapTouch_InitStruct);
void CapTouch_Cmd(CAPTOUCH_TypeDef *CapTouch, u8 NewState);
void CapTouch_INTConfig(CAPTOUCH_TypeDef *CapTouch, uint32_t CapTouch_IT, u8 newState);
void CapTouch_INTClearPendingBit(CAPTOUCH_TypeDef *CapTouch, u32 CapTouch_IT);
u32 CapTouch_GetRawISR(CAPTOUCH_TypeDef *CapTouch);
u32 CapTouch_GetISR(CAPTOUCH_TypeDef *CapTouch);
void CapTouch_SetScanInterval(CAPTOUCH_TypeDef *CapTouch, u32 Interval);
void CapTouch_ChCmd(CAPTOUCH_TypeDef *CapTouch, u8 Channel, u8 NewState);
u32 CapTouch_GetChStatus(CAPTOUCH_TypeDef *CapTouch, u32 Channel);
void CapTouch_SetChDiffThres(CAPTOUCH_TypeDef *CapTouch, u8 Channel, u32 Threshold);
void CapTouch_SetChMbias(CAPTOUCH_TypeDef *CapTouch, u8 Channel, u8 Mbias);
u32 CapTouch_GetChDiffThres(CAPTOUCH_TypeDef *CapTouch, u8 Channel);
u32 CapTouch_GetNoiseThres(CAPTOUCH_TypeDef *CapTouch, u8 Channel, u8 type);
u32 CapTouch_GetChBaseline(CAPTOUCH_TypeDef *CapTouch, u8 Channel);
u32 CapTouch_GetChAveData(CAPTOUCH_TypeDef *CapTouch, u8 Channel);
/**
* @}
*/
/** @defgroup CapTouch_Exported_Debug_Functions CapTouch Debug Functions
* @{
*/
void CapTouch_DbgCmd(CAPTOUCH_TypeDef *CapTouch, u8 NewState);
void CapTouch_DbgDumpReg(CAPTOUCH_TypeDef *CapTouch);
void CapTouch_DbgDumpETC(CAPTOUCH_TypeDef *CapTouch, u32 ch);
u32 CapTouch_DbgRawData(CAPTOUCH_TypeDef *CapTouch);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup CapTouch_Register_Definitions CapTouch Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup CT_CTRL
* @{
*****************************************************************************/
#define BIT_CT_BL_ENABLE ((u32)0x0000001 << 8) /*Bit[8], bits for base init enable*/
#define BIT_CT_DBN_CNT ((u32)0x0000003 << 5) /*Bit[6:5], bits for debounce cnt*/
#define BIT_CT_DBN_ENABLE ((u32)0x0000001 << 4) /*Bit[4], bits for base init enable*/
#define BIT_CT_ENABLE ((u32)0x0000001 << 0) /*Bit[8], bits for captouch function enable*/
/** @} */
/**************************************************************************//**
* @defgroup CT_SP_CTRL
* @{
*****************************************************************************/
#define BIT_CT_SMP_AVE ((u32)0x00000007 << 16) /*Bit[18:16], bits for every chanel sample cnt*/
#define BIT_CT_SCAN_INTERVAL ((u32)0x00000fff << 0) /*Bit[11:0], bits for pre guard timer set*/
/** @} */
/**************************************************************************//**
* @defgroup CT_ETC_CTRL
* @{
*****************************************************************************/
#define BIT_CT_ETC_N_THRES ((u32)0x000000ff << 24) /*Bit[31:24], bits for Max negative threshold*/
#define BIT_CT_ETC_P_THRES ((u32)0x000000ff << 16) /*Bit[23:16], bits for Max positive threshold*/
#define BIT_CT_ETC_STEP ((u32)0x0000000f << 12) /*Bit[15:12], bits for ETC setp for every update*/
#define BIT_CT_ETC_FACTOR ((u32)0x0000000f << 8) /*Bit[11:8], bits for ETC interval timer*/
#define BIT_CT_ETC_SCAN_INTERVAL ((u32)0x0000007f << 1) /*Bit[7:1], bits for ETC scan interval timer set*/
#define BIT_CT_ETC_ENABLE ((u32)0x00000001 << 0) /*Bit[0], bits for ETC function Enable*/
/** @} */
/**************************************************************************//**
* @defgroup CT_SNR
* @{
*****************************************************************************/
#define BIT_CT_SNR_NOISE ((u32)0x00000fff << 16) /*Bit[27:16], bit raw noise data for SNR*/
#define BIT_CT_SNR_TOUCH ((u32)0x00000fff << 0) /*Bit[11:0], bit raw touch data for SNR*/
/** @} */
/**************************************************************************//**
* @defgroup CT_MODE_CTRL
* @{
*****************************************************************************/
#define BIT_CT_CHANNEL_SEL ((u32)0x00000007 << 5) /*Bit[7:5], bits for captouch channel select*/
#define BIT_CT_AUTO_CHANNEL_ENABLE ((u32)0x00000001 << 4) /*Bit[4], bits for captouch auto channel swith enable*/
#define BIT_CT_DBG_ENABLE ((u32)0x00000001 << 0) /*Bit[0], bits for captouch debug mode enable*/
/** @} */
/**************************************************************************//**
* @defgroup CT_FIFO_STATUS
* @{
*****************************************************************************/
#define BIT_CT_FIFO_OFFSET ((u32)0x00000007 << 4) /*Bit[6:4], bits for key column select*/
#define BIT_CT_FIFO_EMPTY ((u32)0x00000001 << 1) /*Bit[1], bit for fifo full flag*/
#define BIT_CT_FIFO_FULL ((u32)0x00000001 << 0) /*Bit[0], bit for fifo full flag*/
/** @} */
/**************************************************************************//**
* @defgroup CT_FIFO
* @{
*****************************************************************************/
#define BIT_CT_FIFO_VLD ((u32)0x00000001 << 31) /*Bit[31], bit for fifo data valid flag*/
#define BIT_CT_FIFO_DATA ((u32)0x00000fff << 0) /*Bit[11:0], bit for fifo raw data*/
/** @} */
/**************************************************************************//**
* @defgroup CT_IER_ISR_RAWISR
* @{
*****************************************************************************/
#define BIT_CT_OVER_N_NOISE_THRESHOLD_INT ((u32)0x00000001 << 18) /*Bit[18], bit for captouch over negetive noise thresh interrupt enable*/
#define BIT_CT_FIFO_OVERFLOW_INT ((u32)0x00000001 << 17) /*Bit[17], bit for captouch fifo overflow interrupt enable*/
#define BIT_CT_OVER_P_NOISE_THRESHOLD_INT ((u32)0x00000001 << 16) /*Bit[16], bit for captouch over positive noise thresh interrupt enable*/
#define BIT_CT_TOUCH_RELEASE_INT ((u32)0x0000001f << 8) /*Bit[12:8], bit for captouch release interrupt enable*/
#define BIT_CT_TOUCH_PRESS_INT ((u32)0x0000001f <<0) /*Bit[4:0], bit for captouch press interrupt enable*/
#define BIT_CT_ALL_INT_EN ((u32)0x00031f1f)
/** @} */
/**************************************************************************//**
* @defgroup CT_ICR_ALL
* @{
*****************************************************************************/
#define BIT_CT_ALL_INT_CLR ((u32)0x00000001 << 0) /*Bit[0], bit for clear all interrupt status*/
/** @} */
/**************************************************************************//**
* @defgroup CT_ICR
* @{
*****************************************************************************/
#define BIT_CT_N_NOISE_OVERFLOW_INT_CLR ((u32)0x00000001 << 18) /*Bit[18], bit for captouch negetive noise interrupt clear*/
#define BIT_CT_FIFO_OVERFLOW_INT_CLR ((u32)0x00000001 << 17) /*Bit[17], bit for captouch fifo overflow interrupt clear*/
#define BIT_CT_P_NOISE_OVERFLOW_INT_CLR ((u32)0x00000001 << 16) /*Bit[16], bit for captouch positive noise interrupt clear*/
#define BIT_CT_TOUCH_RELEASE_INT_CLR ((u32)0x0000001f << 8) /*Bit[12:8], bit for captouch release interrupt clear*/
#define BIT_CT_TOUCH_PRESS_INT_CLR ((u32)0x0000001f <<0) /*Bit[4:0], bit for captouch press interrupt clear*/
#define BIT_CT_ALL_INT_CLR_MASK ((u32)0x00071f1f)
/** @} */
/**************************************************************************//**
* @defgroup CT_CHX_CTRL
* @{
*****************************************************************************/
#define BIT_CT_CHX_TOUCH_THRES ((u32)0x00000fff << 16) /*Bit[27:16], bit for touch difference threshold*/
#define BIT_CT_CHX_BASELINE ((u32)0x00000fff << 4) /*Bit[15:4], bit for touch pad baseline*/
#define BIT_CT_CHX_ENABLE ((u32)0x00000001 << 0) /*Bit[0], bit for touch pad channel enable*/
/** @} */
/**************************************************************************//**
* @defgroup CT_CHX_ATHR
* @{
*****************************************************************************/
#define BIT_MASK_CHX_N_ENT ((u32)0x000000ff << 24)
#define BIT_MASK_CHX_P_ENT ((u32)0x000000ff << 16)
#define BIT_CT_CHX_TOUCH_ATHRES ((u32)0x00000fff << 0) /*Bit[11:0], bit for touch difference absolute threshold*/
/** @} */
/**************************************************************************//**
* @defgroup CT_CHX_MBIAS
* @{
*****************************************************************************/
#define BIT_CT_CHX_MBIAS ((u32)0x0000003f << 0) /*Bit[6], bit for touch key mbias current*/
/** @} */
/**************************************************************************//**
* @defgroup CT_CHX_DATA
* @{
*****************************************************************************/
#define BIT_CT_CHX_POLARITY ((u32)0x00000001 << 28) /*Bit[28], bit for diff data ploarity*/
#define BIT_CT_CHX_DIFF ((u32)0x00000fff <<16) /*Bit[27:16], bit for diff between average data and baseline*/
#define BIT_CT_CHX_DATA ((u32)0x00000fff << 0) /*Bit[11:0], bit for captouch channelx average data*/
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
#endif
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8711b_clk.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the following
* functionalities of clock control:
* - NCO32K clock
* - NCO8M clock
* - CPU clock
* - XTAL clock get
* - OSC32K clock
* - EXT32K clock
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_CLK_H_
#define _RTL8721D_CLK_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup CLOCK
* @brief CLOCK driver modules
* @{
*/
/** @addtogroup CLOCK
* @verbatim
*****************************************************************************************
* NCO32K
*****************************************************************************************
* -RTC clock in
* -TIM0-TIM3 clock in
* -WIFI 32K clock in
*****************************************************************************************
* OSC32K OSC8M
*****************************************************************************************
* -OSC32K is used to calibration OSC8M
* -OSC8M is used for LP UART when SOC suspend and close XTAL
*****************************************************************************************
*****************************************************************************************
* NCO8M
*****************************************************************************************
* -used for LP UART when SOC active
* -Clock in is XTAL (40MHz)
* -Clock out is 8MHz
*
*****************************************************************************************
* HS CPU clock
*****************************************************************************************
* -CLK_KM4_200M: 200MHz
* -CLK_KM4_100M: 100MHz
* -CLK_KM4_50M: 50MHz
* -CLK_KM4_25M: 25MHz
* -CLK_KM4_XTAL: XTAL
*
*****************************************************************************************
* XTAL clock
*****************************************************************************************
* -Get XTAL clock from EFUSE setting:
* -40000000
* -25000000
* -13000000
* -19200000
* -20000000
* -26000000
* -38400000
* -17664000
* -16000000
* -14318000
* -12000000
* -52000000
* -48000000
* -26000000
* -27000000
* -24000000
*****************************************************************************************
* EXT32K
*****************************************************************************************
* -External 32K: 32K clock from external 32k source
* -Internal 32K: 32K clock from internal 32K source: NCO32K
*
*****************************************************************************************
* @endverbatim
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CLK_Exported_Constants CLK Exported Constants
* @{
*/
/** @defgroup SDM32K_Cal_Type_definitions
* @{
*/
#define SDM32K_ONE_CAL 0
#define SDM32K_AUTO_CAL 1
#define SDM32K_ALWAYS_CAL 2
/**
* @}
*/
/** @defgroup LP_CPU_CLK_definitions
* @{
*/
#define CLK_KM0_XTAL 0 /* if XTAL is 26MHz, we can use it */
#define CLK_KM0_XTALDIV2 1 /* if XTAL is 40MHz, we should use it */
#define CLK_KM0_ANA_4M 2 /* if XTAL OFF, default config */
/**
* @}
*/
/** @defgroup HS_CPU_CLK_definitions
* @{
*/
#define CLK_KM4_200M 0
#define CLK_KM4_100M 1
#define CLK_KM4_50M 2
#define CLK_KM4_25M 3
#define CLK_KM4_XTAL 4
/**
* @}
*/
/** @defgroup PLL_SEL_definitions
* @{
*/
#define PLL_I2S 0
#define PLL_PCM 1
/** @defgroup PLL_ClkTune_definitions
* @{
*/
#define PLL_AUTO 0
#define PLL_FASTER 1
#define PLL_SLOWER 2
/**
* @}
*/
/** @defgroup OSC2M_Cal_definitions
* @{
*/
#define OSC2M_CAL_CYC_16 0
#define OSC2M_CAL_CYC_32 1
#define OSC2M_CAL_CYC_64 2
#define OSC2M_CAL_CYC_128 3
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SDM32K_CLK_Exported_Functions SDM32K_CLK Exported Functions
* @{
*/
_LONG_CALL_ void SDM32K_Enable(u32 AutoCalibration);
_LONG_CALL_ void SDM32K_RTCCalEnable(u32 RTCCalibration);
/**
* @}
*/
/** @defgroup EXT32K_CLK_Exported_Functions EXT32K_CLK Exported Functions
* @{
*/
_LONG_CALL_ void EXT32K_Cmd(u32 NewStatus);
/**
* @}
*/
/** @defgroup CPU_CLK_Exported_Functions CPU_CLK Exported Functions
* @{
*/
_LONG_CALL_ u32 CPU_ClkGet(u8 Is_FPGA);
_LONG_CALL_ void CPU_ClkSet(u8 CpuType);
/**
* @}
*/
/** @defgroup XTAL_CLK_Exported_Functions XTAL_CLK Exported Functions
* @{
*/
_LONG_CALL_ u32 XTAL_ClkGet(void);
/**
* @}
*/
/** @defgroup NCO2M_CLK_Exported_Functions NCO2M_CLK Exported Functions
* @{
*/
_LONG_CALL_ void NCO2M_Init(u32 clk_out_Hz);
_LONG_CALL_ void NCO2M_Cmd(u32 NewState);
/**
* @}
*/
/** @defgroup PLL_Exported_Functions PLL Exported Functions
* @{
*/
_LONG_CALL_ void PLL_I2S_Set(u32 new_state);
_LONG_CALL_ void PLL_PCM_Set(u32 new_state);
_LONG_CALL_ void PLL2_Set(u32 BitMask, u32 NewState);
_LONG_CALL_ void PLL3_Set(u32 BitMask, u32 NewState);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup CLK_Register_Definitions CLK Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup REG_SYS_SYSPLL_CTRL2
* @{
*****************************************************************************/
#define BIT_SYS_SYSPLL_CK_ADC_EN (0x00000001 << 25) /*!< Set ADC PLL EN */
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Other definations --------------------------------------------------------*/
u32 OSC2M_Calibration(u32 cal_osc_cycles, u32 ppm_limit);
u32 OSC131K_Calibration(u32 ppm_limit);
void OSC4M_Init(void);
#endif //_RTL8721D_CLK_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_comparator.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the Comparator firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_COMPARE_H_
#define _RTL8721D_COMPARE_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup Comparator
* @brief Comparator driver modules
* @{
*/
/** @addtogroup Comparator
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* Comparator:
* - Base Address: Comparator
* - Channel: 4
* - Adjustable internal comparison voltage, 0~3.3v, each step 0.1v
* - Adjustable internal divider resistors
* - Cooperate with ADC comparator-assist mode
*
*****************************************************************************************
* How to use Comparator
*****************************************************************************************
* To use Comparator, the following steps are mandatory:
*
* 1. Enable the ADC & Comparator interface clock:
* RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
*
* 2. Fill the CMP_InitStruct with the desired parameters.
* CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct)
*
* 3. Init Comparator with the parameters in CMP_InitStruct.
* CMP_Init(CMP_InitTypeDef* CMP_InitStruct)
*
* 4. Activate the Comparator:
* CMP_Cmd(ENABLE).
*
* 5. Enbale specified mode:
* CMP_SWTrigCmd(ENABLE)/CMP_AutoCSwCmd(ENABLE)/ \
* CMP_TimerTrigCmd(Tim_Idx, PeriodMs, ENABLE)
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup COMP_Exported_Types COMP Exported Types
* @{
*/
/**
* @brief Comparator Init structure definition
*/
typedef struct {
u8 CMP_ChIndex; /*!< Specifies the channel index */
u8 CMP_Ref0; /*!< Specifies the internal reference voltage0, the value can be 0~31,
Vref0 = CMP_Ref0*0.1v */
u8 CMP_Ref1; /*!< Specifies the internal reference voltage1, the value can be 0~31,
Vref1 = CMP_Ref1*0.1v */
u8 CMP_WakeType; /*!< Specifies this channel wakeup system or ADC when criterion matches.
This parameter can be a value or combination of
@ref COMP_Compare_Wakeup_Type_Definitions */
u8 CMP_WakeSysCtrl; /*!< Specifies the criteria of when comparator channel should wakeup
system, which can be a value of
@ref COMP_Compare_Control_Definitions */
u8 CMP_WakeADCCtrl; /*!< Specifies the criteria of when comparator channel should wakeup
ADC, which can be a value of
@ref COMP_Compare_Control_Definitions */
} CMP_CHTypeDef;
typedef struct {
CMP_CHTypeDef CMP_ChanCtrl[4]; /*!< Specifies the comparator channel control parameters */
} CMP_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup COMP_Exported_Constants COMP Exported Constants
* @{
*/
/** @defgroup COMP_Chn_Selection
* @{
*/
#define COMP_CH0 ((u8)0x00)
#define COMP_CH1 ((u8)0x01)
#define COMP_CH2 ((u8)0x02)
#define COMP_CH3 ((u8)0x03)
#define COMP_CH_NUM (4)
#define IS_COMP_CHN_SEL(SEL) (((SEL) == COMP_CH0) || \
((SEL) == COMP_CH1) || \
((SEL) == COMP_CH2) || \
((SEL) == COMP_CH3))
/**
* @}
*/
/** @defgroup COMP_Compare_Control_Definitions
* @{
*/
#define COMP_SMALLER_THAN_REF0 ((u8)0x00) /*!< Vin < Vref0 */
#define COMP_GREATER_THAN_REF1 ((u8)0x01) /*!< Vin >= Vref1 */
#define COMP_WITHIN_REF0_AND_REF1 ((u8)0x02) /*!< Vin > Vref0 && Vin < Vref1 */
/**
* @}
*/
/** @defgroup COMP_Compare_Wakeup_Type_Definitions
* @{
*/
#define COMP_WK_SYS BIT(1)
#define COMP_WK_ADC BIT(0)
#define COMP_WK_NONE 0
/**
* @}
*/
/**
* @}
*/
/** @defgroup COMP_Exported_Functions COMP Exported Functions
* @{
*/
_LONG_CALL_ void CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct);
_LONG_CALL_ void CMP_Init(CMP_InitTypeDef* CMP_InitStruct);
_LONG_CALL_ void CMP_Cmd(u32 NewState);
_LONG_CALL_ u32 CMP_Busy(void);
_LONG_CALL_ u32 CMP_GetISR(void);
_LONG_CALL_ void CMP_INTClearPendingBit(u32 Cmp_IT);
_LONG_CALL_ u32 CMP_GetCompStatus(u8 channel);
_LONG_CALL_ u32 CMP_GetLastChan(void);
_LONG_CALL_ void CMP_ResetCSwList(void);
_LONG_CALL_ void CMP_AutoCSwCmd(u32 NewState);
_LONG_CALL_ void CMP_TimerTrigCmd(u8 Tim_Idx, u32 PeriodMs, u32 NewState);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup COMP_Register_Definitions COMP Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup REG_COMP_REF_CHx
* @{
*****************************************************************************/
#define BIT_SHIFT_COMP_REF1 16
#define BIT_MASK_COMP_REF1 (u32)(0x0000001F << BIT_SHIFT_COMP_REF1)
#define BIT_SHIFT_COMP_REF0 0
#define BIT_MASK_COMP_REF0 (u32)(0x0000001F << BIT_SHIFT_COMP_REF0)
/** @} */
/**************************************************************************//**
* @defgroup REG_COMP_INTR_CTRL
* @{
*****************************************************************************/
#define BIT_SHIFT_COMP_WK_SYS_CTRL(x) (17 + 3*x)
#define BIT_MASK_COMP_WK_SYS_CTRL(x) (u32)(0x00000003 << BIT_SHIFT_COMP_WK_SYS_CTRL(x))
#define BIT_SHIFT_COMP_WK_SYS_EN(x) (16 + 3*x)
#define BIT_COMP_WK_SYS_EN(x) (u32)(0x00000001 << BIT_SHIFT_COMP_WK_SYS_EN(x))
#define BIT_SHIFT_COMP_WK_ADC_CTRL(x) (1 + 3*x)
#define BIT_MASK_COMP_WK_ADC_CTRL(x) (u32)(0x00000003 << BIT_SHIFT_COMP_WK_ADC_CTRL(x))
#define BIT_SHIFT_COMP_WK_ADC_EN(x) (3*x)
#define BIT_COMP_WK_ADC_EN(x) (u32)(0x00000001 << BIT_SHIFT_COMP_WK_ADC_EN(x))
/** @} */
/**************************************************************************//**
* @defgroup REG_COMP_AUTOSW_EN
* @{
*****************************************************************************/
#define BIT_COMP_AUTOSW_EN BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup REG_COMP_EN_TRIG
* @{
*****************************************************************************/
#define BIT_COMP_DBG_EN BIT(2)
#define BIT_COMP_EN_TRIG BIT(1)
#define BIT_COMP_ENABLE BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup REG_COMP_CHSW_LIST
* @{
*****************************************************************************/
#define BIT_SHIFT_COMP_CHSW(x) (4*x)
#define BIT_COMP_CHSW(x) (u32)(0x0000000F << BIT_SHIFT_COMP_CHSW(x))
/** @} */
/**************************************************************************//**
* @defgroup REG_COMP_LAST_CH
* @{
*****************************************************************************/
#define BIT_COMP_LAST_CH (u32)(0x00000003)
/** @} */
/**************************************************************************//**
* @defgroup REG_COMP_BUSY_STS
* @{
*****************************************************************************/
#define BIT_COMP_BUSY_STS BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup REG_COMP_CH_STS
* @{
*****************************************************************************/
#define BIT_SHIFT_COMP_CH_STS(x) (2*x)
#define BIT_COMP_CH_STS(x) (u32)(0x3 << BIT_SHIFT_COMP_CH_STS(x))
/** @} */
/**************************************************************************//**
* @defgroup REG_COMP_RST_LIST
* @{
*****************************************************************************/
#define BIT_COMP_RST_LIST BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup REG_COMP_AUTO_SHUT
* @{
*****************************************************************************/
#define BIT_COMP_AUTO_SHUT BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup REG_COMP_EXT_TRIG_CTRL
* @{
*****************************************************************************/
#define BIT_COMP_EXT_WK_TIMER BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup REG_COMP_EXT_TRIG_TIMER_SEL
* @{
*****************************************************************************/
#define BIT_COMP_EXT_WK_TIMER_SEL (u32)(0x00000007)
/** @} */
/**************************************************************************//**
* @defgroup REG_COMP_EXT_WK_SHUT_CTRL
* @{
*****************************************************************************/
#define BIT_SHIFT_COMP_CHSW_CNT (8)
#define BIT_MASK_COMP_CHSW_CNT (u32)(0x000000FF << BIT_SHIFT_COMP_CHSW_CNT)
#define BIT_MASK_COMP_EXT_WK_SHUT_CNT (u32)(0x000000FF)
/** @} */
/**************************************************************************//**
* @defgroup REG_COMP_ANALOG
* @{
*****************************************************************************/
#define BIT_SD_POSEDGE BIT(1)
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
#endif /* _RTL8721D_COMPARE_H_ */
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_crc.h
* @author
* @version V1.0.0
* @date 2017-10-10
* @brief This file contains all the functions prototypes for the IPsec firmware
* library
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_CRC_H_
#define _RTL8721D_CRC_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup CRC
* @brief CRYPTO driver modules
* @{
*/
/** @addtogroup CRC
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* -CRC engine only used for IPsec secure mode
* -Register base address: 0x5007xxxx
* -CRC support mode: command mode and DMA mode
* -support programmable Polynomial coefficients, initial value, and XOR output value
*****************************************************************************************
* How to use crc
*****************************************************************************************
* -open CRC function & clock
*
* -call following API for set crc parameter:
* -CRC_Init(CRC_InitTypeDef* CRC_InitStruct)
*
* -call following API for crc calculation:
* -CRC_Calculate
*
*****************************************************************************************
* @endverbatim
*/
#define CRC_S_BASE 0x50022100
#define CRC_S_MODULE ((volatile CRC_TypeDef*)CRC_S_BASE)
/* Exported Types --------------------------------------------------------*/
/** @defgroup CRC_Exported_Types CRC Exported Types
* @{
*/
/**
* @brief CRC Init structure definition
*/
typedef struct {
u32 CRC_Type; /*!< Specifies CRC type
This parameter can be a value of @ref CRC_type */
u32 CRC_Polynom; /*!< Specifies CRC polynom
This parameter can be set by user according to CRC order */
u32 CRC_InitVal; /*!< Specifies CRC intial value
This parameter can be set by user according to CRC order */
u32 CRC_Xor; /*!< Specifies CRC xor output value
This parameter can be set by user according to CRC order */
u32 CRC_Iswap; /*!< Specifies CRC input swap
This parameter must be set to a value in the 0~7 range */
u32 CRC_Oswap; /*!< Specifies CRC output swap
This parameter must be set to a value 0(not swap) or 1(swap) */
u32 CRC_DmaMode; /*!< Specifies CRC mode
This parameter can be a value of @ref CRC_dma_mode */
} CRC_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_Exported_Constants CRC Exported Constants
* @{
*/
/** @defgroup CRC_type CRC Type
* @{
*/
#define CRC_TYPE_32 ((u32)0x00000000)
#define CRC_TYPE_24 ((u32)0x00000001)
#define CRC_TYPE_16 ((u32)0x00000002)
#define CRC_TYPE_12 ((u32)0x00000003)
#define CRC_TYPE_10 ((u32)0x00000004)
#define CRC_TYPE_8 ((u32)0x00000005)
#define CRC_TYPE_7 ((u32)0x00000006)
#define CRC_TYPE_5 ((u32)0x00000007)
#define IS_CRC_TYPE(TYPE) (((TYPE) == CRC_TYPE_32) || \
((TYPE) == CRC_TYPE_24) || \
((TYPE) == CRC_TYPE_16) || \
((TYPE) == CRC_TYPE_12) || \
((TYPE) == CRC_TYPE_10) || \
((TYPE) == CRC_TYPE_8) || \
((TYPE) == CRC_TYPE_7) || \
((TYPE) == CRC_TYPE_5))
/**
* @}
*/
/** @defgroup CRC_dma_mode CRC dma mode
* @{
*/
#define CRC_CMD_MODE ((u32)0x00000000)
#define CRC_DMA_MODE ((u32)0x00000001)
#define IS_CRC_MODE(MODE) (((MODE) == CRC_CMD_MODE) || \
((MODE) == CRC_DMA_MODE))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
_LONG_CALL_ void CRC_StructInit(CRC_InitTypeDef* CRC_InitStruct);
_LONG_CALL_ int CRC_Init(CRC_InitTypeDef* CRC_InitStruct);
_LONG_CALL_ int CRC_Calculate(CRC_InitTypeDef* CRC_InitStruct, IN const u8* message, IN const u32 msglen, OUT u32* pCrc);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup CRC_Register_Definitions CRC Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup CRC_RST
* @{
*****************************************************************************/
#define CRC_RESET ((u32)0x00000001) /*BIT[0], CRC reset*/
/** @} */
/**************************************************************************//**
* @defgroup CRC_OP
* @{
*****************************************************************************/
#define CRC_ISWAP ((u32)0x00000007) /* Bit[2:0], swap input data swap */
#define CRC_OSWAP ((u32)0x00000001<<3) /* Bit[3], swap output data swap */
#define CRC_SEL ((u32)0x00000007<<4) /* Bit[6:4], crc sel */
#define CRC_DMA ((u32)0x00000001<<7) /* Bit[7], DMA mode */
#define CRC_BE ((u32)0x00000003<<8) /* Bit[9:8], byte type */
#define CRC_LAST ((u32)0x00000001<<12) /* Bit[12], crc last */
#define CRC_LENGTH ((u32)0xFFFF0000) /* Bit[31:16], length */
/** @} */
/**************************************************************************//**
* @defgroup CRC_STAT
* @{
*****************************************************************************/
#define CRC_BUSY ((u32)0x00000001) /* Bit[0], still busy in previous execution */
#define CRC_OK ((u32)0x00000001<<1) /* Bit[1], finish execution */
#define CRC_INTR_MASK ((u32)0x00000001<<2) /* Bit[2], interrupt mask */
#define CRC_LITTLE_ENDIAN ((u32)0x00000001<<3) /* Bit[3], little endian */
#define CRC_STAT_MASK ((u32)0x0000000E) /* Bit[3:1], status mask */
/** @} */
/**************************************************************************//**
* @defgroup CRC_CNT
* @{
*****************************************************************************/
#define CRC_COUNT ((u32)0x0000FFFF) /*BIT[15:0], count number in bytes*/
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
#define CRC_TIMEOUT 10000
#endif
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_crypto.h
* @author
* @version V1.0.0
* @date 2017-09-15
* @brief This file contains all the functions prototypes for the IPsec firmware
* library
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_CRYPTO_H_
#define _RTL8721D_CRYPTO_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup CRYPTO
* @brief CRYPTO driver modules
* @{
*/
/** @addtogroup CRYPTO
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* -Authentication or Cipher use hardware to improve data process performance
* -Two mode: secure mode and non-secure mode
* -Register base address: Secure mode -0x5007xxxx, non-secure mode -0x4007xxxx
* -IPclk: 100MHz
*****************************************************************************************
* Authentication
*****************************************************************************************
* -MD5
* -SHA1
* -SHA2
* -HMAC-MD5
* -HMAC-SHA1
* -HMAC-SHA2
* -Poly1305
* -Sequential hash
*
*****************************************************************************************
* Cipher
*****************************************************************************************
* -AES-CBC
* -AES-ECB
* -AES-CFB
* -AES-OFB
* -AES-CTR
* -AES-GCM
* -3DES-CBC
* -3DES-ECB
* -3DES-CFB
* -3DES-OFB
* -3DES-CTR
* -DES-CBC
* -DES-ECB
* -DES-CFB
* -DES-OFB
* -DES-CTR
*
*****************************************************************************************
* How to use crypto
*****************************************************************************************
* Method 1 (use the lowest level API)
*****************************************************************************************
* -call CRYPTO_Init to open IPSEC function & clock
*
* -call following API for set key:
* -CRYPTO_SetSecurityModeAD
*
* -call following API for authentication/encrypt/decrypt:
* -CRYPTO_ProcessAD
*
*****************************************************************************************
* @endverbatim
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup CRYPTO_Exported_Types CRYPTO Exported Types
* @{
*/
/**
* @brief CRYPTO source descriptor structure definition
*/
typedef union {
struct {
u32 key_len:4; /*Offset 0, Bit[3:0], key length */
u32 iv_len:4; /*Offset 0, Bit[7:3], IV length */
u32 keypad_len:8; /*Offset 0, Bit[15:8], pad length */
u32 hash_iv_len:6; /*Offset 0, Bit[21:16], Hash initial value length */
u32 ap:2; /*Offset 0, Bit[23:22], auto-padding */
u32 cl:2; /*Offset 0, Bit[25:24], Command length */
u32 priv_key:1; /*Offset 0, Bit[26], Secure Key */
u32 otp_key:1; /*Offset 0, Bit[27], Secure Key */
u32 ls:1; /*Offset 0, Bit[28], Last segment descriptor */
u32 fs:1; /*Offset 0, Bit[29], First segment descriptor */
u32 rs:1; /*Offset 0, Bit[30], Read data source */
u32 rsvd:1; /*Offset 0, Bit[31], Reserved */
} b;
struct {
u32 apl:8; /*Offset 0, Bit[7:0], Auth padding length */
u32 a2eo:5; /*Offset 0, Bit[12:8], Auth to encryption offset */
u32 zero:1; /*Offset 0, Bit[13], 0/1 */
u32 enl:14; /*Offset 0, Bit[27:14], Encryption data length */
u32 ls:1; /*Offset 0, Bit[28], Last segment descriptor */
u32 fs:1; /*Offset 0, Bit[29], First segment descriptor */
u32 rs:1; /*Offset 0, Bit[30], Read data source */
u32 rsvd:1; /*Offset 0, Bit[31], Reserved */
} d;
u32 w;
} rtl_crypto_srcdesc_t;
/**
* @brief CRYPTO destination descriptor structure definition
*/
typedef union {
struct {
u32 adl:8; /*Offset 0, Bit[7:0], Auth data length */
u32 rsvd1:19; /*Offset 0, Bit[26:8], Reserved */
u32 enc:1; /*Offset 0, Bit[27], Cipher or auth */
u32 ls:1; /*Offset 0, Bit[28], Last segment descriptor */
u32 fs:1; /*Offset 0, Bit[29], First segment descriptor */
u32 ws:1; /*Offset 0, Bit[30], Write data source */
u32 rsvd2:1; /*Offset 0, Bit[31], Reserved */
} auth;
struct {
u32 enl:24; /*Offset 0, Bit[23:0], Auth padding length */
u32 rsvd1:3; /*Offset 0, Bit[26:24], Reserved */
u32 enc:1; /*Offset 0, Bit[27], Cipher or auth */
u32 ls:1; /*Offset 0, Bit[28], Last segment descriptor */
u32 fs:1; /*Offset 0, Bit[29], First segment descriptor */
u32 ws:1; /*Offset 0, Bit[30], Write data source */
u32 rsvd2:1; /*Offset 0, Bit[31], Reserved */
} cipher;
u32 w;
} rtl_crypto_dstdesc_t;
/**
* @brief CRYPTO command buffer structure definition
*/
typedef struct rtl_crypto_cl_struct_s {
// offset 0 :
u32 cipher_mode:4; /*Offset 0, Bit[3:0], Cipher mode */
u32 cipher_eng_sel:2; /*Offset 0, Bit[5:4], Cipher algorithm selected */
u32 rsvd1:1; /*Offset 0, Bit[6], Reserved */
u32 cipher_encrypt:1; /*Offset 0, Bit[7], Encryption or decryption */
u32 aes_key_sel:2; /*Offset 0, Bit[9:8], AES key length */
u32 des3_en:1; /*Offset 0, Bit[10], 3DES */
u32 des3_type:1; /*Offset 0, Bit[11], 3DES type */
u32 ckbs:1; /*Offset 0, Bit[12], Cipher key byte swap */
u32 hmac_en:1; /*Offset 0, Bit[13], HMAC */
u32 hmac_mode:3; /*Offset 0, Bit[16:14], Hash algorithm */
u32 hmac_seq_hash_last:1; /*Offset 0, Bit[17], the last payload(seq hash) */
u32 engine_mode:3; /*Offset 0, Bit[20:18], engine mode */
u32 hmac_seq_hash_first:1; /*Offset 0, Bit[21], the first payload(seq hash) */
u32 hmac_seq_hash:1; /*Offset 0, Bit[22], Seqential hash */
u32 hmac_seq_hash_no_wb:1; /*Offset 0, Bit[23], Result hash output */
u32 icv_total_length:8; /*Offset 0, Bit[31:24], icv length */
// offset 4
u32 aad_last_data_size:4; /*Offset 4, Bit[3:0], AAD last block data size */
u32 enc_last_data_size:4; /*Offset 4, Bit[7:4], Message last block data size */
u32 pad_last_data_size:3; /*Offset 4, Bit[10:8], Hash padding last block data size */
u32 ckws:1; /*Offset 4, Bit[11], Cipher key word swap */
u32 enc_pad_last_data_size:3; /*Offset 4, Bit[14:12], Encryption padding last block data size */
u32 hsibs:1; /*Offset 4, Bit[15], Hash sequential initial value byte swap */
u32 caws:1; /*Offset 4, Bit[16], Cipher align word swap */
u32 cabs:1; /*Offset 4, Bit[17], Cipher align byte swap */
u32 ciws:1; /*Offset 4, Bit[18], Cipher input word swap */
u32 cibs:1; /*Offset 4, Bit[19], Cipher input byte swap */
u32 cows:1; /*Offset 4, Bit[20], Cipher output word swap */
u32 cobs:1; /*Offset 4, Bit[21], Cipher output byte swap */
u32 codws:1; /*Offset 4, Bit[22], Cipher output double word swap */
u32 cidws:1; /*Offset 4, Bit[23], Cipher input double word swap */
u32 haws:1; /*Offset 4, Bit[24], Hash align word swap */
u32 habs:1; /*Offset 4, Bit[25], Hash align byte swap */
u32 hiws:1; /*Offset 4, Bit[26], Hash input word swap */
u32 hibs:1; /*Offset 4, Bit[27], Hash input byte swap */
u32 hows:1; /*Offset 4, Bit[28], Hash output word swap */
u32 hobs:1; /*Offset 4, Bit[29], Hash output byte swap */
u32 hkws:1; /*Offset 4, Bit[30], Hash key word swap */
u32 hkbs:1; /*Offset 4, Bit[31], Hash key byte swap */
// offset 8
u32 hash_pad_len:8; /*Offset 8, Bit[7:0], Hash padding total length */
u32 header_total_len:6; /*Offset 8, Bit[13:8], A2EO total length */
u32 apl:2; /*Offset 8, Bit[15:14], Encryption padding total length*/
u32 enl:16; /*Offset 8, Bit[15:14], Message total length */
// offset
u32 ap0; /*Offset 12, Bit[31:0], Message length[31:0] */
u32 ap1; /*Offset 16, Bit[31:0], Message length[63:32] */
u32 ap2; /*Offset 20, Bit[31:0], Message length[95:64] */
u32 ap3; /*Offset 24, Bit[31:0], Message length[127:96] */
} rtl_crypto_cl_t;
/**
* @brief CRYPTO adapter definition
*/
typedef struct _HAL_CRYPTO_ADAPTER_ {
u8 isInit; /*0: not init, 1: init */
u8 isIntMode; /*0: disable interrupt mode, 1: enable interrupt mode*/
u32 cipher_type; /*cipher type */
u8 des; /*DES */
u8 trides; /*3DES */
u8 aes; /*AES */
u8 chacha; /*ChaCha */
u8 isDecrypt; /*0: encryption, 1: decryption */
u32 auth_type; /*auth type */
u8 isHMAC; /*0: not HMAC, 1: HMAC */
u8 isMD5; /*MD5 */
u8 isSHA1; /*SHA1 */
u8 isSHA2; /*SHA2 */
u8 sha2type; /*SHA2 type: SHA2_224/SHA2_256 */
u32 enc_last_data_size; /*message last data size */
u32 aad_last_data_size; /*AAD last data size */
u32 lenAuthKey; /*Auth key length */
const u8* pAuthKey; /*Auth key */
u32 digestlen; /*digest */
// sequential hash
u8 hmac_seq_hash_first; /* seq hash the first message payload block */
u8 hmac_seq_hash_last; /* seq hash the last message payload block */
u32 hmac_seq_hash_total_len; /* seq hash message total length */
u8 hmac_seq_is_recorded; /* enter seq hash or not */
u8 *hmac_seq_last_message; /* previous message payload */
u32 hmac_seq_last_msglen; /* previous message payload length */
u8 hmac_seq_buf_is_used_bytes;/* seq buf used bytes(total 64-bytes) */
u32 lenCipherKey; /*Cipher key length */
const u8* pCipherKey; /*Cipher key */
u32 a2eo, apl_aad, enl, apl; /*length */
u8 *ipad; /*HMAC ipad */
u8 *opad; /*HMAC opad */
// crc
//int crc_order; /*CRC order */
volatile u8 g_IOPAD[64*2+4] __attribute__((aligned(4)));
volatile u8 gcm_iv[32] __attribute__((aligned(4)));
volatile u8 cl_buffer[32] __attribute__((aligned(4)));
volatile u8 hmac_seq_buf[64] __attribute__((aligned(4)));
} HAL_CRYPTO_ADAPTER, *PHAL_CRYPTO_ADAPTER ;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRYPTO_Exported_Constants CRYPTO Exported Constants
* @{
*/
/** @defgroup CRYPTO_LENGTH_definitions
* @{
*/
#define CRYPTO_MAX_DIGEST_LENGTH 32 /* SHA256 Digest length : 32 */
#define CRYPTO_MAX_KEY_LENGTH 32 /* MAX is AES-256 : 32 byte, 3DES : 24 byte */
#define CRYPTO_PADSIZE 64
#define CRYPTO_AUTH_PADDING 64
#define CRYPTO_MD5_DIGEST_LENGTH 16
#define CRYPTO_SHA1_DIGEST_LENGTH 20
#define CRYPTO_SHA2_DIGEST_LENGTH 32
/**
* @}
*/
/** @defgroup CRYPTO_ATHENTICATION_TYPE_definitions
* @{
*/
#define AUTH_TYPE_NO_AUTH ((u32)-1)
#define AUTH_TYPE_MASK_FUNC 0x3 /* bit 0, bit 1*/
#define AUTH_TYPE_MD5 0x2
#define AUTH_TYPE_SHA1 0x0
#define AUTH_TYPE_SHA2 0x1
#define AUTH_TYPE_MASK_HMAC 0x4 /* bit 2 */
#define AUTH_TYPE_HMAC_MD5 (AUTH_TYPE_MD5 | AUTH_TYPE_MASK_HMAC)
#define AUTH_TYPE_HMAC_SHA1 (AUTH_TYPE_SHA1 | AUTH_TYPE_MASK_HMAC)
#define AUTH_TYPE_HMAC_SHA2 (AUTH_TYPE_SHA2 | AUTH_TYPE_MASK_HMAC)
#define AUTH_TYPE_MASK_FUNC_ALL (AUTH_TYPE_MASK_FUNC| AUTH_TYPE_MASK_HMAC)
// SHA2
#define AUTH_TYPE_MASK_SHA2 0x30 /* bit 3,4 */
#define AUTH_TYPE_SHA2_224 0x10
#define AUTH_TYPE_SHA2_256 0x20
#define AUTH_TYPE_SHA2_224_ALL (AUTH_TYPE_SHA2_224|AUTH_TYPE_SHA2)
#define AUTH_TYPE_SHA2_256_ALL (AUTH_TYPE_SHA2_256|AUTH_TYPE_SHA2)
#define AUTH_TYPE_HMAC_SHA2_224_ALL (AUTH_TYPE_SHA2_224|AUTH_TYPE_HMAC_SHA2)
#define AUTH_TYPE_HMAC_SHA2_256_ALL (AUTH_TYPE_SHA2_256|AUTH_TYPE_HMAC_SHA2)
typedef enum _SHA2_TYPE_ {
SHA2_NONE = 0,
SHA2_224 = 224/8,
SHA2_256 = 256/8,
SHA2_384 = 384/8,
SHA2_512 = 512/8
} SHA2_TYPE;
/**
* @}
*/
/** @defgroup CRYPTO_CIPHER_TYPE_definitions
* @{
*/
#define CIPHER_TYPE_NO_CIPHER ((u32)-1)
#define CIPHER_TYPE_MODE_ENCRYPT 0x80
#define CIPHER_TYPE_MASK_FUNC 0x30 /* 0x00 : DES, 0x10: 3DES, 0x20: AES */
#define CIPHER_TYPE_FUNC_DES 0x00
#define CIPHER_TYPE_FUNC_3DES 0x10
#define CIPHER_TYPE_FUNC_AES 0x20
#define CIPHER_TYPE_FUNC_CHACHA 0x30
#define CIPHER_TYPE_MASK_BLOCK 0xF /*0x0 : ECB, 0x1: CBC, 0x2: CFB , 0x3 : OFB , 0x4 : CTR, 0x5 : GCTR, 0x6: GMAC, 0x7: GHASH, 0x8: GCM*/
#define CIPHER_TYPE_BLOCK_ECB 0x0
#define CIPHER_TYPE_BLOCK_CBC 0x1
#define CIPHER_TYPE_BLOCK_CFB 0x2
#define CIPHER_TYPE_BLOCK_OFB 0x3
#define CIPHER_TYPE_BLOCK_CTR 0x4
#define CIPHER_TYPE_BLOCK_GCTR 0x5
#define CIPHER_TYPE_BLOCK_GMAC 0x6
#define CIPHER_TYPE_BLOCK_GHASH 0x7
#define CIPHER_TYPE_BLOCK_GCM 0x8
#define CIPHER_TYPE_BLOCK_CHACHA 0x1
//
#define CIPHER_TYPE_DES_ECB 0x0
#define CIPHER_TYPE_DES_CBC 0x1
#define CIPHER_TYPE_DES_CFB 0x2
#define CIPHER_TYPE_DES_OFB 0x3
#define CIPHER_TYPE_DES_CTR 0x4
#define CIPHER_TYPE_3DES_ECB 0x10
#define CIPHER_TYPE_3DES_CBC 0x11
#define CIPHER_TYPE_3DES_CFB 0x12
#define CIPHER_TYPE_3DES_OFB 0x13
#define CIPHER_TYPE_3DES_CTR 0x14
#define CIPHER_TYPE_AES_ECB 0x20
#define CIPHER_TYPE_AES_CBC 0x21
#define CIPHER_TYPE_AES_CFB 0x22
#define CIPHER_TYPE_AES_OFB 0x23
#define CIPHER_TYPE_AES_CTR 0x24 // 0x29
#define CIPHER_TYPE_AES_GCTR 0x25
#define CIPHER_TYPE_AES_GMAC 0x26
#define CIPHER_TYPE_AES_GHASH 0x27
#define CIPHER_TYPE_AES_GCM 0x28
#define CIPHER_TYPE_CHACHA_POLY1305 0x30 // chacha+poly1305
#define CIPHER_TYPE_CHACHA 0x31
#define CIPHER_TYPE_POLY1305 0x33 // poly1305 - mode 2
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup CRYPTO_Exported_Functions CRYPTO Exported Functions
* @{
*****************************************************************************/
/** @defgroup Crypto_Normal_Functions
* @{
*/
_LONG_CALL_ void CRYPTO_MemDump(const u8 *start, u32 size, char * strHeader);
_LONG_CALL_ void CRYPTO_RegDump(void);
_LONG_CALL_ void CRYPTO_CleanCmdOk(void);
_LONG_CALL_ void CRYPTO_ClearAllINT(void);
_LONG_CALL_ void CRYPTO_Reset(HAL_CRYPTO_ADAPTER *pIE);
_LONG_CALL_ int CRYPTO_SetSecurityModeAD(HAL_CRYPTO_ADAPTER *pIE, IN const u32 cipher_type, IN const u32 auth_type,IN const void* pCipherKey, IN const u32 lenCipherKey, IN const void* pAuthKey, IN const u32 lenAuthKey);
_LONG_CALL_ int CRYPTO_Init(HAL_CRYPTO_ADAPTER *pIE);
_LONG_CALL_ int CRYPTO_ProcessAD(HAL_CRYPTO_ADAPTER *pIE, IN const u8 *message, IN const u32 msglen, IN const u8 *pIv, IN const u32 ivlen, IN const u8 *paad, IN const u32 aadlen, OUT u8 *pResult, OUT u8 *pTag);
_LONG_CALL_ int CRYPTO_CipherInit(HAL_CRYPTO_ADAPTER *pIE, IN const u32 cipher_type, IN const u8 *key, IN const u32 keylen);
_LONG_CALL_ int CRYPTO_CipherEncryptAD(HAL_CRYPTO_ADAPTER *pIE, IN const u8* message, IN const u32 msglen, IN const u8* piv, IN const u32 ivlen, IN const u8* paad, IN const u32 aadlen, OUT u8* pResult, OUT u8* pTag);
_LONG_CALL_ int CRYPTO_CipherDecryptAD(HAL_CRYPTO_ADAPTER *pIE, IN const u8* message, IN const u32 msglen, IN const u8* piv, IN const u32 ivlen, IN const u8* paad, IN const u32 aadlen, OUT u8* pResult, OUT u8* pTag);
_LONG_CALL_ int CRYPTO_SendSeqBuf(u8 *pDigest);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup CRYPTO_Register_Definitions CRYPTO Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup CRYPTO_SDSR
* @{
*****************************************************************************/
#define SFIFO_EMPTY_CNT ((u32)0x000000FF) /* Bit[7:0], Source Descriptor FIFO empty counter */
#define SWPTR ((u32)0x0000FF00) /* Bit[15:8], Source Descriptor FIFO write pointer */
#define SRPTR ((u32)0x00FF0000) /* Bit[23:16], Source Descriptor FIFO read pointer */
#define SRC_FAIL ((u32)0x00000001<<24) /* Bit[24], Source Descriptor fail interrupt */
#define SRC_FAIL_STATUS ((u32)0x00000003<<25) /* Bit[26:25], Source Descriptor fail status */
#define SRC_FAIL_M ((u32)0x00000001<<27) /* Bit[27], Source Descriptor fail interrupt mask */
#define PK_UP ((u32)0x00000001<<30) /* Bit[30], packet base update wptr to engine */
#define SRC_RST ((u32)0x00000001<<31) /* Bit[31], Source Descriptor reset(only for pk_up=1'b1) */
/** @} */
/**************************************************************************//**
* @defgroup CRYPTO_RST_ISR_CON
* @{
*****************************************************************************/
#define SOFT_RST ((u32)0x00000001) /* Bit[0], Software Reset write 1 to reset */
#define DMA_BUSY ((u32)0x00000001<<3) /* Bit[3], Ipsec dma busy */
#define CMD_OK ((u32)0x00000001<<4) /* Bit[4], Command OK interrupt */
#define INTR_MODE ((u32)0x00000001<<7) /* Bit[7], Select ok interrupt mode */
#define INTR_NORMAL_MODE ((u32)0x00000000<<7) /* Bit[7], interrupt normal mode */
#define INTR_COUNT_MODE ((u32)0x00000001<<7) /* Bit[7], interrupt counter mode */
#define OK_INTR_CNT ((u32)0x000000FF<<8) /* Bit[15:8], OK interrupt counter */
#define CLEAR_OK_INTR_NUM ((u32)0x000000FF<<16) /* Bit[23:16], Clear OK interrupt number */
#define IPSEC_RST ((u32)0x00000001<<31) /* Bit[31], Ipsec engine Reset Write 1 to reset the crypto engine and DMA engine */
/** @} */
/**************************************************************************//**
* @defgroup CRYPTO_IMR
* @{
*****************************************************************************/
#define CMD_OK_M ((u32)0x00000001) /* Bit[0], Command OK interrupt Mask */
#define SRC_ERR0_M ((u32)0x00000001<<3) /* Bit[3], Source Descriptor Error 0 Interrupt Mask */
#define SRC_ERR1_M ((u32)0x00000001<<4) /* Bit[4], Source Descriptor Error 1 Interrupt Mask */
#define SRC_ERR2_M ((u32)0x00000001<<5) /* Bit[5], Source Descriptor Error 2 Interrupt Mask */
#define SRC_ERR3_M ((u32)0x00000001<<6) /* Bit[6], Source Descriptor Error 3 Interrupt Mask */
#define SRC_ERR4_M ((u32)0x00000001<<7) /* Bit[7], Source Descriptor Error 4 Interrupt Mask */
#define SRC_ERR5_M ((u32)0x00000001<<8) /* Bit[8], Source Descriptor Error 5 Interrupt Mask */
#define SRC_ERR6_M ((u32)0x00000001<<9) /* Bit[9], Source Descriptor Error 6 Interrupt Mask */
#define SRC_ERR7_M ((u32)0x00000001<<10) /* Bit[10], Source Descriptor Error 7 Interrupt Mask */
#define SRC_ERR8_M ((u32)0x00000001<<11) /* Bit[11], Source Descriptor Error 8 Interrupt Mask */
#define SRC_ERR9_M ((u32)0x00000001<<12) /* Bit[12], Source Descriptor Error 9 Interrupt Mask */
#define DST_ERR1_M ((u32)0x00000001<<13) /* Bit[13], Destination Descriptor Error 1 Interrupt Mask */
#define DST_ERR2_M ((u32)0x00000001<<14) /* Bit[14], Destination Descriptor Error 2 Interrupt Mask */
#define DST_ERR3_M ((u32)0x00000001<<15) /* Bit[15], Destination Descriptor Error 3 Interrupt Mask */
#define DST_ERR4_M ((u32)0x00000001<<16) /* Bit[16], Destination Descriptor Error 4 Interrupt Mask */
#define DST_ERR5_M ((u32)0x00000001<<17) /* Bit[17], Destination Descriptor Error 5 Interrupt Mask */
#define DST_ERR6_M ((u32)0x00000001<<18) /* Bit[18], Destination Descriptor Error 6 Interrupt Mask */
/** @} */
/**************************************************************************//**
* @defgroup CRYPTO_DEBUG
* @{
*****************************************************************************/
#define DMA_WAIT_CYCLE ((u32)0x0000FFFF) /* Bit[15:0], Wait dma_wait_cycle to assert next dma request */
#define ARBITER_MODE ((u32)0x00000001<<16) /* Bit[16], dma arbiter mode */
#define DEBUG_PORT_SEL ((u32)0x0000000F<<20) /* Bit[23:20], dma arbiter mode */
#define ENGINE_CLK_EN ((u32)0x00000001<<24) /* Bit[24], Ipsec Engine clock enable */
#define DEBUG_WB ((u32)0x00000001<<31) /* Bit[31], Debug : write back mode */
/** @} */
/**************************************************************************//**
* @defgroup CRYPTO_ERR_STAT
* @{
*****************************************************************************/
#define SRC_ERR0 ((u32)0x00000001) /* Bit[0], Source Descriptor Error 0 interrupt */
#define SRC_ERR1 ((u32)0x00000001<<1) /* Bit[1], Source Descriptor Error 1 interrupt */
#define SRC_ERR2 ((u32)0x00000001<<2) /* Bit[2], Source Descriptor Error 2 interrupt */
#define SRC_ERR3 ((u32)0x00000001<<3) /* Bit[3], Source Descriptor Error 3 interrupt */
#define SRC_ERR4 ((u32)0x00000001<<4) /* Bit[4], Source Descriptor Error 4 interrupt */
#define SRC_ERR5 ((u32)0x00000001<<5) /* Bit[5], Source Descriptor Error 5 interrupt */
#define SRC_ERR6 ((u32)0x00000001<<6) /* Bit[6], Source Descriptor Error 6 interrupt */
#define SRC_ERR7 ((u32)0x00000001<<7) /* Bit[7], Source Descriptor Error 7 interrupt */
#define SRC_ERR8 ((u32)0x00000001<<8) /* Bit[8], Source Descriptor Error 8 interrupt */
#define SRC_ERR9 ((u32)0x00000001<<9) /* Bit[9], Source Descriptor Error 9 interrupt */
#define DST_ERR1 ((u32)0x00000001<<10) /* Bit[10], Destination Descriptor Error 1 interrupt */
#define DST_ERR2 ((u32)0x00000001<<11) /* Bit[11], Destination Descriptor Error 2 interrupt */
#define DST_ERR3 ((u32)0x00000001<<12) /* Bit[12], Destination Descriptor Error 2 interrupt */
#define DST_ERR4 ((u32)0x00000001<<13) /* Bit[13], Destination Descriptor Error 4 interrupt */
#define DST_ERR5 ((u32)0x00000001<<14) /* Bit[14], Destination Descriptor Error 5 interrupt */
#define DST_ERR6 ((u32)0x00000001<<15) /* Bit[15], Destination Descriptor Error 6 interrupt */
/** @} */
/**************************************************************************//**
* @defgroup CRYPTO_SWAP_BURST
* @{
*****************************************************************************/
#define SET_SWAP ((u32)0x00000001) /* Bit[0], Byte swap for command setting data */
#define KEY_IV_SWAP ((u32)0x00000001<<1) /* Bit[1], Byte swap for key and iv */
#define KEY_PAD_SWAP ((u32)0x00000001<<2) /* Bit[2], Byte swap for hmac key */
#define HASH_INITIAL_VALUE_SWAP ((u32)0x00000001<<3) /* Bit[3], Byte swap for sequential hash initial value */
#define DMA_IN_LITTLE_ENDIAN ((u32)0x00000001<<4) /* Bit[4], Input data is little endian */
#define TX_BYTE_SWAP ((u32)0x00000001<<8) /* Bit[8], Byte swap for dma_tx engine input data */
#define DATA_OUT_LITTLE_ENDIAN ((u32)0x00000001<<9) /* Bit[9], Output data is little endian */
#define MAC_OUT_LITTLE_ENDIAN ((u32)0x00000001<<10) /* Bit[10], Output mac is little endian */
#define RX_WD_SWAP ((u32)0x00000001<<11) /* Bit[11], Word swap for dma_rx engine input data */
#define TX_WD_SWAP ((u32)0x00000001<<12) /* Bit[12], Word swap for dma_tx engine input data */
#define DMA_BURST_LENGTH ((u32)0x0000003F<<16) /* Bit[21:16], dma burst length */
/** @} */
/**************************************************************************//**
* @defgroup CRYPTO_DDSR
* @{
*****************************************************************************/
#define DFIFO_EMPTY_CNT ((u32)0x000000FF) /* Bit[7:0], Destination Descriptor FIFO empty counter */
#define DWPTR ((u32)0x0000FF00) /* Bit[15:8], Destination Descriptor FIFO write pointer */
#define DRPTR ((u32)0x00FF0000) /* Bit[23:16], Destination Descriptor FIFO read pointer */
#define DST_FAIL ((u32)0x00000001<<24) /* Bit[24], Destination Descriptor fail interrupt */
#define DST_FAIL_STATUS ((u32)0x00000003<<25) /* Bit[26:25], Destination Descriptor fail status */
#define DST_FAIL_M ((u32)0x00000001<<27) /* Bit[27], Destination Descriptor fail interrupt mask */
#define DST_RST ((u32)0x00000001<<31) /* Bit[31], Destination Descriptor reset(only for pk_up=1'b1) */
/** @} */
/**************************************************************************//**
* @defgroup CRYPTO_DESC_PKT_CONF
* @{
*****************************************************************************/
/******************** Bits definition for register *******************/
#define DBG_SPTR (u32)0x000000FF) /* Bit[7:0], Source Descriptor FIFO empty counter */
#define DBG_DPTR (u32)0x0000FF00) /* Bit[15:8], Destination Descriptor FIFO write pointer */
#define PK_ARBITER ((u32)0x00000003<<16) /* Bit[17:16], Packet arbiter */
#define BUS1_PRIORITY_TH ((u32)0x00000003<<24) /* Bit[25:24], Bus1 priority threshold */
#define BUS2_PRIORITY_TH ((u32)0x00000003<<26) /* Bit[27:26], Bus2 priority threshold */
#define PK_ARBITER_MODE ((u32)0x00000003<<30) /* Bit[31:30], Packet arbiter mode */
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
#define FIFOCNT_TIMEOUT 0x100000
extern HAL_CRYPTO_ADAPTER crypto_engine;
extern struct _driver_call_os_func_map driver_call_os_func_map;
__STATIC_INLINE
int rtl_cryptoEngine_init(void)
{
return CRYPTO_Init(NULL);
}
/* *** dump macro definition *** */
#undef crypto_dbg_mem_dump
#define crypto_dbg_mem_dump(start, size, str_header) \
if (ConfigDebug[LEVEL_INFO] & BIT(MODULE_IPSEC)) { \
DiagPrintf("%s(): memdump : address: %08x, size: %d\n", "rtl_cryptoEngine_dbg", start, size); \
CRYPTO_MemDump((const u8*)(start), size, (char*)(str_header)); \
}
#endif
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/

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@ -0,0 +1,239 @@
/**
******************************************************************************
* @file rtl_8721d_crypto_api.h
* @author
* @version V1.0.0
* @date 2017-10-26
* @brief This file provides firmware functions to manage the following
* functionalities of the HW crypto:
* - Initialization
* - MD5
* - SHA1/SHA2
* - HMAC
* - AES CBC/ECB/CFB/OFB/CTR/GCM
* - 3DES CBC/ECB/CFB/OFB/CTR
* - DES CBC/ECB/CFB/OFB/CTR
* - Chacha20-poly1305
* - Sequential hash
* - CRC
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef __RTL8721D_CRYPTO_API_H__
#define __RTL8721D_CRYPTO_API_H__
#include "rtl8721d_crypto.h"
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup CRYPTO
* @brief CRYPTO driver modules
* @{
*/
/** @addtogroup CRYPTO
* @verbatim
*****************************************************************************************
* Method 2 (use upper level API, for user use)
*****************************************************************************************
* -call rtl_cryptoEngine_init to open IPSEC function & clock
*
* -call following API for set key:
* -rtl_crypto_xxx_init
*
* -call following API for authentication/encrypt/decrypt:
* authentication -rtl_crypto_xxx_process or
* sequential hash -rtl_crypto_xxx_update and
* -rtl_crypto_xxx_final
*
* encrypt -rtl_crypto_xxx_encrypt
* decrypt -rtl_crypto_xxx_decrypt
*
*****************************************************************************************
* @endverbatim
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRYPTO_Exported_Constants CRYPTO Exported Constants
* @{
*/
/** @defgroup CRYPTO_Process_Status_definitions
* @{
*/
#define _ERRNO_CRYPTO_DESC_NUM_SET_OutRange -2
#define _ERRNO_CRYPTO_BURST_NUM_SET_OutRange -3
#define _ERRNO_CRYPTO_NULL_POINTER -4
#define _ERRNO_CRYPTO_ENGINE_NOT_INIT -5
#define _ERRNO_CRYPTO_ADDR_NOT_4Byte_Aligned -6
#define _ERRNO_CRYPTO_KEY_OutRange -7
#define _ERRNO_CRYPTO_MSG_OutRange -8
#define _ERRNO_CRYPTO_IV_OutRange -9
#define _ERRNO_CRYPTO_AUTH_TYPE_NOT_MATCH -10
#define _ERRNO_CRYPTO_CIPHER_TYPE_NOT_MATCH -11
#define _ERRNO_CRYPTO_KEY_IV_LEN_DIFF -12
#define _ERRNO_CRYPTO_HASH_FINAL_NO_UPDATE -13
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup CRYPTO_Exported_Functions CRYPTO Exported Functions
* @{
*****************************************************************************/
/** @defgroup Authentication_Functions
* @{
*/
_LONG_CALL_ int rtl_crypto_md5(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_md5_init(void);
_LONG_CALL_ int rtl_crypto_md5_process(IN const u8* message, const IN u32 msglen, OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_md5_update(IN const u8* message, IN const u32 msglen);
_LONG_CALL_ int rtl_crypto_md5_final(OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_sha1(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_sha1_init(void);
_LONG_CALL_ int rtl_crypto_sha1_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_sha1_update(IN const u8* message, IN const u32 msglen);
_LONG_CALL_ int rtl_crypto_sha1_final(OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_sha2(IN const SHA2_TYPE sha2type, IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_sha2_init(IN const SHA2_TYPE sha2type);
_LONG_CALL_ int rtl_crypto_sha2_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_sha2_update(IN const u8* message, IN const u32 msglen);
_LONG_CALL_ int rtl_crypto_sha2_final(OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_hmac_md5(IN const u8* message, IN const u32 msglen, IN const u8* key, IN const u32 keylen, OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_hmac_md5_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_hmac_md5_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_hmac_md5_update(IN const u8* message, IN const u32 msglen);
_LONG_CALL_ int rtl_crypto_hmac_md5_final(OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_hmac_sha1(IN const u8* message, IN const u32 msglen, IN const u8* key, IN const u32 keylen, OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_hmac_sha1_start(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_hmac_sha1_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_hmac_sha1_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_hmac_sha1_update(IN const u8* message, IN const u32 msglen);
_LONG_CALL_ int rtl_crypto_hmac_sha1_final(OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_hmac_sha2(IN const SHA2_TYPE sha2type, IN const u8* message, IN const u32 msglen, IN const u8* key, IN const u32 keylen, OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_hmac_sha2_start(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_hmac_sha2_init(IN const SHA2_TYPE sha2type, IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_hmac_sha2_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_hmac_sha2_update(IN const u8* message, IN const u32 msglen);
_LONG_CALL_ int rtl_crypto_hmac_sha2_final(OUT u8* pDigest);
/**
* @}
*/
/** @defgroup Cipher_Functions
* @{
*/
_LONG_CALL_ int rtl_crypto_aes_cbc_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_aes_cbc_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_aes_cbc_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_aes_ecb_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_aes_ecb_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_aes_ecb_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_aes_ctr_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_aes_ctr_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_aes_ctr_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_aes_cfb_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_aes_cfb_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_aes_cfb_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_aes_ofb_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_aes_ofb_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_aes_ofb_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_aes_gcm_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_aes_gcm_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u8* aad, IN const u32 aadlen, OUT u8* pResult, OUT u8* pTag);
_LONG_CALL_ int rtl_crypto_aes_gcm_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u8* aad, IN const u32 aadlen, OUT u8* pResult, OUT u8* pTag);
_LONG_CALL_ int rtl_crypto_3des_cbc_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_3des_cbc_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_3des_cbc_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_3des_ecb_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_3des_ecb_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_3des_ecb_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_3des_ctr_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_3des_ctr_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_3des_ctr_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_3des_cfb_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_3des_cfb_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_3des_cfb_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_3des_ofb_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_3des_ofb_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_3des_ofb_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_des_cbc_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_des_cbc_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_des_cbc_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_des_ecb_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_des_ecb_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_des_ecb_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_des_ctr_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_des_ctr_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_des_ctr_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_des_cfb_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_des_cfb_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_des_cfb_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_des_ofb_init(IN const u8* key, IN const u32 keylen);
_LONG_CALL_ int rtl_crypto_des_ofb_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_des_ofb_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_poly1305_init(IN const u8 *key);
_LONG_CALL_ int rtl_crypto_poly1305_process(IN const u8 *message, IN const u32 msglen, OUT u8 *pDigest);
_LONG_CALL_ int rtl_crypto_poly1305(IN const u8* message, IN const u32 msglen, IN const u8* key, OUT u8* pDigest);
_LONG_CALL_ int rtl_crypto_chacha_init(IN const u8* key);
_LONG_CALL_ int rtl_crypto_chacha_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 count, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_chacha_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* iv, IN const u32 count, OUT u8* pResult);
_LONG_CALL_ int rtl_crypto_chacha_poly1305_init(IN const u8* key);
_LONG_CALL_ int rtl_crypto_chacha_poly1305_encrypt(IN const u8* message, IN const u32 msglen, IN const u8* nonce, IN const u8* aad, IN const u32 aadlen, OUT u8* pResult, OUT u8 *pTag);
_LONG_CALL_ int rtl_crypto_chacha_poly1305_decrypt(IN const u8* message, IN const u32 msglen, IN const u8* nonce, IN const u8* aad, IN const u32 aadlen, OUT u8* pResult, OUT u8 *pTag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* __RTL8721D_CRYPTO_API_H__ */
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_deepsleep.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the following
* functionalities of the soc power management circut:
* - wakeup timer
* - wakeup pin
* - sleep option
* - sleep mode
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_DSLP_H_
#define _RTL8721D_DSLP_H_
void app_dslp_peripheral_init(void);
#endif //_RTL8721D_DSLP_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_delay.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the following
* functionalities of the systimer & delay:
* - SYSTIMER_GetPassTime
* - SYSTIMER_TickGet
* - DelayUs
* - DelayMs
* - DelayNop
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _8721D_DELAY_H_
#define _8721D_DELAY_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup DELAY
* @brief DELAY driver modules
* @{
*/
/** @addtogroup DELAY
* @verbatim
*****************************************************************************************
* Delay
*****************************************************************************************
* - DelayUs
* - DelayMs
* - DelayNop
*
*****************************************************************************************
* Sys Timer
*****************************************************************************************
* - TIMM00 is used as systimer, so TIMM00 can not be used for other purpose
* - init when boot in rom code
* - resolution is 31us
* - you can get timer tick use SYSTIMER_TickGet, every tick is 31us
* - you can get passing time use SYSTIMER_GetPassTime in ms
*
*****************************************************************************************
* @endverbatim
*/
/** @defgroup DELAY_Exported_Functions DELAY Exported Functions
* @{
*/
_LONG_CALL_ void SYSTIMER_Init(void);
_LONG_CALL_ u32 SYSTIMER_TickGet(void);
_LONG_CALL_ u32 SYSTIMER_GetPassTime(u32 start);
_LONG_CALL_ void DelayUs(u32 us);
_LONG_CALL_ void DelayMs(u32 ms);
_LONG_CALL_ void DelayNop(u32 count);
#define HalDelayUs DelayUs
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
extern u32 RBSS_UDELAY_DIV;
static inline u32 RTIM_TestTimer_GetCount(void)
{
return RTIM_GetCount(TIMM05);
}
#endif//_8721D_DELAY_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_efuse.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the EFUSE firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _8710B_EFUSE_H_
#define _8710B_EFUSE_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup EFUSE
* @brief EFUSE driver modules
* @{
*/
/** @addtogroup EFUSE
* @verbatim
*****************************************************************************************
* logical map (512B)
*****************************************************************************************
*
* 0x00~0x1F 32bytes system autoload
* 0x20~0xCF WIFI calibration data
* 0xD0~0x11F HCI CIS
* 0x130~0x13F SW/RF Reserved
* 0x160~0x17F 32bytes USER1
* 0x180~0x19F 32bytes USER2
* 0x1A0~0x1Bf 32bytes USER3
* 0x1C0~0x1Df USB HCI
*
*****************************************************************************************
* physical map (256B)
*****************************************************************************************
*
* 0x00~0x7E 127bytes for logical efuse, user can read
* 0x80~0x9F 32bytes for user OTP, user can read
* 0xA0~0xAF 16bytes OTF KEY, can not read by user
* 0xB0~0xBF 16bytes RDP KEY, can not read by user
* 0xC0 1byte RDP EN, can not read by user
* 0xC1~0xD2 18bytes for Security section
* 0xD3 1byte JTAG ON/OFF
* 0xD4~0xEF 29bytes RF rsvd, user can read
* 0xF0~0xFF 16bytes RTK rsvd, user can read
*
*****************************************************************************************
* USER Section (3 * 32B)
*****************************************************************************************
* can be changed after write
*
* USER1 32B = 4 sections * 8B
* USER2 32B = 4 sections * 8B
* USER3 32B = 4 sections * 8B
*
*****************************************************************************************
* OTP Section (32B)
*****************************************************************************************
*
* can not be changed after write
*
* OTP 32B
*
*****************************************************************************************
* FW protection
*****************************************************************************************
*
* can not be changed after write
*
* OTF KEY: 16B, can not read
* RDP KEY: 16B, can not read
* RDP EN: 1B, can not read
* JTAG OFF: 1B
*
*****************************************************************************************
* @endverbatim
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EFUSE_Exported_Constants EFUSE Exported Constants
* @{
*/
/** @defgroup EFUSE_LOGICAL_definitions
* @{
*/
#define EFUSE_MAP_LEN_8711B 1024 /*!< logical map len in byte */
#define EFUSE_MAX_SECTION_8711B (EFUSE_MAP_LEN_8711B >> 3) /*!< logical map len in section */
#define PGPKT_DATA_SIZE 8 /*!< logical map section len */
/* logical EFUSE User area */
#define USER_SECTION (0x160 >> 3)/*!< user area section index */
/**
* @}
*/
/** @defgroup EFUSE_PHYSICAL_definitions
* @{
*/
#define OTP_SECTION 0x80 /*!< EFUSE OTP area: physical address */
#define OTP_SECTION_LEN 0x20 /*!< EFUSE OTP area: 32 bytes */
/* physical EFUSE len */
#define EFUSE_REAL_CONTENT_LEN 512
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
/* physical EFUSE write forbid */
#define LOGICAL_MAP_SECTION_LEN 0x11E /*!< logical mapping efuse len in physical address */
#define EFUSE_OOB_PROTECT_BYTES (EFUSE_REAL_CONTENT_LEN - LOGICAL_MAP_SECTION_LEN) // Security + RF + MAC + OTP
/**
* @}
*/
/** @defgroup EFUSE_CHIPID_definitions
* @{
*/
//#define CHIPID_8710BN 0xFF /* PACKAGE_QFN32 */
//#define CHIPID_8710BU 0xFE /* PACKAGE_QFN48_MCM */
//#define CHIPID_8711BN 0xFD /* PACKAGE_QFN48 */
//#define CHIPID_8711BG 0xFC /* PACKAGE_QFN68 */
//#define CHIPID_8710BN_L0 0xFB /* PACKAGE_QFN32 L0 */
/**
* @}
*/
/** @defgroup EFUSE_VOLTAGE_definitions
* @{
*/
#define L25EOUTVOLTAGE 7
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EFUSE_Exported_Functions EFUSE Exported Functions
* @{
*/
/** @defgroup EFUSE_Physical_Address_functions
* @{
*/
_LONG_CALL_ extern void EFUSEPowerSwitch(u8 bWrite, u8 PwrState, u8 L25OutVoltage);
_LONG_CALL_ extern u32 EFUSERead8(u32 CtrlSetting, u32 Addr, u8 *Data, u8 L25OutVoltage);
/* please use EFUSE_PMAP_WRITE8, dont use this API direclty, or chip will be damaged */
_LONG_CALL_ extern u32 EFUSEWrite8(u32 CtrlSetting, u32 Addr, u8 Data, u8 L25OutVoltage);
_LONG_CALL_ extern u32 EFUSE_LogicalMap_Read(u8 *pbuf);
/* please use EFUSE_LMAP_WRITE, dont use this API direclty, or chip will be damaged */
_LONG_CALL_ extern u32 EFUSE_LogicalMap_Write(u32 addr, u32 cnts, u8 *data);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Other functions --------------------------------------------------------*/
#define EFUSE_POLL_TIMES 20000
#define EFUSE_SECURE_START 0x150 /* 0x150~0x17F: TrustZone Secure EFUSE */
#define EFUSE_SECURE_END 0x17F
#define EFUSE_RDP_KEY_ADDR 0x170 /* 0x170~0x17F: 16B*/
#define EFUSE_SWD_PWD_ADDR 0x180 /* 0x180~0x18F: 16B */
#define RSIP_KEY_ADDR 0x190 /* 0x190~0x19F: 16B */
#define SBOOT_PK_ADDR 0x1A0 /* 0x1A0~0x1BF: 32B*/
#define EFUSE_SEC_CONFIG_ADDR0 0x1C0 /* 0x1c0 & 0x1c1, security config, please ref REG_LP_EFUSE_PROTECTION for bit define */
#define EFUSE_SEC_CONFIG_ADDR1 0x1C1 /* 0x1c0 & 0x1c1, security config, please ref REG_LP_EFUSE_PROTECTION for bit define */
extern u8 EFUSE_MAP[1024];
__STATIC_INLINE u32 EFUSE_PMAP_READ8(u32 CtrlSetting, u32 Addr, u8 *Data, u8 L25OutVoltage)
{
return EFUSERead8(CtrlSetting, Addr, Data, L25OutVoltage);
}
__STATIC_INLINE u32 EFUSE_PMAP_WRITE8(u32 CtrlSetting, u32 Addr, u8 Data, u8 L25OutVoltage)
{
if (is_power_supply18() == TRUE) {
DBG_8195A("Please Switch to 3.3V to PG EFUSE !!!!!");
//while (1);
return FALSE;
} else {
return EFUSEWrite8(CtrlSetting, Addr, Data, L25OutVoltage);
}
}
__STATIC_INLINE u32 EFUSE_LMAP_READ(u8 *pbuf)
{
return EFUSE_LogicalMap_Read(pbuf);
}
__STATIC_INLINE u32 EFUSE_LMAP_WRITE(u32 addr, u32 cnts, u8 *data)
{
if (is_power_supply18() == TRUE) {
DBG_8195A("Please Switch to 3.3V to PG EFUSE !!!!!");
//while (1);
return FALSE;
} else {
return EFUSE_LogicalMap_Write(addr, cnts, data);
}
}
__STATIC_INLINE u32 EFUSE_IsSecure(u32 Addr)
{
if (TrustZone_IsSecure()) {
if ((Addr >= 0x150) && (Addr <= 0x17F)) {
return TRUE;
}
}
return FALSE;
}
/**
* @brief Get EFUSE physical address remain length.
* @param none
* @retval EFUSE physical address remain length
*/
__STATIC_INLINE u32 EFUSE_RemainLength(void)
{
u32 Idx = 0;
u8 DataTemp0, WordEn;
//find start add
while(Idx < LOGICAL_MAP_SECTION_LEN){
EFUSERead8(0, Idx, &DataTemp0, L25EOUTVOLTAGE);
if (DataTemp0 != 0xff) {
if((DataTemp0&0x0f) == 0xf){
Idx++;
EFUSERead8(0, Idx, &DataTemp0, L25EOUTVOLTAGE);
WordEn = ((~DataTemp0)&0x0f);
while(WordEn!=0){
if (WordEn & BIT0) {
Idx = Idx + 2;
}
WordEn = WordEn>>1;
}
}
else {
WordEn = ((~DataTemp0)&0x0f);
while(WordEn!=0){
if (WordEn & BIT0) {
Idx = Idx + 2;
}
WordEn = WordEn>>1;
}
}
}
else {
break;
}
Idx++;
}
return (LOGICAL_MAP_SECTION_LEN - Idx);
}
#endif //_8710B_EFUSE_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_flash.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the Flash firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_SPI_FLASH_H
#define _RTL8710B_SPI_FLASH_H
#include "rtl8721d_flashclk.h"
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup FLASH
* @brief SPI Flash driver modules
* @{
*/
/** @addtogroup FLASH
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* SPI_Flash_Controller is used to communicate with SPI_Flash.
* Support auto mode and user mode to access Flash.
* Support multi-channel(1/2/4)data bit to transmit/receive.
* Programmable feature:
* SPI channel number - Control channel bits of serial transfer.
* SPI Clock rate - Control the bit rate of serial transfer.
* Flash command registers - Flexible to set the different command codes for
* different flash vendors in automatic mode.
* Dummy cycles- Allow users to add dummy cycles in receiving data path for
* timing tuning or extra pipelining registers.
* Flash address size- Define the size of Flash to enable the slave select output
* in automatic mode.
*
*****************************************************************************************
* How to use SPI_Flash_Controller to Read/Program/Erase flash
*****************************************************************************************
* To use the SPI_Flash_Controller to Read/Program/Erase flash, you can follow the steps
* below:
*
* 1. Enable SPIC clock by using RCC_PeriphClockCmd(APBPeriph_FLASH, APBPeriph_FLASH_CLOCK_XTAL, ENABLE) function.
*
* 2. Call Pinmux_SpicCtrl(PinLocation, ON) to configure SPIC pinmux.
*
* 3. Fill the variable flash_init_para of type FLASH_InitTypeDef with default parameters
* using one of the following functions according to flash vendor:
* flash vendor Struct Init Function
* Winbond FLASH_StructInit(&flash_init_para)
* Gigadevice FLASH_StructInit_GD(&flash_init_para)
* Micron FLASH_StructInit_Micron(&flash_init_para)
* MXIC FLASH_StructInit_MXIC(&flash_init_para)
*
* Note: (1)We support 4 flash chip vendors above in SDK.
* (2)If the flash chip type is Gigadevic and flash size is more than 2MB,
* you must set the FLASH_cmd_wr_status2 parameter in flash_init_para
* according to spec, because the Write Status Register1 command is
* different from write Status Register2 command.
* (3)If it is Micron flash chip, it is mandatory to set dummy cycles to
* Nonvolatile Configuration Register of flash. The number of dummy cycles is
* determined by Clock Frequency and Bit Mode according to spec.
* (4)If the flash chip type is Micron N25q00aa, you must set FLASH_cmd_chip_e
* parameter according to spec because it is different from default setting.
*
* 4. Initialize SPIC to designated BitMode using FLASH_Init().
*
* 5. Enable Quad I/O by setting QuadEnable bit in FLASH status register.
*
* 6. Switch SPIC to higher clock rate using RCC_PeriphClockCmd(APBPeriph_FLASH, APBPeriph_FLASH_CLOCK_PLL, ENABLE) function.
*
* 7. Calibrate by calling FLASH_CalibrationNew() function.
*
* 8. Then you can Read/Program/Erase flash by calling corresponding functions.
* Remember to add flash_write_lock() function before those operations and
* flash_write_unlock() after them to protect them when FLASH XIP.
*
* Note: (1)If flash code has some updates when XIP, you need to flush cache by calling
* Cache_Flush() function.
* (2)When XIP, the flash initialization and calibration have already finished,
* you can Read/Program/Erase flash directly without excuting 1~6 steps described
* above.
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Types FLASH Exported Types
* @{
*/
/**
* @brief FLASH Init structure definition
*/
typedef struct {
u32 FLASH_Id; /*!< Specifies the flash vendor ID.
This parameter can be a value of @ref FLASH_VENDOR_ID_definitions */
u8 FLASH_cur_bitmode; /*!< Specifies the current bitmode of SPIC.
This parameter can be a value of @ref FLASH_BIT_Mode_definitions */
u8 FLASH_baud_rate; /*!< Specifies the spi_sclk divider value. The frequency of spi_sclk is derived from:
Frequency of spi_sclk = Frequency of oc_clk / (2 * FLASH_baud_rate) */
u8 FLASH_baud_boot; /*!< Specifies the spi_sclk divider value for rom boot. The frequency of spi_sclk is derived from:
Frequency of spi_sclk = Frequency of oc_clk / (2 * FLASH_baud_rate) */
u32 FLASH_cur_cmd; /*!< Specifies the current read cmd which is used to read data from flash
in current bitmode. */
/* status bits define */
u32 FLASH_QuadEn_bit; /*!< Specifies the QE bit in status register which is used to enable Quad I/O mode . */
u32 FLASH_Busy_bit; /*!< Specifies the WIP(Write in Progress) bit in status register which indicates whether
the device is busy in program/erase/write status register progress. */
u32 FLASH_WLE_bit; /*!< Specifies the WEL(Write Enable Latch) bit in status register which indicates whether
the device will accepts program/erase/write status register instructions*/
u32 FLASH_Status2_exist; /*!< Specifies whether this flash chip has Status Register2 or not.
This parameter can be 0/1. 0 means it doesn't have Status Register2, 1 means
it has Status Register2.*/
/* calibration data */
u8 FLASH_rd_sample_phase_cal; /*!< Specifies the read sample phase obtained from calibration. this is cal sample phase get from high speed cal */
u8 FLASH_rd_sample_phase; /*!< Specifies the read sample phase obtained from calibration. this is current sample phase */
u8 FLASH_rd_dummy_cyle[3]; /*!< Specifies the read dummy cycle of different bitmode according to
flash datasheet*/
/* valid R/W command set */
u32 FLASH_rd_dual_o; /*!< Specifies dual data read cmd */
u32 FLASH_rd_dual_io; /*!< Specifies dual data/addr read cmd */
u32 FLASH_rd_quad_o; /*!< Specifies quad data read cmd */
u32 FLASH_rd_quad_io; /*!< Specifies quad data/addr read cmd */
u32 FLASH_wr_dual_i; /*!< Specifies dual data write cmd */
u32 FLASH_wr_dual_ii; /*!< Specifies dual data/addr write cmd */
u32 FLASH_wr_quad_i; /*!< Specifies quad data write cmd */
u32 FLASH_wr_quad_ii; /*!< Specifies quad data/addr write cmd */
u32 FALSH_dual_valid_cmd; /*!< Specifies valid cmd of dual bitmode to program/read flash in auto mode */
u32 FALSH_quad_valid_cmd; /*!< Specifies valid cmd of quad bitmode to program/read flash in auto mode */
/* other command set */
u8 FLASH_cmd_wr_en; /*!< Specifies the Write Enable(WREN) instruction which is for setting WEL bit*/
u8 FLASH_cmd_rd_id; /*!< Specifies the Read ID instruction which is for getting the identity of the flash divice.*/
u8 FLASH_cmd_rd_status; /*!< Specifies the Read Status Register instruction which is for getting the status of flash */
u8 FLASH_cmd_rd_status2; /*!< Specifies the Read Status Register2 instruction which is for getting the status2 of flash */
u8 FLASH_cmd_wr_status; /*!< Specifies the Write Status Register instruction which is for setting the status register of flash */
u8 FLASH_cmd_wr_status2; /*!< Specifies the Write Status Register2 instruction which is for setting the status register2 of flash.
In some flash chips, status2 write cmd != status1 write cmd,
like: GD25Q32C, GD25Q64C,GD25Q128C etc.*/
u8 FLASH_cmd_chip_e; /*!< Specifies the Erase Chip instruction which is for erasing the whole chip*/
u8 FLASH_cmd_block_e; /*!< Specifies the Erase Block instruction which is for erasing 64kB*/
u8 FLASH_cmd_sector_e; /*!< Specifies the Erase Sector instruction which is for erasing 4kB*/
u8 FLASH_cmd_pwdn_release; /*!< Specifies the Release from Deep Power Down instruction which is for exiting power down mode.*/
u8 FLASH_cmd_pwdn; /*!< Specifies the Deep Power Down instruction which is for entering power down mode.*/
/* debug log */
u8 debug; /*!< Specifies whether or not to print debug log.*/
/* new calibration */
u8 phase_shift_idx; /*!< Specifies the phase shift idx in new calibration.*/
u8 FLASH_addr_phase_len; /*!< Specifies the number of bytes in address phase (between command phase and write/read phase).
This parameter can be 0/1/2/3. 0 means 4-byte address mode in SPI Flash.*/
u8 FLASH_pseudo_prm_en; /*!< Specifies whether SPIC enables SPIC performance read mode or not.*/
u8 FLASH_pinmux; /*!< Specifies which pinmux is used. PINMUX_S0 or PINMUX_S1*/
u32 FLASH_rd_fast_single; /*!< Specifies fast read cmd in auto mode.*/
} FLASH_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
* @{
*/
/** @defgroup FLASH_CLK_Div_definitions
* @{
*/
#define FLASH_CLK_DIV2P0 0
#define FLASH_CLK_DIV2P5 1
#define FLASH_CLK_DIV3P0 2
#define FLASH_CLK_DIV3P5 3
#define FLASH_CLK_DIV4P0 4
/**
* @}
*/
/** @defgroup FLASH_BIT_Mode_definitions
* @{
*/
#define SpicOneBitMode 0
#define SpicDualBitMode 1
#define SpicQuadBitMode 2
/**
* @}
*/
/** @defgroup FLASH_ERASE_Type_definitions
* @{
*/
#define EraseChip 0
#define EraseBlock 1
#define EraseSector 2
/**
* @}
*/
/** @defgroup FLASH_WAIT_Type_definitions
* @{
*/
#define WAIT_SPIC_BUSY 0
#define WAIT_FLASH_BUSY 1
#define WAIT_WRITE_DONE 2
#define WAIT_WRITE_EN 3
/**
* @}
*/
/** @defgroup SPIC_ADDR_PHASE_LEN_definitions
* @{
*/
#define ADDR_3_BYTE 0x3
#define ADDR_4_BYTE 0x0
#define ADDR_3_BYTE_USER_PRM 0x0
#define ADDR_4_BYTE_USER_PRM 0x4
/**
* @}
*/
/** @defgroup WINBOND_W25Q16DV_Spec
* @{
*/
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_RDSR2 0x35 //read status register-2
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0xD8 //0x52 //64K Block Erase
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
#define FLASH_CMD_4PP 0x32 //quad page program //this is diff with MXIC
#define FLASH_CMD_FF 0xFF //Release Read Enhanced
#define FLASH_CMD_REMS2 0x92 // read ID for 2x I/O mode //this is diff with MXIC
#define FLASH_CMD_REMS4 0x94 // read ID for 4x I/O mode //this is diff with MXIC
#define FLASH_CMD_RDSCUR 0x48 // read security register //this is diff with MXIC
#define FLASH_CMD_WRSCUR 0x42 // write security register //this is diff with MXIC
#define FLASH_DM_CYCLE_2O 0x08
#define FLASH_DM_CYCLE_2IO 0x04
#define FLASH_DM_CYCLE_4O 0x08
#define FLASH_DM_CYCLE_4IO 0x06
#define FLASH_STATUS_BUSY ((u32)0x00000001)
#define FLASH_STATUS_WLE ((u32)0x00000002)
/**
* @}
*/
/** @defgroup WINBOND_W25Q256FV_Spec
* @{
*/
#define FLASH_CMD_ENT_ADDR4B 0xB7
#define FLASH_CMD_EXT_ADDR4B 0xE9
/**
* @}
*/
/** @defgroup FLASH_VENDOR_ID_definitions
* @{
*/
#define FLASH_ID_OTHERS 0
#define FLASH_ID_MXIC 1
#define FLASH_ID_WINBOND 2
#define FLASH_ID_MICRON 3
#define FLASH_ID_EON 4
#define FLASH_ID_GD 5
#define FLASH_ID_BOHONG 6
/**
* @}
*/
/** @defgroup FLASH_MANUFACTURER_ID_definitions
* @{
*/
#define MANUFACTURER_ID_MXIC 0xC2
#define MANUFACTURER_ID_WINBOND 0xEF
#define MANUFACTURER_ID_MICRON 0x20
#define MANUFACTURER_ID_BOHONG 0x68
#define MANUFACTURER_ID_GD 0xC8
#define MANUFACTURER_ID_EON 0x1C
#define MANUFACTURER_ID_FM 0xA1
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
* @{
*/
_LONG_CALL_ void FLASH_Erase(u32 EraseType, u32 Address);
_LONG_CALL_ void FLASH_SetStatus(u8 Cmd, u32 Len, u8* Status);
_LONG_CALL_ void FLASH_SetStatusBits(u32 SetBits, u32 NewState);
_LONG_CALL_ void FLASH_WaitBusy(u32 WaitType);
_LONG_CALL_ void FLASH_WriteEn(void);
_LONG_CALL_ void FLASH_TxCmd(u8 cmd, u8 DataPhaseLen, u8* pData);
_LONG_CALL_ void FLASH_RxCmd(u8 cmd, u32 read_len, u8* read_data);
_LONG_CALL_ void FLASH_StructInit(FLASH_InitTypeDef* FLASH_InitStruct);
_LONG_CALL_ void FLASH_StructInit_Micron(FLASH_InitTypeDef* FLASH_InitStruct);
_LONG_CALL_ void FLASH_StructInit_MXIC(FLASH_InitTypeDef* FLASH_InitStruct);
_LONG_CALL_ void FLASH_StructInit_GD(FLASH_InitTypeDef* FLASH_InitStruct);
_LONG_CALL_ u8 FLASH_Init(u8 SpicBitMode);
_LONG_CALL_ void FLASH_SetSpiMode(FLASH_InitTypeDef *FLASH_InitStruct, u8 SpicBitMode);
_LONG_CALL_ void FLASH_DeepPowerDown(u32 NewState);
_LONG_CALL_ void FLASH_TxData256B(u32 StartAddr, u32 DataPhaseLen, u8* pData);
_LONG_CALL_ void FLASH_TxData12B(u32 StartAddr, u8 DataPhaseLen, u8* pData);
_LONG_CALL_ void FLASH_RxData(u8 cmd, u32 StartAddr, u32 read_len, u8* read_data);
_LONG_CALL_ u32 FLASH_Calibration(FLASH_InitTypeDef* FLASH_InitStruct, u8 SpicBitMode, u8 LineDelay);
_LONG_CALL_ u32 FLASH_ClockDiv(u8 Div);
_LONG_CALL_ u32 FLASH_CalibrationNew(FLASH_InitTypeDef* FLASH_InitStruct, u8 SpicBitMode, u8 Div, u8 CalStep, u8 LineDelay, u8 StartIdx);
_LONG_CALL_ u32 FLASH_CalibrationNewCmd(u32 NewStatus);
_LONG_CALL_ u32 FLASH_CalibrationPhaseIdx(u8 phase_idx);
_LONG_CALL_ u32 FLASH_CalibrationPhase(u8 phase_int, u8 phase_sel);
_LONG_CALL_ u32 FLASH_Calibration500MPSCmd(u32 NewStatus);
_LONG_CALL_ u32 FLASH_CalibrationInit(u8 CalibrationEnd);
_LONG_CALL_ void FLASH_ClockSwitch(u32 Source, u32 Protection);
_LONG_CALL_ int FLASH_WriteStream(u32 address, u32 len, u8 * data);
/**
* @}
*/
/** @defgroup FLASH_Exported_XIP_Functions FLASH Exported XIP Functions
* @note these functions will lock cpu when exec to forbit XIP, and flush cache after exec
* @{
*/
void FLASH_Write_Lock(void);
void FLASH_Write_Unlock(void);
void FLASH_RxCmdXIP(u8 cmd, u32 read_len, u8* read_data);
void FLASH_SetStatusXIP(u8 Cmd, u32 Len, u8* Status);
void FLASH_SetStatusBitsXIP(u32 SetBits, u32 NewState);
void FLASH_TxData12BXIP(u32 StartAddr, u8 DataPhaseLen, u8* pData);
void FLASH_TxData256BXIP(u32 StartAddr, u32 DataPhaseLen, u8* pData);
void FLASH_EraseXIP(u32 EraseType, u32 Address);
void FLASH_EreaseDwordsXIP(u32 address, u32 dword_num);
void FLASH_Write_IPC_Int(VOID *Data, u32 IrqStatus, u32 ChanNum);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup FLASH_Register_Definitions FLASH Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup SPIC_CTRLR0
* @{
*****************************************************************************/
/******************** Bits definition for SPIC_CTRLR0 register *******************/
#define BIT_CMD_CH(x) (((x) & 0x00000003) << 20)
#define BIT_DATA_CH(x) (((x) & 0x00000003) << 18)
#define BIT_ADDR_CH(x) (((x) & 0x00000003) << 16)
#define BIT_TMOD(x) (((x) & 0x00000003) << 8)
#define BIT_SCPOL (0x00000001 << 7)
#define BIT_SCPH (0x00000001 << 6)
/** @} */
/**************************************************************************//**
* @defgroup SPIC_CTRLR1
* @{
*****************************************************************************/
/******************** Bits definition for SPIC_CTRLR1 register *******************/
#define BIT_NDF(x) ((x) & 0xffff)
/** @} */
/**************************************************************************//**
* @defgroup SPIC_SSIENR
* @{
*****************************************************************************/
/******************** Bits definition for SPIC_SSIENR register *******************/
#define BIT_ATCK_CMD (0x00000001 << 1)
#define BIT_SPIC_EN (0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup SPIC_SER
* @{
*****************************************************************************/
/******************** Bits definition for SPIC_SER register *******************/
#define BIT_SER (0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup SPIC_BAUDR
* @{
*****************************************************************************/
/******************** Bits definition for SPIC_BAUDR register *******************/
#define BIT_SCKDV(x) ((x) & 0x0fff)
/** @} */
/**************************************************************************//**
* @defgroup SPIC_SR
* @{
*****************************************************************************/
/******************** Bits definition for SPIC_SR register *******************/
#define BIT_TXE (0x00000001 << 5)
#define BIT_RFF (0x00000001 << 4)
#define BIT_RFNE (0x00000001 << 3)
#define BIT_TFE (0x00000001 << 2)
#define BIT_TFNF (0x00000001 << 1)
#define BIT_BUSY (0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup SPIC_IMR
* @{
*****************************************************************************/
/******************** Bits definition for SPIC_IMR register *******************/
#define BIT_TXSIM (0x00000001 << 9)
#define BIT_ACEIM (0x00000001 << 8)
#define BIT_BYEIM (0x00000001 << 7)
#define BIT_WBEIM (0x00000001 << 6)
#define BIT_FSEIM (0x00000001 << 5)
#define BIT_RXFIM (0x00000001 << 4)
#define BIT_RXOIM (0x00000001 << 3)
#define BIT_RXUIM (0x00000001 << 2)
#define BIT_TXOIM (0x00000001 << 1)
#define BIT_TXEIM (0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup SPIC_ISR
* @{
*****************************************************************************/
/******************** Bits definition for SPIC_ISR register *******************/
#define BIT_TXSIS (0x00000001 << 9)
#define BIT_ACEIS (0x00000001 << 8)
#define BIT_BYEIS (0x00000001 << 7)
#define BIT_WBEIS (0x00000001 << 6)
#define BIT_FSEIS (0x00000001 << 5)
#define BIT_RXFIS (0x00000001 << 4)
#define BIT_RXOIS (0x00000001 << 3)
#define BIT_RXUIS (0x00000001 << 2)
#define BIT_TXOIS (0x00000001 << 1)
#define BIT_TXEIS (0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup SPIC_RISR
* @{
*****************************************************************************/
/******************** Bits definition for SPIC_RISR register *******************/
#define BIT_ACEIR (0x00000001 << 8)
#define BIT_BYEIR (0x00000001 << 7)
#define BIT_WBEIR (0x00000001 << 6)
#define BIT_FSEIR (0x00000001 << 5)
#define BIT_RXFIR (0x00000001 << 4)
#define BIT_RXOIR (0x00000001 << 3)
#define BIT_RXUIR (0x00000001 << 2)
#define BIT_TXOIR (0x00000001 << 1)
#define BIT_TXEIR (0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup SPIC_CTRLR2
* @{
*****************************************************************************/
/******************** Bits definition for SPIC_CTRLR2 register *******************/
#define BIT_FIFO_ENTRY(x) (((x) & 0x0000000f) << 4)
#define BIT_WR_SEQ (0x00000001 << 3)
#define BIT_WPN_DNUM (0x00000001 << 2) /* Indicate the WPn input pin of SPI Flash is connected to, 0(default): WP=spi_sout[2], 1:WP=spi_sout[3]. */
#define BIT_WPN_SET (0x00000001 << 1) /* To implement write protect function. spi_wen_out and the bit of spi_sout which connects to WPN would be initial to 0. */
#define BIT_SO_DUM (0x00000001) /* SO input pin of SPI Flash, 0: SO connects to spi_sout[0]. 1(default): SO connects to spi_sout[1].*/
/** @} */
/**************************************************************************//**
* @defgroup SPIC_ADDR_LENGTH
* @{
*****************************************************************************/
/******************** Bits definition for SPIC_ADDR_LENGTH register *******************/
#define BIT_ADDR_PHASE_LENGTH(x) ((x) & 0x00000007)
/** @} */
/**************************************************************************//**
* @defgroup SPIC_AUTO_LENGTH
* @{
*****************************************************************************/
/******************** Bits definition for SPIC_AUTO_LENGTH register *******************/
#define BIT_CS_H_WR_DUM_LEN(x) (((x) & 0x0000000f) << 28)
#define BIT_CS_H_RD_DUM_LEN(x) (((x) & 0x00000003) << 26)
#define BIT_AUTO_DUM_LEN(x) (((x) & 0x000000ff) << 18)
#define BIT_AUTO_ADDR_LENGTH(x) (((x) & 0x00000003) << 16)
#define BIT_RD_DUMMY_LENGTH(x) (((x) & 0x00000fff))
/** @} */
/**************************************************************************//**
* @defgroup SPIC_VALID_CMD
* @{
*****************************************************************************/
/******************** Bits definition for SPIC_VALID_CMD register *******************/
#define BIT_CTRLR0_CH (0x00000001 << 12)
#define BIT_PRM_EN (0x00000001 << 11)
#define BIT_WR_BLOCKING (0x00000001 << 9)
#define BIT_WR_QUAD_II (0x00000001 << 8)
#define BIT_WR_QUAD_I (0x00000001 << 7)
#define BIT_WR_DUAL_II (0x00000001 << 6)
#define BIT_WR_DUAL_I (0x00000001 << 5)
#define BIT_RD_QUAD_IO (0x00000001 << 4)
#define BIT_RD_QUAD_O (0x00000001 << 3)
#define BIT_RD_DUAL_IO (0x00000001 << 2)
#define BIT_RD_DUAL_I (0x00000001 << 1)
#define BIT_FRD_SINGEL (0x00000001)
#define SPIC_VALID_CMD_MASK (0x7fff)
#define DUAL_PRM_CYCLE_NUM 4
#define QUAD_PRM_CYCLE_NUM 2
/** @} */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Other definations --------------------------------------------------------*/
extern FLASH_InitTypeDef flash_init_para;
extern u32 SPIC_CALIB_PATTERN[2];
typedef void (*FLASH_STRUCT_INIT_FUNC)(FLASH_InitTypeDef* FLASH_InitStruct);
#define SPIC_LOWSPEED_SAMPLE_PHASE 1
#endif //_RTL8710B_SPI_FLASH_H
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_flashclk.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the Flash Clock firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_FLASH_CLK_H
#define _RTL8710B_FLASH_CLK_H
/* Other definations --------------------------------------------------------*/
typedef enum {
FlashClass1 = 0,
FlashClass2,
FlashClass3,
FlashClass4,
FlashClass5,
FlashClass6,
FlashClassUser = 0xFE,
FlashClassNone = 0xFF,
} FlashClass;
typedef struct {
u32 flash_id;
u32 id_mask;
u8 flash_class;
u32 sta_mask;
VOID (*FlashInitHandler) (VOID);
} FlashInfo_TypeDef;
typedef struct {
u8 phase_int;
u8 phase_frac;
} FLASH_CLK_Phase;
typedef struct {
u8 div_int;
u8 div_frac;
} FLASH_CLK_Div;
extern u8 NEW_CALIBREATION_END[];
#endif //_RTL8710B_FLASH_CLK_H
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_gdma.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the GDMA firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_GDMA_H_
#define _RTL8710B_GDMA_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup GDMA GDMA
* @{
*/
/** @addtogroup GDMA
* @verbatim
*******************************************************************************************
* Introduction
*******************************************************************************************
* AmebaD supports two GDMAs, GDMA0 in KM0, and GDMA0 in KM4. GDMA0 in KM0 has four channels,
* while GDMA0 in KM4 has six channels. The Msize of channel 0 can be up to 256 when copy data
* from mem0 to mem1(between different memory), and the Msize should be no more than 8 in
* other situations.
*
* GDMA0 in KM0:
* - Base Address: GDMA0_REG_BASE(KM0)
*
* - Channel index: 0~3
*
* - Block size range: 1~4095
*
* - Transfer Type and Flow Control:
* TTFCMemToMem (Memory to Memory)
* TTFCMemToPeri (Memory to Peripheral)
* TTFCPeriToMem (Peripheral to Memory)
* TTFCPeriToPeri (Peripheral to Peripheral)
*
* - Source and destination data width:
* TrWidthOneByte
* TrWidthTwoBytes
* TrWidthFourBytes
*
* - Source and destination burst transaction length:
* MsizeOne (One Byte)
* MsizeFour (Four Bytes)
* MsizeEight (Eight Bytes)
* MsizeSixteen (sixteen Bytes, only channel0 supports in some situations)
*
* - IRQ:
* GDMA0_CHANNEL0_IRQ_LP,
* GDMA0_CHANNEL1_IRQ_LP,
* GDMA0_CHANNEL2_IRQ_LP,
* GDMA0_CHANNEL3_IRQ_LP,
*
* - GDMA handshake interface with peripherals:
* GDMA_HANDSHAKE_INTERFACE_UART3_TX
* GDMA_HANDSHAKE_INTERFACE_UART3_TX
* GDMA_HANDSHAKE_INTERFACE_I2C0_TX
* GDMA_HANDSHAKE_INTERFACE_I2C0_RX
* GDMA_HANDSHAKE_INTERFACE_ADC_RX
* GDMA_HANDSHAKE_INTERFACE_SGPIO_TX
*
*
* GDMA0 in KM4:
* - Base Address: GDMA0_REG_BASE(KM4)
*
* - Channel index: 0~5
*
* - Block size range: 1~4095
*
* - Transfer Type and Flow Control:
* TTFCMemToMem (Memory to Memory)
* TTFCMemToPeri (Memory to Peripheral)
* TTFCPeriToMem (Peripheral to Memory)
* TTFCPeriToPeri (Peripheral to Peripheral)
*
* - Source and destination data width:
* TrWidthOneByte
* TrWidthTwoBytes
* TrWidthFourBytes
*
* - Source and destination burst transaction length:
* MsizeOne (One Byte)
* MsizeFour (Four Bytes)
* MsizeEight (Eight Bytes)
* MsizeSixteen (sixteen Bytes, only channel0 supports in some situations)
* - IRQ:
* GDMA0_CHANNEL0_IRQ,
* GDMA0_CHANNEL1_IRQ
* GDMA0_CHANNEL2_IRQ
* GDMA0_CHANNEL3_IRQ
* GDMA0_CHANNEL4_IRQ
* GDMA0_CHANNEL5_IRQ
*
* - GDMA handshake interface with peripherals:
* GDMA_HANDSHAKE_INTERFACE_UART0_TX
* GDMA_HANDSHAKE_INTERFACE_UART0_RX
* GDMA_HANDSHAKE_INTERFACE_UART1_TX
* GDMA_HANDSHAKE_INTERFACE_UART1_RX
* GDMA_HANDSHAKE_INTERFACE_SPI0_TX
* GDMA_HANDSHAKE_INTERFACE_SPI0_RX
* GDMA_HANDSHAKE_INTERFACE_SPI1_TX
* GDMA_HANDSHAKE_INTERFACE_SPI1_RX
* GDMA_HANDSHAKE_INTERFACE_USI0_TX
* GDMA_HANDSHAKE_INTERFACE_USI0_RX
* GDMA_HANDSHAKE_INTERFACE_AUDIO_TX
* GDMA_HANDSHAKE_INTERFACE_AUDIO_RX
*
*****************************************************************************************
* how to use GDMA
*****************************************************************************************
* To use the GDMA, the following steps are mandatory:
*
* 1. Allocate a GDMA channel using the follwoing function.
* GDMA_ChnlAlloc(u32 GDMA_Index, IRQ_FUN IrqFun, u32 IrqData, u32 IrqPriority)
*
* @note This function also includes the following operation:
* - register irq handler if use interrupt mode
* - enable NVIC interrupt
* - register the GDMA channel to use
* - enable GDMA peripheral clock
*
* 2. Program GDMA index, GDMA channel, data width, Msize, transfer direction, address increment mode,
* hardware handshake interface, reload control, interrupt type, block size, multi-block configuration
* and the source and destination address using the GDMA_Init() function.
*
* 3. Enable the corresponding interrupt using the function.
* GDMA_INTConfig() and register the uart irq handler if you need to use interrupt mode.
*
* @note This step is included in the "step 2"(GDMA_Init()).
*
* 4. Enable GDMA using function GDMA_Cmd().
*
*
* @endverbatim
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup GDMA_Exported_Types GDMA Exported Types
* @{
*/
/**
* @brief GDMA Init structure definition
*/
typedef struct {
u8 GDMA_Index; /*!< Specifies the GDMA index.
This parameter can be the value 0.
@note AmebaD supports two GDMAs, GDMA0 in KM0, and GDMA0 in KM4.*/
u8 GDMA_ChNum; /*!< Specifies the GDMA channel number.
This parameter can be the value 0 ~ 5.
@note GDMA in KM0 has four channels, channel0 ~ channel3,
while GDMA in KM4 has six channels, channel0 ~ channel5.*/
u32 GDMA_DIR; /*!< Specifies the GDMA transmission direction.
This parameter can be a value of @ref GDMA_data_transfer_direction */
u32 GDMA_DstDataWidth; /*!< Specifies the GDMA destination transfer width.
This parameter can be a value of @ref GDMA_source_data_size */
u32 GDMA_SrcDataWidth; /*!< Specifies the GDMA transfer width.
This parameter can be a value of @ref GDMA_source_data_size */
u32 GDMA_DstInc; /*!< Specifies the GDMA destination address increment mode.
This parameter can be a value of @ref GDMA_incremented_mode */
u32 GDMA_SrcInc; /*!< Specifies the GDMA source address increment mode.
This parameter can be a value of @ref GDMA_incremented_mode */
u32 GDMA_DstMsize; /*!< Specifies the GDMA destination burst transaction length.
This parameter can be a value of @ref GDMA_Msize */
u32 GDMA_SrcMsize; /*!< Specifies the GDMA source burst transaction length.
This parameter can be a value of @ref GDMA_Msize */
u32 GDMA_SrcAddr; /*!< Specifies the GDMA source address.
This parameter can be a value of the memory or peripheral space address,
depending on the GDMA data transfer direction.If this address is configured,
GDMA will move data from here to the destination address space*/
u32 GDMA_DstAddr; /*!< Specifies the GDMA destination address.
This parameter can be a value of the memory or peripheral space address,
depending on the GDMA data transfer direction.If this address is configured,
GDMA will move data here from source address space*/
u16 GDMA_BlockSize; /*!< Specifies the GDMA block transfer size.
This parameter can be a value between 0 ~ 4095.
@note This parameter indicates the total number of single transactions for
every block transfer. The field for this parameter locates in CTLx[43:32], so
the value of this parameter must be no more than 0xffff.*/
u32 GDMA_IsrType; /*!< Specifies the GDMA interrupt types.
This parameter can be a value of @ref DMA_interrupts_definition */
u32 GDMA_ReloadSrc; /*!< Specifies the GDMA automatic source reload .
This parameter can be the 0 or 1.(0 : disable / 1 : enable).
@note if this value is setted 1, source address register can be automatically
reloaded from its initial value at the end of every block for multi-block transfers.
this parameter is only valid in multi block transmission mode*/
u32 GDMA_ReloadDst; /*!< Specifies the GDMA automatic destination reload .
This parameter can be the 0 or 1.(0 : disable / 1 : enable).
@note if this parameter is set 1, destination address register can be automatically
reloaded from its initial value at the end of every block for multi-block transfers.
this parameter is only valid in multi block transmission mode*/
u32 GDMA_LlpDstEn; /*!< Specifies the GDMA whether block chaining is enabled or disabled on the destination
side only.
@note this parameter is only valid in multi-block transmission mode*/
u32 GDMA_LlpSrcEn; /*!< Specifies the GDMA whether block chaining is enabled or disabled on the source
side only.
@note this parameter is only valid in multi-block transmission mode*/
u32 GDMA_SrcHandshakeInterface; /*!< Specifies the GDMA hardware handshaking interface for the source
peripheral of a GDMA channel.
This parameter can be a value of @ref DMA_HS_Interface_definition */
u32 GDMA_DstHandshakeInterface; /*!< Specifies the GDMA hardware handshaking interface for the destination
peripheral of a GDMA channel.
This parameter can be a value of @ref DMA_HS_Interface_definition */
u32 MuliBlockCunt; /*!< Specifies the GDMA Multi-block counter.
This parameter is used in multi-block transmission.*/
u32 MaxMuliBlock; /*!< Specifies the GDMA Max block number in Multi-block transmission.
This parameter is used in multi-block transmission.*/
u32 SecureTransfer; /*!< Specifies the GDMA secure transmission.
This parameter is used in secure world of trustzone.*/
} GDMA_InitTypeDef, *PGDMA_InitTypeDef;
/**
* @brief GDMA LLI ELE structure definition
*/
typedef struct {
u32 Sarx; /*!< Specifies the GDMA channel x Source Address Register (SARx) value field of a block descriptor
in block chaining.
This parameter stores the source address of the current block transfer.*/
u32 Darx; /*!< Specifies the GDMA channel x Destination Address Register(DARx) value field of a block descriptor
in block chaining.
This parameter stores the destination address of the current block transfer.*/
u32 Llpx; /*!< Specifies the GDMA channel x Linked List Pointer Register(LLPx) value field of a block descriptor
in block chaining.
This parameter is a address, which points to the next block descriptor.*/
u32 CtlxLow; /*!< Specifies the GDMA channel x Control Register(CTRx) Low 32 bit value field of a block descriptor
in block chaining.
This parameter stores the DMA control parameters of the current block transfer.*/
u32 CtlxUp; /*!< Specifies the GDMA channel x Control Register(CTRx) High 32 bit value field of a block descriptor
in block chaining.
This parameter stores the DMA control parameters of the current block transfer.*/
u32 Temp; /*!< Specifies the reserved GDMA channel x register value field of a block descriptor
in block chaining.*/
}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE;
/**
* @brief GDMA CH LLI structure definition
*/
struct GDMA_CH_LLI {
GDMA_CH_LLI_ELE LliEle; /*!< Specifies the GDMA Linked List Item Element structure field of Linked List Item
in block chaining.
This structure variable stores the necessary parameters of a block descriptor.*/
u32 BlockSize; /*!< Specifies the GDMA block size of one block in block chaining.
This parameter indicates the block size of the current block transfer.*/
struct GDMA_CH_LLI *pNextLli; /*!< Specifies the GDMA Linked List Item pointer.
This parameter stores the address pointing to the next Linked List Item
in block chaining.*/
};
/**
* @}
*/
/** @defgroup GDMA_Exported_Constants GDMA Exported Constants
* @{
*/
#if defined (ARM_CORE_CM4)
#define MAX_GDMA_INDX (0)
#define MAX_GDMA_CHNL (5)
#else
#define MAX_GDMA_INDX (0)
#define MAX_GDMA_CHNL (3)
#endif
#define IS_GDMA_ChannelNum(NUM) ((NUM) <= MAX_GDMA_CHNL)
#define IS_GDMA_Index(NUM) ((NUM) <= MAX_GDMA_INDX)
/** @defgroup GDMA_data_transfer_direction GDMA Data Transfer Direction
* @{
*/
#define TTFCMemToMem ((u32)0x00000000)
#define TTFCMemToPeri ((u32)0x00000001)
#define TTFCPeriToMem ((u32)0x00000002)
#define TTFCPeriToPeri ((u32)0x00000003)
#define TTFCPeriToMem_PerCtrl ((u32)0x00000004)
#define IS_GDMA_DIR(DIR) (((DIR) == TTFCMemToMem) || \
((DIR) == TTFCMemToPeri) || \
((DIR) == TTFCPeriToMem) ||\
((DIR) == TTFCPeriToPeri) ||\
((DIR) == TTFCPeriToMem_PerCtrl))
/**
* @}
*/
/** @defgroup GDMA_source_data_size GDMA Source Data Size
* @{
*/
#define TrWidthOneByte ((u32)0x00000000)
#define TrWidthTwoBytes ((u32)0x00000001)
#define TrWidthFourBytes ((u32)0x00000002)
#define IS_GDMA_DATA_SIZE(SIZE) (((SIZE) == TrWidthOneByte) || \
((SIZE) == TrWidthTwoBytes) || \
((SIZE) == TrWidthFourBytes))
/**
* @}
*/
/** @defgroup GDMA_Msize GDMA Msize
* @{
*/
#define MsizeOne ((u32)0x00000000)
#define MsizeFour ((u32)0x00000001)
#define MsizeEight ((u32)0x00000002)
#define MsizeSixteen ((u32)0x00000003)
#define IS_GDMA_MSIZE(SIZE) (((SIZE) == MsizeOne) || \
((SIZE) == MsizeFour) || \
((SIZE) == MsizeEight)||\
((SIZE) == MsizeSixteen))
/**
* @}
*/
/** @defgroup GDMA_incremented_mode GDMA Source Incremented Mode
* @{
*/
#define IncType ((u32)0x00000000)
#define DecType ((u32)0x00000001)
#define NoChange ((u32)0x00000002)
#define IS_GDMA_IncMode(STATE) (((STATE) == IncType) || \
((STATE) == DecType) || \
((STATE) == NoChange))
/**
* @}
*/
/** @defgroup GDMA_interrupts_definition GDMA Interrupts Definition
* @{
*/
#define TransferType ((u32)0x00000001)
#define BlockType ((u32)0x00000002)
#define SrcTransferType ((u32)0x00000004)
#define DstTransferType ((u32)0x00000008)
#define ErrType ((u32)0x000000010)
#define IS_GDMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFE0) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup GDMA_Reload_definition GDMA Reload Definition
* @{
*/
#define CLEAN_RELOAD_SRC ((u32)0x00000001)
#define CLEAN_RELOAD_DST ((u32)0x00000002)
#define CLEAN_RELOAD_SRC_DST ((u32)0x00000003)
/**
* @}
*/
/** @defgroup GDMA0_HS_Interface_definition GDMA HandShake Interface Definition
* @{
*/
#define GDMA_HANDSHAKE_INTERFACE_UART0_TX (0)
#define GDMA_HANDSHAKE_INTERFACE_UART0_RX (1)
#define GDMA_HANDSHAKE_INTERFACE_UART1_TX (2)
#define GDMA_HANDSHAKE_INTERFACE_UART1_RX (3)
#define GDMA_HANDSHAKE_INTERFACE_UART3_TX (6)
#define GDMA_HANDSHAKE_INTERFACE_UART3_RX (7)
#define GDMA_HANDSHAKE_INTERFACE_SPI0_TX (4)
#define GDMA_HANDSHAKE_INTERFACE_SPI0_RX (5)
#define GDMA_HANDSHAKE_INTERFACE_SPI1_TX (6)
#define GDMA_HANDSHAKE_INTERFACE_SPI1_RX (7)
#define GDMA_HANDSHAKE_INTERFACE_I2C0_TX (2)
#define GDMA_HANDSHAKE_INTERFACE_I2C0_RX (3)
#define GDMA_HANDSHAKE_INTERFACE_ADC_RX (5)
#define GDMA_HANDSHAKE_INTERFACE_AUDIO_TX (10)
#define GDMA_HANDSHAKE_INTERFACE_AUDIO_RX (11)
#define GDMA_HANDSHAKE_INTERFACE_USI0_TX (8)
#define GDMA_HANDSHAKE_INTERFACE_USI0_RX (9)
#define GDMA_HANDSHAKE_INTERFACE_SGPIO_TX (4)
/**
* @}
*/
/** @defgroup GDMA1_HS_Interface_definition GDMA HandShake Interface Definition.
** @brief this definition is not supported in the amebaD
* @{
*/
#define GDMA_HANDSHAKE_TIMER_CAPTURE_UP (0)
#define GDMA_HANDSHAKE_TIMER_CAPTURE_CH0 (1)
#define GDMA_HANDSHAKE_TIMER_PWM_UP (2)
#define GDMA_HANDSHAKE_TIMER_PWM_CH0 (3)
#define GDMA_HANDSHAKE_TIMER_PWM_CH1 (4)
#define GDMA_HANDSHAKE_TIMER_PWM_CH2 (5)
#define GDMA_HANDSHAKE_TIMER_PWM_CH3 (6)
#define GDMA_HANDSHAKE_TIMER_PWM_CH4 (7)
#define GDMA_HANDSHAKE_TIMER_PWM_CH5 (8)
/**
* @}
*/
/**
* @}
*/
/** @defgroup GDMA_Exported_Functions GDMA Exported Functions
* @{
*/
_LONG_CALL_ void GDMA_StructInit(PGDMA_InitTypeDef GDMA_InitStruct);
_LONG_CALL_ void GDMA_Init(u8 GDMA_Index, u8 GDMA_ChNum, PGDMA_InitTypeDef GDMA_InitStruct);
_LONG_CALL_ void GDMA_SetLLP(u8 GDMA_Index, u8 GDMA_ChNum, u32 MultiBlockCount, struct GDMA_CH_LLI *pGdmaChLli);
_LONG_CALL_ void GDMA_Cmd(u8 GDMA_Index, u8 GDMA_ChNum, u32 NewState);
_LONG_CALL_ void GDMA_INTConfig(u8 GDMA_Index, u8 GDMA_ChNum, u32 GDMA_IT, u32 NewState);
_LONG_CALL_ u32 GDMA_ClearINTPendingBit(u8 GDMA_Index, u8 GDMA_ChNum, u32 GDMA_IT);
_LONG_CALL_ u32 GDMA_ClearINT(u8 GDMA_Index, u8 GDMA_ChNum);
_LONG_CALL_ void GDMA_ChCleanAutoReload(u8 GDMA_Index, u8 GDMA_ChNum, u32 CleanType);
_LONG_CALL_ void GDMA_SetSrcAddr(u8 GDMA_Index, u8 GDMA_ChNum, u32 SrcAddr);
_LONG_CALL_ u32 GDMA_GetSrcAddr(u8 GDMA_Index, u8 GDMA_ChNum);
_LONG_CALL_ u32 GDMA_GetDstAddr(u8 GDMA_Index, u8 GDMA_ChNum);
_LONG_CALL_ void GDMA_SetDstAddr(u8 GDMA_Index, u8 GDMA_ChNum, u32 DstAddr);
_LONG_CALL_ void GDMA_SetBlkSize(u8 GDMA_Index, u8 GDMA_ChNum, u32 BlkSize);
_LONG_CALL_ u32 GDMA_GetBlkSize(u8 GDMA_Index, u8 GDMA_ChNum);
_LONG_CALL_ BOOL GDMA_ChnlRegister (u8 GDMA_Index, u8 GDMA_ChNum);
_LONG_CALL_ void GDMA_ChnlUnRegister (u8 GDMA_Index, u8 GDMA_ChNum);
_LONG_CALL_ u8 GDMA_ChnlAlloc(u32 GDMA_Index, IRQ_FUN IrqFun, u32 IrqData, u32 IrqPriority);
_LONG_CALL_ void GDMA_ChnlFree(u8 GDMA_Index, u8 GDMA_ChNum);
_LONG_CALL_ u8 GDMA_GetIrqNum(u8 GDMA_Index, u8 GDMA_ChNum);
/**
* @}
*/
/* Registers Definitions ----------------------------------------------------------------*/
/** @defgroup GDMA_Register_Definitions GDMA Register Definitions
* @{
*/
/**************************************************************************//**
* @defgroup GDMA_CTL
* @{
*****************************************************************************/
/******************** Bits definition for CTL register *******************/
#define BIT_CTLX_LO_INT_EN ((u32)(0x00000001 << 0)) /*Lower word Bit[0].Interrupt Enable Bit.*/
#define BIT_CTLX_LO_LLP_DST_EN ((u32)(0x00000001 << 27)) /*Lower word Bit[27].Block chaining is enabled on the destination side only*/
#define BIT_CTLX_LO_LLP_SRC_EN ((u32)(0x00000001 << 28)) /*Lower word Bit[28].Block chaining is enabled on the source side only*/
#define BIT_CTLX_LO_DST_TR_WIDTH ((u32)(0x00000007 << 1)) /*Lower word Bit[3:1].Destination Transfer Width*/
#define BIT_CTLX_LO_SRC_TR_WIDTH ((u32)(0x00000007 << 4)) /*Lower word Bit[6:4].Source Transfer Width*/
#define BIT_CTLX_LO_DINC ((u32)(0x00000003 << 7)) /*Lower word Bit[8:7].Destination Address Increment*/
#define BIT_CTLX_LO_SINC ((u32)(0x00000003 << 9)) /*Lower word Bit[10:9].Source Address Increment*/
#define BIT_CTLX_LO_DEST_MSIZE ((u32)(0x00000007 << 11)) /*Lower word Bit[13:11].Destination Burst Transaction Length*/
#define BIT_CTLX_LO_SRC_MSIZE ((u32)(0x00000007 << 14)) /*Lower word Bit[16:14].Source Burst Transaction Length*/
#define BIT_CTLX_LO_SRC_GATHER_EN ((u32)(0x00000001 << 17)) /*Lower word Bit[17].Source gather enable bit*/
#define BIT_CTLX_LO_DST_SCATTER_EN ((u32)(0x00000001 << 18)) /*Lower word Bit[18].Destination gather enable bit*/
#define BIT_CTLX_LO_TT_FC ((u32)(0x00000007 << 20)) /*Lower word Bit[22:20].Transfer Type and Flow Control*/
#define BIT_CTLX_LO_DMS ((u32)(0x00000003 << 23)) /*Lower word Bit[24:23].Destination Master Select*/
#define BIT_CTLX_LO_SMS ((u32)(0x00000003 << 25)) /*Lower word Bit[26:25].Source Master Select*/
//#define BIT_CTLX_UP_DONE ((u32)(0x00000001 << 12)) /*Upper word Bit[12].Done bit, RTK DMAC dont have this bit */
#define BIT_CTLX_UP_BLOCK_BS ((u32)(0x00000FFF << 0)) /*Upper word Bit[11:0].Block Transfer Size.*/
/** @} */
/**************************************************************************//**
* @defgroup GDMA_CFG
* @{
*****************************************************************************/
/******************** Bits definition for CFG register *******************/
#define BIT_CFGX_LO_RELOAD_SRC ((u32)(0x00000001 << 30)) /*Lower word Bit[30].Automatic Source Reload bit*/
#define BIT_CFGX_LO_RELOAD_DST ((u32)(0x00000001 << 31)) /*Lower word Bit[31].Automatic Destination Reload bit*/
#define BIT_CFGX_UP_SEC_DISABLE ((u32)(0x00000001 << 3)) /*Upper word Bit[10:7]. write 0 to enable secure transfer, default is 0 */
#define BIT_CFGX_UP_SRC_PER ((u32)(0x0000000F << 7)) /*Upper word Bit[10:7].hardware handshaking interface for source peripheral*/
#define BIT_CFGX_UP_DEST_PER ((u32)(0x0000000F << 11)) /*Upper word Bit[14:11].hardware handshaking interface for destination peripheral*/
#define BIT_CFGX_UP_FIFO_MODE ((u32)(0x00000001<<1 )) /*Upper word Bit[1].hardware FIFO Mode Select, write 1 to enable*/
/** @} */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Register Address Offset Definitions --------------------------------------------------------*/
/******************** Address Offset Definition for GDMA Registers *******************/
#define REG_GDMA_CH_OFF (0x058) /*address space value between two DMA channels*/
#define REG_GDMA_CH_SAR (0x000) /*Source Address Register(SAR) address offset*/
#define REG_GDMA_CH_DAR (0x008) /*Destination Address Register(DAR) address offset*/
#define REG_GDMA_CH_LLP (0x010) /*Linked List Pointer(LLP) Register address offset*/
#define REG_GDMA_CH_CTL (0x018) /*Control Register(CTR) address offset*/
#define REG_GDMA_CH_SSTAT (0x020) /*Source Status(SSTAT) Register address offset*/
#define REG_GDMA_CH_DSTAT (0x028) /*Destination Status(DSTAT) Register address offset*/
#define REG_GDMA_CH_SSTATAR (0x030) /*Source Status Address(SSTATA) Register address offset*/
#define REG_GDMA_CH_DSTATAR (0x038) /*Destination Status Address(DSTATA) Register address offset*/
#define REG_GDMA_CH_CFG (0x040) /*Configuration(CFG) Register address offset*/
#define REG_GDMA_CH_SGR (0x048) /*Source Gather Register(SGR) address offset*/
#define REG_GDMA_CH_DSR (0x050) /*Destination Scatter Register(DSR) address offset*/
/********************** Address Offset Definition for Interrupt Raw Status Registers *******************/
#define REG_GDMA_RAW_INT_BASE (0x2C0) /*Base address for Interrupt Raw Status Registers*/
#define REG_GDMA_RAW_INT_TFR (0x2C0) /*address offset for DMA Transfer Complete Interrupt Raw Status Register(RawTfr)*/
#define REG_GDMA_RAW_INT_BLOCK (0x2c8) /*address offset for Block Transfer Complete Interrupt Raw Status Register(RawBlock)*/
#define REG_GDMA_RAW_INT_SRC_TRAN (0x2D0) /*address offset for Source Transaction Complete Interrupt Raw Status Register(RawSrcTran)*/
#define REG_GDMA_RAW_INT_DST_TRAN (0x2D8) /*address offset for Destination Transaction Complete Interrupt Raw Status Register(RawDstTran)*/
#define REG_GDMA_RAW_INT_ERR (0x2E0) /*address offset for Error Interrupt Raw Status Register(RawDstTran)*/
/********************** Address Offset Definition for Interrupt Status Registers *******************/
#define REG_GDMA_STATUS_INT_BASE (0x2E8) /*Base address for Interrupt Status Registers*/
#define REG_GDMA_STATUS_INT_TFR (0x2E8) /*address offset for DMA Transfer Complete Interrupt Status Register(StatusTfr)*/
#define REG_GDMA_STATUS_INT_BLOCK (0x2F0) /*address offset for Block Transfer Complete Interrupt Status Register(StatusBlock)*/
#define REG_GDMA_STATUS_INT_SRC_TRAN (0x2F8) /*address offset for Source Transaction Complete Interrupt Status Register(StatusSrcTran)*/
#define REG_GDMA_STATUS_INT_DST_TRAN (0x300) /*address offset for Destination Transaction Complete Interrupt Status Register(StatusDstTran)*/
#define REG_GDMA_STATUS_INT_ERR (0x308) /*address offset for Error Interrupt Status Register(StatusErr)*/
/********************** Address Offset Definition for Interrupt Mask Registers *******************/
#define REG_GDMA_MASK_INT_BASE (0x310) /*Base address for Interrupt Mask Registers*/
#define REG_GDMA_MASK_INT_TFR (0x310) /*address offset for DMA Transfer Complete Interrupt Mask Register(MaskTfr)*/
#define REG_GDMA_MASK_INT_BLOCK (0x318) /*address offset for Block Transfer Complete Interrupt Mask Register(MaskBlock)*/
#define REG_GDMA_MASK_INT_SRC_TRAN (0x320) /*address offset for Source Transaction Complete Interrupt Mask Register(MaskSrcTran)*/
#define REG_GDMA_MASK_INT_DST_TRAN (0x328) /*address offset for Destination Transaction Complete Interrupt Mask Register(MaskDstTran)*/
#define REG_GDMA_MASK_INT_INT_ERR (0x330) /*address offset for Error Interrupt Mask Register(MaskErr)*/
/********************** Address Offset Definition for Interrupt Clear Registers *******************/
#define REG_GDMA_CLEAR_INT_BASE (0x338) /*Base address for Interrupt Clear Registers*/
#define REG_GDMA_CLEAR_INT_TFR (0x338) /*address offset for DMA Transfer Complete Interrupt Clear Register(ClearTfr)*/
#define REG_GDMA_CLEAR_INT_BLOCK (0x340) /*address offset for Block Transfer Complete Interrupt Clear Register(ClearBlock)*/
#define REG_GDMA_CLEAR_INT_SRC_TRAN (0x348) /*address offset for Source Transaction Complete Interrupt Clear Register(ClearSrcTran)*/
#define REG_GDMA_CLEAR_INT_DST_TRAN (0x350) /*address offset for Destination Transaction Complete Interrupt Clear Register(ClearDstTran)*/
#define REG_GDMA_CLEAR_INT_ERR (0x358) /*address offset for Error Interrupt Clear Register(ClearErr)*/
/********************* Address Offset Definition for Combined Interrupt Status Register ***********/
#define REG_GDMA_STATUS_INT (0x360) /*address offset for Combined Interrupt Status Register*/
/********************** Address Offset Definition for Software Handshaking Registers *************/
#define REG_GDMA_REQ_SRC (0x368) /*address offset for Source Software Transaction Request Register(ReqSrcReg)*/
#define REG_GDMA_REQ_DST (0x370) /*address offset for Destination Software Transaction Request Register(ReqDstReg)*/
#define REG_GDMA_REQ_SGL_REQ (0x378) /*address offset for Single Source Transaction Request Register(SglReqSrcReg)*/
#define REG_GDMA_REQ_DST_REQ (0x380) /*address offset for Single Destination Transaction Request Register(SglReqDstReg)*/
#define REG_GDMA_REQ_LST_SRC (0x388) /*address offset for Last Source Transaction Request Register(LstSrcReg)*/
#define REG_GDMA_REQ_LST_DST (0x390) /*address offset for Last Destination Transaction Request Register(LstDstReg)*/
/********************** Address Offset Definition for Miscellaneous Registers *************/
#define REG_GDMA_DMAC_CFG (0x398) /*address offset for DMA Configuration Register(DmaCfgReg)*/
#define REG_GDMA_CH_EN (0x3A0) /*address offset for DMA Channel Enable Register(ChEnReg)*/
#define REG_GDMA_DMA_ID (0x3A8) /*address offset for DMA ID Register(DmaIdReg)*/
#define REG_GDMA_DMA_TEST (0x3B0) /*address offset for DMA Test Register(DmaTestReg)*/
#define REG_GDMA_DMA_COM_PARAMS6 (0x3C8) /*address offset for DMA Component Parameters Register 6(DMA_COMP_PARAMS_6)*/
#define REG_GDMA_DMA_COM_PARAMS5 (0x3D0) /*address offset for DMA Component Parameters Register 5(DMA_COMP_PARAMS_5)*/
#define REG_GDMA_DMA_COM_PARAMS4 (0x3D8) /*address offset for DMA Component Parameters Register 4(DMA_COMP_PARAMS_4)*/
#define REG_GDMA_DMA_COM_PARAMS3 (0x3E0) /*address offset for DMA Component Parameters Register 3(DMA_COMP_PARAMS_3)*/
#define REG_GDMA_DMA_COM_PARAMS2 (0x3E8) /*address offset for DMA Component Parameters Register 2(DMA_COMP_PARAMS_2)*/
#define REG_GDMA_DMA_COM_PARAMS1 (0x3F0) /*address offset for DMA Component Parameters Register 1(DMA_COMP_PARAMS_1)*/
#define REG_GDMA_DMA_COM_PARAMS0 (0x3F8) /*address offset for DMA Component ID Register. Bit[63:32]: DMA_COMP_VERSION
Bit[31:0]:DMA_COMP_TYPE*/
__STATIC_INLINE void GDMA_BurstEnable(u32 ch_num, u32 NewState) {
GDMA_TypeDef* GDMA = ((GDMA_TypeDef *) GDMA_BASE);
u32 ValTemp = 0;
if (TrustZone_IsSecure()) {
GDMA = ((GDMA_TypeDef *) GDMA0S_REG_BASE);
}
ValTemp=GDMA->CH[ch_num].CFG_HIGH;
if (NewState == ENABLE) {
ValTemp |=BIT_CFGX_UP_FIFO_MODE;
} else {
ValTemp &= (~ BIT_CFGX_UP_FIFO_MODE);
}
GDMA->CH[ch_num].CFG_HIGH=ValTemp;
}
/* Other Definitions -------------------------------------------------------------------*/
#endif //_RTL8710B_GDMA_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_gpio.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the GPIO firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_GPIO_H_
#define _RTL8721D_GPIO_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup GPIO
* @brief GPIO driver modules
* @{
*/
/** @addtogroup GPIO
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* GPIO:
* - Base Address: GPIO
* - Port number: support A/B two ports
* - Pin number: 0 ~ 31(portA), 0 ~ 31(portB)
* - IRQ: GPIO_IRQ
* - portA/B can be configured to interrupt mode
*
*****************************************************************************************
* How to use GPIO in normal mode
*****************************************************************************************
* To use GPIO peripheral in normal mode, the following steps are mandatory:
*
* 1. Enable the GPIO interface clock using
* RCC_PeriphClockCmd(APBPeriph_GPIO, APBPeriph_GPIO_CLOCK, ENABLE);
*
* 2. Fill the GPIO_InitStruct with the desired parameters.
*
* 3. configure GPIO with the configuration(GPIO mode, pull up/down) of step2:
* GPIO_Init(&GPIO_InitStruct)
*
* 4. Read or write GPIO pin according to GPIO out/in mode using
* GPIO_ReadDataBit() or GPIO_WriteBit()
*
*****************************************************************************************
* How to use GPIO in interrupt mode
*****************************************************************************************
* To use GPIO in interrupt mode, the following steps are mandatory:
*
* 1. Enable the GPIO interface clock using
* RCC_PeriphClockCmd(APBPeriph_GPIO, APBPeriph_GPIO_CLOCK, ENABLE);
*
* 2. Fill the GPIO_InitStruct with the desired parameters.
*
* 3. configure GPIO with the configuration(GPIO mode, pull up/down) of step2:
* GPIO_Init(&GPIO_InitStruct)
*
* 4. Register a user interrupt handler:
* GPIO_UserRegIrq
*
* 5. Configure interrupt mode(trigger, polarity, debounce):
* GPIO_INTMode()
*
* 6. Enable the interrupt of a specified pin:
* GPIO_INTConfig()
*
* @note PortA/B can configure interrupt mode.
*
*****************************************************************************************
* How to use GPIO port (multiple GPIO pins)
*****************************************************************************************
* To use GPIO port, the following steps are mandatory:
*
* 1. Enable the GPIO interface clock using
* RCC_PeriphClockCmd(APBPeriph_GPIO, APBPeriph_GPIO_CLOCK, ENABLE);
*
* 2. Configure GPIO data direction(IN/OUT)
* GPIO_PortDirection()
*
* 3. Read or write GPIO pin according to GPIO out/in mode using
* GPIO_PortRead()
* GPIO_PortWrite()
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct {
u32 GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_Mode_parameter_definitions */
u32 GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
This parameter can be a value of @ref GPIO_Pull_parameter_definitions */
u32 GPIO_ITTrigger; /*!< Specifies interrupt mode is level or edge trigger
This parameter can be a value of @ref GPIO_INT_Trigger_parameter_definitions */
u32 GPIO_ITPolarity; /*!< Specifies interrupt mode is high or low active trigger
This parameter can be a value of @ref GPIO_INT_Polarity_parameter_definitions */
u32 GPIO_ITDebounce; /*!< Specifies enable or disable de-bounce for interrupt
This parameter can be a value of @ref GPIO_INT_Debounce_parameter_definitions*/
u32 GPIO_Pin; /*!< Specifies the selected pins.
This parameter contains two parts: Pin: [7:5]: port number; [4:0]: pin number */
} GPIO_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_Mode_parameter_definitions
* @{
*/
#define GPIO_Mode_IN 0x00 /*!< GPIO Input Mode */
#define GPIO_Mode_OUT 0x01 /*!< GPIO Output Mode */
#define GPIO_Mode_INT 0x02 /*!< GPIO Interrupt Mode */
/**
* @}
*/
/** @defgroup GPIO_Pull_parameter_definitions
* @{
*/
#define GPIO_PuPd_NOPULL 0x00 /*!< GPIO Interrnal HIGHZ */
#define GPIO_PuPd_DOWN 0x01 /*!< GPIO Interrnal Pull DOWN */
#define GPIO_PuPd_UP 0x02 /*!< GPIO Interrnal Pull UP */
#define GPIO_PuPd_SHUTDOWN 0x03 /*!< GPIO Interrnal PAD shutdown */
/**
* @}
*/
/** @defgroup GPIO_INT_Trigger_parameter_definitions
* @{
*/
#define GPIO_INT_Trigger_LEVEL 0x0 /*!< This interrupt is level trigger */
#define GPIO_INT_Trigger_EDGE 0x1 /*!< This interrupt is edge trigger */
#define GPIO_INT_Trigger_BOTHEDGE 0x2 /*!< This interrupt is both-edge trigger */
#define IS_GPIOIT_LEVEL_TYPE(TYPE) (((TYPE) == GPIO_INT_Trigger_LEVEL)\
|| ((TYPE) == GPIO_INT_Trigger_EDGE)\
|| ((TYPE) == GPIO_INT_Trigger_BOTHEDGE))
/**
* @}
*/
/** @defgroup GPIO_INT_Polarity_parameter_definitions
* @{
*/
#define GPIO_INT_POLARITY_ACTIVE_LOW 0x0 /*!< Setting interrupt to low active: falling edge or low level */
#define GPIO_INT_POLARITY_ACTIVE_HIGH 0x1 /*!< Setting interrupt to high active: rising edge or high level */
#define IS_GPIOIT_POLARITY_TYPE(TYPE) (((TYPE) == GPIO_INT_POLARITY_ACTIVE_LOW)\
|| ((TYPE) == GPIO_INT_POLARITY_ACTIVE_HIGH))
/**
* @}
*/
/** @defgroup GPIO_INT_Debounce_parameter_definitions
* @{
*/
#define GPIO_INT_DEBOUNCE_DISABLE 0x0 /*!< Disable interrupt debounce */
#define GPIO_INT_DEBOUNCE_ENABLE 0x1 /*!< Enable interrupt debounce */
#define IS_GPIOIT_DEBOUNCE_TYPE(TYPE) (((TYPE) == GPIO_INT_DEBOUNCE_DISABLE)\
|| ((TYPE) == GPIO_INT_DEBOUNCE_ENABLE))
/**
* @}
*/
/** @defgroup GPIO_Pin_State_definitions
* @{
*/
#define GPIO_PIN_LOW 0 /*!< Pin state is low */
#define GPIO_PIN_HIGH 1 /*!< Pin state is high */
/**
* @}
*/
/** @defgroup GPIO_Port_definitions
* @{
*/
#define GPIO_PORT_A 0 /*!< Port number A */
#define GPIO_PORT_B 1 /*!< Port number B */
/**
* @}
*/
/** @defgroup GPIO_IRQ_Event_definitions
* @{
*/
#define HAL_IRQ_NONE 0 /*!< No interrupt event */
#define HAL_IRQ_RISE 1 /*!< Rising edge or high level interrupt event */
#define HAL_IRQ_FALL 2 /*!< Falling edge or low level interrupt event */
/**
* @}
*/
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @{
*/
_LONG_CALL_ void GPIO_WriteBit(u32 GPIO_Pin, u32 BitVal);
_LONG_CALL_ u32 GPIO_ReadDataBit(u32 GPIO_Pin);
_LONG_CALL_ void GPIO_DeInit(u32 GPIO_Pin);
_LONG_CALL_ void GPIO_UserRegIrq(u32 GPIO_Pin, VOID *IrqHandler, VOID *IrqData);
_LONG_CALL_ void GPIO_INTMode(u32 GPIO_Pin, u32 NewState, u32 GPIO_ITTrigger, u32 GPIO_ITPolarity, u32 GPIO_ITDebounce);
_LONG_CALL_ void GPIO_INTConfig(u32 GPIO_Pin, u32 NewState);
_LONG_CALL_ void GPIO_Init(GPIO_InitTypeDef *GPIO_InitStruct);
_LONG_CALL_ u32 GPIO_INTHandler(IN VOID *pData);
_LONG_CALL_ void GPIO_Direction(u32 GPIO_Pin, u32 data_direction);
_LONG_CALL_ u32 GPIO_PortRead(u32 GPIO_Port, u32 GPIO_Mask);
_LONG_CALL_ void GPIO_PortWrite(u32 GPIO_Port, u32 GPIO_Mask, u32 Port_State);
_LONG_CALL_ void GPIO_PortDirection(u32 GPIO_Port, u32 GPIO_Mask, u32 data_direction);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
typedef void (*GPIO_IRQ_FUN)(VOID *Data, u32 Id);
typedef void (*GPIO_USER_IRQ_FUN)(u32 Id);
#endif // end of "#define _RTL8721D_GPIO_H_"
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_i2c.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_I2C_H_
#define _RTL8710B_I2C_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @addtogroup I2C I2C
* @{
*/
/** @addtogroup I2C
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* I2C0:
* - Base Address: I2C0_DEV
* - IPclk: 62.5Mhz
* - Speed: Standard (up to 100 kHz) and Fast (up to 400 kHz) Modes
* - Address: 7/10-bit Address Mode
* - SocPs: SleepMode (clock gating & power gating)
* - Slave: Slave0
* - IRQ: I2C0_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_I2C0_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_I2C0_RX
*
*****************************************************************************************
* How to use Normal I2C
*****************************************************************************************
* To use the normal i2c mode, the following steps are mandatory:
*
* 1. Enable peripheral clock using the follwoing functions.(it is enabled by default)
* RCC_PeriphClockCmd(APBPeriph_I2Cx, APBPeriph_I2Cx_CLOCK, ENABLE);
*
* 2. configure the I2C pinmux.
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_I2C)
*
* 3. Program Role, Address Mode, Speed Mode, I2C CLK, Slave address, Threshold, Feature Supports
* I2C_StructInit()
*
* 4. Init Hardware use step3 parameters:
* I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef* I2C_InitStruct)
*
* 5. Enable the NVIC and the corresponding interrupt using following function if you need
* to use interrupt mode.
* I2C_INTConfig(): I2C IRQ Mask set
* InterruptRegister(): register the i2c irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 6. Enable i2c module using I2C_Cmd().
*
*****************************************************************************************
* How to use i2c in DMA Register mode
*****************************************************************************************
* To use the i2c in DMA mode, the following steps are mandatory:
*
* 1. Enable peripheral clock using the follwoing functions.(it is enabled by default)
* RCC_PeriphClockCmd(APBPeriph_I2Cx, APBPeriph_I2Cx_CLOCK, ENABLE);
*
* 2. configure the I2C pinmux.
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_I2C)
*
* 3. Program Role, Address Mode, Speed Mode, I2C CLK, Slave address, Threshold, Feature Supports
* I2C_StructInit()
*
* 4. Init Hardware use step3 parameters:
* I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef* I2C_InitStruct)
*
* 5. Enable i2c module using I2C_Cmd().
*
* 6. GDMA related configurations(source address/destination address/block size etc.)
* I2C_TXGDMA_Init():Init and Enable I2C TX GDMA
* I2C_RXGDMA_Init():Init and Enable I2C RX GDMA
*
* 7. I2C DMA Mode Register mode set.
* I2C_DmaMode1Config():Configures the I2Cx Control Register DMA mode
*
* 8. Active the I2C TX/RX DMA Request using I2C_DMAControl().
*
*****************************************************************************************
* How to use i2c in Sleep mode
*****************************************************************************************
* To use the i2c in Low Power mode, the following steps are mandatory:
*
* 1. Enable peripheral clock using the follwoing functions.(it is enabled by default)
* RCC_PeriphClockCmd(APBPeriph_I2Cx, APBPeriph_I2Cx_CLOCK, ENABLE);
*
* 2. configure the I2C pinmux.
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_I2C)
*
* 3. Program Role, Address Mode, Speed Mode, I2C CLK, Slave address, Threshold, Feature Supports
* I2C_StructInit()
*
* 4. Init Hardware use step3 parameters:
* I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef* I2C_InitStruct)
*
* 5. Enable the NVIC and the corresponding interrupt using following function if you need
* to use interrupt mode.
* I2C_INTConfig(): I2C IRQ Mask set
* InterruptRegister(): register the i2c irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 6. Enable address matching interrupts for wake up
* I2C_INTConfig(): I2C Addr match IRQ Mask set
* BIT_IC_INTR_MASK_M_ADDR_1_MATCH refer to refer to I2C Slave0 Address Match
*
* 7. Set wake up event using the follwoing functions.
* SOCPS_SetWakeEvent()
*
* 8. Set power ext option BIT_SYSON_PMOPT_SLP_ANACK_EN to Enable ANA clock and
* BIT_SYSON_PMOPT_SLP_ANACK_SEL to select 4M clock for power save mode, then hardware
* will automatically switch to the 4M clock when enter sleep state.
* SOCPS_PWROptionExt()
*
* 9. Clear address matching interrupts after address matching interrupts
* I2C_WakeUp()
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types --------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
/**
* @brief I2C Init structure definition
*/
typedef struct {
u32 I2CIdx; /*!< Specifies the I2C Device Index.
This parameter should be 0 */
u32 I2CMaster; /*!< Specifies the I2C Role.
This parameter can be a value of @ref I2C_Role_definitions */
u32 I2CAddrMod; /*!< Specifies the I2C Addressing Mode.
This parameter can be a value of @ref I2C_Addr_Mode_definitions */
u32 I2CSpdMod; /*!< Specifies the I2C Speed Mode. Now the circuit don't support High Speed Mode.
This parameter can be a value of @ref I2C_Speed_Mode_definitions */
u32 I2CRXTL; /*!< Specifies the I2C RX FIFO Threshold. It controls the level of
entries(or above) that triggers the RX_FULL interrupt.
This parameter must be set to a value in the 0-255 range. A value of 0 sets
the threshold for 1 entry, and a value of 255 sets the threshold for 256 entry*/
u32 I2CTXTL; /*!< Specifies the I2C TX FIFO Threshold.It controls the level of
entries(or below) that triggers the TX_EMPTY interrupt.
This parameter must be set to a value in the 0-255 range. A value of 0 sets
the threshold for 0 entry, and a value of 255 sets the threshold for 255 entry*/
u32 I2CMstReSTR; /*!< Specifies the I2C Restart Support of Master. */
u32 I2CMstGC; /*!< Specifies the I2C General Call Support of Master. */
u32 I2CMstStartB; /*!< Specifies the I2C Start Byte Support of Master. */
u32 I2CSlvNoAck; /*!< Specifies the I2C Slave No Ack Support. */
u32 I2CSlvAckGC; /*!< Specifies the I2C Slave Acks to General Call. */
u32 I2CAckAddr; /*!< Specifies the I2C Target Address in I2C Master Mode or
Ack Address in I2C Slave0 Mode.
This parameter must be set to a value in the 0-127 range if the I2C_ADDR_7BIT
is selected or 0-1023 range if the I2C_ADDR_10BIT is selected. */
u32 I2CSlvSetup; /*!< Specifies the I2C SDA Setup Time. It controls the amount of time delay
introduced in the rising edge of SCL¡ªrelative to SDA changing¡ªby holding SCL low
when I2C Device operating as a slave transmitter, in units of ic_clk period.
This parameter must be set to a value in the 0-255 range. It must be set larger than I2CSdaHd */
u32 I2CSdaHd; /*!< Specifies the I2C SDA Hold Time. It controls the amount of
hold time on the SDA signal after a negative edge of SCL in both master
and slave mode, in units of ic_clk period.
This parameter must be set to a value in the 0-0xFFFF range. */
u32 I2CClk; /*!< Specifies the I2C Bus Clock (in kHz). It is closely related to I2CSpdMod */
u32 I2CIPClk; /*!< Specifies the I2C IP Clock (in Hz). */
u32 I2CFilter; /*!< Specifies the I2C SCL/SDA Spike Filter. */
u32 I2CTxDMARqLv; /*!< Specifies the I2C TX DMA Empty Level. dma_tx_req signal is generated when
the number of valid data entries in the transmit FIFO is equal to or below the DMA
Transmit Data Level Register. The value of DMA Transmit Data Level Register is equal
to this value. This parameter must be set to a value in the 0-31 range. */
u32 I2CRxDMARqLv; /*!< Specifies the I2C RX DMA Full Level. dma_rx_req signal is generated when
the number of valid data entries in the transmit FIFO is equal to or above the DMA
Receive Data Level Register. The value of DMA Receive Data Level Register is equal to
this value+1. This parameter must be set to a value in the 0-31 range. */
u32 I2CDMAMod; /*!< Specifies the I2C DMA Mode.
This parameter can be a value of @ref I2C_DMA_Mode_definitions */
u32 I2CAckAddr1; /*!< Specifies the I2C Ack Address in I2C Slave1 Mode. I2C Slave1 only
support I2C_ADDR_7BIT mode. This parameter must be set to a value in the 0-127 range. */
}I2C_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_Peripheral_definitions
* @{
*/
#define IS_I2C_ALL_PERIPH(PERIPH) ((PERIPH) == I2C0_DEV)
/**
* @}
*/
/** @defgroup I2C_Addr_Mode_definitions
* @{
*/
#define I2C_ADDR_7BIT ((u32)0x00000000)
#define I2C_ADDR_10BIT ((u32)0x00000001)
#define IS_I2C_ADDR_MODE(MODE) (((MODE) == I2C_ADDR_7BIT) || \
((MODE) == I2C_ADDR_10BIT))
/**
* @}
*/
/** @defgroup I2C_Speed_Mode_definitions
* @{
*/
#define I2C_SS_MODE ((u32)0x00000001)
#define I2C_FS_MODE ((u32)0x00000002)
#define I2C_HS_MODE ((u32)0x00000003)
#define IS_I2C_SPEED_MODE(MODE) (((MODE) == I2C_SS_MODE) || \
((MODE) == I2C_FS_MODE) || \
((MODE) == I2C_HS_MODE))
/**
* @}
*/
/** @defgroup I2C_Role_definitions
* @{
*/
#define I2C_SLAVE_MODE ((u32)0x00000000)
#define I2C_MASTER_MODE ((u32)0x00000001)
/**
* @}
*/
/** @defgroup I2C_DMA_Mode_definitions
* @{
*/
#define I2C_DMA_LEGACY ((u32)0x00000000)
#define I2C_DMA_REGISTER ((u32)0x00000001)
#define I2C_DMA_DESCRIPTOR ((u32)0x00000002)
#define IS_I2C_DMA_MODE(MODE) (((MODE) == I2C_DMA_LEGACY) || \
((MODE) == I2C_DMA_REGISTER) || \
((MODE) == I2C_DMA_DESCRIPTOR))
/**
* @}
*/
/** @defgroup I2C_DMA_DATA_LENGTH
* @{
*/
#define IS_I2C_DMA_DATA_LEN(LENGTH) ((LENGTH) <= 0xFFFF)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup I2C_Exported_Functions I2C Exported Functions
* @{
*/
/** @defgroup I2C_Exported_Normal_Functions I2C Exported Normal Functions
* @{
*/
_LONG_CALL_ void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef* I2C_InitStruct);
_LONG_CALL_ void I2C_Cmd(I2C_TypeDef *I2Cx, u8 NewState);
_LONG_CALL_ void I2C_ClearAllINT(I2C_TypeDef *I2Cx);
_LONG_CALL_ u32 I2C_GetRawINT(I2C_TypeDef *I2Cx);
_LONG_CALL_ u32 I2C_GetINT(I2C_TypeDef *I2Cx);
_LONG_CALL_ u8 I2C_CheckFlagState(I2C_TypeDef *I2Cx, u32 I2C_FLAG);
_LONG_CALL_ void I2C_INTConfig(I2C_TypeDef *I2Cx, u32 I2C_IT, u32 NewState);
_LONG_CALL_ void I2C_ClearINT(I2C_TypeDef *I2Cx, u32 INTrAddr);
_LONG_CALL_ void I2C_SetSpeed(I2C_TypeDef *I2Cx, u32 SpdMd, u32 I2Clk, u32 I2CIPClk);
_LONG_CALL_ void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
_LONG_CALL_ u8 I2C_ReceiveData(I2C_TypeDef *I2Cx);
/**
* @}
*/
/** @defgroup I2C_Exported_Master_Functions I2C Exported Master Functions
* @{
*/
_LONG_CALL_ void I2C_MasterSendNullData(I2C_TypeDef *I2Cx, u8* pBuf, u8 I2CCmd, u8 I2CStop, u8 I2CReSTR);
_LONG_CALL_ void I2C_MasterSend(I2C_TypeDef *I2Cx, u8* pBuf, u8 I2CCmd, u8 I2CStop, u8 I2CReSTR);
_LONG_CALL_ void I2C_MasterWrite(I2C_TypeDef *I2Cx, u8* pBuf, u8 len);
_LONG_CALL_ void I2C_MasterReadDW(I2C_TypeDef *I2Cx, u8* pBuf, u8 len);
_LONG_CALL_ u8 I2C_MasterRead(I2C_TypeDef *I2Cx, u8* pBuf, u8 len);
_LONG_CALL_ void I2C_MasterRepeatRead(I2C_TypeDef* I2Cx, u8* pWriteBuf, u8 Writelen, u8* pReadBuf, u8 Readlen);
_LONG_CALL_ void I2C_SetSlaveAddress(I2C_TypeDef *I2Cx, u16 Address);
/**
* @}
*/
/** @defgroup I2C_Exported_Slave_Functions I2C Exported Slave Functions
* @{
*/
_LONG_CALL_ void I2C_SlaveWrite(I2C_TypeDef *I2Cx, u8* pBuf, u8 len);
_LONG_CALL_ void I2C_SlaveRead(I2C_TypeDef *I2Cx, u8* pBuf, u8 len);
_LONG_CALL_ void I2C_SlaveSend(I2C_TypeDef *I2Cx, u8 Data);
/**
* @}
*/
/** @defgroup I2C_Exported_DMA_Functions I2C Exported DMA Functions
* @{
*/
_LONG_CALL_ void I2C_DMAControl(I2C_TypeDef *I2Cx, u32 DmaCtrl, u8 NewState);
_LONG_CALL_ void I2C_DmaMode1Config(I2C_TypeDef *I2Cx, u32 I2C_DmaCmd, u32 I2C_DmaBLen);
_LONG_CALL_ void I2C_DmaMode2Config(I2C_TypeDef *I2Cx, u32 I2C_DmaCmd, u32 I2C_DmaBLen);
_LONG_CALL_ BOOL I2C_TXGDMA_Init(u8 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pTxBuf, int TxCount);
_LONG_CALL_ BOOL I2C_RXGDMA_Init(u8 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pRxBuf, int RxCount);
/**
* @}
*/
/** @defgroup I2C_Exported_PowerSave_Functions I2C Exported PowerSave Functions
* @{
*/
_LONG_CALL_ void I2C_Sleep_Cmd(I2C_TypeDef *I2Cx, u32 NewStatus);
_LONG_CALL_ void I2C_WakeUp(I2C_TypeDef *I2Cx);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup I2C_Register_Definitions I2C Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup IC_CON
* @{
*****************************************************************************/
#define BIT_CTRL_IC_CON_IC_SLAVE_DISABLE_1 ((u32)0x00000001 << 7)
#define BIT_CTRL_IC_CON_IC_SLAVE_DISABLE ((u32)0x00000001 << 6)
#define BIT_CTRL_IC_CON_IC_RESTART_EN ((u32)0x00000001 << 5)
#define BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE ((u32)0x00000001 << 3)
#define BIT_CTRL_IC_CON_SPEED ((u32)0x00000003 << 1)
#define BIT_CTRL_IC_CON_MASTER_MODE ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup IC_TAR
* @{
*****************************************************************************/
#define BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER ((u32)0x00000001 << 12)
#define BIT_CTRL_IC_TAR_SPECIAL ((u32)0x00000001 << 11)
#define BIT_CTRL_IC_TAR_GC_OR_START ((u32)0x00000001 << 10)
#define BIT_CTRL_IC_TAR ((u32)0x000003ff)
/** @} */
/**************************************************************************//**
* @defgroup IC_SAR
* @{
*****************************************************************************/
#define BIT_CTRL_IC_SAR ((u32)0x000003ff)
/** @} */
/**************************************************************************//**
* @defgroup IC_DATA_CMD
* @{
*****************************************************************************/
#define BIT_CTRL_IC_DATA_CMD_NULLDATA ((u32)0x00000001 << 11)
#define BIT_CTRL_IC_DATA_CMD_RESTART ((u32)0x00000001 << 10)
#define BIT_CTRL_IC_DATA_CMD_STOP ((u32)0x00000001 << 9)
#define BIT_CTRL_IC_DATA_CMD_CMD ((u32)0x00000001 << 8)
#define BIT_CTRL_IC_DATA_CMD_DAT ((u32)0x000000ff)
/** @} */
/**************************************************************************//**
* @defgroup IC_INTR_STAT
* @{
*****************************************************************************/
#define BIT_IC_INTR_STAT_R_DMA_I2C_DONE ((u32)0x00000001 << 15)
#define BIT_IC_INTR_STAT_R_ADDR_2_MATCH ((u32)0x00000001 << 13) /* refer to I2C Slave1 Address Match */
#define BIT_IC_INTR_STAT_R_ADDR_1_MATCH ((u32)0x00000001 << 12) /* refer to I2C Slave0 Address Match */
#define BIT_IC_INTR_STAT_R_GEN_CALL ((u32)0x00000001 << 11)
#define BIT_IC_INTR_STAT_R_START_DET ((u32)0x00000001 << 10)
#define BIT_IC_INTR_STAT_R_STOP_DET ((u32)0x00000001 << 9)
#define BIT_IC_INTR_STAT_R_ACTIVITY ((u32)0x00000001 << 8)
#define BIT_IC_INTR_STAT_R_RX_DONE ((u32)0x00000001 << 7)
#define BIT_IC_INTR_STAT_R_TX_ABRT ((u32)0x00000001 << 6)
#define BIT_IC_INTR_STAT_R_RD_REQ ((u32)0x00000001 << 5)
#define BIT_IC_INTR_STAT_R_TX_EMPTY ((u32)0x00000001 << 4)
#define BIT_IC_INTR_STAT_R_TX_OVER ((u32)0x00000001 << 3)
#define BIT_IC_INTR_STAT_R_RX_FULL ((u32)0x00000001 << 2)
#define BIT_IC_INTR_STAT_R_RX_OVER ((u32)0x00000001 << 1)
#define BIT_IC_INTR_STAT_R_RX_UNDER ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup IC_INTR_MASK
* @{
*****************************************************************************/
#define BIT_IC_INTR_MASK_M_DMA_I2C_DONE ((u32)0x00000001 << 15)
#define BIT_IC_INTR_MASK_M_ADDR_2_MATCH ((u32)0x00000001 << 13) /* refer to I2C Slave1 Address Match */
#define BIT_IC_INTR_MASK_M_ADDR_1_MATCH ((u32)0x00000001 << 12) /* refer to I2C Slave0 Address Match */
#define BIT_IC_INTR_MASK_M_GEN_CALL ((u32)0x00000001 << 11)
#define BIT_IC_INTR_MASK_M_START_DET ((u32)0x00000001 << 10)
#define BIT_IC_INTR_MASK_M_STOP_DET ((u32)0x00000001 << 9)
#define BIT_IC_INTR_MASK_M_ACTIVITY ((u32)0x00000001 << 8)
#define BIT_IC_INTR_MASK_M_RX_DONE ((u32)0x00000001 << 7)
#define BIT_IC_INTR_MASK_M_TX_ABRT ((u32)0x00000001 << 6)
#define BIT_IC_INTR_MASK_M_RD_REQ ((u32)0x00000001 << 5)
#define BIT_IC_INTR_MASK_M_TX_EMPTY ((u32)0x00000001 << 4)
#define BIT_IC_INTR_MASK_M_TX_OVER ((u32)0x00000001 << 3)
#define BIT_IC_INTR_MASK_M_RX_FULL ((u32)0x00000001 << 2)
#define BIT_IC_INTR_MASK_M_RX_OVER ((u32)0x00000001 << 1)
#define BIT_IC_INTR_MASK_M_RX_UNDER ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup IC_RAW_INTR_STAT
* @{
*****************************************************************************/
#define BIT_IC_RAW_INTR_STAT_DMA_I2C_DONE ((u32)0x00000001 << 15)
#define BIT_IC_RAW_INTR_STAT_ADDR_2_MATCH ((u32)0x00000001 << 13) /* refer to I2C Slave1 Address Match */
#define BIT_IC_RAW_INTR_STAT_ADDR_1_MATCH ((u32)0x00000001 << 12) /* refer to I2C Slave0 Address Match */
#define BIT_IC_RAW_INTR_STAT_GEN_CALL ((u32)0x00000001 << 11)
#define BIT_IC_RAW_INTR_STAT_START_DET ((u32)0x00000001 << 10)
#define BIT_IC_RAW_INTR_STAT_STOP_DET ((u32)0x00000001 << 9)
#define BIT_IC_RAW_INTR_STAT_ACTIVITY ((u32)0x00000001 << 8)
#define BIT_IC_RAW_INTR_STAT_RX_DONE ((u32)0x00000001 << 7)
#define BIT_IC_RAW_INTR_STAT_TX_ABRT ((u32)0x00000001 << 6)
#define BIT_IC_RAW_INTR_STAT_RD_REQ ((u32)0x00000001 << 5)
#define BIT_IC_RAW_INTR_STAT_TX_EMPTY ((u32)0x00000001 << 4)
#define BIT_IC_RAW_INTR_STAT_TX_OVER ((u32)0x00000001 << 3)
#define BIT_IC_RAW_INTR_STAT_RX_FULL ((u32)0x00000001 << 2)
#define BIT_IC_RAW_INTR_STAT_RX_OVER ((u32)0x00000001 << 1)
#define BIT_IC_RAW_INTR_STAT_RX_UNDER ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup IC_ENABLE
* @{
*****************************************************************************/
#define BIT_CTRL_IC_ENABLE ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup IC_STATUS
* @{
*****************************************************************************/
#define BIT_IC_STATUS_BUS_BUSY ((u32)0x00000001 << 7)
#define BIT_IC_STATUS_SLV_ACTIVITY ((u32)0x00000001 << 6)
#define BIT_IC_STATUS_MST_ACTIVITY ((u32)0x00000001 << 5)
#define BIT_IC_STATUS_RFF ((u32)0x00000001 << 4)
#define BIT_IC_STATUS_RFNE ((u32)0x00000001 << 3)
#define BIT_IC_STATUS_TFE ((u32)0x00000001 << 2)
#define BIT_IC_STATUS_TFNF ((u32)0x00000001 << 1)
#define BIT_IC_STATUS_ACTIVITY ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup IC_SDA_HOLD
* @{
*****************************************************************************/
#define BIT_CTRL_IC_SDA_HOLD ((u32)0x0000ffff)
/** @} */
/**************************************************************************//**
* @defgroup IC_TX_ABRT_SOURCE
* @{
*****************************************************************************/
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX ((u32)0x00000001 << 15)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST ((u32)0x00000001 << 14)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO ((u32)0x00000001 << 13)
#define BIT_IC_TX_ABRT_SOURCE_ARB_LOST ((u32)0x00000001 << 12)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS ((u32)0x00000001 << 11)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT ((u32)0x00000001 << 10)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT ((u32)0x00000001 << 9)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT ((u32)0x00000001 << 8)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET ((u32)0x00000001 << 7)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET ((u32)0x00000001 << 6)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ ((u32)0x00000001 << 5)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK ((u32)0x00000001 << 4)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK ((u32)0x00000001 << 3)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK ((u32)0x00000001 << 2)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK ((u32)0x00000001 << 1)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup IC_SLV_DATA_NACK_ONLY
* @{
*****************************************************************************/
#define BIT_CTRL_IC_SLV_DATA_NACK_ONLY ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup IC_DMA_CR
* @{
*****************************************************************************/
#define BIT_IC_DMA_CR_TDMAE ((u32)0x00000001 << 1)
#define BIT_IC_DMA_CR_RDMAE ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup IC_SDA_SETUP
* @{
*****************************************************************************/
#define BIT_CTRL_IC_SDA_SETUP ((u32)0x000000ff)
/** @} */
/**************************************************************************//**
* @defgroup IC_ACK_GENERAL_CALL
* @{
*****************************************************************************/
#define BIT_CTRL_IC_ACK_GENERAL_CALL ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup IC_DMA_CMD
* @{
*****************************************************************************/
#define BIT_IC_DMA_CMD_RESTART ((u32)0x00000001 << 7)
#define BIT_IC_DMA_CMD_STOP ((u32)0x00000001 << 6)
#define BIT_IC_DMA_CMD_RW ((u32)0x00000001 << 5) /* 0 is write, 1 is read */
#define BIT_IC_DMA_CMD_ENABLE ((u32)0x00000001) /* HW auto clear after transfer done */
/** @} */
/**************************************************************************//**
* @defgroup IC_DMA_MOD
* @{
*****************************************************************************/
#define BIT_IC_DMA_MOD ((u32)0x00000003)
/** @} */
/**************************************************************************//**
* @defgroup IC_SLEEP
* @{
*****************************************************************************/
#define BIT_IC_SLEEP_CLOCK_GATED ((u32)0x00000001 << 1)
#define BIT_IC_SLEEP_CLOCK_CONTROL ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup IC_FILTER
* @{
*****************************************************************************/
#define BIT_IC_FILTER_DIG_FLTR_SEL ((u32)0x00000001 << 8)
#define BIT_CTRL_IC_FILTER_DIG_FLTR_DEG ((u32)0x0000000F)
/** @} */
/**************************************************************************//**
* @defgroup IC_SAR1
* @{
*****************************************************************************/
#define BIT_CTRL_IC_SAR1 ((u32)0x0000007F)
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
//I2C Timing Parameters
#define I2C_SS_MIN_SCL_HTIME 4000 //the unit is ns.
#define I2C_SS_MIN_SCL_LTIME 4700 //the unit is ns.
#define I2C_FS_MIN_SCL_HTIME 600 //the unit is ns.
#define I2C_FS_MIN_SCL_LTIME 1300 //the unit is ns.
#define I2C_HS_MIN_SCL_HTIME_100 60 //the unit is ns, with bus loading = 100pf
#define I2C_HS_MIN_SCL_LTIME_100 120 //the unit is ns., with bus loading = 100pf
#define I2C_HS_MIN_SCL_HTIME_400 160 //the unit is ns, with bus loading = 400pf
#define I2C_HS_MIN_SCL_LTIME_400 320 //the unit is ns., with bus loading = 400pf
typedef struct
{
I2C_TypeDef* I2Cx;
u32 Tx_HandshakeInterface;
u32 Rx_HandshakeInterface;
IRQn_Type IrqNum;
} I2C_DevTable;
extern const I2C_DevTable I2C_DEV_TABLE[1];
extern u32 I2C_SLAVEWRITE_PATCH;
extern u32 IC_FS_SCL_HCNT_TRIM;
extern u32 IC_FS_SCL_LCNT_TRIM;
#endif
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_i2s.h
* @author
* @version V1.0.0
* @date 2017-11-03
* @brief This file contains all the functions prototypes for the I2S firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_I2S_H_
#define _RTL8721D_I2S_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup I2S
* @brief I2S driver modules
* @{
*/
/** @addtogroup I2S
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* I2S:
* - Base Address: I2S_DEV
* - Source clk: 45.1584MHz or 98.304MHz(default)
* - Sample rate: 8K, 12K, 16K, 24K, 32K, 48K, 64K, 96K, 192K, 384K
* 7.35K, 11.025K, 14.7K, 22.05K, 29.4K, 44.1K, 58.8K, 88.2K, 176.4K
* - Sample bit: 16 bit, 24 bit, 32bit
* - Page num & page size: Max page_num=4, Max page_size=16K byte
* - IRQ: I2S0_PCM0_IRQ
* - FIFO: 64 * 32bit
* - Burst size: 4/8/12/16 dword
*
*****************************************************************************************
* How to use I2S
*****************************************************************************************
* To use I2S peripheral, the following steps are mandatory:
*
* 1. Enable Lx bus clock:
* RCC_PeriphClockCmd(APBPeriph_LXBUS, APBPeriph_LXBUS_CLOCK, ENABLE);
*
* 2. Enable PLL clock:
* PLL_I2S_Set(ENABLE);
* PLL_PCM_Set(ENABLE);
*
* 3. Enable the I2S interface clock and function using
* RCC_PeriphClockCmd(APBPeriph_I2S0, APBPeriph_I2S0_CLOCK, ENABLE);
*
* 4. I2S pinmux:
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_I2S).
*
* 5. Fill the I2S_InitStruct with the desired parameters.
*
* 6. configure I2S with the corresponding configuration.
* I2S_Init(I2S_DEV, &I2S_Adapter.I2SInitStruct)
*
* 7. Activate the I2S peripheral:
* I2S_Cmd(I2S_DEV, ENABLE).
*
* 8. Configure interrupts:
* I2S_INTConfig()
*
* @note All other functions can be used separately to modify, if needed,
* a specific feature of the I2S
*****************************************************************************************
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2S_Exported_Types I2S Exported Types
* @{
*/
/**
* @brief I2S Init structure definition
*/
typedef struct {
u32 I2S_SlaveMode; /*!< Specifies the I2S operating mode
This parameter can be a value of @ref I2S_device_mode */
u32 I2S_WordLen; /*!< Specifies the I2S word length
This parameter can be a value of @ref I2S_word_length */
u32 I2S_Justify; /*!< Specifies the I2S digital interface format
This parameter can be a value of @ref I2S_format */
u32 I2S_EndianSwap; /*!< Specifies the I2S endian mode
This parameter can be a value of @ref I2S_endian_swap */
u32 I2S_ChNum; /*!< Specifies the I2S channel number
This parameter can be a value of @ref I2S_channel_number */
u32 I2S_PageNum; /*!< Specifies the I2S page number
This parameter must be set to a value in the 2~4 range */
u32 I2S_PageSize; /*!< Specifies the I2S page size
This parameter must be set to a value in the 1~4096 Word range */
u32 I2S_Rate; /*!< Specifies the I2S sample rate
This parameter can be a value of @ref I2S_sample_rate */
u32 I2S_TRxAct; /*!< Specifies the I2S transfer direction
This parameter can be a value of @ref I2S_direction */
u32 I2S_InterLoopback;/*!< Specifies the I2S internal/external loopback
This parameter must be set to a value 0(external) or 1(internal) */
u32 I2S_Mute; /*!< Specifies the I2S mute function
This parameter can be a value of @ref I2S_mute */
u32 I2S_BurstSize; /*!< Specifies the I2S DMA burst size
This parameter can be a value of @ref I2S_burst_size */
u32 I2S_SckSwap; /*!< Specifies the I2S SCK invert
This parameter can be a value of @ref I2S_sck_swap */
u32 I2S_WsSwap; /*!< Specifies whether DAC appears in right or left phase of WS clock.
This parameter can be a value of @ref I2S_ws_swap */
u32 I2S_EdgeSwap; /*!< Specifies I2S edge swap, data is latched on SCK negative(falling) or positive(rising) edge.
This parameter can be a value of @ref I2S_edge_sw */
} I2S_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2S_Exported_Constants I2S Exported Constants
* @{
*/
/** @defgroup I2S_device_mode I2S Device Mode
* @{
*/
#define I2S_MASTER_MODE ((u32)0x00000000)
#define I2S_SLAVE_MODE ((u32)0x00000001)
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MASTER_MODE) || \
((MODE) == I2S_SLAVE_MODE))
/**
* @}
*/
/** @defgroup I2S_word_length I2S Word Length
* @{
*/
#define I2S_WL_16 ((u32)0x00000000)
#define I2S_WL_24 ((u32)0x00000001)
#define I2S_WL_32 ((u32)0x00000002)
#define IS_I2S_WORD_LEN(LEN) (((LEN) == I2S_WL_16) || \
((LEN) == I2S_WL_24) || \
((LEN) == I2S_WL_32))
/**
* @}
*/
/** @defgroup I2S_format I2S Interface Format
* @{
*/
#define I2S_JY_I2S ((u32)0x00000000)
#define I2S_JY_LEFT ((u32)0x00000001)
#define I2S_JY_RIGHT ((u32)0x00000002)
#define IS_I2S_JUSTIFY(FORMAT) (((FORMAT) == I2S_JY_I2S) || \
((FORMAT) == I2S_JY_LEFT) || \
((FORMAT) == I2S_JY_RIGHT))
/**
* @}
*/
/** @defgroup I2S_endian_swap I2S Endian Swap
* @{
*/
#define I2S_ES_BIG ((u32)0x00000000)
#define I2S_ES_LITTLE ((u32)0x00000001)
#define IS_I2S_ENDIAN_SWAP(SWAP) (((SWAP) == I2S_ES_LITTLE) || \
((SWAP) == I2S_ES_BIG))
/**
* @}
*/
/** @defgroup I2S_direction I2S Bus Direction(Transmit/Receive)
* @{
*/
#define I2S_ONLY_RX ((u32)0x00000000)
#define I2S_ONLY_TX ((u32)0x00000001)
#define I2S_TXRX ((u32)0x00000002)
#define IS_I2S_DIR(DIR) (((DIR) == I2S_ONLY_RX) || \
((DIR) == I2S_ONLY_TX) || \
((DIR) == I2S_TXRX))
/**
* @}
*/
/** @defgroup I2S_channel_number I2S Channel Number
* @{
*/
#define I2S_CH_STEREO ((u32)0x00000000)
#define I2S_CH_5p1 ((u32)0x00000001)
#define I2S_CH_MONO ((u32)0x00000002)
#define IS_I2S_CHN_NUM(NUM) (((NUM) == I2S_CH_STEREO) || \
((NUM) == I2S_CH_5p1) || \
((NUM) == I2S_CH_MONO))
/**
* @}
*/
/** @defgroup I2S_mute I2S Mute Function
* @{
*/
#define I2S_UNMUTE ((u32)0x00000000)
#define I2S_MUTE ((u32)0x00000001)
#define IS_I2S_MUTE(MUTE) (((MUTE) == I2S_UNMUTE) || \
((MUTE) == I2S_MUTE))
/**
* @}
*/
/** @defgroup I2S_burst_size I2S Burst Size
* @{
*/
#define I2S_BURST_4 ((u32)0x00000003)
#define I2S_BURST_8 ((u32)0x00000007)
#define I2S_BURST_12 ((u32)0x0000000B)
#define I2S_BURST_16 ((u32)0x0000000F)
#define IS_I2S_BST_NUM(NUM) (((NUM) == I2S_BURST_4) || \
((NUM) == I2S_BURST_8) || \
((NUM) == I2S_BURST_12) || \
((NUM) == I2S_BURST_16))
/**
* @}
*/
/** @defgroup I2S_sck_swap I2S SCK Invert
* @{
*/
#define I2S_SCK_NOINV ((u32)0x00000000)
#define I2S_SCK_INV ((u32)0x00000001)
#define IS_I2S_SCK_SWAP(SWAP) (((SWAP) == I2S_SCK_NOINV) || \
((SWAP) == I2S_SCK_INV))
/**
* @}
*/
/** @defgroup I2S_ws_swap I2S WS Swap
* @{
*/
#define I2S_WS_LEFT_PHA ((u32)0x00000000)
#define I2S_WS_RIGHT_PHA ((u32)0x00000001)
#define IS_I2S_WS_SWAP(SWAP) (((SWAP) == I2S_WS_LEFT_PHA) || \
((SWAP) == I2S_WS_RIGHT_PHA))
/**
* @}
*/
/** @defgroup I2S_edge_sw I2S Edge Swap
* @{
*/
#define I2S_NEGATIVE_EDGE ((u32)0x00000000)
#define I2S_POSITIVE_EDGE ((u32)0x00000001)
#define IS_I2S_EDGE_SWAP(SWAP) (((SWAP) == I2S_NEGATIVE_EDGE) || \
((SWAP) == I2S_POSITIVE_EDGE))
/**
* @}
*/
/** @defgroup I2S_sample_rate I2S Sample Rate
* @{
*/
#define I2S_SR_8KHZ ((u32)0x00000000)
#define I2S_SR_12KHZ ((u32)0x00000001)
#define I2S_SR_16KHZ ((u32)0x00000002)
#define I2S_SR_24KHZ ((u32)0x00000003)
#define I2S_SR_32KHZ ((u32)0x00000004)
#define I2S_SR_48KHZ ((u32)0x00000005)
#define I2S_SR_64KHZ ((u32)0x00000006)
#define I2S_SR_96KHZ ((u32)0x00000007)
#define I2S_SR_192KHZ ((u32)0x00000008)
#define I2S_SR_384KHZ ((u32)0x00000009)
#define I2S_SR_7p35KHZ ((u32)0x00000010)
#define I2S_SR_11p025KHZ ((u32)0x00000011)
#define I2S_SR_14p7KHZ ((u32)0x00000012)
#define I2S_SR_22p05KHZ ((u32)0x00000013)
#define I2S_SR_29p4KHZ ((u32)0x00000014)
#define I2S_SR_44p1KHZ ((u32)0x00000015)
#define I2S_SR_58p8KHZ ((u32)0x00000016)
#define I2S_SR_88p2KHZ ((u32)0x00000017)
#define I2S_SR_176p4KHZ ((u32)0x00000018)
#define IS_I2S_SAMPLE_RATE(RATE) (((RATE) == I2S_SR_8KHZ) || \
((RATE) == I2S_SR_12KHZ) || \
((RATE) == I2S_SR_16KHZ) || \
((RATE) == I2S_SR_24KHZ) || \
((RATE) == I2S_SR_32KHZ) || \
((RATE) == I2S_SR_48KHZ) || \
((RATE) == I2S_SR_64KHZ) || \
((RATE) == I2S_SR_96KHZ) || \
((RATE) == I2S_SR_192KHZ) || \
((RATE) == I2S_SR_384KHZ) || \
((RATE) == I2S_SR_7p35KHZ) || \
((RATE) == I2S_SR_11p025KHZ) || \
((RATE) == I2S_SR_14p7KHZ) || \
((RATE) == I2S_SR_22p05KHZ) || \
((RATE) == I2S_SR_29p4KHZ) || \
((RATE) == I2S_SR_44p1KHZ) || \
((RATE) == I2S_SR_58p8KHZ) || \
((RATE) == I2S_SR_88p2KHZ) || \
((RATE) == I2S_SR_176p4KHZ))
/**
* @}
*/
/**
* @}
*/
/* Exported Functions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup I2S_Exported_Functions I2S Exported Functions
* @{
*****************************************************************************/
_LONG_CALL_ void I2S_Init(I2S_TypeDef* I2Sx, I2S_InitTypeDef* I2S_InitStruct);
_LONG_CALL_ void I2S_Cmd(I2S_TypeDef* I2Sx, u8 NewState);
_LONG_CALL_ void I2S_INTConfig(I2S_TypeDef* I2Sx, u32 I2STxIntrMSK, u32 I2SRxIntrMSK);
_LONG_CALL_ void I2S_SetRate(I2S_TypeDef* I2Sx, u32 I2S_Rate);
_LONG_CALL_ u32 I2S_GetVersion(I2S_TypeDef* I2Sx);
_LONG_CALL_ void I2S_SetMute(I2S_TypeDef* I2Sx, u32 NewState);
_LONG_CALL_ void I2S_SetBurstSize(I2S_TypeDef* I2Sx, u32 I2S_BurstSize);
_LONG_CALL_ void I2S_SetWordLen(I2S_TypeDef* I2Sx, u32 I2S_WordLen);
_LONG_CALL_ void I2S_SetChNum(I2S_TypeDef* I2Sx, u32 I2S_ChNum);
_LONG_CALL_ void I2S_SetPageNum(I2S_TypeDef* I2Sx, u32 I2S_PageNum);
_LONG_CALL_ void I2S_SetPageSize(I2S_TypeDef* I2Sx, u32 I2S_PageSize);
_LONG_CALL_ void I2S_SetDirection(I2S_TypeDef* I2Sx, u32 I2S_TRxAct);
_LONG_CALL_ void I2S_INTClear(I2S_TypeDef* I2Sx, u32 I2STxIntrClr, u32 I2SRxIntrClr);
_LONG_CALL_ void I2S_INTClearAll(I2S_TypeDef* I2Sx);
_LONG_CALL_ void I2S_ISRGet(I2S_TypeDef* I2Sx, u32* I2STxIsr, u32* I2SRxIsr);
_LONG_CALL_ void I2S_SetDMABuf(I2S_TypeDef* I2Sx, u8 *I2STxData, u8 *I2SRxData);
_LONG_CALL_ u32 I2S_GetTxPage(I2S_TypeDef* I2Sx);
_LONG_CALL_ void I2S_TxPageDMA_EN(I2S_TypeDef* I2Sx, u32 I2STxIdx);
_LONG_CALL_ void I2S_RxPageDMA_EN(I2S_TypeDef* I2Sx, u32 I2SRxIdx);
_LONG_CALL_ void I2S_TxDmaCmd(I2S_TypeDef* I2Sx, u32 NewState);
_LONG_CALL_ void I2S_RxDmaCmd(I2S_TypeDef* I2Sx, u32 NewState);
_LONG_CALL_ u32 I2S_TxPageBusy( I2S_TypeDef* I2Sx, u32 page_index);
_LONG_CALL_ void I2S_SetRxPageAddr( u32 page_index, u32 page_address);
_LONG_CALL_ void I2S_SetTxPageAddr( u32 page_index, u32 page_address);
_LONG_CALL_ void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
_LONG_CALL_ u32 I2S_GetTxPageAddr( u32 page_index);
_LONG_CALL_ u32 I2S_GetRxPageAddr( u32 page_index);
_LONG_CALL_ u32 I2S_GetRxPage( I2S_TypeDef* I2Sx);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup I2S_Register_Definitions I2S Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup I2S_CONTROL
* @{
*****************************************************************************/
#define BIT_CTRL_CTLX_I2S_EN ((u32)0x00000001 << 0)
#define BIT_CTRL_CTLX_I2S_TX_ACT_MASK ((u32)0x00000003 << 1)
#define BIT_CTRL_CTLX_I2S_CHN_NUM_MASK ((u32)0x00000003 << 3)
#define BIT_CTRL_CTLX_I2S_INTERNAL ((u32)0x00000001 << 7)
#define BIT_CTRL_CTLX_I2S_ENDIAN_SWAP ((u32)0x00000001 << 12)
#define BIT_CTRL_CTLX_I2S_BURST_SIZE_MASK ((u32)0x0000001F << 18)
#define BIT_CTRL_CTLX_I2S_MUTE ((u32)0x00000001 << 27)
#define BIT_CTRL_CTLX_I2S_WORD_LEN_MASK ((u32)0x00000003 << 29)
#define BIT_CTRL_CTLX_I2S_SW_RSTN ((u32)0x00000001 << 31)
/** @} */
/**************************************************************************//**
* @defgroup I2S_SETTING
* @{
*****************************************************************************/
#define BIT_SETTING_I2S_PAGE_SIZE_MASK ((u32)0x00000FFF)
#define BIT_SETTING_I2S_PAGE_NUM_MASK ((u32)0x00000003 << 12)
#define BIT_SETTING_I2S_RATE_MASK ((u32)0x0000000F << 14)
#define BIT_CTRL_CTLX_I2S_CLK_SRC ((u32)0x00000001 << 18)
/** @} */
/**************************************************************************//**
* @defgroup I2S_TX_INT_MASK_STATUS
* @{
*****************************************************************************/
#define I2S_TX_INT_PAGE0_OK ((u32)0x00000001 << 0)
#define I2S_TX_INT_PAGE1_OK ((u32)0x00000001 << 1)
#define I2S_TX_INT_PAGE2_OK ((u32)0x00000001 << 2)
#define I2S_TX_INT_PAGE3_OK ((u32)0x00000001 << 3)
#define I2S_TX_INT_PAGE0_UNAVA ((u32)0x00000001 << 4)
#define I2S_TX_INT_PAGE1_UNAVA ((u32)0x00000001 << 5)
#define I2S_TX_INT_PAGE2_UNAVA ((u32)0x00000001 << 6)
#define I2S_TX_INT_PAGE3_UNAVA ((u32)0x00000001 << 7)
#define I2S_TX_INT_EMPTY ((u32)0x00000001 << 8)
/** @} */
/**************************************************************************//**
* @defgroup I2S_RX_INT_MASK_STATUS
* @{
*****************************************************************************/
#define I2S_RX_INT_PAGE0_OK ((u32)0x00000001 << 0)
#define I2S_RX_INT_PAGE1_OK ((u32)0x00000001 << 1)
#define I2S_RX_INT_PAGE2_OK ((u32)0x00000001 << 2)
#define I2S_RX_INT_PAGE3_OK ((u32)0x00000001 << 3)
#define I2S_RX_INT_PAGE0_UNAVA ((u32)0x00000001 << 4)
#define I2S_RX_INT_PAGE1_UNAVA ((u32)0x00000001 << 5)
#define I2S_RX_INT_PAGE2_UNAVA ((u32)0x00000001 << 6)
#define I2S_RX_INT_PAGE3_UNAVA ((u32)0x00000001 << 7)
#define I2S_RX_INT_FULL ((u32)0x00000001 << 8)
/** @} */
/**************************************************************************//**
* @defgroup I2S_PAGE_OWN
* @{
*****************************************************************************/
#define BIT_IS_PAGE_OWN ((u32)0x80000000)
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
#endif /* _RTL8721D_I2S_H_ */
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8710b_inic.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the USB & SDIO INIC firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_INIC_H_
#define _RTL8721D_INIC_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup INIC
* @brief INIC driver modules
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup INIC_Exported_Types INIC Exported Types
* @{
*/
/**
* @brief INIC TX DESC structure definition
* @note: Ameba1 is 6 dword, but AmebaZ is 4 dwords
*/
typedef struct {
/* u4Byte 0 */
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(INIC_TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
/* u4Byte 1 */
u32 type:8; // bit[7:0], the packet type
u32 data:8; // bit[8:15], the value to be written to the memory
u32 reply:1; // bit[16], request to send a reply message
u32 rsvd0:15;
/* u4Byte 2 */
u32 start_addr; // 1) memory write/read start address 2) RAM start_function address
/* u4Byte 3 */
u32 data_len:16; // bit[15:0], the length to write/read
u32 rsvd2:16; // bit[31:16]
} INIC_TX_DESC, *PINIC_TX_DESC;
/**
* @brief INIC RX DESC structure definition
* @note: Ameba1 is 6 dword, but AmebaZ is 4 dwords
*/
typedef struct {
/* u4Byte 0 */
u32 pkt_len:16; // bit[15:0], the packet size
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 rsvd0:6; // bit[29:24]
u32 icv:1; //icv error
u32 crc:1; // crc error
/* u4Byte 1 */
/************************************************/
/*****************receive packet type*********************/
/* 0x82: 802.3 packet */
/* 0x80: 802.11 packet */
/* 0x10: C2H command */
/* 0x50: Memory Read */
/* 0x52: Memory Write */
/* 0x54: Memory Set */
/* 0x60: Indicate the firmware is started */
u32 type:8; // bit[7:0], the type of this packet
u32 rsvd1:24; // bit[31:8]
/* u4Byte 2 */
u32 start_addr;
/* u4Byte 3 */
u32 data_len:16; // bit[15:0], the type of this packet
u32 result:8; // bit[23:16], the result of memory write command
u32 rsvd2:8; // bit[31:24]
} INIC_RX_DESC, *PINIC_RX_DESC;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup INIC_Exported_Constants INIC Exported Constants
* @{
*/
/** @defgroup INIC_packet_type_definitions
* @{
*/
#define TX_PACKET_802_3 (0x83)
#define TX_PACKET_802_11 (0x81)
#define TX_H2C_CMD (0x11)
#define TX_MEM_READ (0x51)
#define TX_MEM_WRITE (0x53)
#define TX_MEM_SET (0x55)
#define TX_FM_FREETOGO (0x61)
#define TX_PACKET_USER (0x41)
#define TX_REG_WRITE (0xE3)
#define TX_FLASH_READ (0xF1)
#define TX_FLASH_WRITE (0xF3)
#define TX_FLASH_SECERASE (0xF5)
#define TX_FLASH_CHECKSUM (0xF7)
#define RX_PACKET_802_3 (0x82)
#define RX_PACKET_802_11 (0x80)
#define RX_C2H_CMD (0x10)
#define RX_MEM_READ (0x50)
#define RX_MEM_WRITE (0x52)
#define RX_MEM_SET (0x54)
#define RX_FM_FREETOGO (0x60)
#define RX_PACKET_USER (0x40)
#define RX_REG_WRITE (0xE4)
#define RX_FLASH_READ (0xF2)
#define RX_FLASH_WRITE (0xF4)
#define RX_FLASH_SECERASE (0xF6)
#define RX_FLASH_CHECKSUM (0xF8)
/**
* @}
*/
/** @defgroup INIC_DESC_Size_definitions
* @{
*/
#define SIZE_RX_DESC (sizeof(INIC_RX_DESC))
#define SIZE_TX_DESC (sizeof(INIC_TX_DESC))
/**
* @}
*/
/**
* @}
*/
/** @defgroup INIC_Exported_Functions INIC Exported Functions
* @{
*/
//_LONG_CALL_
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif //_RTL8710B_INIC_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_ipc.h
* @author
* @version V1.0.0
* @date 2017-11-06
* @brief This file contains all the functions prototypes for the Internal Processor Communication(IPC)
*
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_IPC_H_
#define _RTL8721D_IPC_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup IPC
* @brief IPC driver modules
* @{
*/
/** @addtogroup IPC
* @verbatim
*****************************************************************************************
* Internal Processor Communication(IPC) Introduction
*****************************************************************************************
* -32 core-to-core interrupts.
* -16 hardware semephone.
* -CPU ID get.
*****************************************************************************************
* @endverbatim
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IPC_Exported_Functions IPC Exported Functions
* @{
*/
void IPC_INTConfig(IPC_TypeDef *IPCx, u8 IPC_ChNum, u32 NewState);
void IPC_IERSet(IPC_TypeDef *IPCx, u32 IPC_Chs);
u32 IPC_IERGet(IPC_TypeDef *IPCx);
void IPC_INTRequest(IPC_TypeDef *IPCx, u8 IPC_ChNum);
void IPC_INTClear(IPC_TypeDef *IPCx, u8 IPC_ChNum);
u32 IPC_INTGet(IPC_TypeDef *IPCx);
u32 IPC_CPUID(void);
u32 IPC_INTHandler(void *Data);
void IPC_INTUserHandler(u8 IPC_ChNum, VOID *IrqHandler, VOID *IrqData);
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IPC_Exported_Constants IPC Exported Constants
* @{
*/
/* Channel Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup IPC_Channel_Definitions IPC Channel Definitions
* @{
*****************************************************************************/
#define IPC_INT_CHAN_SHELL_SWITCH 0 /*!< KM0 <--> KM4 Switch shell */
#define IPC_INT_CHAN_WIFI_FW 1 /*!< KM0 <-- KM4 FW INFO*/
#define IPC_INT_CHAN_FLASHPG_REQ 2 /*!< KM0 <--> KM4 Flash Program REQUEST*/
#define IPC_INT_KM4_TICKLESS_INDICATION 3 /*!< KM0 <-- KM4 tickless indicate */
/** @} */
/**************************************************************************//**
* @defgroup IPC0_USER_BUF_Definitions LP IPC User IDX Definitions
* @{
*****************************************************************************/
#define IPC_USER_BUF_LOG_RP 7 /*!< logbuf write pointer */
#define IPC_USER_BUF_LOG_WP 8 /*!< logbuf read pointer */
/** @} */
/**************************************************************************//**
* @defgroup IPC_SEM_IDX_Definitions LP IPC SEM IDX Definitions
* @{
*****************************************************************************/
#define IPC_SEM_INDEX_LOG 0 /*!< KM0 <-- KM4 log print */
/** @} */
/**
* @}
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup IPC_Exported_Constants IPC Exported Types
* @{
*/
/* Other definations --------------------------------------------------------*/
typedef void (*IPC_IRQ_FUN)(VOID *Data, u32 IrqStatus, u32 ChanNum);
typedef enum
{
IPC_USER_POINT = 0,
IPC_USER_DATA = 1
} USER_MSG_TYP_DEF;
typedef struct _IPC_INIT_TABLE_ {
u32 USER_MSG_TYPE;
void (*func)(VOID *Data, u32 IrqStatus, u32 ChanNum);
VOID *IrqData;
}IPC_INIT_TABLE, *PIPC_INIT_TABLE;
extern const IPC_INIT_TABLE ipc_init_config[];
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_ipc_api.h
* @author
* @version V1.0.0
* @date 2018-06-11
* @brief This file contains all the functions prototypes for the IPC API function
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_IPC_API_H
#define _RTL8721D_IPC_API_H
void ipc_table_init(VOID);
void ipc_send_message(u8 IPC_ChNum, u32 Message);
u32 ipc_get_message(u8 IPC_ChNum);
#endif
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_ir.h
* @author
* @version V1.0.0
* @date 2017-09-18
* @brief This file contains all the functions prototypes for the IR firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_IR_H_
#define _RTL8721D_IR_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup IR
* @{
*/
/** @addtogroup IR
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* IR:
* - Base Address: IR_DEV
* - IPclk: SCLK, normally is 100MHz
* - carrier clock: 25k~500k
* - work mode: Half Duplex
* - SocPs: SleepMode not support
* - accuracy:3%
* - IRQ: IR_IRQ
* - GDMA support: not support
*
*****************************************************************************************
* PINMUX
*****************************************************************************************
*/
//1TODO: -to be define:derek
/*
*****************************************************************************************
* How to use IR TX
*****************************************************************************************
* To use the IR tx function, the following steps are mandatory:
*
* 1. Enable peripheral clock and power:
* RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
*
* 2. Configure the IR pinmux
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_IR)
*
* 3. Set parameters, change some parameter if needed
* void IR_StructInit(IR_InitTypeDef *IR_InitStruct)
*
* 4. Init hardware use step3 parameters.
* void IR_Init(IR_InitTypeDef *IR_InitStruct)
*
* 5. Enable IRQ using following function if needed
* IR_INTConfig(): IR IRQ Enable set
* InterruptRegister(): register the IR irq handler
*
* 6. Send TX data to FIFO
*
*****************************************************************************************
* How to use IR RX
*****************************************************************************************
* To use the IR rx function, the following steps are mandatory:
*
* 1. Enable peripheral clock and power:
* RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
*
* 2. Configure the IR pinmux
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_IR)
*
* 3. Set parameters, change some parameter if needed
* void IR_StructInit(IR_InitTypeDef *IR_InitStruct)
*
* 4. Init hardware use step3 parameters.
* void IR_Init(IR_InitTypeDef *IR_InitStruct)
*
* 5. Enable IRQ using following function if needed
* IR_INTConfig(): IR IRQ Enable set
* InterruptRegister(): register the IR irq handler
*
* 6. Recieve Data from Rx fifo
* @endverbatim
*/
/*============================================================================*
* Types
*============================================================================*/
/** @defgroup IR_Exported_Types IR Exported Types
* @{
*/
/**
* @brief IR initialize parameters
*
* IR initialize parameters
*/
typedef struct
{
u32 IR_Clock; /*!< Specifies the IR IP core Input clock. */
u32 IR_Freq; /*!< Specifies the clock frequency. This parameter is IR carrier freqency whose unit is Hz.
This parameter can be a value of @ref IR_Frequency */
u32 IR_DutyCycle; /*!< Specifies the IR duty cycle. */
u32 IR_Mode; /*!< Specifies the IR mode.
This parameter can be a value of @ref IR_Mode */
u32 IR_TxIdleLevel; /*!< Specifies the IR output level in Tx mode
This parameter can be a value of @ref IR_Idle_Status */
u32 IR_TxInverse; /*!< Specifies inverse FIFO data or not in TX mode
This parameter can be a value of @ref IR_TX_Data_LEVEL */
u32 IR_TxFIFOThrLevel; /*!< Specifies TX FIFO interrupt threshold in TX mode. When TX FIFO depth <= threshold value, trigger interrupt.
This parameter can be a value of @ref IR_Tx_Threshold */
u32 IR_TxCOMP_CLK; /*!< Specifies TX compensation clk. This CLK used when @ref IR_Tx_DATA_TYPE = IR_TX_CLK_Self_Def.*/
u32 IR_RxStartMode; /*!< Specifies Start mode in RX mode
This parameter can be a value of @ref IR_Rx_Start_Mode */
u32 IR_RxFIFOThrLevel; /*!< Specifies RX FIFO interrupt threshold in RX mode. when RX FIFO depth > threshold value, trigger interrupt.
This parameter can be a value of @ref IR_Rx_Threshold */
u32 IR_RxFIFOFullCtrl; /*!< Specifies data discard mode in RX mode when RX FIFO is full and receiving new data
This parameter can be a value of @ref IR_RX_FIFO_DISCARD_SETTING */
u32 IR_RxTriggerMode; /*!< Specifies trigger in RX mode
This parameter can be a value of @ref IR_RX_Trigger_Mode */
u32 IR_RxFilterTime; /*!< Specifies filter time in RX mode
This parameter can be a value of @ref IR_RX_Filter_Time */
u32 IR_RxCntThrType; /*!< Specifies counter level type when trigger IR_INT_RX_CNT_THR interrupt in RX mode
This parameter can be a value of @ref IR_RX_COUNTER_THRESHOLD_TYPE */
u32 IR_RxCntThr; /*!< Specifies counter threshold value when trigger IR_INT_RX_CNT_THR interrupt in RX mode */
} IR_InitTypeDef, *PIR_InitTypeDef;
/** End of group IR_Exported_Types
* @}
*/
/*============================================================================*
* Constants
*============================================================================*/
/** @defgroup IR_Exported_Constants IR Exported Constants
* @{
*/
/** @defgroup IR_Peripheral_definitions
* @{
*/
#define IS_IR_ALL_PERIPH(PERIPH) ((PERIPH) == IR_DEV)
/**
* @}
*/
/** @defgroup IR_Frequency IR Frequency
* @{
*/
#define IS_IR_FREQUENCY(F) (((F) >= 5000) && ((F) <= 500000))
/**
* @}
*/
/** @defgroup IR_TRXFIFO
* @{
*/
#define IR_TX_FIFO_SIZE 32
#define IR_RX_FIFO_SIZE 32
/**
* @}
*/
/** @defgroup IR_Mode IR Mode
* @{
*/
#define IR_MODE_TX (0x00000000U << 31)
#define IR_MODE_RX (0x00000001U << 31)
#define IR_MODE(MODE) ((MODE) & (0x00000001U << 31))
#define IS_IR_MODE(MODE) (((MODE) == IR_MODE_TX) || ((MODE) == IR_MODE_RX))
/**
* @}
*/
/** @defgroup IR_TX_Data_LEVEL IR TX Data Level
* @{
*/
#define IR_TX_DATA_NORMAL (0x00000000 << 14)
#define IR_TX_DATA_INVERSE (0x00000001 << 14)
#define IR_TX_DATA_CARRIER_NORMAL (0x00000000 << 13)
#define IR_TX_DATA_CARRIER_INVERSE (0x00000001 << 13)
#define IR_TX_DATA_LEVEL_MASK (IR_TX_DATA_INVERSE|IR_TX_DATA_CARRIER_INVERSE)
#define IS_IR_TX_DATA_TYPE(TYPE) (((TYPE) & (~IR_TX_DATA_LEVEL_MASK)) == 0)
/** End of group IR_TX_Data_LEVEL
* @}
*/
/** @defgroup IR_Tx_Threshold IR TX Threshold
* @{
*/
#define IR_TX_FIFO_THRESHOLD(THD) ((THD) << 8)
#define IS_IR_TX_FIFO_THRESHOLD(THD) ((THD) <= IR_TX_FIFO_SIZE)
#define IR_TX_FIFO_THRESHOLD_MASK ((0x0000001f) << 8)
/** End of group IR_Tx_Threshold
* @}
*/
/** @defgroup IR_Idle_Status IR Idle Status
* @{
*/
#define IR_IDLE_OUTPUT_LOW (0x00000000 << 6)
#define IR_IDLE_OUTPUT_HIGH (0x00000001 << 6)
#define IS_IR_IDLE_STATUS(LEVEL) (((LEVEL) == IR_IDLE_OUTPUT_HIGH) || \
((LEVEL) == IR_IDLE_OUTPUT_LOW))
/** End of group IR_Idle_Status
* @}
*/
/** @defgroup IR_Rx_Start_Ctrl
* @{
*/
#define IR_RX_AUTO_MODE (0x00000001 << 27)
#define IR_RX_MANUAL_MODE (0x00000000 << 27)
#define IS_RX_START_MODE(MODE) (((MODE) == IR_RX_AUTO_MODE) || \
((MODE) == IR_RX_MANUAL_MODE))
#define IS_RX_RX_TRIGGER_EDGE(EDGE) (((EDGE) == IR_RX_FALL_EDGE) || \
((EDGE) == IR_RX_RISING_EDGE) || \
((EDGE) == IR_RX_DOUBLE_EDGE))
/** End of group IR_Rx_Start_Ctrl
* @}
*/
/** @defgroup IR_RX_Filter_Time
* @{
*/
#define IR_RX_FILTER_TIME_20NS (0x00000000 << 21)
#define IR_RX_FILTER_TIME_30NS (0x00000001 << 21)
#define IR_RX_FILTER_TIME_40NS (0x00000002 << 21)
#define IR_RX_FILTER_TIME_50NS (0x00000003 << 21)
#define IR_RX_FILTER_TIME_60NS (0x00000004 << 21)
#define IR_RX_FILTER_TIME_70NS (0x00000005 << 21)
#define IR_RX_FILTER_TIME_80NS (0x00000006 << 21)
#define IR_RX_FILTER_TIME_90NS (0x00000007 << 21)
#define IS_IR_RX_FILTER_TIME_CTRL(CTRL) (((CTRL) == IR_RX_FILTER_TIME_20NS) || \
((CTRL) == IR_RX_FILTER_TIME_30NS) || \
((CTRL) == IR_RX_FILTER_TIME_40NS) || \
((CTRL) == IR_RX_FILTER_TIME_50NS) || \
((CTRL) == IR_RX_FILTER_TIME_60NS) || \
((CTRL) == IR_RX_FILTER_TIME_70NS) || \
((CTRL) == IR_RX_FILTER_TIME_80NS) || \
((CTRL) == IR_RX_FILTER_TIME_90NS))
/** End of group IR_RX_Filter_Time
* @}
*/
/** @defgroup IR_RX_FIFO_DISCARD_SETTING
* @{
*/
#define IR_RX_FIFO_FULL_DISCARD_NEWEST (0x00000001 << 13)
#define IR_RX_FIFO_FULL_DISCARD_OLDEST (0x00000000 << 13)
#define IS_IR_RX_FIFO_FULL_DISCARD_CTRL(CTRL) (((CTRL) == IR_RX_FIFO_FULL_DISCARD_NEWEST) || \
((CTRL) == IR_RX_FIFO_FULL_DISCARD_OLDEST))
/** End of group IR_RX_FIFO_DISCARD_SETTING
* @}
*/
/** @defgroup IR_Rx_Threshold IR RX Threshold
* @{
*/
#define IR_RX_FIFO_THRESHOLD(THD) ((THD) <<8)
#define IS_IR_RX_FIFO_THRESHOLD(THD) ((THD) <= IR_RX_FIFO_SIZE)
#define IR_RX_FIFO_THRESHOLD_MASK ((0x0000001f) << 8)
/** End of group IR_Rx_Threshold
* @}
*/
/** @defgroup IR_INT_EN
* @{
*/
#define IS_TX_INT_MASK(MASK) (((MASK) & (~IR_TX_INT_ALL_MASK)) == 0)
#define IS_TX_INT(MASK) (((MASK) & (~IR_TX_INT_ALL_EN)) == 0)
#define IS_TX_INT_CLR(MASK) (((MASK) & (~IR_TX_INT_ALL_CLR)) == 0)
#define IS_RX_INT_MASK(MASK) (((MASK) & (~IR_RX_INT_ALL_MASK)) == 0)
#define IS_RX_INT(MASK) (((MASK) & (~IR_RX_INT_ALL_EN)) == 0)
#define IS_RX_INT_CLR(MASK) (((MASK) & (~IR_RX_INT_ALL_CLR)) == 0)
/** End of group IR_Rx_INT_EN
* @}
*/
/** @defgroup IR_RX_COUNTER_THRESHOLD
* @{
*/
#define IR_RX_COUNT_LOW_LEVEL (0x00000000U << 31)
#define IR_RX_COUNT_HIGH_LEVEL (0x00000001U << 31)
#define IS_IR_RX_COUNT_LEVEL_CTRL(CTRL) (((CTRL) == IR_RX_COUNT_LOW_LEVEL) || \
((CTRL) == IR_RX_COUNT_HIGH_LEVEL))
#define IS_IR_RX_COUNTER_THRESHOLD(THD) ((THD) <= 0x7fffffff)
/** End of group IR_RX_COUNTER_THRESHOLD
* @}
*/
/** End of group IR_Exported_Constants
* @}
*/
/*============================================================================*
* Functions
*============================================================================*/
/** @defgroup IR_Exported_Functions IR Exported Functions
* @{
*/
void IR_DeInit(void);
void IR_Init(IR_TypeDef *IRx, IR_InitTypeDef *IR_InitStruct);
void IR_StructInit(IR_InitTypeDef *IR_InitStruct);
void IR_Cmd(IR_TypeDef *IRx, u32 mode, u32 NewState);
void IR_SetRxCounterThreshold(IR_TypeDef *IRx, u32 IR_RxCntThrType, u32 IR_RxCntThr);
void IR_SendBuf(IR_TypeDef *IRx, u32 *pBuf, u32 len, u32 IsLastPacket);
void IR_ReceiveBuf(IR_TypeDef *IRx, u32 *pBuf, u32 len);
void IR_INTConfig(IR_TypeDef *IRx, u32 IR_INT, u32 newState);
void IR_MaskINTConfig(IR_TypeDef *IRx, u32 IR_INT, u32 newState);
u32 IR_GetINTStatus(IR_TypeDef *IRx);
u32 IR_GetIMR(IR_TypeDef *IRx);
u32 IR_FSMRunning(IR_TypeDef *IRx);
void IR_ClearINTPendingBit(IR_TypeDef *IRx, u32 IR_CLEAR_INT);
void IR_SetTxThreshold(IR_TypeDef *IRx, uint8_t thd);
void IR_SetRxThreshold(IR_TypeDef *IRx, uint8_t thd);
u32 IR_GetTxFIFOFreeLen(IR_TypeDef *IRx);
u32 IR_GetRxDataLen(IR_TypeDef *IRx);
void IR_SendData(IR_TypeDef *IRx, u32 data);
void IR_StartManualRxTrigger(IR_TypeDef *IRx);
u32 IR_ReceiveData(IR_TypeDef *IRx);
void IR_ClearTxFIFO(IR_TypeDef *IRx);
void IR_ClearRxFIFO(IR_TypeDef *IRx);
/** @} */ /* End of group IR_Exported_Functions */
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup IR_Register_Definitions IR Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup IR_CLK_DIV
* @{
*****************************************************************************/
#define IR_CLOCK_DIV ((u32)0x0000003F) /*BIT[11:0], IR CLOCK DIV*/
/** @} */
/**************************************************************************//**
* @defgroup IR_TX_CONFIG
* @{
*****************************************************************************/
#define IR_MODE_SEL ((u32)0x00000001 << 31) /*BIT[31], IR Work mode*/
#define IR_TX_START ((u32)0x00000001 << 30) /*BIT[30], IR TX FSM start*/
#define IR_TX_DUTY_NUM ((u32)0x0000003F << 16) /*BIT[27:16], IR TX DUTY NUM*/
#define IR_TX_OUTPUT_INVERSE ((u32)0x00000001 << 14) /*BIT[14], IR Inverse active output*/
#define IR_TX_DE_INVERSE ((u32)0x00000001 << 13) /*BIT[13], IR Inverse FIFO define*/
#define IR_TX_FIFO_LEVEL_TH ((u32)0x0000000F << 8) /*BIT[12:8], IR TX FIFO interrupt threshold*/
#define IR_TX_IDEL_STATE ((u32)0x00000001 << 6) /*BIT[6], IR TX output State in idle*/
#define IR_TX_FIFO_OVER_INT_MASK ((u32)0x00000001 << 5) /*BIT[5], IR TX FIFO overflow Interrupt mask*/
#define IR_TX_FIFO_OVER_INT_EN ((u32)0x00000001 << 4) /*BIT[4], IR TX FIFO overflow Interrupt enable*/
#define IR_TX_FIFO_LEVEL_INT_MASK ((u32)0x00000001 << 3) /*BIT[3], IR TX FIFO Level Interrupt mask*/
#define IR_TX_FIFO_EMPTY_INT_MASK ((u32)0x00000001 << 2) /*BIT[2], IR TX FIFO Empty Interrupt mask*/
#define IR_TX_FIFO_LEVEL_INT_EN ((u32)0x00000001 << 1) /*BIT[1], IR TX FIFO Level Interrupt enable*/
#define IR_TX_FIFO_EMPTY_INT_EN ((u32)0x00000001 << 0) /*BIT[0], IR TX FIFO Empty Interrupt enable*/
#define IR_TX_INT_ALL_MASK ((u32)0x0000002C)
#define IR_TX_INT_ALL_EN ((u32)0x00000013)
/** @} */
/**************************************************************************//**
* @defgroup IR_TX_SR
* @{
*****************************************************************************/
#define IR_TX_FIFO_EMPTY_STATUS ((u32)0x00000001 << 15) /*BIT[15], IR TX_FIFO_EMPTY status*/
#define IR_TX_FIFO_FULL_STATUS ((u32)0x00000001 << 14) /*BIT[14], IR TX_FIFO_FULL status*/
#define IR_TX_FIFO_LEVEL ((u32)0x0000003f << 8) /*BIT[13:8], IR TX FIFO DATA number*/
#define IR_TX_FSM_STATUS ((u32)0x00000001 << 4) /*BIT[4], IR TX FSM status*/
#define IR_TX_FIFO_OVER_INT_STATUS ((u32)0x00000001 << 2) /*BIT[2], IR TX FIFO overflow Interrupt status*/
#define IR_TX_FIFO_LEVEL_INT_STATUS ((u32)0x00000001 << 1) /*BIT[1], IR TX FIFO Level Interrupt stauts*/
#define IR_TX_FIFO_EMPTY_INT_STATUS ((u32)0x00000001 << 0) /*BIT[0], IR TX FIFO Empty Interrupt status*/
/** @} */
/**************************************************************************//**
* @defgroup IR_TX_COMPE_DIV
* @{
*****************************************************************************/
#define IR_TX_COMPESATION_DIV ((u32)0x0000003F) /*BIT[11:0], IR COMP CLOCK DIV*/
/** @} */
/**************************************************************************//**
* @defgroup IR_TX_INT_CLR
* @{
*****************************************************************************/
#define IR_TX_FIFO_OVER_INT_CLR ((u32)0x00000001 << 3) /*BIT[3], IR TX FIFO overflow Interrupt clear*/
#define IR_TX_FIFO_LEVEL_INT_CLR ((u32)0x00000001 << 2) /*BIT[2], IR TX FIFO Level Interrupt clear*/
#define IR_TX_FIFO_EMPTY_INT_CLR ((u32)0x00000001 << 1) /*BIT[1], IR TX FIFO Empty Interrupt clear*/
#define IR_TX_FIFO_CLR ((u32)0x00000001 << 0) /*BIT[0], IR TX FIFO clear*/
#define IR_TX_INT_ALL_CLR ((u32)0x0000000E)
/** @} */
/**************************************************************************//**
* @defgroup IR_TX_FIFO
* @{
*****************************************************************************/
#define IR_TX_DATA_CARRIER_MASK ((u32)0x00000001 << 31) /*BIT[31], IR TX DATA Carrier*/
#define IR_TX_DATA_END_MASK ((u32)0x00000001 << 30) /*BIT[30], IR TX End Flag*/
#define IR_TX_CLK_NORMAL ((u32)0x00000000 << 28) /*BIT[29:28], IR TX DATA cycle unit = 1*carrier cycle*/
#define IR_TX_CLK_1P5 ((u32)0x00000001 << 28) /*BIT[29:28], IR TX DATA cycle unit = 1.5*carrier cycle*/
#define IR_TX_CLK_1P25 ((u32)0x00000002 << 28) /*BIT[29:28], IR TX DATA cycle unit = 1.25*carrier cycle*/
#define IR_TX_CLK_COMP ((u32)0x00000003 << 28) /*BIT[29:28], IR TX DATA cycle unit = 1*compensation cycle*/
#define IR_TX_DATA_TIME ((u32)0x0FFFFFFF << 0) /*BIT[27:0], IR TX FIFO overflow Interrupt clear*/
/** @} */
/**************************************************************************//**
* @defgroup IR_RX_CONFIG
* @{
*****************************************************************************/
#define IR_RX_START ((u32)0x00000001 << 28) /*BIT[28], IR RX FSM start*/
#define IR_RX_START_MODE ((u32)0x00000001 << 27) /*BIT[27], IR RX start mode*/
#define IR_RX_MANUAL_START ((u32)0x00000001 << 26) /*BIT[26], IR RX manual start trigger*/
#define IR_RX_FALL_EDGE ((u32)0x00000000 << 24) /*BIT[25:24], IR RX auto start trigger edge*/
#define IR_RX_RISING_EDGE ((u32)0x00000001 << 24) /*BIT[25:24], IR RX auto start trigger edge*/
#define IR_RX_DOUBLE_EDGE ((u32)0x00000002 << 24) /*BIT[25:24], IR RX auto start trigger edge*/
#define IR_RX_FILTER_STAGETX ((u32)0x00000002 << 21) /*BIT[23:21], IR RX filter*/
#define IR_RX_FIFO_ERROR_INT_MASK ((u32)0x00000001 << 19) /*BIT[19], IR RX FIFO read underflow Interrupt mask*/
#define IR_RX_CNT_THR_INT_MASK ((u32)0x00000001 << 18) /*BIT[18], IR RX CNT threshold Interrupt mask*/
#define IR_RX_FIFO_OF_INT_MASK ((u32)0x00000001 << 17) /*BIT[17], IR RX FIFO overflow Interrupt mask*/
#define IR_RX_CNT_OF_INT_MASK ((u32)0x00000001 << 16) /*BIT[16], IR RX CNT overflow Interrupt mask*/
#define IR_RX_FIFO_LEVEL_INT_MASK ((u32)0x00000001 << 15) /*BIT[15], IR RX FIFO threshold Interrupt mask*/
#define IR_RX_FIFO_FULL_INT_MASK ((u32)0x00000001 << 14) /*BIT[14], IR RX FIFO FULL Interrupt mask*/
#define IR_RX_INT_ALL_MASK ((u32)0x0000003F << 14)
#define IR_RX_FIFO_DISCARD_SET ((u32)0x00000001 << 13) /*BIT[13], IR RX FIFO discard set*/
#define IR_RX_FIFO_LEVEL_TH ((u32)0x0000000F << 8) /*BIT[12:8], IR TX FIFO interrupt threshold*/
#define IR_RX_FIFO_ERROR_INT_EN ((u32)0x00000001 << 5) /*BIT[5], IR RX FIFO read underflow Interrupt enable*/
#define IR_RX_CNT_THR_INT_EN ((u32)0x00000001 << 4) /*BIT[4], IR RX CNT threshold Interrupt enable*/
#define IR_RX_FIFO_OF_INT_EN ((u32)0x00000001 << 3) /*BIT[3], IR RX FIFO overflow Interrupt enable*/
#define IR_RX_CNT_OF_INT_EN ((u32)0x00000001 << 2) /*BIT[2], IR RX CNT overflow Interrupt enable*/
#define IR_RX_FIFO_LEVEL_INT_EN ((u32)0x00000001 << 1) /*BIT[1], IR RX FIFO threshold Interrupt enable*/
#define IR_RX_FIFO_FULL_INT_EN ((u32)0x00000001 << 0) /*BIT[0], IR RX FIFO FULL Interrupt enable*/
#define IR_RX_INT_ALL_EN ((u32)0x0000003F)
/** @} */
/**************************************************************************//**
* @defgroup IR_RX_SR
* @{
*****************************************************************************/
#define IR_RX_FIFO_EMPTY_STATUS ((u32)0x00000001 << 17) /*BIT[17], IR RX FIFO Empty status*/
#define IR_RX_FIFO_LEVEL ((u32)0x0000003f << 8) /*BIT[13:8], IR RX FIFO Level status*/
#define IR_RX_FSM_STATUS ((u32)0x00000001 << 7) /*BIT[7], IR RX FSM status*/
#define IR_RX_FIFO_ERROR_INT_STATUS ((u32)0x00000001 << 5) /*BIT[5], IR RX FIFO read underflow Interrupt status*/
#define IR_RX_CNT_THR_INT_STATUS ((u32)0x00000001 << 4) /*BIT[4], IR RX CNT threshold Interrupt status*/
#define IR_RX_FIFO_OF_INT_STATUS ((u32)0x00000001 << 3) /*BIT[3], IR_RX FIFO overflow Interrupt status*/
#define IR_RX_CNT_OF_INT_STATUS ((u32)0x00000001 << 2) /*BIT[2], IR_RX CNT overflow Interrupt status*/
#define IR_RX_FIFO_LEVEL_INT_STATUS ((u32)0x00000001 << 1) /*BIT[1], IR_RX FIFO threshold Interrupt status*/
#define IR_RX_FIFO_FULL_INT_STATUS ((u32)0x00000001 << 0) /*BIT[0], IR RX FIFO FULL Interrupt status*/
/** @} */
/**************************************************************************//**
* @defgroup IR_RX_INT_CLR
* @{
*****************************************************************************/
#define IR_RX_FIFO_CLR ((u32)0x00000001 << 8) /*BIT[8], IR TX FIFO clear*/
#define IR_RX_FIFO_ERROR_INT_CLR ((u32)0x00000001 << 5) /*BIT[5], IR RX FIFO read underflow Interrupt clear*/
#define IR_RX_CNT_THR_INT_CLR ((u32)0x00000001 << 4) /*BIT[4], IR RX CNT threshold Interrupt clear*/
#define IR_RX_FIFO_OF_INT_CLR ((u32)0x00000001 << 3) /*BIT[3], IR_RX FIFO overflow Interrupt clear*/
#define IR_RX_CNT_OF_INT_CLR ((u32)0x00000001 << 2) /*BIT[2], IR_RX CNT overflow Interrupt clear*/
#define IR_RX_FIFO_LEVEL_INT_CLR ((u32)0x00000001 << 1) /*BIT[1], IR_RX FIFO threshold Interrupt clear*/
#define IR_RX_FIFO_FULL_INT_CLR ((u32)0x00000001 << 0) /*BIT[0], IR RX FIFO FULL Interrupt clear*/
#define IR_RX_INT_ALL_CLR ((u32)0x0000003F)
/** @} */
/**************************************************************************//**
* @defgroup IR_RX_CNT_INT_SEL
* @{
*****************************************************************************/
#define IR_RX_COUNT_LEVEL ((u32)0x00000001 << 31) /*BIT[31], IR RX CNT LEVEL*/
#define IR_RX_COUNTER_THRESHOLD ((u32)0x7FFFFFFF) /*BIT[30:0], IR RX CYCLE*/
/** @} */
/**************************************************************************//**
* @defgroup IR_RX_FIFO
* @{
*****************************************************************************/
#define IR_RX_LEVEL ((u32)0x00000001 << 31) /*BIT[31], IR RX LEVEL*/
#define IR_RX_COUNTER ((u32)0x7FFFFFFF) /*BIT[30:0], IR RX CYCLE*/
/** @} */
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
/** @} */ /* End of group IR */
/** @} */ /* End of group AmebaD_Periph_Driver */
#endif /* _RTL8721D_IR_H_ */
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_keyscan.h
* @author
* @version V1.0.0
* @date 2017-10-16
* @brief This file contains all the functions prototypes for the keyscan.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_KEYSCAN_H_
#define _RTL8721D_KEYSCAN_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @addtogroup KeyScan KeyScan
* @{
*/
/** @addtogroup KeyScan
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* KEYSCAN:
* - Base Address: KEYSCAN_DEV
* - Sclk: 32K/10Mhz
* - Keypad Array: Up to 6*6 (36), multi-key detect
* - Scan Clock: Configurable, up to 10Mhz
* - Work Mode: Event Trigger Mode and Regular Scan Mode
* - Debounce Timer: Configurable
* - SocPs: Sleep Mode (clock gating & power gating)
* - IRQ: KeyScan_IRQ
*
*****************************************************************************************
* How to use Normal KeyScan
*****************************************************************************************
* To use the normal KeyScan mode, the following steps are mandatory:
*
* 1. Enable KeyScan peripheral clock
*
* 2. configure the KeyScan pinmux.
*
* 3. Program Scan clock, Work Mode, Columns and Rows select, Dobounce Timer, Threshold
* KeyScan_StructInit(KeyScan_InitTypeDef* KeyScan_InitStruct)
*
* 4. Init Hardware use step3 parameters:
* KeyScan_Init(KEYSCAN_TypeDef *KeyScan, KeyScan_InitTypeDef* KeyScan_InitStruct)
*
* 5. Enable the NVIC and the corresponding interrupt using following function if you need
* to use interrupt mode.
* KeyScan_INTConfig(): KeyScan IRQ Enable set
* KeyScan_INTMask(): KeyScan IRQ mask set
* InterruptRegister(): register the keyscan irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 6. Enable KeyScan module using KeyScan_Cmd().
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types --------------------------------------------------------*/
/** @defgroup KeyScan_Exported_Types KeyScan Exported Types
* @{
*/
/**
* @brief KeyScan Init structure definition
*/
typedef struct {
u32 KS_ClkDiv; /*!< Specifies Keyscan clock divider. Scan_clk = Bus clock/(KS_ClkDiv+1).
This parameter must be set to a value in the 0x0-0xfff range. */
u32 KS_WorkMode; /*!< Specifies Keyscan work mode.
This parameter can be a value of @ref KeyScan_Work_Mode_definitions */
u32 KS_RowSel; /*!< Specifies which row(s) is used.
This parameter must be set to a value in the 0x1-0xff range. */
u32 KS_ColSel; /*!< Specifies which column(s) is used.
This parameter must be set to a value in the 0x1-0xff range. */
u32 KS_DebounceCnt; /*!< Specifies Keyscan Debounce Timer. Debounce Timer = (KS_DebounceCnt +1)* Scan_clk.
This parameter must be set to a value in the 0x0-0xfff range. */
u32 KS_IntervalCnt; /*!< Specifies Keyscan Scan Interval Timer. Interval Timer = (KS_IntervalCnt +1)* Scan_clk.
This parameter must be set to a value in the 0x0-0xfff range. */
u32 KS_ReleaseCnt; /*!< Specifies Keyscan All Release Timer. Release Timer = (KS_ReleaseCnt+1) * Scan_clk.
This parameter must be set to a value in the 0x0-0xfff range. */
u32 KS_LimitLevel; /*!< Specifies the max allowable key number be pressed at a time
This parameter can be a value of @ref KeyScan_FIFO_LimitLevel_Control */
u32 KS_ThreholdLevel; /*!< Specifies Keyscan FIFO threshold to trigger KS_FIFO_FULL
This parameter can be a value of @ref KeyScan_FIFO_ThreholdLevel_Control */
u32 KS_OverCtrl; /*!< Specifies Keyscan FIFO over control.
This parameter can be a value of @ref KeyScan_FIFO_Overflow_Control */
}KeyScan_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup KeyScan_Exported_Constants KeyScan Exported Constants
* @{
*/
/** @defgroup KeyScan_Peripheral_definitions
* @{
*/
#define IS_KEYSCAN_ALL_PERIPH(PERIPH) ((PERIPH) == KEYSCAN_DEV)
/**
* @}
*/
/** @defgroup KeyScan_Work_Mode_definitions
* @{
*/
#define KS_REGULAR_SCAN_MODE ((u32)0x00000000 << 3)
#define KS_EVENT_TRIGGER_MODE ((u32)0x00000001 << 3)
#define IS_KS_WORK_MODE(MODE) (((MODE) == KS_REGULAR_SCAN_MODE) || \
((MODE) == KS_EVENT_TRIGGER_MODE))
/**
* @}
*/
/** @defgroup KeyScan_FIFO_Overflow_Control
* @{
*/
#define KS_FIFO_OVER_CTRL_DIS_NEW ((u32)0x00000000 << 1)
#define KS_FIFO_OVER_CTRL_DIS_LAST ((u32)0x00000001 << 1)
#define IS_KS_FIFO_OVER_CTRL(CTRL) (((CTRL) == KS_FIFO_OVER_CTRL_DIS_NEW) || \
((CTRL) == KS_FIFO_OVER_CTRL_DIS_LAST))
/**
* @}
*/
/** @defgroup KeyScan_FIFO_LimitLevel_Control
* @{
*/
#define IS_KS_FIFO_LIMIT_LEVEL(DATA_NUM) ((DATA_NUM) <= 6)
/**
* @}
*/
/** @defgroup KeyScan_FIFO_ThreholdLevel_Control
* @{
*/
#define IS_KS_FIFO_TH_LEVEL(DATA_NUM) (((DATA_NUM) > 0) && ((DATA_NUM) < 16))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup KeyScan_Exported_Functions KeyScan Exported Functions
* @{
*/
/** @defgroup KeyScan_Exported_Normal_Functions KeyScan Exported Normal Functions
* @{
*/
_LONG_CALL_ void KeyScan_StructInit(KeyScan_InitTypeDef* KeyScan_InitStruct);
_LONG_CALL_ void KeyScan_Init(KEYSCAN_TypeDef *KeyScan, KeyScan_InitTypeDef* KeyScan_InitStruct);
_LONG_CALL_ void KeyScan_INTConfig(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_IT, u8 newState);
_LONG_CALL_ void KeyScan_ClearINT(KEYSCAN_TypeDef *KeyScan, u32 KeyScan_IT);
_LONG_CALL_ u32 KeyScan_GetRawINT(KEYSCAN_TypeDef *KeyScan);
_LONG_CALL_ u32 KeyScan_GetINT(KEYSCAN_TypeDef *KeyScan);
_LONG_CALL_ u8 KeyScan_GetDataNum(KEYSCAN_TypeDef *KeyScan);
_LONG_CALL_ void KeyScan_ClearFIFOData(KEYSCAN_TypeDef *KeyScan);
_LONG_CALL_ BOOL KeyScan_GetFIFOState(KEYSCAN_TypeDef *KeyScan, u32 KeyScan_Flag);
_LONG_CALL_ void KeyScan_Read(KEYSCAN_TypeDef *KeyScan, u32 *outBuf, u8 count);
_LONG_CALL_ void KeyScan_Cmd(KEYSCAN_TypeDef *KeyScan, u8 NewState);
_LONG_CALL_ void KeyScan_SetColRow(KEYSCAN_TypeDef *KeyScan, u32 column_sel, u32 row_sel);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup KeyScan_Register_Definitions KeyScan Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup KS_CLK_DIV
* @{
*****************************************************************************/
#define BIT_KS_CLK_DIV ((u32)0x00000fff) /*Bit[11:0], bits for clock division*/
/** @} */
/**************************************************************************//**
* @defgroup KS_TIM_CFG0
* @{
*****************************************************************************/
#define BIT_KS_POST_GUARD_TIMER ((u32)0x0000000f << 24) /*Bit[27:24], bits for post guard timer set*/
#define BIT_KS_PRE_GUARD_TIMER ((u32)0x0000000f << 16) /*Bit[19:16], bits for pre guard timer set*/
#define BIT_KS_DEB_TIMER ((u32)0x00000fff) /*Bit[11:0], bits for debounce timer set*/
/** @} */
/**************************************************************************//**
* @defgroup KS_TIM_CFG1
* @{
*****************************************************************************/
#define BIT_KS_INTERVAL_TIMER ((u32)0x00000fff << 16) /*Bit[27:16], bits for interval timer set*/
#define BIT_KS_RELEASE_TIMER ((u32)0x00000fff) /*Bit[11:0], bits for all release timer set*/
/** @} */
/**************************************************************************//**
* @defgroup KS_CTRL
* @{
*****************************************************************************/
#define BIT_KS_WORK_MODE ((u32)0x00000001 << 3) /*Bit[3], bit for keyscan work mode select*/
#define BIT_KS_BUSY_STATUS ((u32)0x00000001 << 1) /*Bit[1], bit for FSM busy status*/
#define BIT_KS_RUN_ENABLE ((u32)0x00000001) /*Bit[0], bit for enable internal key scan scan clock*/
/** @} */
/**************************************************************************//**
* @defgroup KS_FIFO_CFG
* @{
*****************************************************************************/
#define BIT_KS_FIFO_LIMIT_LEVEL ((u32)0x0000000f << 24) /*Bit[27:24], bits for fifo limit level set*/
#define BIT_KS_FIFO_THREHOLD_LEVEL ((u32)0x0000000f << 16) /*Bit[19:16], bits for fifo threshold set*/
#define BIT_KS_FIFO_OV_CTRL ((u32)0x00000001 << 1) /*Bit[1], bit for fifo overflow control*/
#define BIT_KS_FIFO_CLR ((u32)0x00000001) /*Bit[0], bit for fifo data clear*/
/** @} */
/**************************************************************************//**
* @defgroup KS_COL_CFG
* @{
*****************************************************************************/
#define BIT_KS_COLUMN_SEL ((u32)0x000000ff) /*Bit[7:0], bits for key column select*/
/** @} */
/**************************************************************************//**
* @defgroup KS_ROW_CFG
* @{
*****************************************************************************/
#define BIT_KS_ROW_SEL ((u32)0x000000ff) /*Bit[7:0], bits for key row select*/
/** @} */
/**************************************************************************//**
* @defgroup KS_DATA_NUM
* @{
*****************************************************************************/
#define BIT_KS_FIFO_FULL ((u32)0x00000001 << 17) /*Bit[17], bit for fifo full flag*/
#define BIT_KS_FIFO_EMPTY ((u32)0x00000001 << 16) /*Bit[16], bit for fifo empty flag*/
#define BIT_KS_FIFO_DATA_LEVEL ((u32)0x0000001f) /*Bit[4:0], bits for fifo data level*/
/** @} */
/**************************************************************************//**
* @defgroup KS_DATA
* @{
*****************************************************************************/
#define BIT_KS_PRESS_EVENT ((u32)0x00000001 << 8) /*Bit[8], bit for key press event*/
#define BIT_KS_RELEASE_EVENT ((u32)0x00000000 << 8) /*Bit[8], bit for key release event*/
#define BIT_KS_EVENT_FLAG ((u32)0x0000000f << 8) /*Bit[11:8], bits for keyscan event*/
#define BIT_KS_ROW_INDEX ((u32)0x0000000f << 4) /*Bit[7:4], bits for key row index*/
#define BIT_KS_COL_INDEX ((u32)0x0000000f) /*Bit[3:0], bits for key column index*/
#define BIT_KS_DATA ((u32)0x00000fff) /*Bit[11:8], bits for keyscan data*/
/** @} */
/**************************************************************************//**
* @defgroup KS_IMR
* @{
*****************************************************************************/
#define BIT_KS_SCAN_EVENT_INT_MSK ((u32)0x00000001 << 6) /*Bit[6], bit for key event interrupt mask*/
#define BIT_KS_FIFO_LIMIT_INT_MSK ((u32)0x00000001 << 5) /*Bit[5], bit for keyscan fifo limit interrupt mask*/
#define BIT_KS_FIFO_OVERFLOW_INT_MSK ((u32)0x00000001 << 4) /*Bit[4], bit for keyscan fifo overflow interrupt mask*/
#define BIT_KS_FIFO_FULL_INT_MSK ((u32)0x00000001 << 3) /*Bit[3], bit for keyscan fifo full interrupt mask*/
#define BIT_KS_SCAN_FINISH_INT_MSK ((u32)0x00000001 << 2) /*Bit[2], bit for keyscan finish interrupt mask*/
#define BIT_KS_FIFO_NOTEMPTY_INT_MSK ((u32)0x00000001 << 1) /*Bit[1], bit for keyscan fifo not empty interrupt mask*/
#define BIT_KS_ALL_RELEASE_INT_MSK ((u32)0x00000001) /*Bit[0], bit for keyscan all release interrupt mask*/
#define BIT_KS_ALL_INT_MSK ((u32)0x0000007f)
/** @} */
/**************************************************************************//**
* @defgroup KS_ICR
* @{
*****************************************************************************/
#define BIT_KS_FIFO_LIMIT_INT_CLR ((u32)0x00000001 << 5) /*Bit[5], bit for keyscan fifo limit interrupt clear*/
#define BIT_KS_FIFO_OVERFLOW_INT_CLR ((u32)0x00000001 << 4) /*Bit[4], bit for keyscan fifo overflow interrupt clear*/
#define BIT_KS_SCAN_FINISH_INT_CLR ((u32)0x00000001 << 2) /*Bit[2], bit for keyscan finish interrupt clear*/
#define BIT_KS_ALL_RELEASE_INT_CLR ((u32)0x00000001) /*Bit[0], bit for keyscan all release interrupt clear*/
#define BIT_KS_ALL_INT_CLR ((u32)0x0000007f)
/** @} */
/**************************************************************************//**
* @defgroup KS_ISR
* @{
*****************************************************************************/
#define BIT_KS_SCAN_EVENT_INT_STATUS ((u32)0x00000001 << 6) /*Bit[6], bit for key event interrupt status*/
#define BIT_KS_FIFO_LIMIT_INT_STATUS ((u32)0x00000001 << 5) /*Bit[5], bit for keyscan fifo limit interrupt status*/
#define BIT_KS_FIFO_OVERFLOW_INT_STATUS ((u32)0x00000001 << 4) /*Bit[4], bit for keyscan fifo overflow interrupt status*/
#define BIT_KS_FIFO_FULL_INT_STATUS ((u32)0x00000001 << 3) /*Bit[3], bit for keyscan fifo full interrupt status*/
#define BIT_KS_SCAN_FINISH_INT_STATUS ((u32)0x00000001 << 2) /*Bit[2], bit for keyscan finish interrupt status*/
#define BIT_KS_FIFO_NOTEMPTY_INT_STATUS ((u32)0x00000001 << 1) /*Bit[1], bit for keyscan fifo not empty interrupt status*/
#define BIT_KS_ALL_RELEASE_INT_STATUS ((u32)0x00000001) /*Bit[0], bit for keyscan all release interrupt status*/
/** @} */
/**************************************************************************//**
* @defgroup KS_ISR_RAW
* @{
*****************************************************************************/
#define BIT_KS_SCAN_EVENT_RAW_INT_STATUS ((u32)0x00000001 << 6) /*Bit[6], bit for key event raw interrupt status*/
#define BIT_KS_FIFO_LIMIT_RAW_INT_STATUS ((u32)0x00000001 << 5) /*Bit[5], bit for keyscan fifo limit raw interrupt status*/
#define BIT_KS_FIFO_OVERFLOW_RAW_INT_STATUS ((u32)0x00000001 << 4) /*Bit[4], bit for keyscan fifo overflow raw interrupt status*/
#define BIT_KS_FIFO_FULL_RAW_INT_STATUS ((u32)0x00000001 << 3) /*Bit[3], bit for keyscan fifo full raw interrupt status*/
#define BIT_KS_SCAN_FINISH_RAW_INT_STATUS ((u32)0x00000001 << 2) /*Bit[2], bit for keyscan finish raw interrupt status*/
#define BIT_KS_FIFO_NOTEMPTY_RAW_INT_STATUS ((u32)0x00000001 << 1) /*Bit[1], bit for keyscan fifo not empty raw interrupt status*/
#define BIT_KS_ALL_RELEASE_RAW_INT_STATUS ((u32)0x00000001) /*Bit[0], bit for keyscan all release raw interrupt status*/
/** @} */
/**************************************************************************//**
* @defgroup KS_DUMMY
* @{
*****************************************************************************/
#define BIT_DUMMY_H ((u32)0x00000001 << 8) /*Bit[15:8], bit for Dummy_h*/
#define BIT_DUMMY_L ((u32)0x00000001 << 2) /*Bit[7:2], bit for Dummy_l*/
#define BIT_KS_DISCHARGE ((u32)0x00000001 << 1) /*Bit[1], bit for discharge the column spurious capacitance,1 for enable discharge*/
#define BIT_KS_INTERVAL_POLARITY ((u32)0x00000001) /*Bit[0], bit for configure the column polarity in debounce and interval phase,1 for drive low*/
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
#endif
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_loguart.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for UART LOG firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _8710B_DIAG_H_
#define _8710B_DIAG_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup DIAG
* @brief DIAG driver modules
* @{
*/
/** @addtogroup DIAG
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* -Control API for LOGUART.
* -These API is used by system, user should not use these API if not needed.
* -LOGUART is UART2.
*
*****************************************************************************************
* pinmux
*****************************************************************************************
* -S0: GPIOA_16/17: QFN48, QFN68, QFN48-MCM.
* -S1: GPIOA_29/30: QFN32.
* -EFUSE 0x19[6]: 0: S1 PA29 & PA30, 1: S0 PA16 & PA17.
*
*****************************************************************************************
* @endverbatim
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DIAG_Exported_Constants DIAG Exported Constants
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DIAG_Exported_Functions DIAG Exported Functions
* @{
*/
_LONG_CALL_ void LOGUART_DiagInit(BOOL InitConsol);
_LONG_CALL_ void LOGUART_PutChar(u8 c);
_LONG_CALL_ u8 LOGUART_GetChar(BOOL PullMode);
_LONG_CALL_ u8 LOGUART_Readable(void);
_LONG_CALL_ u32 LOGUART_GetIMR(void);
_LONG_CALL_ void LOGUART_SetIMR (u32 SetValue);
_LONG_CALL_ void LOGUART_WaitBusy(void);
_LONG_CALL_ void LOGUART_SetBaud_FromFlash(void);
#define DiagPutChar LOGUART_PutChar
#define DiagGetChar LOGUART_GetChar
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Other definations --------------------------------------------------------*/
#endif //_8710B_DIAG_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_ota.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the OTA functions.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_OTA_H_
#define _RTL8721D_OTA_H_
/** @addtogroup AmebaD_Platform
* @{
*/
#define SERVER_LOCAL 1
#define SERVER_CLOUD 2
#define SERVER_TYPE SERVER_LOCAL /*configure OTA demo type*/
#define MAX_IMG_NUM 2
#define HTTP_OTA_UPDATE
#define HTTPS_OTA_UPDATE
#define SDCARD_OTA_UPDATE
#if (defined HTTP_OTA_UPDATE) || (defined HTTPS_OTA_UPDATE)
#define HEADER_BAK_LEN 32
typedef struct {
u32 status_code;
u32 header_len;
u8 *body;
u32 body_len;
u8 *header_bak;
u32 parse_status;
} http_response_result_t;
#endif
/** @defgroup OTA
* @brief OTA driver modules
* @{
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup OTA_Exported_Types OTA Exported Types
* @{
*/
/**
* @brief OTA firmware file header structure definition
*/
typedef struct
{
u32 FwVer; /*!< Specifies the OTA firmware verision.
This parameter is in first Dword in the firmware file. */
u32 HdrNum;/*!< Specifies the OTA firmware header number.
This parameter indicates how many headers in firmware file. */
}update_file_hdr;
/**
* @brief OTA firmware file image header structure definition
*/
typedef struct
{
u8 ImgId[4]; /*!< Specifies the OTA image ID.
This parameter is used to identify the OTA header needed. */
u32 ImgHdrLen; /*!< Specifies the OTA image header length.
This parameter indicates the Image Header Length. */
u32 Checksum; /*!< Specifies the OTA image checksum.
This parameter is used to judge whether the image received is correct. */
u32 ImgLen; /*!< Specifies the OTA image length. */
u32 Offset; /*!< Specifies the the location in the total firmware file. */
u32 FlashAddr; /*!< Specifies the flash offset address of the corresponding image. */
}update_file_img_hdr;
/**
* @brief OTA firmware file download information structure definition
*/
typedef struct
{
u32 ImgId; /*!< Specifies the Image ID.*/
u32 FlashAddr; /*!< Specifies the Flash Address.
This parameter is used to write the Image to the flash. */
u32 ImgOffset; /*!< Specifies the Image location in Firmware header.
This parameter indicates the Image location in firmware file. */
u32 ImageLen; /*!< Specifies the OTA image length. */
}update_dw_info;
/**
* @brief OTA target image header structure definition
*/
typedef struct
{
update_file_hdr FileHdr; /*!< Specifies the firmware file header. */
update_file_img_hdr FileImgHdr[MAX_IMG_NUM]; /*!< Specifies the target OTA image firmware file header. */
u8 Sign[MAX_IMG_NUM][9]; /*!< Specifies the signature of target image. */
u8 ValidImgCnt; /*!< Specifies valid image number in file. */
}update_ota_target_hdr;
/* Exported constants --------------------------------------------------------*/
/** @defgroup OTA_Exported_Constants OTA Exported Constants
* @{
*/
/** @defgroup OTA_system_parameter_definitions
* @{
*/
#define BACKUP_SECTOR (FLASH_RESERVED_DATA_BASE) /*back up system data offset address*/
#define LS_IMG2_OTA1_ADDR 0x08006000 /* KM0 OTA1 start address*/
#define LS_IMG2_OTA2_ADDR 0x08106000 /* KM0 OTA2 start address*/
#define BUF_SIZE 512 /*the size of the buffer used for receiving firmware data from server*/
#define OTA_IMAG 0 /*identify the OTA image*/
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup OTA_Exported_Functions OTA Exported Functions
* @{
*/
u32 OTA_Change(u32 OTAIdx);
void* ota_update_malloc(unsigned int size);
void ota_update_free(void *buf);
#if (SERVER_TYPE == SERVER_LOCAL)
void ota_platform_reset(void);
int ota_write_ota2_addr(uint32_t ota_addr);
u32 ota_get_cur_index(void);
int ota_readstream_user(u32 address, u32 len, u8 * data);
u32 recv_file_info_from_server(u8 * Recvbuf, u32 len, int socket);
u32 recv_ota_file_hdr(u8 * Recvbuf, u32 * len, update_ota_target_hdr * pOtaTgtHdr, int socket);
u32 get_ota_tartget_header(u8* buf, u32 len, update_ota_target_hdr * pOtaTgtHdr, u8 target_idx);
void erase_ota_target_flash(u32 addr, u32 len);
u32 download_new_fw_from_server(int socket, update_ota_target_hdr * pOtaTgtHdr, u8 targetIdx);
u32 verify_ota_checksum(update_ota_target_hdr * pOtaTgtHdr);
u32 change_ota_signature(update_ota_target_hdr * pOtaTgtHdr, u32 ota_target_index);
#endif
#if (defined HTTP_OTA_UPDATE) || (defined HTTPS_OTA_UPDATE)
int parser_url( char *url, char *host, u16 *port, char *resource);
int parse_http_response(unsigned char *response, unsigned int response_len, http_response_result_t *result);
#ifdef HTTP_OTA_UPDATE
int update_ota_http_connect_server(int server_socket, char *host, int port);
u32 recv_ota_file_hdr_http(u8 * Recvbuf, u32 writelen, u32 * len, update_ota_target_hdr * pOtaTgtHdr, int socket);
int http_read_socket( int socket, u8 *recevie_buf, int buf_len );
u32 download_new_fw_from_server_http(u8* first_buf, unsigned int firstbuf_len, int socket, update_ota_target_hdr * pOtaTgtHdr, u8 targetIdx);
int http_update_ota(char *host, int port, char *resource);
#endif
#ifdef HTTPS_OTA_UPDATE
#include <mbedtls/config.h>
#include <mbedtls/platform.h>
#include <mbedtls/net_sockets.h>
#include <mbedtls/ssl.h>
u32 recv_ota_file_hdr_https(u8 * Recvbuf, u32 writelen, u32 * len, update_ota_target_hdr * pOtaTgtHdr, mbedtls_ssl_context * ssl);
int https_read_socket(mbedtls_ssl_context * ssl, u8 * recevie_buf, int buf_len);
u32 download_new_fw_from_server_https(u8 * first_buf, unsigned int firstbuf_len, mbedtls_ssl_context * ssl, update_ota_target_hdr * pOtaTgtHdr, u8 targetIdx);
int https_update_ota(char *host, int port, char *resource);
#endif
#endif
#ifdef SDCARD_OTA_UPDATE
int sdcard_update_ota(char* filename);
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif //_RTL8721D_OTA_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_otf.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the flash run time decrypt firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_RSIP_H_
#define _RTL8721D_RSIP_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup PROTECTION
* @brief PROTECTION driver modules
* @{
*/
/** @addtogroup PROTECTION
* @verbatim
*****************************************************************************************
* RSIP(OTF) Introduction
*****************************************************************************************
* -used for flash firmware protection, and flash firmware will be encrypted use AES.
* -16B KEY shoud be written to EFUSE OTP KEY area use EFUSE_OTF_KEY.
* -Enable should be write to EFUSE 0x19[5].
*****************************************************************************************
* @endverbatim
*/
/* Exported constants --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PROTECTION_Exported_Functions OTF Exported Functions
* @{
*/
_LONG_CALL_ void RSIP_Cmd(u32 NewStatus);
_LONG_CALL_ void RSIP_OTF_init(u8* IV);
_LONG_CALL_ void RSIP_OTF_Cmd(u32 NewStatus);
_LONG_CALL_ void RSIP_OTF_Mask(u32 MaskIdx, u32 Addr, u32 Len, u32 NewStatus);
_LONG_CALL_ u32 RSIP_KEY_Request(u32 KeyTypeBit);
_LONG_CALL_ void RSIP_MMU_Config(u32 MMUIdx, u32 AddrStart, u32 AddrEnd, u32 IsMinus, u32 AddrOffset);
_LONG_CALL_ void RSIP_MMU_Cmd(u32 MMUIdx, u32 NewStatus);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup RSIP_Register_Definitions OTF Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup OTF_DEC
* @{
*****************************************************************************/
#define REG_SYS_OTF_DEC_CTRL 0x02D8
#define REG_SYS_OTF_DEC_ADDR_MASK0 0x02DC
#define REG_SYS_OTF_DEC_ADDR_MASK1 0x02E4
#define REG_SYS_OTF_DEC_ADDR_MASK2 0x02E8
#define REG_SYS_OTF_DEC_ADDR_MASK3 0x02EC
#define REG_SYS_OTF_DEC_IV_EXT 0x02F0
/** @} */
/**************************************************************************//**
* @defgroup REG_OTF_DEC_CTRL
* @{
*****************************************************************************/
#define OTF_FEN_OTFDEC ((u32)0x00000001) /*!<function enable of OTF decoder */
#define OTF_DEC_IV_BYTE_SWAP ((u32)0x00000002) /*!<Big/little endian conversion for input OTF IV */
#define OTF_DEC_KEY_BYTE_SWAP ((u32)0x00000004) /*!<Big/little endian conversion for input OTF KEY*/
#define OTF_DEC_CIPHER_BYTE_SWAP ((u32)0x00000008) /*!Big/little endian conversion for calculated cipher*/
/** @} */
/**************************************************************************//**
* @defgroup OTF_MASK_ENTRYx_CTRL
* @{
*****************************************************************************/
#define OTF_DEC_BIT_MASK_EN ((u32)0x00000001) /*!<Decoder mask enable for address~address+length */
#define OTF_DEC_BIT_MASK_SIZE ((u32)0x000000FF) /*!<Address range for decoder mask, unit is 4KB */
#define OTF_DEC_BIT_SHIFT_SIZE 8
#define IS_OTF_MASK_SIZE(SIZE) ((((SIZE) & ~OTF_DEC_BIT_MASK_SIZE) == 0x00) && (((SIZE) & OTF_DEC_BIT_MASK_SIZE) != 0x00))
/** @} */
/**************************************************************************//**
* @defgroup MMU_ENTRYx_CTRL
* @{
*****************************************************************************/
#define MMU_BIT_ENTRY_VALID ((u32)0x00000001) /*!< MMU entry_x valid */
#define MMU_BIT_ENTRY_OFFSET_MINUS ((u32)0x00000002) /*!< MMU_ENTRYx_OFFSET flag, 0 Plus, 1 Minus. */
/** @} */
/**************************************************************************//**
* @defgroup RDP_ERROR_STATUS
* @{
*****************************************************************************/
#define RDP_SYSTEMBIN_WRONG ((u32)0x00000001) /*!<system.bin not load to flash */
#define RDP_RDPBIN_WRONG ((u32)0x00000002) /*!<rdp.bin not load to flash */
#define RDP_KEY_REQUEST_TIMEOUT ((u32)0x00000003) /*!<Key request timeout */
#define RDP_NOT_ENABLE ((u32)0x00000004) /*!<RDP not enable in efuse */
#define RDP_CHECKSUM_ERROR ((u32)0x00000005) /*!<Check sum error */
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other definations --------------------------------------------------------*/
#define KEY_REQ_POLL_TIMES 0xFF
#endif
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_pinmap.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the following
* functionalities of pin control:
* - pinmux
* - active pad pull up & pull down
* - sleep pad pull up & pull down
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_PINMAP_H_
#define _RTL8710B_PINMAP_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup PIN
* @brief PIN driver modules
* @{
*/
/** @defgroup PINMAP
* @brief PINMAP driver modules
* @{
*/
/** @addtogroup PINMAP
* @verbatim
*****************************************************************************************
* PINMAP
*****************************************************************************************
* you can use pinmap to config pinmux instead of Pinmux_Config function
* you can use pinmap to config GPIO pull high/low status for power save when enter power save mode
*****************************************************************************************
* How To Use
*****************************************************************************************
* -1) ENABLE MACRO: CONFIG_PINMAP_ENABLE
* -2) Set all pins function in pmap_func based on your board
* -3) Bootloader will call pinmap_init, then all pinmux will be set based on pmap_func
* -4) pinmap_sleep will be called when enter sleep mode, all GPIO will pull high or low based on pmap_func
* -5) pinmap_wake will be called when wake from sleep mode, all GPIO will back to active mode
*****************************************************************************************
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PINMAP_Exported_Types PINMAP Exported Types
* @{
*/
/**
* @brief PINMAP Init structure definition
*/
typedef struct
{
u32 PinName; /*!< Specifies the pin name, This parameter can be a value of @ref PINMUX_Pin_Name_definitions */
u32 FuncPuPd;/*!< Specifies the pin function PU/PD, This parameter can be a value of @ref GPIO_Pull_parameter_definitions */
u32 SleepPuPd;/*!< Specifies the pin sleep PU/PD, This parameter can be a value of @ref GPIO_Pull_parameter_definitions */
u32 DSleepPuPd;/*!< Specifies the pin deep sleep PU/PD, This parameter can be a value of @ref GPIO_Pull_parameter_definitions */
u32 LowPowerPin;/*!< Specifies if it is a low power pin or touch pin, if so, this pin will keep state in DSLP state */
} PMAP_TypeDef;
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PINMAP_Exported_Functions PINMAP Exported Functions
* @{
*/
void pinmap_init(void);
void pinmap_sleep(void);
void pinmap_deepsleep(void);
void pinmap_wake(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Other definations --------------------------------------------------------*/
#define GPIO_PuPd_KEEP 0xFF /* keep pupd unchanged */
#endif //_RTL8710B_PINMAP_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_pinmux.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the pinmux firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _HAL_8721D_PINMUX_
#define _HAL_8721D_PINMUX_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup PIN
* @brief PIN driver modules
* @{
*/
/** @defgroup PINMUX
* @brief PINMUX modules
* @{
*/
/** @addtogroup PINMUX
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* -Every GPIO pin can be set to some function based on pinmux spec.
* -Every GPIO pin can set internal pull-up, pull-down based on pinmux spec.
*
*====================================================================
* pad control Spec.
*====================================================================
* -[31:16] reserved
* -[15] pad shut down enable
* -[14] H3L1 for SDIO pad, other pad reserved
* -[13] pull resistor selection
* -[12] schmitt trigger enable
* -[11:10] pad driving strength
* -[9] pull down resistor enable
* -[8] pull up resistor enable
* -[7:5] reserved for function id extend
* -[4:0] function id
*
*****************************************************************************************
* How to use Pinmux
*****************************************************************************************
* 1. Set the Internal pad function type for each pin using the follwoing function:
* Pinmux_Config(u8 PinName, u32 PinFunc)
*
* 2. Set the Internal pad pull type for each pin using the follwoing function:
* PAD_PullCtrl(u8 PinName, u8 PullType)
*
*****************************************************************************************
* @endverbatim
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PINMUX_Exported_Constants PINMUX Exported Constants
* @{
*/
/** @defgroup PINMUX_Pin_Name_definitions
* @note: Pin_Name = (((port)<<5)|(pin))
* @{
*/
#define _PA_0 (0x00) //0x400
#define _PA_1 (0x01) //0x404
#define _PA_2 (0x02) //0x408
#define _PA_3 (0x03) //0x40C
#define _PA_4 (0x04) //0x410
#define _PA_5 (0x05) //0x414
#define _PA_6 (0x06) //0x418
#define _PA_7 (0x07) //0x41C
#define _PA_8 (0x08) //0x420
#define _PA_9 (0x09) //0x424
#define _PA_10 (0x0A) //0x428
#define _PA_11 (0x0B) //0x42C
#define _PA_12 (0x0C) //0x430
#define _PA_13 (0x0D) //0x434
#define _PA_14 (0x0E) //0x438
#define _PA_15 (0x0F) //0x43C
#define _PA_16 (0x10) //0x440
#define _PA_17 (0x11) //0x444
#define _PA_18 (0x12) //0x448
#define _PA_19 (0x13) //0x44C
#define _PA_20 (0x14) //0x450
#define _PA_21 (0x15) //0x454
#define _PA_22 (0x16) //0x458
#define _PA_23 (0x17) //0x45C
#define _PA_24 (0x18) //0x460
#define _PA_25 (0x19) //0x464
#define _PA_26 (0x1A) //0x468
#define _PA_27 (0x1B) //0x46C
#define _PA_28 (0x1C) //0x470
#define _PA_29 (0x1D) //0x474
#define _PA_30 (0x1E) //0x478
#define _PA_31 (0x1F) //0x47C
#define _PB_0 (0x20) //0x480
#define _PB_1 (0x21) //0x484
#define _PB_2 (0x22) //0x488
#define _PB_3 (0x23) //0x48C
#define _PB_4 (0x24) //0x490
#define _PB_5 (0x25) //0x494
#define _PB_6 (0x26) //0x498
#define _PB_7 (0x27) //0x49C
#define _PB_8 (0x28) //0x4A0
#define _PB_9 (0x29) //0x4A4
#define _PB_10 (0x2A) //0x4A8
#define _PB_11 (0x2B) //0x4AC
#define _PB_12 (0x2C) //0x4B0
#define _PB_13 (0x2D) //0x4B4
#define _PB_14 (0x2E) //0x4B8
#define _PB_15 (0x2F) //0x4Bc
#define _PB_16 (0x30) //0x4C0
#define _PB_17 (0x31) //0x4C4
#define _PB_18 (0x32) //0x4C8
#define _PB_19 (0x33) //0x4CC
#define _PB_20 (0x34) //0x4D0
#define _PB_21 (0x35) //0x4D4
#define _PB_22 (0x36) //0x4D8
#define _PB_23 (0x37) //0x4DC
#define _PB_24 (0x38) //0x4E0
#define _PB_25 (0x39) //0x4E4
#define _PB_26 (0x3A) //0x4E8
#define _PB_27 (0x3B) //0x4EC
#define _PB_28 (0x3C) //0x4F0
#define _PB_29 (0x3D) //0x4F4
#define _PB_30 (0x3E) //0x4F8
#define _PB_31 (0x3F) //0x4FC
#define _PNC (0xFFFFFFFF)
/**
* @}
*/
/** @defgroup PINMUX_Port_And_Pin_definitions
* @{
*/
#define PORT_NUM(pin) ((pin>>5) & 0x03)
#define PIN_NUM(pin) (pin & 0x1f)
/**
* @}
*/
/** @defgroup PINMUX_PAD_Control_definitions
* @{
*/
#define PAD_BIT_SHUT_DWON BIT(15)
#define PAD_BIT_SDIO_H3L1 BIT(14)
#define PAD_BIT_PULL_RESISTOR_SEL BIT(13)
#define PAD_BIT_SCHMITT_TRIGGER_EN BIT(12)
#define PAD_BIT_PULL_RESISTOR_SMALL BIT(11) /* for PAD C/F/G */
#define PAD_BIT_SHIFT_DRIVING_STRENGTH 10
#define PAD_BIT_MASK_DRIVING_STRENGTH 0x03
#define PAD_BIT_PULL_DOWN_RESISTOR_EN BIT(9)
#define PAD_BIT_PULL_UP_RESISTOR_EN BIT(8)
#define PAD_BIT_SHIFT_FUNCTION_ID 0
#define PAD_BIT_MASK_FUNCTION_ID 0x1F
/**
* @}
*/
/** @defgroup GPIO_Pull_Resistor_definitions
* @{
*/
#define GPIO_Resistor_LARGE 0x00 /*!< GPIO Resistor LARGE */
#define GPIO_Resistor_SMALL 0x01 /*!< GPIO Resistor SMALL */
/**
* @}
*/
/** @defgroup PINMUX_Function_definitions
* @{
*/
#define PINMUX_FUNCTION_GPIO (0)
#define PINMUX_FUNCTION_UART (1)
#define PINMUX_FUNCTION_UART_RTSCTS (2)
#define PINMUX_FUNCTION_LOGUART (2)
#define PINMUX_FUNCTION_SPIM (3)
#define PINMUX_FUNCTION_SPIS (3)
#define PINMUX_FUNCTION_RTC (4)
#define PINMUX_FUNCTION_TIMINPUT (4)
#define PINMUX_FUNCTION_EXT32K (28)
#define PINMUX_FUNCTION_RTCOUT (28)
#define PINMUX_FUNCTION_TIMINPUT_HS (22)
#define PINMUX_FUNCTION_IR (5)
#define PINMUX_FUNCTION_SPIF (6)
#define PINMUX_FUNCTION_I2C (7)
#define PINMUX_FUNCTION_SDIOD (8)
#define PINMUX_FUNCTION_SDIOH (8)
#define PINMUX_FUNCTION_PWM (9)
#define PINMUX_FUNCTION_PWM_HS (9)
#define PINMUX_FUNCTION_PWM_LP (10)
#define PINMUX_FUNCTION_SWD (11)
#define PINMUX_FUNCTION_I2S (12)
#define PINMUX_FUNCTION_DMIC (12)
#define PINMUX_FUNCTION_KEYSCAN_ROW (29)
#define PINMUX_FUNCTION_KEYSCAN_COL (30)
#define PINMUX_FUNCTION_LCD (13)
#define PINMUX_FUNCTION_USB (14)
#define PINMUX_FUNCTION_QDEC (15)
#define PINMUX_FUNCTION_SGPIO (16)
#define PINMUX_FUNCTION_RFE (18)
#define PINMUX_FUNCTION_BTCOEX (19)
#define PINMUX_FUNCTION_WIFIFW (20)
#define PINMUX_FUNCTION_EXT_PCM (20)
#define PINMUX_FUNCTION_BB_PIN (21)
#define PINMUX_FUNCTION_SIC (22)
#define PINMUX_FUNCTION_WAKEUP (31)
#define PINMUX_FUNCTION_DBGPORT (23)
#define PINMUX_FUNCTION_BBDBG (25)
/**
* @}
*/
/** @defgroup PINMUX_Peripheral_Location_definitions
* @note just used by function PINMUX_Ctrl
* @{
*/
#define PINMUX_S0 (0)
#define PINMUX_S1 (1)
#define PINMUX_S2 (2)
#define PINMUX_S3 (3)
/**
* @}
*/
/** @defgroup PINMUX_PAD_DrvStrength_definitions
* @{
*/
#define PAD_DRV_STRENGTH_0 (0x00000000 << 9)
#define PAD_DRV_STRENGTH_1 (0x00000001 << 9)
#define PAD_DRV_STRENGTH_2 (0x00000002 << 9)
#define PAD_DRV_STRENGTH_3 (0x00000003 << 9)
#define PAD_DRV_STRENGTH_4 (0x00000004 << 9)
#define PAD_DRV_STRENGTH_5 (0x00000005 << 9)
#define PAD_DRV_STRENGTH_6 (0x00000006 << 9)
#define PAD_DRV_STRENGTH_7 (0x00000007 << 9)
/**
* @}
*/
/**
* @}
*/
/** @defgroup PINMUX_Exported_Functions PINMUX Exported Functions
* @{
*/
_LONG_CALL_ void PAD_CMD(u8 PinName, u8 NewStatus);
_LONG_CALL_ void PAD_DrvStrength(u8 PinName, u32 DrvStrength);
_LONG_CALL_ void PAD_PullCtrl(u8 PinName, u8 PullType);
_LONG_CALL_ void Pinmux_Config(u8 PinName, u32 PinFunc);
_LONG_CALL_ u32 Pinmux_ConfigGet(u8 PinName);
_LONG_CALL_ void Pinmux_UartLogCtrl(u32 PinLocation, BOOL Operation);
_LONG_CALL_ void Pinmux_SpicCtrl(u32 PinLocation, BOOL Operation);
/**
* @brief Set the Internal pad Resistor type.
* @param PinName : value of @ref PINMUX_Pin_Name_definitions.
* @param PullType : the pull type for the pin.This parameter can be one of the following values:
* @arg GPIO_Resistor_LARGE
* @arg GPIO_Resistor_SMALL
* @retval None
* @note Just for PAD C/F/G:
* @note PA[12]/PA[13]/PA[14]/PA[15]/PA[16]/PA[17]/PA[18]/PA[19]/PA[20]/PA[21]/PA[25]/PA[26] 4.7K/50K
* @note PA[29]/PA[30]/PA[31] 4.7K/10K
*/
static inline void PAD_ResistorCtrl(u8 PinName, u8 RType)
{
u32 Temp = 0;
/* get PADCTR */
Temp = PINMUX->PADCTR[PinName];
/* set resistor small */
Temp |= PAD_BIT_PULL_RESISTOR_SMALL; /* by default is small */
/* set large if needed */
if (RType == GPIO_Resistor_LARGE) {
Temp &= ~PAD_BIT_PULL_RESISTOR_SMALL;
}
/* set PADCTR register */
PINMUX->PADCTR[PinName] = Temp;
}
/**
* @brief Turn off pinmux SWD function.
* @retval None
*/
static inline void Pinmux_Swdoff(void)
{
u32 Temp = 0;
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_SWD_PMUX_EN);
Temp &= (~BIT_LSYS_SWD_PMUX_EN);
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_SWD_PMUX_EN, Temp);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Other definations --------------------------------------------------------*/
#define FLASH_S0_CS_GPIO _PB_18
#define FLASH_S1_CS_GPIO _PB_16
#endif //_HAL_8721D_PINMUX_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_pmc.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the following
* functionalities of the soc power management circut:
* - wakeup timer
* - wakeup pin
* - sleep option
* - sleep mode
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_PMC_H_
#define _RTL8721D_PMC_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup PMC
* @brief PMC driver modules
* @{
*/
/** @addtogroup PMC
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* we support following soc power save functions:
* - sleep clock gating
* - sleep power gating
* - deep standby
* - deep sleep
*
*****************************************************************************************
* sleep power gating
*****************************************************************************************
* following functions can be used when power gating:
* -UART0/UART1
* -TIM4/TIM5
* -RTC
* -WIFI
* -SDIO
* -USB
* -I2C0/I2C1
* -ADC
* -GPIO
* -REGU timer
* -normal wakepin
* -ANA timer
* following functions will be closed when power gating:
* -UART2 LOGUART
* -TIM0-TIM3
* -SPIC flash
*
*****************************************************************************************
* deep standby
*****************************************************************************************
* following functions can be used when deep standby:
* -RTC
* -REGU timer
* -normal wakepin
* -ANA timer
*
*****************************************************************************************
* deep sleep
*****************************************************************************************
* following functions can be used when deep standby:
* -REGU timer
* -REGU wakepin
*
*****************************************************************************************
* wakepin (A18/A5/A22/A23: mux normal wakepin and REGU wakepin)
*****************************************************************************************
* normal wakepin:
* -SLP_CG
* -SLP_PG
* -STDBY
* REGU wakepin:
* -just used in DSLP (1.2V closed)
* -just support high acive, so this pin should pull low on your board
*
*****************************************************************************************
*****************************************************************************************
* SLP & SNZ power option
*****************************************************************************************
* BIT_SYSON_PMOPT_SLP_EN_SWR & BIT_SYSON_PMOPT_SNZ_EN_SWR
* -we have two 1.2V LDO
* -BIG LDO: SWR mode or LDO mode (can config )
* -LITTLE LDO: a little 1.2v LDO
* -BIT_SYSON_PMOPT_SLP_EN_SWR
* -ENABLE/DISABLE BIG LDO when SLP
* BIT_SYSON_PMOPT_SNZ_EN_SWR
* -ENABLE/DISABLE BIG LDO when SNZ, WIFI & ADC need open BIG LDO when SNZ
*
* BIT_SYSON_PMOPT_SLP_EN_PWM & BIT_SYSON_PMOPT_SNZ_EN_PWM
* -BIT_SYSON_PMOPT_SLP_EN_PWM
* -ENABLE/DISABLE LDO heavy loading current mode when SLP
* -BIT_SYSON_PMOPT_SNZ_EN_PWM
* -ENABLE/DISABLE heavy loading current mode when SNZ, WIFI & ADC need heavy loading when SNZ
*
* BIT_SYSON_PMOPT_SLP_XTAL_EN & BIT_SYSON_PMOPT_SNZ_XTAL_EN
* -WIFI and SOC both need XTAL when work,
* -but WIFI have individual option to control XTAL, so BIT_SYSON_PMOPT_SNZ_XTAL_EN not needed
*
* BIT_SYSON_PMOPT_SLP_SYSPLL_EN & BIT_SYSON_PMOPT_SNZ_SYSPLL_EN
* -WIFI and SOC both have individual PLL, here is SOC 500M PLL
* -So BIT_SYSON_PMOPT_SNZ_SYSPLL_EN not needed
*
* BIT_SYSON_SNFEVT_WIFI_MSK = 1 & BIT_SYSON_BYPASS_SNZ_SLP = 1
* - after OS suspend, platform will enter SNZ and close CPU, then platform enter sleep mode when WIFI 32K
* - BIT_SYSON_PMOPT_SNZ_EN_SOC should never open, or CPU will not close when platform will enter SNZ
*
* BIT_SYSON_SNFEVT_WIFI_MSK = 1 & BIT_SYSON_BYPASS_SNZ_SLP = 0 (not use this config)
* - after OS suspend, platform will enter sleep mode & close CPU after WIFI 32K
*****************************************************************************************
* @endverbatim
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PMC_Exported_Constants PMC Exported Constants
* @{
*/
/** @defgroup SOCPS_PS_Wakeup_Pin_definitions
* @{
*/
#define WAKUP_0 ((u32)0x00000000)/*!< see aon_wakepin */
#define WAKUP_1 ((u32)0x00000001)/*!< see aon_wakepin */
#define WAKUP_2 ((u32)0x00000002)/*!< see aon_wakepin */
#define WAKUP_3 ((u32)0x00000003)/*!< see aon_wakepin */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
typedef struct
{
u32 km0_config_wifi_enable;
u32 km0_enable_key_touch;
u32 km0_tickles_debug; /* open km0 tickles log, it will encrease power consumption */
u32 km0_osc2m_close; /* just uart and normal ADC(2M/12=166K) use it, captouch ADC use 131K */
u32 km0_pg_enable;
u32 km0_rtc_calibration;
u32 km0_audio_pad_enable;
/* debug */
u32 km0_fw_idle_time;
u32 km0_clk_down_time;
u32 km0_rf_off_time;
u32 km0_gating_time;
u32 km0_rf_on_time;
u32 km0_wake_time;
u32 km0_dur1;
} PSCFG_TypeDef;
typedef struct
{
u32 wifi_app_ctrl_tdma; /* Enable APP Control TDMA */
u32 wifi_ultra_low_power; /* Enable WIFI low power RX */
u32 km4_cache_enable; /* km4 cache enable, carefull about SRAM data sync when use DMA */
u32 km0_dslp_force_reinit; /* km0 reinit all when wake from DLPS */
} WIFICFG_TypeDef;
extern PSCFG_TypeDef ps_config;
extern WIFICFG_TypeDef wifi_config;
void SOCPS_SetWakeEventAON(u32 Option, u32 NewStatus);
void SOCPS_SleepCG_RAM(VOID);
void SOCPS_SWR_PFMForce(u32 NewStatus);
int SOCPS_WakeEvent(void);
#endif //_RTL8721D_PMC_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_psram.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the PSRAM firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_PSRAM_H
#define _RTL8710B_PSRAM_H
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup PSRAM
* @brief PSRAM driver modules
* @{
*/
/** @addtogroup PSRAM
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* PSRAM_Controller is used to communicate with PSRAM
* PSRAM:
* - IPclk: 50Mhz
* - Memory Size: 32M bits
* - Address Mapping: 0x0200_0000 ~ 0x0240_0000
* - Access: direct access or dpin mode
* - IRQ: PSRAMC_IRQ
* - GDMA: Support
*
*****************************************************************************************
* How to use PSRAM_Controller to direct access PSRAM memory
*****************************************************************************************
* To direct access PSRAM memory, the following steps are mandatory:
*
* 1. Program read/write Latency, access mode, refresh_rate
* PSRAM_CTRL_StructInit(PCTL_InitTypeDef *PCTL_InitStruct)
*
* 2. Init Hardware use step1 parameters:
* PSRAM_CTRL_Init(PCTL_InitTypeDef *PCTL_InitStruct)
*
* 3. Calibration the best rwds delay line:
* PSRAM_calibration()
*
* 4. Access PSRAM memory normally
*
*****************************************************************************************
* How to use PSRAM_Controller to access PSRAM by Dpin mode
*****************************************************************************************
* To access PSRAM by Dpin mode, the following steps are mandatory:
*
* 1. Program read/write Latency, access mode, refresh_rate
* PSRAM_CTRL_StructInit(PCTL_InitTypeDef *PCTL_InitStruct)
*
* 2. Init Hardware use step1 parameters:
* PSRAM_CTRL_Init(PCTL_InitTypeDef *PCTL_InitStruct)
*
* 3. Calibration the best rwds delay line:
* PSRAM_calibration()
*
* 4. Generate PSRAM command address value for dpin mode
* PSRAM_CTRL_CA_Gen()
*
* 5. Access PSRAM memory/registers by dpin mode
* PSRAM_CTRL_DPin_Mem():Access PSRAM memory
* PSRAM_CTRL_DPin_Reg():Access PSRAM register
*
* @note: Cache should be disable during DPIN mode
*
*****************************************************************************************
* How to use PSRAM_Controller to access PSRAM by DMA mode
*****************************************************************************************
* To access PSRAM by DMA mode, the following steps are mandatory:
*
* 1. Program read/write Latency, access mode, refresh_rate
* PSRAM_CTRL_StructInit(PCTL_InitTypeDef *PCTL_InitStruct)
*
* 2. Init Hardware use step1 parameters:
* PSRAM_CTRL_Init(PCTL_InitTypeDef *PCTL_InitStruct)
*
* 3. Calibration the best rwds delay line:
* PSRAM_calibration()
*
* 4. Alloc a free channel for PSRAM GDMA and register GDMA IRQ callback function and data
* GDMA_ChnlAlloc()
*
* 5. GDMA related configurations(source address/destination address/block size etc.)
* GDMA_StructInit():Fills GDMA_InitStruct member with its default value
* GDMA_Init():Init GDMA
* GDMA_BurstEnable():Enable GDMA Burst Transmission
*
* 6. Active the PSRAM DMA Request using the function GDMA_Cmd()
*
* @note: The Maximum Msize of Channel0 is different from other Channels
* Maximum Msize of Channel0 is 256
* Maximum Msize of Channel1 ~ Channel5 is 8
*
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PSRAM_Exported_Types PSRAM Exported Types
* @{
*/
/**
* @brief PSRAM Init structure definition
*/
typedef struct {
u8 PCTL_dfi_cs_wr_dly; /*!< Specifies the latency contrast between PHY write data path latency
and PHY command path latency.
This parameter must be set to a value in the 0-15 range */
u8 PCTL_dfi_cs_rd_dly; /*!< Specifies the latency contrast between PHY read data enable path
latency and PHY command path latency .
This parameter must be set to a value in the 0-15 range */
u8 PCTL_tphy_wrdata; /*!< Specifies the delay latency from DFI write command to DFI write data.
This parameter is proposed to set PCTL_wl+2 */
u8 PCTL_fix_tphy_lat; /*!< Specifies thePSRAM_LPC_CTRL uses TPHY_WRDATA or TPHY_RDDATA only .
This parameter can be a value of @ref PSRAM_TPHY_LAT_definitions */
u8 PCTL_tphy_rddata; /*!< Specifies the delay latency from DFI read command to DFI read data.
This parameter is proposed to set PCTL_rl+3 */
u8 PCTL_dfi_path_dly; /*!< Specifies which TPHY_WRATA/TPHY_RDDATA cycle to sample DFI latency.
This parameter is proposed to set PCTL_wl */
u8 PCTL_wl; /*!< Specifies the PSRAM write latency .
This parameter must be set to a value in the 3-6 range */
u8 PCTL_rl; /*!< Specifies the PSRAM read latency.
This parameter must be set to a value in the 3-6 range */
u32 PCTL_tcph_ps; /*!< Specifies the PSRAM CE# pin HIGH cycles between subsequent command.
This parameter unit is ps */
u32 PCTL_tpu_ps; /*!< Specifies the time between access PSRAM and RESET# pin high.
This parameter unit is ps */
u32 PCTL_tcem_ps; /*!< Specifies the maximum average Refresh commands delay cycles.
This parameter unit is ps */
u32 PCTL_clk_ps; /*!< Specifies the PSRAM clock cycle.
This parameter unit is ps */
u8 PCTL_mr0_burst_len; /*!< Specifies the PSRAM burst length.
This parameter can be a value of @ref PSRAM_BURST_LENGTH_definitions */
u8 PCTL_mr0_burst_type; /*!< Specifies the PSRAM wrapped burst type.
This parameter can be a value of @ref PSRAM_BURST_TYPE_definitions */
u8 PCTL_mr0_lat_mode; /*!< Specifies the PSRAM whether fix latency.
This parameter can be a value of @ref PSRAM_LATENCY_MODE_definitions */
u8 PCTL_mr0_init_lat; /*!< Specifies the PSRAM initial latency.
This parameter can be a value of @ref PSRAM_INIT_LATENCY_definitions */
u8 PCTL_mr0_drv_strength; /*!< Specifies the PSRAM drive strength.
This parameter can be a value of @ref PSRAM_DRV_STRENGTH_definitions */
u8 PCTL_mr0_dpd_en; /*!< Specifies the PSRAM whether enter deep power pown.
This parameter can be a value of @ref PSRAM_DPD_definitions */
u8 PCTL_mr1_pasr; /*!< Specifies the PSRAM partial array self refresh.
This parameter can be a value of @ref PSRAM_PASR_definitions */
u8 PCTL_mr1_half_slp; /*!< Specifies the PSRAM half sleep mode set.
This parameter can be a value of @ref PSRAM_HALF_SLP_definitions */
u8 PCTL_mr1_refresh_rate; /*!< Specifies the PSRAM refresh rate.
This parameter can be a value of @ref PSRAM_REFRESH_RATE_definitions */
} PCTL_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PSRAM_Exported_Constants PSRAM Exported Constants
* @{
*/
/** @defgroup PSRAM_Peripheral_definitions
* @{
*/
#define IS_PSRAM_ALL_PERIPH(PERIPH) ((PERIPH) == PSRAM_DEV)
/**
* @}
*/
/** @defgroup PSRAM_TPHY_LAT_definitions
* @{
*/
#define PSRAM_FIX_TPHY_LATENCY 1
#define PSRAM_UNSET_TPHY_LATENCY 0
/**
* @}
*/
/** @defgroup PSRAM_BURST_LENGTH_definitions
* @{
*/
#define PSRAM_BURST_LENGTH_128B 0
#define PSRAM_BURST_LENGTH_64B 1
#define PSRAM_BURST_LENGTH_16B 2
#define PSRAM_BURST_LENGTH_32B 3
/**
* @}
*/
/** @defgroup PSRAM_BURST_TYPE_definitions
* @{
*/
#define PSRAM_BURST_VENDOR_TYPE 0
#define PSRAM_BURST_LEGACY_TYPE 1
/**
* @}
*/
/** @defgroup PSRAM_LATENCY_MODE_definitions
* @{
*/
#define PSRAM_2TIMES_LATENCY_FIXED 1
#define PSRAM_VARIABLE_LATENCY 0
/**
* @}
*/
/** @defgroup PSRAM_INIT_LATENCY_definitions
* @{
*/
#define PSRAM_INIT_LATENCY_5CLK 0
#define PSRAM_INIT_LATENCY_6CLK 1
#define PSRAM_INIT_LATENCY_3CLK 0xe
#define PSRAM_INIT_LATENCY_4CLK 0xf
/**
* @}
*/
/** @defgroup PSRAM_DRV_STRENGTH_definitions
* @{
*/
#define PSRAM_DRV_STRENGTH_50OHMS 0
#define PSRAM_DRV_STRENGTH_35OHMS 1
#define PSRAM_DRV_STRENGTH_100OHMS 2
#define PSRAM_DRV_STRENGTH_200OHMS 3
/**
* @}
*/
/** @defgroup PSRAM_DPD_definitions
* @{
*/
#define PSRAM_DPD_MODE 0
#define PSRAM_NORMAL_MODE 1
/**
* @}
*/
/** @defgroup PSRAM_PASR_definitions
* @{
*/
#define PSRAM_PASR_FULL_ARRAY 0
#define PSRAM_PASR_BOT_HALF_ARRAY 1
#define PSRAM_PASR_BOT_QUARTER_ARRAY 2
#define PSRAM_PASR_BOT_EIGHTH_ARRAY 3
#define PSRAM_PASR_NONE 4
#define PSRAM_PASR_TOP_HALF_ARRAY 5
#define PSRAM_PASR_TOP_QUARTER_ARRAY 6
#define PSRAM_PASR_TOP_EIGHTH_ARRAY 7
/**
* @}
*/
/** @defgroup PSRAM_HALF_SLP_definitions
* @{
*/
#define PSRAM_HALF_SLP_DIS 0
#define PSRAM_HALF_SLP_EN 1
/**
* @}
*/
/** @defgroup PSRAM_REFRESH_RATE_definitions
* @{
*/
#define PSRAM_REFRESH_RATE_FAST 0
#define PSRAM_REFRESH_RATE_NORMAL 1
/**
* @}
*/
/** @defgroup PSRAM_BURST_TYPE_definitions
* @{
*/
#define PSRAM_WRAPPED_TYPE 0
#define PSRAM_LINEAR_TYPE 1
#define IS_PSRAM_BURST_TYPE(TYPE) (((TYPE) == PSRAM_WRAPPED_TYPE) || \
((TYPE) == PSRAM_LINEAR_TYPE))
/**
* @}
*/
/** @defgroup PSRAM_ADDR_SPACE_definitions
* @{
*/
#define PSRAM_MEM_SPACE 0
#define PSRAM_REG_SPACE 1
#define IS_PSRAM_ADDR_SPACE(MODE) (((MODE) == PSRAM_MEM_SPACE) || \
((MODE) == PSRAM_REG_SPACE))
/**
* @}
*/
/** @defgroup PSRAM_WR_TRANSACTION_definitions
* @{
*/
#define PSRAM_WRITE_TRANSACTION 0
#define PSRAM_READ_TRANSACTION 1
#define IS_PSRAM_WR_TRANSACTION(MODE) (((MODE) == PSRAM_WRITE_TRANSACTION) || \
((MODE) == PSRAM_READ_TRANSACTION))
/**
* @}
*/
/** @defgroup PSRAM_DPIN_WR_MODE_definitions
* @{
*/
#define PSRAM_DPIN_READ_MODE 0 << 17
#define PSRAM_DPIN_WRITE_MODE 1 << 17
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PSRAM_Exported_Functions PSRAM Exported Functions
* @{
*/
_LONG_CALL_ void PSRAM_CTRL_StructInit(PCTL_InitTypeDef *PCTL_InitStruct);
_LONG_CALL_ void PSRAM_CTRL_Init(PCTL_InitTypeDef *PCTL_InitStruct);
_LONG_CALL_ void PSRAM_CTRL_CA_Gen(u8* PSRAM_CA, u32 StartAddr, u8 BurstType, u8 AddSpace, u8 RW);
_LONG_CALL_ void PSRAM_CTRL_DPin_Mem(u8* PSRAM_CA, u32* PSRAM_data, u32 PSRAM_byteen, u8 RW);
_LONG_CALL_ void PSRAM_CTRL_DPin_Reg(u8* PSRAM_CA, u32* PSRAM_data, u8 RW);
_LONG_CALL_ u32 PSRAM_PHY_REG_Read(u8 offset);
_LONG_CALL_ void PSRAM_PHY_REG_Write(u8 offset, u32 reg_val);
_LONG_CALL_ BOOL PSRAM_calibration(VOID);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/** @defgroup PSRAM_Register_Definitions PSRAM Register Definitions
* @{
*/
/**************************************************************************//**
* @defgroup PSRAM_CCR
* @{
*****************************************************************************/
/******************** Bits definition for CCR register *******************/
#define BIT_PSRAM_CR_UPDATE ((u32)0x00000001 << 31) /*Bit[31],bit for update the internal timing/control registers or Quick INIT done*/
#define BIT_PSRAM_FLUSH_FIFO ((u32)0x00000001 << 8) /*Bit[8],bit for flush all FIFO in PSRAM_LPC_CTRL*/
#define BIT_PSRAM_DPIN ((u32)0x00000001 << 3) /*Bit[3],bit for start to set PSRAM command function*/
#define BIT_PSRAM_INIT ((u32)0x00000001) /*Bit[0],bit for start to issue PSRAM initialization sequence*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_DCR
* @{
*****************************************************************************/
/******************** Bits definition for DCR register *******************/
#define BIT_PSRAM_AADMUX ((u32)0x00000001 << 20) /*Bit[20], bit for indicate the target PSRAM is AADMUX type or ADMUX or mormal type*/
#define BIT_PSRAM_PAGE_SIZE ((u32)0x0000000f << 16) /*Bit[19:16], bits for indicate the target PSRAM page size*/
#define BIT_PSRAM_SUSPEND_EN ((u32)0x00000001 << 9) /*Bit[9], bit for indicate PSRAM_CTRL support SUSPEND command*/
#define BIT_PSRAM_CLK_EN ((u32)0x00000001 << 8) /*Bit[8], bit for indicate PSRAM at asynchronous mode clock enable*/
#define BIT_PSRAM_CRE_EN ((u32)0x00000001 << 7) /*Bit[7], bit for indicate access PSRAM register mode*/
#define BIT_PSRAM_DFI_RATE ((u32)0x00000007 << 4) /*Bit[6:4], bits for set DFI ratio*/
#define BIT_PSRAM_DDR_MODE ((u32)0x00000001 << 3) /*Bit[3], bit for indicate the PSRAM work at DDR mode or SDR mode*/
#define BIT_PSRAM_ASYNC_MODE ((u32)0x00000001 << 2) /*Bit[2], bit for indicate the PSRAM work at asynchronous mode or synchronous mode*/
#define BIT_PSRAM_DQ ((u32)0x00000003) /*Bit[1:0], bits for set the PSRAM architecture*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_IOCR0
* @{
*****************************************************************************/
/******************** Bits definition for IOCR0 register *******************/
#define BIT_PSRAM_DFI_PATH_DLY_MASK ((u32)0x0000001f << 25) /*Bit[29:25], bits for select which TPHY_WRATA/TPHY_RDDATA cycle to sample dfi_latency_en*/
#define BIT_PSRAM_DFI_PATH_DLY_SHIFT 25
#define BIT_PSRAM_TPHY_RDDATA_EN_MASK ((u32)0x0000001f << 20) /*Bit[24:20], bits for setting the delay latency from DFI read command to dfi_rddata_en signal*/
#define BIT_PSRAM_TPHY_RDDATA_EN_SHIFT 20
#define BIT_PSRAM_FIX_TPHY_LAT_MASK ((u32)0x00000001 << 19) /*Bit[19], bit for PSRAM_LPC_CTRL uses TPHY_WRDATA or TPHY_RDDATA only*/
#define BIT_PSRAM_FIX_TPHY_LAT_SHIFT 19
#define BIT_PSRAM_TPHY_WRDATA_MASK ((u32)0x0000001f << 12) /*Bit[16:12], bits for setting the delay latency from DFI write command to DFI write data*/
#define BIT_PSRAM_TPHY_WRDATA_SHIFT 12
#define BIT_PSRAM_RD_PIPE_MASK ((u32)0x0000000f << 8) /*Bit[11:8], bits for SDR mode read data delay setting*/
#define BIT_PSRAM_RD_PIPE_SHIFT 8
#define BIT_PSRAM_DFI_CS_RD_DLY_MASK ((u32)0x0000000f << 4) /*Bit[7:4], bits for setting the latency contrast between PHY write data path latency and
PHY command path latency*/
#define BIT_PSRAM_DFI_CS_RD_DLY_SHIFT 4
#define BIT_PSRAM_DFI_CS_WR_DLY_MASK ((u32)0x0000000f) /*Bit[3:0], bits for setting the latency contrast between PHY read data enable path latency
and PHY command path latency*/
#define BIT_PSRAM_DFI_CS_WR_DLY_SHIFT 0
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_CSR
* @{
*****************************************************************************/
/******************** Bits definition for CSR register *******************/
#define BIT_PSRAM_DPIN_MODE ((u32)0x00000003 << 17) /*Bit[18:17], bit for DPIN mode decode*/
#define BIT_PSRAM_MEM_IDLE ((u32)0x00000001 << 8) /*Bit[8], bit for disable memory access state*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_DRR
* @{
*****************************************************************************/
/******************** Bits definition for DRR register *******************/
#define BIT_PSRAM_PU_TIME_MASK ((u32)0x0000007f << 15) /*Bit[21:15], bits for If non-defined CR_INTI_RMBIT configuration*/
#define BIT_PSRAM_PU_TIME_SHIFT 15
#define BIT_PSRAM_CEM_TIME_MASK ((u32)0x000007ff << 4) /*Bit[14:4], bits for Maximum average Refresh commands delay cycles*/
#define BIT_PSRAM_CEM_TIME_SHIFT 4
#define BIT_PSRAM_CPH_TIME_MASK ((u32)0x0000000f) /*Bit[3:0], bits for PSRAM CE# pin HIGH cycles between subsequent command*/
#define BIT_PSRAM_CPH_TIME_SHIFT 0
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_CMD_DPIN_NDGE
* @{
*****************************************************************************/
/******************** Bits definition for CMD_DPIN_NDGE register *******************/
#define BIT_PSRAM_DPIN_ADDR_NDGE ((u32)0x00ffffff) /*Bit[23:0], bits for PSRAM command address value in DPIN function at negative edge*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_CMD_DPIN
* @{
*****************************************************************************/
/******************** Bits definition for CMD_DPIN register *******************/
#define BIT_PSRAM_DPIN_ADDR_POSI ((u32)0x00ffffff) /*Bit[23:0], bits for PSRAM command address value in DPIN function at positive edge*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_CR_TDPIN
* @{
*****************************************************************************/
/******************** Bits definition for CR_TDPIN register *******************/
#define BIT_PSRAM_DFI_RESET_N ((u32)0x00000001) /*Bit[0], bit for set the PSRAM TDPIN register value*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_MR_INFO
* @{
*****************************************************************************/
/******************** Bits definition for MR_INFO register *******************/
#define BIT_PSRAM_RL_LATENCY_MASK ((u32)0x0000001f << 5) /*Bit[9:5], bits for indicate PSRAM read latency counter*/
#define BIT_PSRAM_RL_LATENCY_SHIFT 5
#define BIT_PSRAM_WL_LATENCY_MASK ((u32)0x0000001f) /*Bit[4:0], bits for indicate PSRAM write latency counter*/
#define BIT_PSRAM_WL_LATENCY_SHIFT 0
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_MR0
* @{
*****************************************************************************/
/******************** Bits definition for MR0 register *******************/
#define BIT_PSRAM_MR0_MASK ((u32)0x0000ffff) /*Bit[15:0], bits for setting the value to PSRAM CR0 register in initialization flow*/
#define BIT_PSRAM_MR0_BURST_DPD_MODE_MASK ((u32)0x00000001)
#define BIT_PSRAM_MR0_BURST_DPD_MODE_SHIFT 15
#define BIT_PSRAM_MR0_BURST_DRV_STRENGTH_MASK ((u32)0x00000007)
#define BIT_PSRAM_MR0_BURST_DRV_STRENGTH_SHIFT 12
#define BIT_PSRAM_MR0_BURST_RSVD_MASK ((u32)0x0000000f)
#define BIT_PSRAM_MR0_BURST_RSVD_SHIFT 8
#define BIT_PSRAM_MR0_BURST_INIT_LAT_MASK ((u32)0x0000000f)
#define BIT_PSRAM_MR0_BURST_INIT_LAT_SHIFT 4
#define BIT_PSRAM_MR0_BURST_LAT_MODE_MASK ((u32)0x00000001)
#define BIT_PSRAM_MR0_BURST_LAT_MODE_SHIFT 3
#define BIT_PSRAM_MR0_BURST_TYPE_MASK ((u32)0x00000001)
#define BIT_PSRAM_MR0_BURST_TYPE_SHIFT 2
#define BIT_PSRAM_MR0_BURST_LENGTH_MASK ((u32)0x00000003)
#define BIT_PSRAM_MR0_BURST_LENGTH_SHIFT 0
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_MR1
* @{
*****************************************************************************/
/******************** Bits definition for MR1 register *******************/
#define BIT_PSRAM_MR1_MASK ((u32)0x0000ffff) /*Bit[15:0], bits for setting the value to PSRAM CR1 register in initialization flow*/
#define BIT_PSRAM_MR1_REFRESH_RATE_MASK ((u32)0x00000001)
#define BIT_PSRAM_MR1_REFRESH_RATE_SHIFT 6
#define BIT_PSRAM_MR1_HALF_SLP_MODE_MASK ((u32)0x00000001)
#define BIT_PSRAM_MR1_HALF_SLP_MODE_SHIFT 5
#define BIT_PSRAM_MR1_PASR_MASK ((u32)0x00000007)
#define BIT_PSRAM_MR1_PASR_SHIFT 0
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_DPDRI
* @{
*****************************************************************************/
/******************** Bits definition for DPDRI register *******************/
#define BIT_PSRAM_DPIN_DATA_INDEX ((u32)0x0000000f) /*Bit[3:0], bits for indicate select which DPIN DATA register .*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_DPDR
* @{
*****************************************************************************/
/******************** Bits definition for DPDR register *******************/
#define BIT_PSRAM_DPIN_DATA ((u32)0xffffffff) /*Bit[31:0], bits for indicate the data which will be written to PSRAM or the data
read from PSRAM.*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_PCTL_SVN_ID
* @{
*****************************************************************************/
/******************** Bits definition for PCTL_SVN_ID register *******************/
#define BIT_PSRAM_CTRL_GIT_CNT ((u32)0x0000ffff << 16) /*Bit[31:16], bits for indicate the Git counter of the released RTL code.*/
#define BIT_PSRAM_CTRL_RELEASE_DATE ((u32)0x0000ffff) /*Bit[15:0], bits for indicate the IP release date for the particular project.*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_PCTL_IDR
* @{
*****************************************************************************/
/******************** Bits definition for PCTL_IDR register *******************/
#define BIT_PSRAM_CTRL_CR_VER ((u32)0x0000ffff << 16) /*Bit[31:16], bits for control register version number.*/
#define BIT_PSRAM_CTRL_CR_PCTL_DEF ((u32)0x0000ffff) /*Bit[15:0], bits for user definition or support PSRAM type.*/
/** @} */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************** Bits definition for REG_PSRAM_CAL_CTRL register *******************/
#define BIT_PSRAM_CFG_CAL_INTR ((u32)0x00000001 << 16) /*Bit[16], bit for Interrupt flag raised by calibration.*/
#define BIT_PSRAM_CFG_CAL_INTR_MASK ((u32)0x00000001 << 8) /*Bit[8], bit for Calibration fail interrupt mask.*/
#define BIT_PSRAM_CFG_CAL_THD_MASK ((u32)0x0000000f) /*Bit[7:4], bits for Error check threshold value , used as a filter*/
#define BIT_PSRAM_CFG_CAL_THD_SHIFT 4
#define BIT_PSRAM_CFG_CAL_EN ((u32)0x00000001) /*Bit[0], bit for Hardware auto calibration enable.*/
/******************** Bits definition for REG_PSRAM_CAL_PARA register *******************/
#define BIT_PSRAM_CFG_CAL_JMIN_MASK ((u32)0x00000007) /*Bit[26:24], bits for Minimum J.*/
#define BIT_PSRAM_CFG_CAL_JMIN_SHIFT 24
#define BIT_PSRAM_CFG_CAL_JMAX_MASK ((u32)0x0000000f) /*Bit[19:16], bits for Maximum J.*/
#define BIT_PSRAM_CFG_CAL_JMAX_SHIFT 16
#define BIT_PSRAM_CFG_CAL_J_MASK ((u32)0x0000000f) /*Bit[11:8], bits for Initial value J calibrated by software.*/
#define BIT_PSRAM_CFG_CAL_J_SHIFT 8
#define BIT_PSRAM_CFG_CAL_N_MASK ((u32)0x0000001f) /*Bit[4:0], bits for Initial value N calibrated by software.*/
#define BIT_PSRAM_CFG_CAL_N_SHIFT 0
/******************** Bits definition for REG_PSRAM_CAL_STATUS register *******************/
#define BIT_PSRAM_CFG_CAL_CUR_ST_MASK ((u32)0x0000001f) /*Bit[28:24], bits for Calibration current state.*/
#define BIT_PSRAM_CFG_CAL_CUR_ST_SHIFT 24
#define BIT_PSRAM_CFG_CAL_PDST_MASK ((u32)0x00000007) /*Bit[18:16], bits for Calibration check result for last read burst.*/
#define BIT_PSRAM_CFG_CAL_PDST_SHIFT 16
#define BIT_PSRAM_CFG_CAL_CUR_J_MASK ((u32)0x0000000f) /*Bit[11:8], bits for Current value J read from hardware.*/
#define BIT_PSRAM_CFG_CAL_CUR_J_SHIFT 8
#define BIT_PSRAM_CFG_CAL_CUR_N_MASK ((u32)0x0000001f) /*Bit[4:0], bits for Current value N read from hardware.*/
#define BIT_PSRAM_CFG_CAL_CUR_N_SHIFT 0
/******************** Bits definition for REG_PSRAM_CMD_ADDR_INFO_L register *******************/
#define BIT_PSRAM_CMD_ADDR_INFO_L_MASK ((u32)0xffffffff) /*Bit[31:0], bits for Command/Address information[31:0].*/
/******************** Bits definition for REG_PSRAM_CMD_ADDR_INFO_H register *******************/
#define BIT_PSRAM_CMD_ADDR_INFO_H_MASK ((u32)0x0000ffff) /*Bit[15:0], bits for Command/Address information[47:32].*/
/******************** Bits definition for REG_PSRAM_BYTE_CNT_INFO register *******************/
#define BIT_PSRAM_WBYTE_ACCU_MASK ((u32)0x000000ff) /*Bit[31:24], bits for length of write data given by psram controller, will be cleared at the end of this Transaction.*/
#define BIT_PSRAM_WBYTE_ACCU_SHIFT 24
#define BIT_PSRAM_WBYTE_CNT_MASK ((u32)0x000000ff) /*Bit[23:16], bits for length of data written to psram controller, will be cleared at the end of this Transaction.*/
#define BIT_PSRAM_WBYTE_CNT_SHIFT 16
#define BIT_PSRAM_RBYTE_ACCU_MASK ((u32)0x000000ff) /*Bit[15:8], bits for length of read data given by psram controller, will be cleared at the beginning of next Transaction.*/
#define BIT_PSRAM_RBYTE_ACCU_SHIFT 8
#define BIT_PSRAM_RBYTE_CNT_MASK ((u32)0x000000ff) /*Bit[7:0], bits for length of data read from psram controller, will be cleared at the beginning of next Transaction.*/
#define BIT_PSRAM_RBYTE_CNT_SHIFT 0
/******************** Bits definition for REG_PSRAM_TIME_OUT_CTRL register *******************/
#define BIT_PSRAM_TIME_OUT_INTR ((u32)0x00000001 << 31) /*Bit[31], bit for read transaction time out interrupt flag.*/
#define BIT_PSRAM_TIME_OUT_INTR_MASK ((u32)0x00000001 << 23) /*Bit[23], bit for read transaction time out interrupt mask.*/
#define BIT_PSRAM_TIME_OUT_THOLD_MASK ((u32)0x000000ff) /*Bit[7:0], bits for read transaction time out threshold.*/
#define BIT_PSRAM_TIME_OUT_THOLD_SHIFT 0
/******************** Bits definition for REG_PSRAM_DBG_SEL register *******************/
#define BIT_PSRAM_PSRAM_PHY_DBG_SEL_MASK ((u32)0xff) /*Bit[7:0], bits for psram phy debug select signal.*/
#define BIT_PSRAM_PSRAM_PHY_DBG_SEL_SHIFT 0
/******************** Bits definition for REG_PSRAM_DBG_INFO register *******************/
#define BIT_PSRAM_PSRAM_PHY_DBG_MASK ((u32)0xffffffff) /*Bit[31:0], bits for psram phy debug signals.*/
#define BIT_PSRAM_PSRAM_PHY_DBG_SHIFT 0
/******************** PSRAM PHY register *******************/
#define REG_PSRAM_CAL_CTRL 0x000 /*!< PSRAM PHY Calibration control register */
#define REG_PSRAM_CAL_PARA 0x004 /*!< PSRAM PHY Calibration parameter register*/
#define REG_PSRAM_CAL_STATUS 0x008 /*!< PSRAM PHY Calibration status register*/
#define REG_PSRAM_CMD_ADDR_INFO_L 0x010 /*!< PSRAM Command/address information register[31:0]*/
#define REG_PSRAM_CMD_ADDR_INFO_H 0x014 /*!< PSRAM Command/address information register[48:32]*/
#define REG_PSRAM_BYTE_CNT_INFO 0x018 /*!< PSRAM Byte Counts register*/
#define REG_PSRAM_TIME_OUT_CTRL 0x01C /*!< PSRAM Timeout Control register*/
#define REG_PSRAM_DBG_SEL 0x0F0 /*!< PSRAM Debug select register*/
#define REG_PSRAM_DBG_INFO 0x0F8 /*!< PSRAM Debug information register*/
/* Other definations --------------------------------------------------------*/
typedef struct
{
u32 psram_dev_enable; /*enable psram*/
u32 psram_dev_cal_enable; /*enable psram calibration function*/
u32 psram_dev_retention; /*enable psram retention when km4 enter low power mode*/
} PSRAMCFG_TypeDef;
extern PSRAMCFG_TypeDef psram_dev_config;
#endif //_RTL8710B_PSRAM_H
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_qdec.h
* @author
* @version V1.0.0
* @date 2017-10-16
* @brief This file contains all the functions prototypes for the QDecoder.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_QDEC_H_
#define _RTL8721D_QDEC_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @addtogroup QDecoder QDecoder
* @{
*/
/** @addtogroup QDecoder
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* QDEC:
* - Base Address: QDEC_DEV
* - Sclk: 32K/2Mhz
* - HW input : PHA, PHB, IDX
* - Sample Clock: Configurable, up to 2Mhz
* - Debounce Timer: Configurable
* - IRQ: QDECODER_IRQ_LP
*
*****************************************************************************************
* How to use Normal QDecoder
*****************************************************************************************
* To use the normal QDecoder mode, the following steps are mandatory:
*
* 1. configure the QDec pinmux
*
* 2. Init Qdec
* QDEC_StructInit(QDEC_InitTypeDef *QDEC_InitStruct)
* QDEC_Init(QDEC_TypeDef *QDec, QDEC_InitTypeDef *QDEC_InitStruct)
*
* 3. Reset sub-function if need,eg:
* QDEC_RstPC(QDEC_TypeDef *QDec)
* QDEC_RstRC(QDEC_TypeDef *QDec)
* QDEC_RsALL(QDEC_TypeDef *QDec)
*
* 4. Set Interrupt trigger condition as needed
*
* 5. enable velocity function as needed
*
* 6. Polling status or Get stauts according to the interrupt.
*
*****************************************************************************************
* How to enable velocity function
*****************************************************************************************
* To enable the velocity function, the following steps are mandatory:
*
* 1. Init VcMod and VTmr
* QDEC_SetVcMod(QDEC_TypeDef *QDec, u32 mode)
* QDEC_SetVTmr(QDEC_TypeDef *QDec, u32 duration)
*
* 2. Reset velocity status if need.
* QDEC_VtRst(QDEC_TypeDef *QDec)
*
* 3. Configure interrupt if needed
*
* 4. enable velocity function
* QDEC_VT_Cmd(QDEC_TypeDef *QDec, u32 NewState)
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types --------------------------------------------------------*/
/** @defgroup QDecoder_Exported_Types QDecoder Exported Types
* @{
*/
/**
* @brief QDecoder Init structure definition
*/
typedef struct {
u32 QD_SysClk; /*!< Specifies QDec Bus clock .
This parameter can be a value of @ref QDecoder_Bus_Clock_definitions */
u32 QD_SmpClk; /*!< Specifies Qdec sample clock.
This parameter must be set to a value in the (1/32 ~ 1) * QD_SysClk range. */
u32 QD_DebounceTmr; /*!< Specifies glitch width under QD_DebounceTmr * Tsysclk will be filtered.
This parameter must be set to a value in the 0x1-0x7ff range. */
u32 QD_Rc_Mod; /*!< Specifies rotation counter calc mode.
This parameter can be a value of @ref QDecoder_RC_mode_definition */
u32 QD_Cnt_Sc; /*!< Specifies position counter calc mode.
This parameter can be a value of @ref QDecoder_Cnt_Sc_definition */
u32 QD_MPC; /*!< Specifies max position counter value
This parameter must be set to a value in the 0x0-0xffff range. */
u32 QD_IdxMod; /*!< Specifies Qdecoder index signal work mode.
This parameter can be a value of @ref QDecoder_IDX_Mode_definition */
u32 QD_PC_Rst_Mod; /*!< Specifies Qdecoder position counter reset mode.
This parameter can be a value of @ref QDecoder_PC_Reset_Mode_definition*/
u32 QD_PC_Rst_Phase; /*!< Specifies Qdecoder position counter reset phase.
This parameter can be a value of @ref QDecoder_PC_Reset_PHASE_definition*/
u32 QD_VTmr; /*!< Specifies velocity measure timer in ms, .
This parameter can be a value of in the 0x0-0xffffff*Tsysclk range */
u32 QD_VCMod; /*!< Specifies velocity counter mode .
This parameter can be a value of @ref QDecoder_VC_Work_Mode_definitions */
}QDEC_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup QDecoder_Exported_Constants Qdecoder Exported Constants
* @{
*/
/** @defgroup QDecoder_Peripheral_definitions
* @{
*/
#define IS_QDEC_ALL_PERIPH(PERIPH) ((PERIPH) == QDEC_DEV)
/**
* @}
*/
/** @defgroup QDecoder_Bus_Clock_definitions
* @{
*/
#define QD_SYS_CLK_32K ((u32)32768)
#define QD_SYS_CLK_2M ((u32)2000000)
#define IS_QD_SYS_CLK(CLK) (((CLK) == QD_SYS_CLK_32K) || \
((CLK) == QD_SYS_CLK_2M))
/**
* @}
*/
/** @defgroup QDecoder_Clock_selection
* @{
*/
#define QDEC_CLK_SEL_32K ((u32)0x00000001)
#define QDEC_CLK_SEL_2M ((u32)0x00000000)
/**
* @}
*/
/** @defgroup QDecoder_RC_mode_definition
* @{
*/
#define QD_RC_COUNT_IDX ((u32)0x00000000 << 28)
#define QD_RC_COUNT_OF ((u32)0x00000001 << 28)
#define IS_QD_RC_COUNT_MOD(MODE) (((MODE) == QD_RC_COUNT_IDX) || \
((MODE) == QD_RC_COUNT_OF))
/**
* @}
*/
/** @defgroup QDecoder_Cnt_Sc_definition
* @{
*/
#define QD_PC_1PHSAE_1COUNTER ((u32)0x00000000 << 13)
#define QD_PC_2PHSAE_1COUNTER ((u32)0x00000001 << 13)
#define IS_QD_PC_PHASE_COUTER(CNT) (((CNT) == QD_PC_2PHSAE_1COUNTER) || \
((CNT) == QD_PC_1PHSAE_1COUNTER))
/**
* @}
*/
/** @defgroup QDecoder_PC_Chang_Level_definition
* @{
*/
#define QD_PC_CHG_1COUNTER ((u32)0x00000000 << 3)
#define QD_PC_CHG_2COUNTER ((u32)0x00000001 << 3)
#define QD_PC_CHG_4COUNTER ((u32)0x00000002 << 3)
#define IS_QD_PC_CHG_COUTER(CNT) (((CNT) == QD_PC_CHG_1COUNTER) || \
((CNT) == QD_PC_CHG_2COUNTER) ||((CNT) == QD_PC_CHG_4COUNTER))
/**
* @}
*/
/** @defgroup QDecoder_IDX_Mode_definition
* @{
*/
#define QD_IDX_DISABLE ((u32)0x00000000 << 31)
#define QD_IDX_NORMAL (((u32)0x00000001 << 31) | ((u32)0x00000000 << 5))
#define QD_IDX_INVERSE (((u32)0x00000001 << 31) | ((u32)0x00000001 << 5))
#define IS_QD_IDX_MODE(MODE) (((MODE) == QD_IDX_DISABLE) || \
((MODE) == QD_IDX_NORMAL) || ((MODE) == QD_IDX_INVERSE))
/**
* @}
*/
/** @defgroup QDecoder_PC_Reset_PHASE_definition
* @{
*/
#define QD_PC_RST_AUTO_IDX ((u32)0x00000001 << 6)
#define QD_PC_RST_PHASE_00 ((u32)0x00000000 )
#define QD_PC_RST_PHASE_01 ((u32)0x00000001)
#define QD_PC_RST_PHASE_10 ((u32)0x00000002)
#define QD_PC_RST_PHASE_11 ((u32)0x00000003)
#define IS_QD_PC_RST_PHASE(PHASE) (((PHASE) == QD_PC_RST_AUTO_IDX) || \
((PHASE) <= 0x00000003))
/**
* @}
*/
/** @defgroup QDecoder_PC_Reset_Mode_definition
* @{
*/
#define QD_PC_RST_DISABLE ((u32)0x00000000 << 3)
#define QD_PC_RST_ONCE ((u32)0x00000001 << 3)
#define QD_PC_RST_ALWAYS ((u32)0x00000002 << 3)
#define IS_QD_PC_RST_MODE(MODE) (((MODE) == QD_PC_RST_DISABLE) || \
((MODE) == QD_PC_RST_ONCE) || ((MODE) == QD_PC_RST_ALWAYS))
/**
* @}
*/
/** @defgroup QDecoder_VC_Work_Mode_definitions
* @{
*/
#define QD_VC_MOD_ABS ((u32)0x00000000 << 9)
#define QD_VC_MOD_PC ((u32)0x00000001 << 9)
#define IS_QD_VC_MODE(MODE) (((MODE) == QD_VC_MOD_ABS) || \
((MODE) == QD_VC_MOD_PC))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup QDecoder_Exported_Functions QDecoder Exported Functions
* @{
*/
/** @defgroup QDecoder_Exported_Normal_Functions QDec Exported Normal Functions
* @{
*/
void QDEC_DeInit(void);
void QDEC_Init(QDEC_TypeDef *QDec, QDEC_InitTypeDef *QDEC_InitStruct);
void QDEC_StructInit(QDEC_InitTypeDef *QDEC_InitStruct);
void QDEC_Cmd(QDEC_TypeDef *QDec, u32 NewState);
void QDEC_RstPC(QDEC_TypeDef *QDec);
void QDEC_RstRC(QDEC_TypeDef *QDec);
void QDEC_RstALL(QDEC_TypeDef *QDec);
void QDEC_SetCntSC(QDEC_TypeDef *QDec, u32 cnt_sc);
void QDEC_SetPChg(QDEC_TypeDef *QDec, u32 Pchange);
void QDEC_SetPCC(QDEC_TypeDef *QDec, u32 CmpPC);
void QDEC_SetMPC(QDEC_TypeDef *QDec, u32 MaxPC);
void QDEC_SetRCC(QDEC_TypeDef *QDec, u32 CmpRC);
u32 QDEC_GetRC(QDEC_TypeDef *QDec);
u32 QDEC_GetPhase(QDEC_TypeDef *QDec);
u32 QDEC_GetDir(QDEC_TypeDef *QDec);
u32 QDEC_GetPC(QDEC_TypeDef *QDec);
void QDEC_Idx_Cmd(QDEC_TypeDef *QDec, u32 NewState);
void QDEC_SetRstMod(QDEC_TypeDef *QDec, u32 mode, u32 phase);
void QDEC_SetVTmr(QDEC_TypeDef *QDec, u32 duration);
void QDEC_SetVcMod(QDEC_TypeDef *QDec, u32 mode);
void QDEC_VT_Cmd(QDEC_TypeDef *QDec, u32 NewState);
void QDEC_VtRst(QDEC_TypeDef *QDec);
void QDEC_SetVcUpLmt(QDEC_TypeDef *QDec, u32 limt);
void QDEC_SetVcLowLmt(QDEC_TypeDef *QDec, u32 limt);
u32 QDEC_GetVT(QDEC_TypeDef *QDec);
u32 QDEC_GetVC(QDEC_TypeDef *QDec);
u32 QDEC_GetVCCAP(QDEC_TypeDef *QDec);
u32 QDEC_GetPCCAP(QDEC_TypeDef *QDec);
void QDEC_INTConfig(QDEC_TypeDef *QDec, u32 INT, u32 newState);
void QDEC_INTMask(QDEC_TypeDef *QDec, u32 mask, u32 newState);
void QDEC_ClearINT(QDEC_TypeDef *QDec, u32 INT);
u32 QDEC_GetRawINT(QDEC_TypeDef *QDec);
u32 QDEC_GetIMR(QDEC_TypeDef *QDec);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup QDecoder_Register_Definitions QDecoder Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup QDEC_CLK_CFG
* @{
*****************************************************************************/
#define QD_SMP_DIV ((u32)0x0001F000) /*Bit[16:12], Divider for input signal sampling clock*/
#define QD_DBN_TM ((u32)0x000007FF) /*Bit[10:0], Divider for De-bounce timer clock*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_CTRL
* @{
*****************************************************************************/
#define QD_AXIS_EN ((u32)0x00000001 << 31) /*Bit[31], Qdecoder enable control */
#define QD_PC_RST ((u32)0x00000001 << 30) /*Bit[30], Qdecoder position counter reset control*/
#define QD_RC_RST ((u32)0x00000001 << 29) /*Bit[29], Qdecoder rotation counter reset control*/
#define QD_RC_MOD ((u32)0x00000001 << 28) /*Bit[38], Qdecoder rotation mode*/
#define QD_ALL_RST ((u32)0x00000001 << 27) /*Bit[37], Qdecoder ALL reset control*/
#define QD_RC_CMP_INT_EN ((u32)0x00000001 << 24) /*Bit[24], Qdecoder rotation counter compare INT enable*/
#define QD_PC_ERR_INT_EN ((u32)0x00000001 << 23) /*Bit[23], Qdecoder position counter error INT enable*/
#define QD_IDX_PULSE_INT_EN ((u32)0x00000001 << 22) /*Bit[22], Qdecoder index pulse INT enable*/
#define QD_RC_UF_INT_EN ((u32)0x00000001 << 21) /*Bit[21], Qdecoder rotation counter underflow INT enable*/
#define QD_RC_OF_INT_EN ((u32)0x00000001 << 20) /*Bit[20], Qdecoder rotation counter overflow INT enable*/
#define QD_PC_CMP_INT_EN ((u32)0x00000001 << 19) /*Bit[19], Qdecoder position counter compare INT enable*/
#define QD_DR_CH_INT_EN ((u32)0x00000001 << 18) /*Bit[18], Qdecoder direction changed INT enable*/
#define QD_PC_CHG_INT_EN ((u32)0x00000001 << 17) /*Bit[17], Qdecoder position counter changged INT enable*/
#define QD_PC_OF_INT_EN ((u32)0x00000001 << 16) /*Bit[16], Qdecoder position counter overflow INT enable*/
#define QD_PC_UF_INT_EN ((u32)0x00000001 << 15) /*Bit[15], Qdecoder position counter underflow INT enable*/
#define QD_PHASE_ILL_INT_EN ((u32)0x00000001 << 14) /*Bit[14], Qdecoder phase changed illegal INT enable*/
#define QD_COUNTER_INT ((u32)0x01FFC000) /*Qdecoder counter related INT*/
#define QD_CNT_SC ((u32)0x00000001 << 13) /*Bit[13], Qdecoder number of phase state changed for the position accumulation counter*/
#define QD_DB_EN ((u32)0x00000001 << 12) /*Bit[12], Qdecoder de-bouncing enable*/
#define QD_PC_CHG_LEVEL ((u32)0x00000003 << 3) /*Bit[4:3], Qdecoder position changed interrupt trigger level*/
#define QD_MANUAL_INIT ((u32)0x00000001 << 2) /*Bit[2], Qdecoder manually initial disable*/
#define QD_INIT_PHASE ((u32)0x00000003) /*Bit[1:0], Qdecoder init pahse*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_MPC
* @{
*****************************************************************************/
#define QD_CMP_PC ((u32)0x0000FFFF << 16) /*Bit[31:16], Qdecoder position compare register*/
#define QD_MAX_PC ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder Max position counter register*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_RC
* @{
*****************************************************************************/
#define QD_CMP_RC ((u32)0x00000FFF) /*Bit[11:0], Qdecoder rotation compare register*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_PC
* @{
*****************************************************************************/
#define QD_RC ((u32)0x00000FFF << 20) /*Bit[31:20], Qdecoder current rotation counter*/
#define QD_PHASE_STATE ((u32)0x00000003 << 18) /*Bit[19:18], Qdecoder current phase state*/
#define QD_AL_STATUS ((u32)0x00000001 << 17) /*Bit[17], Qdecoder auto load status*/
#define QD_DIR_STATE ((u32)0x00000001 <<16) /*Bit[16], Qdecoder move direction*/
#define QD_PC ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder current position counter*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_ISC
* @{
*****************************************************************************/
#define QD_IDX_EN ((u32)0x00000001 << 31) /*Bit[31], Qdecoder index enable*/
#define QD_AUTO_IDX_EN ((u32)0x00000001 << 6) /*Bit[6], Qdecoder Auto-index enable*/
#define BIT_QD_IDX_INVERSE ((u32)0x00000001 << 5) /*Bit[5], Qdecoder index signal input inverse */
#define QD_POS_RST ((u32)0x00000003 << 3) /*Bit[4:3], Qdecoder position reset control*/
#define QD_POS_RST_PHASE ((u32)0x00000003) /*Bit[1:0], Qdecoder reset phase setting*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_VCTRL
* @{
*****************************************************************************/
#define QD_VT_DIV ((u32)0x000000FF << 16) /*Bit[23:16], Qdecoder Velocity clock divider*/
#define QD_VMUC_MOD ((u32)0x00000001 << 9) /*Bit[9], Qdecoder Velocity counter increase mode*/
#define QD_VUPLMT_INT_EN ((u32)0x00000001 << 7) /*Bit[7], Qdecoder Velocity up limit interrupt enable */
#define QD_VLOWLMT_INT_EN ((u32)0x00000003 << 6) /*Bit[6], Qdecoder Velocity low limit interrupt enable*/
#define QD_VCCAP_INT_EN ((u32)0x00000001 << 4) /*Bit[4], Qdecoder Velocity counter capture interrupt enable */
#define QD_VELOCITY_INT ((u32)0x000000D0)
#define QD_VMUC_RST ((u32)0x00000001 << 2) /*Bit[2], Qdecoder Velocity reset*/
#define QD_VMUC_EN ((u32)0x00000001) /*Bit[0], Qdecoder Velocity enable*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_VC
* @{
*****************************************************************************/
#define QD_VC ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder velocity accumulation counter*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_VCCAP
* @{
*****************************************************************************/
#define QD_VCCAP ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder velocity accumulation counter capture register*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_PCCAP
* @{
*****************************************************************************/
#define QD_PCCAP ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder position counter capture register*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_VTRLD
* @{
*****************************************************************************/
#define QD_VTRLD ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder velocity timer reload register*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_VT
* @{
*****************************************************************************/
#define QD_VT ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder velocity timer register*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_VCOMP
* @{
*****************************************************************************/
#define QD_VUP_LMT ((u32)0x0000FFFF << 16) /*Bit[31:16], Qdecoder velocity counter up limit register*/
#define QD_VLOW_LMT ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder velocity counter low limit register*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_IMR
* @{
*****************************************************************************/
#define QD_RC_COMP_INT_MASK ((u32)0x00000001 << 15) /*Bit[15], Qdecoder rotation counter compare INT mask*/
#define QD_VUPLMT_INT_MASK ((u32)0x00000001 << 13) /*Bit[13], Qdecoder Velocity up limit interrupt mask */
#define QD_VLOWLMT_INT_MASK ((u32)0x00000001 << 12) /*Bit[12], Qdecoder Velocity low limit interrupt mask*/
#define QD_VCCAP_INT_MASK ((u32)0x00000001 << 10) /*Bit[10], Qdecoder Velocity counter capture interrupt mask*/
#define QD_PC_ERR_INT_MASK ((u32)0x00000001 << 9) /*Bit[9], Qdecoder position counter error INT mask*/
#define QD_IDX_PULSE_INT_MASK ((u32)0x00000001 << 8) /*Bit[8], Qdecoder index pulse INT mask*/
#define QD_RC_UF_INT_MASK ((u32)0x00000001 << 7) /*Bit[7], Qdecoder rotation counter underflow INT mask*/
#define QD_RC_OF_INT_MASK ((u32)0x00000001 << 6) /*Bit[6], Qdecoder rotation counter overflow INT mask*/
#define QD_PC_CMP_INT_MASK ((u32)0x00000001 << 5) /*Bit[5], Qdecoder position counter compare INT mask*/
#define QD_DR_CH_INT_MASK ((u32)0x00000001 << 4) /*Bit[4], Qdecoder direction changed INT mask*/
#define QD_PHASE_ILL_INT_MASK ((u32)0x00000001 << 3) /*Bit[3], Qdecoder phase changed illegal INT mask*/
#define QD_PC_UF_INT_MASK ((u32)0x00000001 << 2) /*Bit[2], Qdecoder position counter underflow INT mask*/
#define QD_PC_OF_INT_MASK ((u32)0x00000001 << 1) /*Bit[1], Qdecoder position counter overflow INT mask*/
#define QD_PC_CHG_INT_MASK ((u32)0x00000001 << 0) /*Bit[0], Qdecoder position counter changed INT mask*/
#define QD_ALL_INT_MASK ((u32)0x0000B7FF)
/** @} */
/**************************************************************************//**
* @defgroup QDEC_ISR
* @{
*****************************************************************************/
#define QD_RC_COMP_INT_STATUS ((u32)0x00000001 << 15) /*Bit[15], Qdecoder rotation counter compare INT status*/
#define QD_VUPLMT_INT_STATUS ((u32)0x00000001 << 13) /*Bit[13], Qdecoder Velocity up limit interrupt status */
#define QD_VLOWLMT_INT_STATUS ((u32)0x00000001 << 12) /*Bit[12], Qdecoder Velocity low limit interrupt status*/
#define QD_VCCAP_INT_STATUS ((u32)0x00000001 << 10) /*Bit[10], Qdecoder Velocity counter capture interrupt status*/
#define QD_PC_ERR_INT_STATUS ((u32)0x00000001 << 9) /*Bit[9], Qdecoder position counter error INT status*/
#define QD_IDX_PULSE_INT_STATUS ((u32)0x00000001 << 8) /*Bit[8], Qdecoder index pulse INT status*/
#define QD_RC_UF_INT_STATUS ((u32)0x00000001 << 7) /*Bit[7], Qdecoder rotation counter underflow INT status*/
#define QD_RC_OF_INT_STATUS ((u32)0x00000001 << 6) /*Bit[6], Qdecoder rotation counter overflow INT status*/
#define QD_PC_CMP_INT_STATUS ((u32)0x00000001 << 5) /*Bit[5], Qdecoder position counter compare INT status*/
#define QD_DR_CH_INT_STATUS ((u32)0x00000001 << 4) /*Bit[4], Qdecoder direction changed INT status*/
#define QD_PHASE_ILL_INT_STATUS ((u32)0x00000001 << 3) /*Bit[3], Qdecoder phase changed illegal INT status*/
#define QD_PC_UF_INT_STATUS ((u32)0x00000001 << 2) /*Bit[2], Qdecoder position counter underflow INT status*/
#define QD_PC_OF_INT_STATUS ((u32)0x00000001 << 1) /*Bit[1], Qdecoder position counter overflow INT status*/
#define QD_PC_CHG_INT_STATUS ((u32)0x00000001 << 0) /*Bit[0], Qdecoder position counter changed INT status*/
#define QD_ALL_INT_STATUS ((u32)0x0000B7FF)
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
#endif
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/

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/*
* rtl8721d_ram_libc.h
*
* Definitions for RTL library functions
*/
#ifndef _RTL8721D_RAM_LIBC_H_
#define _RTL8721D_RAM_LIBC_H_
#include <basic_types.h>
#include <diag.h>
#include <va_list.h>
extern int _rtl_vsprintf(char *buf, size_t size, const char *fmt, const int *dp);
extern int _rtl_printf(IN const char* fmt, ...);
extern int _rtl_sprintf(char* str, const char* fmt, ...);
extern int _rtl_snprintf(char* str, size_t size, const char* fmt, ...);
extern int _rtl_vsnprintf(char *buf, size_t size, const char *fmt, va_list ap);
extern int _rtl_sscanf(const char *buf, const char *fmt, ...);
#endif /* _RTL8721D_RAM_LIBC_H_ */

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/**
******************************************************************************
* @file rtl8721d_rtc.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the RTC firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_RTC_H_
#define _RTL8721D_RTC_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup RTC
* @brief RTC driver modules
* @{
*/
/** @addtogroup RTC
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* The real-time clock (RTC) is an independent BCD timer/counter.
* One 32-bit register contains the seconds, minutes, hours (12 or 24-hour format) expressed in binary coded decimal format (BCD).
* and days expressed in binary format.
* Daylight saving time compensation can also be performed.
* One programmable alarm contains seconds, minutes, hours and days with interrupt function,
* and can be triggered by any combination of the time fields.
* A digital calibration feature is available to compensate for some deviation.
* After backup domain reset, all RTC registers are protected against possible parasitic
* write accesses.
* Support a programmable register for RTC trigger SDM32K periodical calibration with active and power save mode.
* As long as the supply voltage remains in the operating range, the RTC never stops,
* regardless of the device status (Run mode, low power mode or under reset).
*
*****************************************************************************************
* How to use RTC
*****************************************************************************************
* To use the RTC, the following steps are mandatory:
*
* 1. Initialize the RTC Clock Source.
* RCC_PeriphClockSource_RTC()
*
* 2. Fill the variable RTC_InitStruct with default parameters, or set the desired parameters manually:
* RTC_StructInit(&RTC_InitStruct)
*
* 3. configure the RTC peripheral with the corresponding configurations contained in RTC_InitStruct:
* Call RTC_Init(&RTC_InitStruct)
*
* 4. Fill the variable RTC_TimeStruct with default parameters() (Time = 00d:00h:00min:00sec)
* RTC_TimeStructInit(&RTC_TimeStruct)
* setting the desired calendar time parameters manually.
*
* 5. Set calendar time:
* RTC_SetTime(RTC_Format_BIN, &RTC_TimeStruct).
*
* 6. If RTC_OUT output is needed, the pinmux configuration is as follows:
* Pinmux_Config(PinName, PINMUX_FUNCTION_RTCOUT)
*
*
*****************************************************************************************
* How to use Alarm
*****************************************************************************************
* To use the Alarm, the following steps are mandatory:
*
* 1. Configure the RTC as described in the first part of this driver.
*
* 2. Fill the variable RTC_AlarmStruct of type RTC_AlarmTypeDef with default parameters
* RTC_AlarmStructInit(&RTC_AlarmStruct)
* or setting the desired Alarm time parameters manually.
*
* 3. configure Alarm:
* RTC_SetAlarm(RTC_Format_BIN, &RTC_AlarmStruct)
*
* 4. Enable alarm and alarm interrupt.
* RTC_AlarmCmd(ENABLE)
*
* 5. Enable IRQ as follows:
* InterruptRegister(RTC_IntHandler, RTC_IRQ, NULL, 4);
* InterruptEn(RTC_IRQ, 4);
*
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RTC_Exported_Types RTC Exported Types
* @{
*/
/**
* @brief RTC Init structure definition
*/
typedef struct {
u32 RTC_HourFormat; /*!< Specifies the RTC Hour Format.
This parameter can be a value of @ref RTC_Hour_Formats */
u32 RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
This parameter must be a value of @ref RTC_Asynchronous_Predivider */
u32 RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
This parameter must be a value of @ref RTC_Synchronous_Predivider */
u32 RTC_DayThreshold; /*!< Specifies the RTC Day Threshold value.
This parameter must be a value of @ref RTC_Day_Threshold */
} RTC_InitTypeDef;
/**
* @brief RTC Time structure definition
*/
typedef struct
{
u16 RTC_Days; /*!< Day in binary format 9bits 0~0x1FF */
u8 RTC_Hours; /*!< Specifies the RTC Time Hour.
This parameter must be set to a value in the 1-12 range
if the RTC_HourFormat_12 is selected or 0-23 range if
the RTC_HourFormat_24 is selected. */
u8 RTC_Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be set to a value in the 0-59 range. */
u8 RTC_Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be set to a value in the 0-59 range. */
u8 RTC_H12_PMAM; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
}RTC_TimeTypeDef;
/**
* @brief RTC Alarm structure definition
*/
typedef struct
{
RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
u32 RTC_AlarmMask; /*!< Specifies the RTC Alarm1 Masks(H:M:S).
This parameter can be a value of @ref RTC_AlarmMask1_Definitions */
u32 RTC_Alarm2Mask; /*!< Specifies the RTC Alarm2 Masks Day).
This parameter can be a value of @ref RTC_AlarmMask2_Definitions */
}RTC_AlarmTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RTC_Exported_Constants RTC Exported Constants
* @{
*/
/** @defgroup RTC_Input_parameter_format_definitions
* @{
*/
#define RTC_Format_BIN ((u32)0x000000000)
#define RTC_Format_BCD ((u32)0x000000001)
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
/**
* @}
*/
/** @defgroup RTC_Hour_Formats
* @{
*/
#define RTC_HourFormat_24 ((u32)0x00000000)
#define RTC_HourFormat_12 ((u32)0x00000080)
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
((FORMAT) == RTC_HourFormat_24))
/**
* @}
*/
/** @defgroup RTC_Asynchronous_Predivider
* @{
*/
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FF)
/**
* @}
*/
/** @defgroup RTC_Synchronous_Predivider
* @{
*/
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FF)
/**
* @}
*/
/** @defgroup RTC_Day_Threshold
* @{
*/
#define RTC_DAYTHRES_MSK ((u32)0xFF800000)
#define IS_RTC_DAY_THRES(DAYS) ((DAYS) <= 0x1FF)
/**
* @}
*/
/** @defgroup RTC_Time_Definitions
* @{
*/
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
/**
* @}
*/
/** @defgroup RTC_AM_PM_Definitions
* @{
*/
#define RTC_H12_AM ((u8)0x00) //AM or 24-hour format
#define RTC_H12_PM ((u8)0x01) //PM
#define IS_RTC_H12_AMPM(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
/**
* @}
*/
/** @defgroup RTC_AlarmMask1_Definitions
* @{
*/
#define RTC_AlarmMask_None ((u32)0x00000000)
#define RTC_AlarmMask_Hours ((u32)0x00800000)
#define RTC_AlarmMask_Minutes ((u32)0x00008000)
#define RTC_AlarmMask_Seconds ((u32)0x00000080)
#define RTC_AlarmMask_All ((u32)0x00808080)
#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F) == 0)
/**
* @}
*/
/** @defgroup RTC_AlarmMask2_Definitions
* @{
*/
#define RTC_Alarm2Mask_None ((u32)0x00000000)
#define RTC_Alarm2Mask_Days ((u32)0x00000200)
#define IS_ALARM2_MASK(MASK) (((MASK) & ~RTC_Alarm2Mask_Days) == 0)
/**
* @}
*/
/** @defgroup RTC_Alarms_Definitions
* @{
*/
#define RTC_Alarm ((u32)0x00000100)
#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_Alarm)
#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & RTC_Alarm) != (u32)0)
/**
* @}
*/
/** @defgroup RTC_Alarms_Interrupt_Definitions
* @{
*/
#define RTC_Alarm_IntEn ((u32)0x00001000)
/**
* @}
*/
/** @defgroup RTC_DayLightSaving_Definitions
* @{
*/
#define RTC_DayLightSaving_SUB1H ((u32)0x00000002)
#define RTC_DayLightSaving_ADD1H ((u32)0x00000001)
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
((SAVE) == RTC_DayLightSaving_ADD1H))
#define RTC_StoreOperation_Reset ((u32)0x00000000)
#define RTC_StoreOperation_Set ((u32)0x00000004)
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
((OPERATION) == RTC_StoreOperation_Set))
/**
* @}
*/
/** @defgroup RTC_Output_selection_Definitions
* @{
*/
#define RTC_Output_Disable ((u32)0x00000000)
#define RTC_Output_Alarm ((u32)0x00000020) ////wakeup
#define RTC_Output_clkspre ((u32)0x00000040) ////1Hz
#define RTC_Output_clkapre ((u32)0x00000060) ////256Hz
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
((OUTPUT) == RTC_Output_Alarm) || \
((OUTPUT) == RTC_Output_clkspre) || \
((OUTPUT) == RTC_Output_clkapre))
/**
* @}
*/
/** @defgroup RTC_Smooth_Calibration_Definitions
* @{
*/
#define RTC_CalibPeriod_1MIN ((u32)0x00000000)
#define RTC_CalibPeriod_2MIN ((u32)0x00010000)
#define RTC_CalibPeriod_3MIN ((u32)0x00020000)
#define RTC_CalibPeriod_4MIN ((u32)0x00030000)
#define RTC_CalibPeriod_5MIN ((u32)0x00040000)
#define RTC_CalibPeriod_6MIN ((u32)0x00050000)
#define RTC_CalibPeriod_7MIN ((u32)0x00060000)
#define RTC_CalibPeriod_8MIN ((u32)0x00070000)
#define IS_RTC_CALIB_PERIOD(DCP) (((DCP) == RTC_CalibPeriod_1MIN) || \
((DCP) == RTC_CalibPeriod_2MIN) || \
((DCP) == RTC_CalibPeriod_3MIN) || \
((DCP) == RTC_CalibPeriod_4MIN) || \
((DCP) == RTC_CalibPeriod_5MIN) || \
((DCP) == RTC_CalibPeriod_6MIN) || \
((DCP) == RTC_CalibPeriod_7MIN) || \
((DCP) == RTC_CalibPeriod_8MIN))
#define RTC_Calib_Disable ((u32)0x00000000)
#define RTC_Calib_Enable ((u32)0x00008000)
#define IS_RTC_CALIB_ENABLE(DCE) (((DCE) == RTC_Calib_Disable) || \
((DCE) == RTC_Calib_Enable))
#define RTC_CalibSign_Positive ((u32)0x00000000)
#define RTC_CalibSign_Negative ((u32)0x00004000)
#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
((SIGN) == RTC_CalibSign_Negative))
#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) <= 0x7F)
/**
* @}
*/
/** @defgroup RTC_32K_Auto_Calibration_Definitions
* @{
*/
#define RTC_32K_AUTOCAL_DISABLE ((u32)0x00000000)
#define RTC_32K_AUTOCAL_MINUTES ((u32)0x00000001)
#define RTC_32K_AUTOCAL_HOURS ((u32)0x00000002)
#define RTC_32K_AUTOCAL_DAYS ((u32)0x00000003)
#define IS_RTC_32K_AUTOCAL_SIGN(SIGN) (((SIGN) == RTC_32K_AUTOCAL_DISABLE) || \
((SIGN) == RTC_32K_AUTOCAL_MINUTES) || \
((SIGN) == RTC_32K_AUTOCAL_HOURS) || \
((SIGN) == RTC_32K_AUTOCAL_DAYS))
/**
* @}
*/
/**
* @}
*/
/** @defgroup RTC_Exported_Functions RTC Exported Functions
* @{
*/
_LONG_CALL_ u32 RTC_BypassShadowCmd(u32 NewState);
_LONG_CALL_ void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
_LONG_CALL_ u32 RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
_LONG_CALL_ void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
_LONG_CALL_ u32 RTC_SetTime(u32 RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
_LONG_CALL_ void RTC_GetTime(u32 RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
_LONG_CALL_ void RTC_DayIntClear(void);
_LONG_CALL_ u32 RTC_DayIntCmd(u32 NewState);
_LONG_CALL_ u32 RTC_DayThresSet(u32 DayThres);
_LONG_CALL_ u32 RTC_DayThresGet(void);
_LONG_CALL_ u32 RTC_SetAlarm(u32 RTC_Format, RTC_AlarmTypeDef* RTC_AlarmStruct);
_LONG_CALL_ void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
_LONG_CALL_ void RTC_GetAlarm(u32 RTC_Format, RTC_AlarmTypeDef* RTC_AlarmStruct);
_LONG_CALL_ void RTC_AlarmCmd(u32 NewState);
_LONG_CALL_ void RTC_AlarmClear(void);
_LONG_CALL_ u32 RTC_DayLightSavingConfig(u32 RTC_DayLightSaving, u32 RTC_StoreOperation);
_LONG_CALL_ u32 RTC_GetStoreOperation(void);
_LONG_CALL_ u32 RTC_OutputConfig(u32 RTC_Output);
_LONG_CALL_ u32 RTC_SmoothCalibConfig(u32 CalibSign, u32 Value, u32 CalibPeriod, u32 Calib_Enable);
_LONG_CALL_ u32 RTC_32KAutoCalibConfig(u32 Cal_Period, u32 Unit_Sel);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup RTC_Register_Definitions RTC Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup RTC_TR
* @{
*****************************************************************************/
#define RTC_TR_DAY ((u32)0xFF800000)
#define RTC_TR_PM ((u32)0x00400000)
#define RTC_TR_HT ((u32)0x00300000)
#define RTC_TR_HU ((u32)0x000F0000)
#define RTC_TR_MNT ((u32)0x00007000)
#define RTC_TR_MNU ((u32)0x00000F00)
#define RTC_TR_ST ((u32)0x00000070)
#define RTC_TR_SU ((u32)0x0000000F)
/** @} */
/**************************************************************************//**
* @defgroup RTC_CR
* @{
*****************************************************************************/
#define RTC_CR_DOVTHIE ((u32)0x00010000)
#define RTC_CR_ALRAIE ((u32)0x00001000)
#define RTC_CR_ALRAE ((u32)0x00000100)
#define RTC_CR_FMT ((u32)0x00000080)
#define RTC_CR_OSEL ((u32)0x00000060)
#define RTC_CR_BYPSHAD ((u32)0x00000008)
#define RTC_CR_BCK ((u32)0x00000004)
#define RTC_CR_SUB1H ((u32)0x00000002)
#define RTC_CR_ADD1H ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup RTC_ISR
* @{
*****************************************************************************/
#define RTC_ISR_RECALPF ((u32)0x00010000)
#define RTC_ISR_DOVTHF ((u32)0x00008000)
#define RTC_ISR_ALRAF ((u32)0x00000100)
#define RTC_ISR_INIT ((u32)0x00000080)
#define RTC_ISR_INITF ((u32)0x00000040)
#define RTC_ISR_RSF ((u32)0x00000020)
#define RTC_ISR_INITS ((u32)0x00000010)
#define RTC_ISR_ALMWF ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup RTC_PRER
* @{
*****************************************************************************/
#define RTC_PRER_PREDIV_A ((u32)0x01FF0000)
#define RTC_PRER_PREDIV_S ((u32)0x000001FF)
/** @} */
/**************************************************************************//**
* @defgroup RTC_CALIBR
* @{
*****************************************************************************/
#define RTC_CALIBR_CALP ((u32)0x00070000)
#define RTC_CALIBR_DCE ((u32)0x00008000)
#define RTC_CALIBR_DCS ((u32)0x00004000)
#define RTC_CALIBR_DC ((u32)0x0000007F)
/** @} */
/**************************************************************************//**
* @defgroup RTC_ALRMAR
* @{
*****************************************************************************/
#define RTC_ALRMAR_MSK2 ((u32)0x00800000)
#define RTC_ALRMAR_PM ((u32)0x00400000)
#define RTC_ALRMAR_HT ((u32)0x00300000)
#define RTC_ALRMAR_HU ((u32)0x000F0000)
#define RTC_ALRMAR_MSK1 ((u32)0x00008000)
#define RTC_ALRMAR_MNT ((u32)0x00007000)
#define RTC_ALRMAR_MNU ((u32)0x00000F00)
#define RTC_ALRMAR_MSK0 ((u32)0x00000080)
#define RTC_ALRMAR_ST ((u32)0x00000070)
#define RTC_ALRMAR_SU ((u32)0x0000000F)
/** @} */
/**************************************************************************//**
* @defgroup RTC_ALRMBR
* @{
*****************************************************************************/
#define RTC_ALRMBR_MSK3 ((u32)0x00000200)
#define RTC_ALRMBR_DT ((u32)0x000001FF)
/** @} */
/**************************************************************************//**
* @defgroup RTC_WPR
* @{
*****************************************************************************/
#define RTC_WPR_KEY ((u32)0x000000FF)
/** @} */
/**************************************************************************//**
* @defgroup RTC_CLKACALR
* @{
*****************************************************************************/
#define RTC_32K_AUTOCAL_SEL ((u32)0x00000003)
#define RTC_AUTOCAL_THRES_MSK ((u32)0x000000FC)
#define IS_RTC_32K_AUTOCALIB_THRES(THRES) (THRES <= 0x3F)
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Masks Definition */
#define RTC_TR_RESERVED_MASK ((u32)0xFFFF7F7F)
#define INITMODE_TIMEOUT ((u32) 0x00010000)
#define SYNCHRO_TIMEOUT ((u32) 0x00020000)
#define RECALPF_TIMEOUT ((u32) 0x00020000)
#define ALARMDIS_TIMEOUT ((u32) 0x00020000)
#endif //_RTL8721D_RTC_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_sdio.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the SDIO firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_SDIO_H_
#define _RTL8710B_SDIO_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup SDIO
* @brief SDIO driver modules
* @{
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup SDIO_Exported_Types SDIO Exported Types
* @{
*/
/**
* @brief SDIO Init structure definition
*/
typedef struct {
/* TXBD */
u32 TXBD_BAR; /*!< Specifies TXBD base address */
u32 TXBD_RING_SIZE; /*!< Specifies TXBD ring size, This parameter must be set to a value in the 0-0xFFFF range. */
u32 TX_BUFFER_SIZE; /*!< Specifies TX buffer size, This parameter must be set to a value in the 0-0xFF range. */
/* RXBD */
u32 RXBD_BAR; /*!< Specifies RXBD base address */
u32 RXBD_RING_SIZE; /*!< Specifies RXBD ring size, This parameter must be set to a value in the 0-0xFFFF range. */
u32 RXBD_FREE_TH; /*!< the threshold of free RX BD count to trigger interrupt */
} SDIO_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SDIO_Exported_Constants SDIO Exported Constants
* @{
*/
/** @defgroup SDIO_MP_CMD_definitions The SDIO MP CMD definations
* @{
*/
#define SDIO_MP_START 1
#define SDIO_MP_STOP 2
#define SDIO_MP_LOOPBACK 3
#define SDIO_MP_STATUS 4
#define SDIO_MP_READ_REG8 5
#define SDIO_MP_READ_REG16 6
#define SDIO_MP_READ_REG32 7
#define SDIO_MP_WRITE_REG8 8
#define SDIO_MP_WRITE_REG16 9
#define SDIO_MP_WRITE_REG32 10
#define SDIO_MP_WAKEUP 11 // wakeup the SDIO task manually, for debugging
#define SDIO_MP_DUMP 12 // start/stop to dump the SDIO status periodically
#define SDIO_MP_CTX 13 // setup continue TX test
#define SDIO_MP_CRX 14 // setup continue RX test
#define SDIO_MP_CRX_DA 15 // setup continue RX with dynamic allocate RX Buf test
#define SDIO_MP_CRX_STOP 16 // setup continue RX test
#define SDIO_MP_DBG_MSG 17 // Debug message On/Off
/**
* @}
*/
/** @defgroup SDIO_RPWM_definitions The SDIO RPWM definations
* @{
*/
#define RPWM2_ACT_BIT (0x00000001 << 0) // Active
#define RPWM2_SLEEP_BIT 0 // Sleep
#define RPWM2_DSTANDBY_BIT (0x00000001 << 1) // Deep Standby
#define RPWM2_PG_BIT 0 // Power Gated
#define RPWM2_FBOOT_BIT (0x00000001 << 2) // fast reboot
#define RPWM2_NBOOT_BIT 0 // normal reboot
#define RPWM2_WKPIN_0_BIT (0x00000001 << 3) // enable GPIO wakeup pin 0
#define RPWM2_WKPIN_1_BIT (0x00000001 << 4) // enable GPIO wakeup pin 1
#define RPWM2_WKPIN_2_BIT (0x00000001 << 5) // enable GPIO wakeup pin 2
#define RPWM2_WKPIN_3_BIT (0x00000001 << 6) // enable GPIO wakeup pin 3
#define RPWM2_WKPIN_0_LV_BIT (0x00000001 << 7) // GPIO wakeup pin 0 wakeup level
#define RPWM2_WKPIN_1_LV_BIT (0x00000001 << 8) // GPIO wakeup pin 1 wakeup level
#define RPWM2_WKPIN_2_LV_BIT (0x00000001 << 9) // GPIO wakeup pin 2 wakeup level
#define RPWM2_WKPIN_3_LV_BIT (0x00000001 << 10) // GPIO wakeup pin 3 wakeup level
#define RPWM2_CG_BIT (0x00000001 << 11) // Clock Gated
#define RPWM2_ACK_BIT (0x00000001 << 14) // Acknowledge
#define RPWM2_TOGGLE_BIT (0x00000001 << 15) // Toggle bit
/**
* @}
*/
/** @defgroup SDIO_CPWM2_definitions The SDIO CPWM2 definations
* @{
*/
#define CPWM2_ACT_BIT (0x00000001 << 0) // Active
#define CPWM2_DSTANDBY_BIT (0x00000001 << 1) // Deep Standby
#define CPWM2_FBOOT_BIT (0x00000001 << 2) // fast reboot
#define CPWM2_INIC_FW_RDY_BIT (0x00000001 << 3) // is the iNIC FW(1) or Boot FW(0)
#define CPWM2_TOGGLE_BIT (0x00000001 << 15) // Toggle bit
/**
* @}
*/
/** @defgroup SDIO_CPWM1_definitions The SDIO CPWM1 definations
* @{
*/
#define CPWM1_TOGGLE_BIT (0x00000001 << 7) // Toggle bit
/**
* @}
*/
/** @defgroup SDIO_EVENT_definitions The SDIO EVENT definations
* @{
*/
#define SDIO_EVENT_RX_PKT_RDY (0x00000001 << 1) // A new SDIO packet ready
#define SDIO_EVENT_DUMP (0x00000001 << 3) // SDIO status dump periodically Enable
#define SDIO_EVENT_EXIT (0x00000001 << 27) // Request to exit the SDIO task
#define SDIO_EVENT_MP_STOPPED (0x00000001 << 28) // The SDIO task is stopped
#define SDIO_EVENT_IRQ_STOPPED (0x00000001 << 29) // The SDIO task is stopped
#define SDIO_EVENT_TX_STOPPED (0x00000001 << 30) // The SDIO task is stopped
#define SDIO_EVENT_RX_STOPPED (0x00000001 << 31) // The SDIO task is stopped
/**
* @}
*/
/**
* @}
*/
/** @defgroup SDIO_Exported_Functions SDIO Exported Functions
* @{
*/
_LONG_CALL_ void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
_LONG_CALL_ void SDIO_Init(SDIO_InitTypeDef* SDIOInit_Struct);
_LONG_CALL_ void SDIO_INTClear(void);
_LONG_CALL_ VOID SDIO_INTConfig(u16 IntMask, u32 NewState);
_LONG_CALL_ u8 SDIO_RPWM1_Get(void);
_LONG_CALL_ u16 SDIO_RPWM2_Get(void);
_LONG_CALL_ void SDIO_CPWM1_Set(u8 Val);
_LONG_CALL_ void SDIO_CPWM2_Set(u16 Val, u32 Newstate);
_LONG_CALL_ u16 SDIO_RXBD_RPTR_Get(void);
_LONG_CALL_ void SDIO_RXBD_WPTR_Set(u16 Val);
_LONG_CALL_ u16 SDIO_TXBD_WPTR_Get(void);
_LONG_CALL_ void SDIO_TXBD_RPTR_Set(u16 Val);
_LONG_CALL_ void SDIO_DMA_Reset(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#define HAL_SDIO_READ32(addr) HAL_READ32(SDIO_DEVICE_REG_BASE, addr)
#define HAL_SDIO_WRITE32(addr, value) HAL_WRITE32(SDIO_DEVICE_REG_BASE, addr, value)
#define HAL_SDIO_READ16(addr) HAL_READ16(SDIO_DEVICE_REG_BASE, addr)
#define HAL_SDIO_WRITE16(addr, value) HAL_WRITE16(SDIO_DEVICE_REG_BASE, addr, value)
#define HAL_SDIO_READ8(addr) HAL_READ8(SDIO_DEVICE_REG_BASE, addr)
#define HAL_SDIO_WRITE8(addr, value) HAL_WRITE8(SDIO_DEVICE_REG_BASE, addr, value)
/* Registers Definitions --------------------------------------------------------*/
#define REG_SPDIO_TXBD_ADDR 0xA0 // 4 Bytes
#define REG_SPDIO_TXBD_SIZE 0xA4 // 4 Bytes
#define REG_SPDIO_TXBD_WPTR 0xA8 // 2 Bytes
#define REG_SPDIO_TXBD_RPTR 0xAC // 2 Bytes
#define REG_SPDIO_RXBD_ADDR 0xB0 // 4 Bytes
#define REG_SPDIO_RXBD_SIZE 0xB4 // 2 Bytes
#define REG_SPDIO_RXBD_C2H_WPTR 0xB6 // 2 Bytes
#define REG_SPDIO_RXBD_C2H_RPTR 0xB8 // 2 Bytes
#define REG_SPDIO_HCI_RX_REQ 0xBA // 1 Byte
#define REG_SPDIO_CPU_RST_DMA 0xBB // 1 Byte
#define REG_SPDIO_RX_REQ_ADDR 0xBC // 2 Bytes
#define REG_SPDIO_CPU_INT_MASK 0xC0 // 2 Bytes
#define REG_SPDIO_CPU_INT_STAS 0xC2 // 2 Bytes
#define REG_SPDIO_CCPWM 0xC4 // 1 Byts
#define REG_SPDIO_CPU_IND 0xC5 // 1 Byte
#define REG_SPDIO_CCPWM2 0xC6 // 2 Bytes
#define REG_SPDIO_CPU_H2C_MSG 0xC8 // 4 Bytes
#define REG_SPDIO_CPU_C2H_MSG 0xCC // 4 Bytes
#define REG_SPDIO_CRPWM 0xD0 // 1 Bytes
#define REG_SPDIO_CRPWM2 0xD2 // 2 Bytes
#define REG_SPDIO_AHB_DMA_CTRL 0xD4 // 4 Bytes
#define REG_SPDIO_RXBD_CNT 0xD8 // 4 Bytes
#define REG_SPDIO_TX_BUF_UNIT_SZ 0xD9 // 1 Bytes
#define REG_SPDIO_RX_BD_FREE_CNT 0xDA // 2 Bytes
#define REG_SPDIO_CPU_H2C_MSG_EXT 0xDC // 4 Bytes
#define REG_SPDIO_CPU_C2H_MSG_EXT 0xE0 // 4 Bytes
/******************** Bits definition for REG_SPDIO_CPU_RST_DMA register *******************/
#define BIT_CPU_RST_SDIO_DMA BIT(7)
/******************** Bits definition for REG_SPDIO_CPU_INT_MASK/REG_SPDIO_CPU_INT_STAS register *******************/
#define BIT_TXFIFO_H2C_OVF BIT(0)
#define BIT_H2C_BUS_RES_FAIL BIT(1)
#define BIT_H2C_DMA_OK BIT(2)
#define BIT_C2H_DMA_OK BIT(3)
#define BIT_H2C_MSG_INT BIT(4)
#define BIT_RPWM1_INT BIT(5)
#define BIT_RPWM2_INT BIT(6)
#define BIT_SDIO_RST_CMD_INT BIT(7)
#define BIT_RXBD_FLAG_ERR_INT BIT(8)
#define BIT_RX_BD_AVAI_INT BIT(9)
#define BIT_HOST_WAKE_CPU_INT BIT(10)
#define SDIO_INIT_INT_MASK (BIT_H2C_DMA_OK | BIT_C2H_DMA_OK | \
BIT_H2C_MSG_INT | BIT_RPWM1_INT | \
BIT_RPWM2_INT |BIT_H2C_BUS_RES_FAIL | \
BIT_RXBD_FLAG_ERR_INT)
/******************** Bits definition for REG_SPDIO_CPU_IND register *******************/
#define BIT_SYSTEM_TRX_RDY_IND BIT(0)
/******************** Bits definition for REG_SPDIO_HCI_RX_REQ register *******************/
#define BIT_HCI_RX_REQ BIT(0)
#endif /* #ifndef _RTL8710B_SDIO_H_ */

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8721D_SDIO_HOST_H_
#define _RTL8721D_SDIO_HOST_H_
#define SDIO_HOST_REG_BASE 0x40026000
#define HAL_SDIO_HOST_READ32(addr) HAL_READ32(SDIO_HOST_REG_BASE, addr)
#define HAL_SDIO_HOST_WRITE32(addr, value) HAL_WRITE32(SDIO_HOST_REG_BASE, addr, value)
#define HAL_SDIO_HOST_READ16(addr) HAL_READ16(SDIO_HOST_REG_BASE, addr)
#define HAL_SDIO_HOST_WRITE16(addr, value) HAL_WRITE16(SDIO_HOST_REG_BASE, addr, value)
#define HAL_SDIO_HOST_READ8(addr) HAL_READ8(SDIO_HOST_REG_BASE, addr)
#define HAL_SDIO_HOST_WRITE8(addr, value) HAL_WRITE8(SDIO_HOST_REG_BASE, addr, value)
/* =============== Register Offset Definition =============== */
#define REG_SDIO_HOST_SDMA_SYS_ADDR 0x00 // 4byte
#define REG_SDIO_HOST_BLK_SIZE 0x04 // 2byte
#define REG_SDIO_HOST_BLK_CNT 0x06 // 2byte
#define REG_SDIO_HOST_ARG 0x08 // 4byte
#define REG_SDIO_HOST_XFER_MODE 0x0C // 2byte
#define REG_SDIO_HOST_CMD 0x0E // 2byte
#define REG_SDIO_HOST_RSP0 0x10 // 4byte
#define REG_SDIO_HOST_RSP2 0x14 // 4byte
#define REG_SDIO_HOST_RSP4 0x18 // 4byte
#define REG_SDIO_HOST_RSP6 0x1C // 4byte
#define REG_SDIO_HOST_BUF_DATA_PORT 0x20 // 4byte
#define REG_SDIO_HOST_PRESENT_STATE 0x24 // 4byte
#define REG_SDIO_HOST_HOST_CTRL 0x28 // 1byte
#define REG_SDIO_HOST_PWR_CTRL 0x29 // 1byte
#define REG_SDIO_HOST_BLK_GAP_CTRL 0x2A // 1byte
#define REG_SDIO_HOST_WAKEUP_CTRL 0x2B // 1byte
#define REG_SDIO_HOST_CLK_CTRL 0x2C // 2byte
#define REG_SDIO_HOST_TIMEOUT_CTRL 0x2E // 1byte
#define REG_SDIO_HOST_SW_RESET 0x2F // 1byte
#define REG_SDIO_HOST_NORMAL_INT_STATUS 0x30 // 2byte
#define REG_SDIO_HOST_ERROR_INT_STATUS 0x32 // 2byte
#define REG_SDIO_HOST_NORMAL_INT_STATUS_EN 0x34 // 2byte
#define REG_SDIO_HOST_ERROR_INT_STATUS_EN 0x36 // 2byte
#define REG_SDIO_HOST_NORMAL_INT_SIG_EN 0x38 // 2byte
#define REG_SDIO_HOST_ERROR_INT_SIG_EN 0x3A // 2byte
#define REG_SDIO_HOST_CAPABILITIES 0x40 // 8byte
#define REG_SDIO_HOST_ADMA_SYS_ADDR 0x58 // 8byte
/* =============================================== */
/* Block Count Register (0x06) */
#define BLK_CNT_REG_MAX 0xFFFF // 65535 blocks
/* Transfer Mode Register (0x0C) */
#define XFER_MODE_DMA_EN BIT0
#define XFER_MODE_BLK_CNT_EN BIT1
#define XFER_MODE_AUTO_CMD12_EN BIT2
#define XFER_MODE_DATA_XFER_DIR BIT4
#define XFER_MODE_MULT_SINGLE_BLK BIT5
/* Present State Register (0x24) */
#define PRES_STATE_CMD_INHIBIT_CMD BIT0
#define PRES_STATE_CMD_INHIBIT_DAT BIT1
#define PRES_STATE_DAT_LINE_ACTIVE BIT2
#define PRES_STATE_CARD_INSERTED BIT16
#define PRES_STATE_DAT0_SIGNAL_LEVEL BIT20
/* Power Control Register (0x29) */
#define PWR_CTRL_SD_BUS_PWR BIT0
/* Clock Control Register (0x2C) */
#define CLK_CTRL_INTERAL_CLK_EN BIT0
#define CLK_CTRL_INTERAL_CLK_STABLE BIT1
#define CLK_CTRL_SD_CLK_EN BIT2
/* Software Reset Register (0x2F) */
#define SW_RESET_FOR_ALL BIT0
#define SW_RESET_FOR_CMD BIT1
#define SW_RESET_FOR_DAT BIT2
/* Normal Interrupt Status (0x30) */
#define NOR_INT_STAT_CMD_COMP BIT0
#define NOR_INT_STAT_XFER_COMP BIT1
#define NOR_INT_STAT_BLK_GAP_EVENT BIT2
#define NOR_INT_STAT_DMA_INT BIT3
#define NOR_INT_STAT_BUF_WR_RDY BIT4
#define NOR_INT_STAT_BUF_RD_RDY BIT5
#define NOR_INT_STAT_CARD_INSERT BIT6
#define NOR_INT_STAT_CARD_REMOVAL BIT7
#define NOR_INT_STAT_CARD_INT BIT8
#define NOR_INT_STAT_ERR_INT BIT15
/* Error Interrupt Status (0x32) */
#define ERR_INT_STAT_CMD_TIMEOUT BIT0
#define ERR_INT_STAT_CMD_CRC BIT1
#define ERR_INT_STAT_CMD_END_BIT BIT2
#define ERR_INT_STAT_CMD_IDX BIT3
#define ERR_INT_STAT_DATA_TIMEOUT BIT4
#define ERR_INT_STAT_DATA_CRC BIT5
#define ERR_INT_STAT_DATA_END_BIT BIT6
#define ERR_INT_STAT_CUR_LIMIT BIT7
#define ERR_INT_STAT_AUTO_CMD12 BIT8
#define ERR_INT_STAT_ADMA BIT9
/* Normal Interrupt Status Enable (0x34) */
#define NOR_INT_STAT_EN_CMD_COMP BIT0
#define NOR_INT_STAT_EN_XFER_COMP BIT1
#define NOR_INT_STAT_EN_BLK_GAP_EVENT BIT2
#define NOR_INT_STAT_EN_DMA_INT BIT3
#define NOR_INT_STAT_EN_BUF_WR_RDY BIT4
#define NOR_INT_STAT_EN_BUF_RD_RDY BIT5
#define NOR_INT_STAT_EN_CARD_INSERT BIT6
#define NOR_INT_STAT_EN_CARD_REMOVAL BIT7
#define NOR_INT_STAT_EN_CARD_INT BIT8
/* Error Interrupt Status Enable (0x36) */
#define ERR_INT_STAT_EN_CMD_TIMEOUT BIT0
#define ERR_INT_STAT_EN_CMD_CRC BIT1
#define ERR_INT_STAT_EN_CMD_END_BIT BIT2
#define ERR_INT_STAT_EN_CMD_IDX BIT3
#define ERR_INT_STAT_EN_DATA_TIMEOUT BIT4
#define ERR_INT_STAT_EN_DATA_CRC BIT5
#define ERR_INT_STAT_EN_DATA_END_BIT BIT6
#define ERR_INT_STAT_EN_CUR_LIMIT BIT7
#define ERR_INT_STAT_EN_AUTO_CMD BIT8
#define ERR_INT_STAT_EN_ADMA BIT9
/* Normal Interrupt Signal Enable (0x38) */
#define NOR_INT_SIG_EN_CMD_COMP BIT0
#define NOR_INT_SIG_EN_XFER_COMP BIT1
#define NOR_INT_SIG_EN_BLK_GAP_EVENT BIT2
#define NOR_INT_SIG_EN_DMA_INT BIT3
#define NOR_INT_SIG_EN_BUF_WR_RDY BIT4
#define NOR_INT_SIG_EN_BUF_RD_RDY BIT5
#define NOR_INT_SIG_EN_CARD_INSERT BIT6
#define NOR_INT_SIG_EN_CARD_REMOVAL BIT7
#define NOR_INT_SIG_EN_CARD_INT BIT8
/* Error Interrupt Signal Enable (0x3A) */
#define ERR_INT_SIG_EN_CMD_TIMEOUT BIT0
#define ERR_INT_SIG_EN_CMD_CRC BIT1
#define ERR_INT_SIG_EN_CMD_END_BIT BIT2
#define ERR_INT_SIG_EN_CMD_IDX BIT3
#define ERR_INT_SIG_EN_DATA_TIMEOUT BIT4
#define ERR_INT_SIG_EN_DATA_CRC BIT5
#define ERR_INT_SIG_EN_DATA_END_BIT BIT6
#define ERR_INT_SIG_EN_CUR_LIMIT BIT7
#define ERR_INT_SIG_EN_AUTO_CMD BIT8
#define ERR_INT_SIG_EN_ADMA BIT9
/* Capabilities Register (0x40) */
#define CAPA_TIMEOUT_CLK_UNIT BIT7
#define CAPA_ADMA2_SUPPORT BIT19
#define CAPA_HIGH_SPEED_SUPPORT BIT21
#define CAPA_VOLT_SUPPORT_33V BIT24
#define CAPA_VOLT_SUPPORT_30V BIT25
#define CAPA_VOLT_SUPPORT_18V BIT26
#define DATA_BLK_LEN 512
#define SCR_REG_LEN 8 // 64 bits
#define SWITCH_FN_STATUS_LEN 64 // 512 bits
#define SD_STATUS_LEN 64 // 512 bits
#define CSD_REG_LEN 16 // 128 bits
/* Switch Function (CMD6) Group */
#define SWITCH_FN_GRP1_DEFAULT BIT0
#define SWITCH_FN_GRP1_HIGH_SPEED BIT1
#define SWITCH_FN_GRP2_DEFAULT BIT0
#define SWITCH_FN_GRP2_FOR_EC BIT1
#define SWITCH_FN_GRP2_VENDOR_SPECIFIC BIT14
/* Operating Condition (ACMD41) */
#define ACMD41_POLL_INTERVAL 10000 // 10 ms
#define ACMD41_INIT_TIMEOUT 1000000 // 1 sec
/* Card Status (R1) */
#define R1_APP_CMD BIT5
#define R1_WP_VIOLATION BIT26
/* Error Interrupt Recovery */
#define HAL_SDH_RECOVERED 0x10
/* 0x0C */
typedef enum
{
WRITE_OP = 0,
READ_OP = 1
}DATA_OPERATION;
/* 0x0E */
typedef enum
{
CMD_GO_IDLE_STATE = 0,
CMD_ALL_SEND_CID = 2,
CMD_SEND_RELATIVE_ADDR = 3,
CMD_SET_DSR = 4,
CMD_SWITCH_FUNC = 6,
CMD_SELECT_DESELECT_CARD = 7,
CMD_SEND_IF_COND = 8,
CMD_SEND_CSD = 9,
CMD_SEND_CID = 10,
CMD_VOLTAGE_SWITCH = 11,
CMD_STOP_TRANSMISSION = 12,
CMD_SEND_STATUS = 13,
CMD_GO_INACTIVE_STATE = 15,
CMD_SET_BLOCKLEN = 16,
CMD_READ_SINGLE_BLOCK = 17,
CMD_READ_MULTIPLE_BLOCK = 18,
CMD_SET_BLOCK_COUNT = 23,
CMD_WRITE_BLOCK = 24,
CMD_WRITE_MULTIPLE_BLOCK = 25,
CMD_PROGRAM_CSD = 27,
CMD_ERASE_WR_BLK_START = 32,
CMD_ERASE_WR_BLK_END = 33,
CMD_ERASE = 38,
CMD_SD_SEND_OP_COND = 41,
CMD_LOCK_UNLOCK = 42,
CMD_SEND_SCR = 51,
CMD_APP_CMD = 55
}CMD_IDX;
typedef enum
{
NORMAL, // 00b
SUSPEND, // 01b
RESUME, // 10b
ABORT // 11b
}CMD_TYPE;
typedef enum
{
NO_DATA, // 00b
WITH_DATA // 01b
}DATA_PRESENT_SEL;
typedef enum
{
NO_RSP, // 00b
RSP_LEN_136, // 01b
RSP_LEN_48, // 10b
RSP_LEN_48_CHK_BUSY // 11b
}RSP_TYPE;
/* 0x28 */
typedef enum
{
SDMA, // 00b
RESERVED, // 01b
ADMA2_32BIT, // 10b
ADMA2_64BIT // 11b
}HOST_DMA_SELECT;
typedef enum
{
MODE_1_BIT = 0,
MODE_4_BIT = 1
}HOST_DATA_WIDTH;
/* 0x29 */
typedef enum
{
VOLT_33V = 7,// 111b
VOLT_30V = 6,// 110b
VOLT_18V = 5 // 101b
}HOST_SD_BUS_VOLT;
/* 0x2C */
typedef enum
{
BASE_CLK = 0x00,
BASE_CLK_DIVIDED_BY_2 = 0x01,
BASE_CLK_DIVIDED_BY_4 = 0x02,
BASE_CLK_DIVIDED_BY_8 = 0x04,
BASE_CLK_DIVIDED_BY_16 = 0x08,
BASE_CLK_DIVIDED_BY_32 = 0x10,
BASE_CLK_DIVIDED_BY_64 = 0x20,
BASE_CLK_DIVIDED_BY_128 = 0x40,
BASE_CLK_DIVIDED_BY_256 = 0x80
}SD_CLK_DIVISOR;
typedef enum
{
SD_CLK_162KHZ,
SD_CLK_325KHZ,
SD_CLK_650KHZ,
SD_CLK_1_3MHZ,
SD_CLK_2_6MHZ,
SD_CLK_5_2MHZ,
SD_CLK_10_4MHZ,
SD_CLK_20_8MHZ,
SD_CLK_41_6MHZ
}SD_CLK_FREQUENCY;
/* Card Status Register */
typedef enum
{
IDLE, // 0
READY, // 1
IDENTIFICATION, // 2
STAND_BY, // 3
TRANSFER, // 4
SENDING_DATA, // 5
RECEIVE_DATA, // 6
PROGRAMMING, // 7
DISCONNECT, // 8
UNKNOWN = 0xFF
}CURRENT_STATE;
/* OCR Register */
typedef enum
{
VDD_27_28 = BIT15,
VDD_28_29 = BIT16,
VDD_29_30 = BIT17,
VDD_30_31 = BIT18,
VDD_31_32 = BIT19,
VDD_32_33 = BIT20,
VDD_33_34 = BIT21,
VDD_34_35 = BIT22,
VDD_35_36 = BIT23,
CARD_CAPA_STATUS = BIT30,
CARD_PWR_UP_STATUS = BIT31
}OCR_VOLTAGE_PROFILE;
/* SCR Register */
typedef enum
{
SD_VER_10 = 0,
SD_VER_110 = 1,
SD_VER_200 = 2
}PHYSICAL_LAYER_SPEC_VER;
/* CSD Register */
typedef enum
{
CLEAR_WRITE_PROTECT = 0,
SET_WRITE_PROTECT = 1
}TEMPORARY_WRITE_PROTECT_STATUS;
/* Switch Function (CMD6) Status Data Structure Version */
typedef enum
{
BUSY_STATUS_UNDEFINED = 0, // bits [511:376] are defined
BUSY_STATUS_DEFINED = 1 // bits [511:272] are defined
}SWITCH_FN_STATUS_DATA_STRUCTURE_VER;
/* Switch Function (CMD6) Busy Status */
typedef enum
{
READY_STATUS = 0,
BUSY_STATUS = 1
}SWITCH_FN_BUSY_STATUS;
/* Switch Function (CMD6) Mode */
typedef enum
{
CHECK_FN = 0x0,
SWITCH_FN = 0x1
}SWITCH_FN_MODE;
/* Switch Function (CMD6) Group 1 */
typedef enum
{
FN1_DEFAULT = 0x0,
FN1_HIGH_SPEED = 0x1,
FN1_KEEP_CURRENT = 0xF
}SWITCH_FN_GROUP_1;
/* Switch Function (CMD6) Group 2 */
typedef enum
{
FN2_DEFAULT = 0x0,
FN2_FOR_EC = 0x1,
FN2_VENDOR_SPECIFIC = 0xE,
FN2_KEEP_CURRENT = 0xF
}SWITCH_FN_GROUP_2;
typedef enum
{
DESEL_CARD = 0,
SEL_CARD = 1
}CARD_SELECTION;
typedef enum
{
SDSC_ONLY = 0,
SDHC_SUPPORT = 1
}HOST_CAPACITY_SUPPORT;
typedef enum
{
BUS_1_BIT = 0,
BUS_4_BIT = 2
}DATA_BUS_WIDTH;
typedef struct _ADMA2_ATTRIB_
{
u16 Valid:1;
u16 End:1;
u16 Int:1;
u16 Rsvd1:1;
u16 Act1:1;
u16 Act2:1;
u16 Rsvd2:10;
}ADMA2_ATTRIB, *PADMA2_ATTRIB;
typedef struct _ADMA2_DESC_FMT_
{
ADMA2_ATTRIB Attrib1;
u16 Len1;
u32 Addr1;
/* Link to next descriptor (if needed) */
ADMA2_ATTRIB Attrib2;
u16 Len2;
u32 Addr2;
}ADMA2_DESC_FMT, *PADMA2_DESC_FMT;
/* 0x0E */
typedef struct _SDIO_HOST_CMD_FMT_
{
u16 RespType:2;
u16 Rsvd0:1;
u16 CmdCrcChkEn:1;
u16 CmdIdxChkEn:1;
u16 DataPresent:1;
u16 CmdType:2;
u16 CmdIdx:6;
u16 Rsvd1:2;
}SDIO_HOST_CMD_FMT, *PSDIO_HOST_CMD_FMT;
typedef struct _SDIO_HOST_CMD_
{
SDIO_HOST_CMD_FMT CmdFmt;
u32 Arg;
}SDIO_HOST_CMD, *PSDIO_HOST_CMD;
HAL_Status
HalSdioHostInitHostRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostInitCardRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostDeInitRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostEnableRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostDisableRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostIrqInitRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostReadBlocksDmaRtl8721d(
IN VOID *Data,
IN u64 ReadAddr,
IN u32 BlockCnt
);
HAL_Status
HalSdioHostWriteBlocksDmaRtl8721d(
IN VOID *Data,
IN u64 WriteAddr,
IN u32 BlockCnt
);
HAL_Status
HalSdioHostStopTransferRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostGetCardStatusRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostGetSdStatusRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostChangeSdClockRtl8721d(
IN VOID *Data,
IN u8 Frequency
);
HAL_Status
HalSdioHostEraseRtl8721d(
IN VOID *Data,
IN u64 StartAddr,
IN u64 EndAddr
);
HAL_Status
HalSdioHostGetWriteProtectRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostSetWriteProtectRtl8721d(
IN VOID *Data,
IN u8 Setting
);
#ifdef CONFIG_SDIO_HOST_VERIFY
#define HAL_MMC_HOST_READ32(addr) HAL_READ32(SDIO_HOST_REG_BASE, addr)
#define HAL_MMC_HOST_WRITE32(addr, value) HAL_WRITE32(SDIO_HOST_REG_BASE, addr, value)
#define HAL_MMC_HOST_READ16(addr) HAL_READ16(SDIO_HOST_REG_BASE, addr)
#define HAL_MMC_HOST_WRITE16(addr, value) HAL_WRITE16(SDIO_HOST_REG_BASE, addr, value)
#define HAL_MMC_HOST_READ8(addr) HAL_READ8(SDIO_HOST_REG_BASE, addr)
#define HAL_MMC_HOST_WRITE8(addr, value) HAL_WRITE8(SDIO_HOST_REG_BASE, addr, value)
/* RTL8721D Register */
// REG_SOC_HCI_COM_FUNC_EN (0x214)
#define SD_DEVICE_IP_ON_BLK BIT0
#define SD_DEVICE_IP_OFF_BLK BIT1
#define SD_HOST_IP_BLK BIT2
// REG_PESOC_HCI_CLK_CTRL0 (0x240)
#define SD_HOST_CLKEN_IN_CPU_RUN_MODE BIT2
// REG_HCI_PINMUX_CTRL (0x2A0)
#define SD_DEVICE_MODE_PINMUX_EN BIT0
#define SD_HOST_MODE_PINMUX_EN BIT1
// 0x40059000
#define SD_HOST_CARD_DETECT_CIRCUIT BIT10
/* SD Host Register */
#define REG_SDMA_SYS_ADDR_ARG 0x00 // 4byte
#define REG_BLOCK_SIZE 0x04 // 2byte
#define REG_BLOCK_COUNT 0x06 // 2byte
#define REG_ARGUMENT1 0x08 // 4byte
#define REG_TRANSFER_MODE 0x0C // 2byte
#define REG_COMMAND 0x0E // 2byte
#define REG_RESPONSE0 0x10 // 4byte
#define REG_RESPONSE2 0x14 // 4byte
#define REG_RESPONSE4 0x18 // 4byte
#define REG_RESPONSE6 0x1C // 4byte
#define REG_BUFFER_DATA_PORT 0x20 // 4byte
#define REG_PRESENT_STATE 0x24 // 4byte
#define REG_HOST_CONTROL1 0x28 // 1byte
#define REG_POWER_CONTROL 0x29 // 1byte
#define REG_BLOCK_GAP_CONTROL 0x2A // 1byte
#define REG_WAKEUP_CONTROL 0x2B // 1byte
#define REG_CLOCK_CONTROL 0x2C // 2byte
#define REG_TIMEOUT_CONTROL 0x2E // 1byte
#define REG_SW_RESET 0x2F // 1byte
#define REG_NORMAL_INT_STATUS 0x30 // 2byte
#define REG_ERROR_INT_STATUS 0x32 // 2byte
#define REG_NORMAL_INT_STATUS_ENABLE 0x34 // 2byte
#define REG_ERROR_INT_STATUS_ENABLE 0x36 // 2byte
#define REG_NORMAL_INT_SIGNAL_ENABLE 0x38 // 2byte
#define REG_ERROR_INT_SIGNAL_ENABLE 0x3A // 2byte
#define REG_CAPABILITIES 0x40 // 8byte
#define REG_ADMA_ADDRESS 0x58 // 8byte
// Transfer Mode (0x0C)
#define BIT_DMA_EN BIT0
#define BIT_BLK_CNT_EN BIT1
#define BIT_AUTO_CMD12_EN BIT2
#define BIT_AUTO_CMD23_EN BIT3
#define BIT_READ_TRANS BIT4
#define BIT_MULTI_BLK BIT5
// Present State (0x24)
#define BIT_CMD_INHIBIT_CMD BIT0
#define BIT_CMD_INHIBIT_DAT BIT1
#define BIT_CARD_INSERTED BIT16
#define BIT_WRITE_PROTECT_SWITCH_PIN BIT19
// Power Control (0x29)
#define BIT_POWER_33 0xE
#define BIT_POWER_30 0xC
#define BIT_POWER_18 0xA
// Clock Control (0x2C)
#define BIT_INTERNAL_CLK_EN BIT0
#define BIT_INTERNAL_CLK_STABLE BIT1
#define BIT_SD_CLK_EN BIT2
// Software Reset (0x2F)
#define BIT_SW_RESET_ALL BIT0
#define BIT_SW_RESET_CMD_LINE BIT1
#define BIT_SW_RESET_DAT_LINE BIT2
// Norma Interrupt Status (0x30)
#define BIT_COMMAND_COMPLETE BIT0
#define BIT_TRANSFER_COMPLETE BIT1
#define BIT_BLOCK_GAP_EVENT BIT2
#define BIT_DMA_INT BIT3
#define BIT_BUFFER_WRITE_RDY BIT4
#define BIT_BUFFER_READ_RDY BIT5
#define BIT_CARD_INSERTION BIT6
#define BIT_CARD_REMOVAL BIT7
#define BIT_CARD_INT BIT8
#define BIT_ERROR_INT BIT15
// Error Interrupt Status (0x32)
#define BIT_DATA_TIME_OUT_ERROR BIT4
#define BIT_DATA_CRC_ERROR BIT5
#define BIT_ADMA_ERROR BIT9
// Capabilities (0x40)
#define BIT_VDD_33 BIT24
#define BIT_VDD_30 BIT25
#define BIT_VDD_18 BIT26
#define ENABLE 1
#define DISABLE 0
#define ADMA_DESC_NUM 50
#define BUFFER_UNIT_SIZE 512
typedef enum _MMC_HOST_TEST_FUNC_ {
MMC_HOST_TEST_HW_INIT, // 0
MMC_HOST_TEST_CARD_INIT, // 1
MMC_HOST_TEST_SEND_CMD, // 2
MMC_HOST_TEST_DEBUG, // 3
MMC_HOST_TEST_SW_RESET, // 4
MMC_HOST_TEST_READ_SINGLE, // 5
MMC_HOST_TEST_WRITE_SINGLE, // 6
MMC_HOST_TEST_READ_MULTI, // 7
MMC_HOST_TEST_WRITE_MULTI, // 8
MMC_HOST_TEST_SINGLE_LONGRUN, // 9
MMC_HOST_TEST_MULTI_LONGRUN, // 10
MMC_HOST_TEST_CARD_DETECTION, // 11
MMC_HOST_TEST_WRITE_PROTECT, // 12
MMC_HOST_TEST_REGISTER_RW, // 13
SD_HOST_HAL_API_VERIFY = 20,
SD_HOST_ERASE_TEST = 21,
SD_HOST_WP_TEST = 22,
SD_HOST_MB_TEST = 23,
SD_HOST_ADMA_MAX_TEST = 24
}MMC_HOST_TEST_FUNC;
typedef enum _RESPONSE_TYPE_ {
No_Response, // 00b
Response_136, // 01b
Response_48, // 10b
Response_48_Busy // 11b
}RESPONSE_TYPE;
typedef enum _COMMAND_TYPE_ {
Normal, // 00b
Suspend, // 01b
Resume, // 10b
Abort // 11b
}COMMAND_TYPE;
typedef enum _DATA_PRESENT_ {
No_Data_Present, // 00b
Data_Present, // 01b
}DATA_PRESENT;
typedef enum _SUPPLY_VOLTAGE_ {
MMC_VDD_27_28 = BIT15,
MMC_VDD_28_29 = BIT16,
MMC_VDD_29_30 = BIT17,
MMC_VDD_30_31 = BIT18,
MMC_VDD_31_32 = BIT19,
MMC_VDD_32_33 = BIT20,
MMC_VDD_33_34 = BIT21,
MMC_VDD_34_35 = BIT22,
MMC_VDD_35_36 = BIT23,
}SUPPLY_VOLTAGE;
typedef enum _COMMAND_INDEX_ {
GO_IDLE_STATE = 0,
ALL_SEND_CID = 2,
SEND_RELATIVE_ADDR = 3,
SET_BUS_WIDTH = 6,
SELECT_CARD = 7,
SEND_IF_COND = 8,
SEND_CSD = 9,
STOP_TRANSMISSION = 12,
SEND_STATUS = 13,
READ_SINGLE_BLOCK = 17,
READ_MULTIPLE_BLOCK = 18,
WRITE_BLOCK = 24,
WRITE_MULTIPLE_BLOCK = 25,
SD_SEND_OP_COND = 41,
APP_CMD = 55,
}COMMAND_INDEX;
typedef enum _TRANSFER_CONFIG_ {
Read_Data = 0,
Write_Data = 1,
Single_Block = 0,
Multiple_Block = 1,
}TRANSFER_CONFIG;
typedef enum _ERROR_STATUS_ {
General_Error, // 0
CRC_Error, // 1
TIME_OUT_ERROR, // 2
CRC_Error_NeedCMD12, // 3
Transfer_OK // 4
}ERROR_STATUS;
typedef enum _CARD_CURRENT_STATE_ {
IDLE_STATE,
READY_STATE,
IDENT_STATE,
STBY_STATE,
TRAN_STATE,
DATA_STATE,
RCV_STATE,
PRG_STATE,
DIS_STATE,
UNKNOWN_STATE
}CARD_CURRENT_STATE;
typedef struct _COMMAND_FORMAT_
{
u16 Resp_Type:2;
u16 Rsvd0:1;
u16 CMD_CRC_Chk:1;
u16 CMD_Idx_Chk:1;
u16 Data_Present:1;
u16 CMD_Type:2;
u16 CMD_Idx:6;
u16 Rsvd1:2;
}COMMAND_FORMAT, *PCOMMAND_FPRMAT;
typedef struct _MMC_COMMAND
{
COMMAND_FORMAT Cmd_Format;
u32 Arg;
}MMC_COMMAND;
typedef struct _MMC_HOST_
{
u32 OCR_Avail;
u32 Resp[4];
u32 CID[4];
u32 RCA;
}MMC_HOST, *PMMC_HOST;
typedef struct _ADMA_ATTR_
{
u16 Valid:1;
u16 End:1;
u16 Int:1;
u16 Rsvd1:1;
u16 Act1:1;
u16 Act2:1;
u16 Rsvd2:10;
}ADMA_ATTR, *PADMA_ATTR;
// 24 bytes
typedef struct _ADMA_DESC_TABLE_
{
// 1st buffer desc
ADMA_ATTR Attribute1;
u16 Length1;
u32 Address1;
// 2nd buffer desc
ADMA_ATTR Attribute2;
u16 Length2;
u32 Address2;
// 3rd buffer desc
ADMA_ATTR Attribute3;
u16 Length3;
u32 Address3;
}ADMA_DESC_TABLE, *PADMA_DESC_TABLE;
// 1024 bytes
typedef struct _ADMA_BUFFER_
{
u8 Data1[512]; /* 1st buffer */
u8 Data2[512]; /* 2nd buffer */
}ADMA_BUFFER, *PADMA_BUFFER;
VOID
SdHostTestApp(
IN u8 *argv[]
);
#endif // end of "#ifdef CONFIG_SDIO_HOST_VERIFY"
#endif /* #ifndef _RTL8721D_SDIO_HOST_H_ */

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@ -0,0 +1,473 @@
/**
******************************************************************************
* @file rtl8721d_sdioh.h
* @author
* @version V1.0.0
* @date 2018-06-29
* @brief This file contains all the functions prototypes for the SDIOH firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_SDIO_HOST_H
#define _RTL8721D_SDIO_HOST_H
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup SDIOH
* @brief SDIOH driver modules
* @{
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup SDIOH_Exported_Types SDIOH Exported Types
* @{
*/
/**
* @brief SDIOH init structure definition
*/
typedef struct {
u8 SDIOH_idle_level; /*!> Indicate the idle pin level mask. When operate in 1-Bit bus width, this value is 0x03.
When operate in 4-Bit bus width, this value is 0x1F. */
} SDIOH_InitTypeDef;
/**
* @brief SDIOH DMA control structure definition
*/
typedef struct {
u32 start_addr; /*!< Specify the DMA start address. Unit: 8 Bytes. */
u16 blk_cnt; /*!< Specify the DMA transfer length. Unit: 512 Bytes). */
u8 op; /*!< Specify the data move direction. Should be a value of @ref SDIOH_DMA_Operation. */
u8 type; /*!< Specify the transfer type. Shold be a value of @ref SDIOH_DMA_Transfer_Type. */
} SDIOH_DmaCtl;
/**
* @brief SDIOH command parameters structure definition
*/
typedef struct{
u32 arg; /*!< Specify the argument to be transfered with command. */
u8 idx; /*!< Specify the command to be transfered. */
u8 rsp_type; /*!< Specify the response type. Should be a value of @ref SDIOH_Card_Response_Classfication. */
u8 rsp_crc_chk; /*!< Specify CRC7 check enable or not. Should be ENABLE or DISABLE. */
u8 data_present; /*!< Specify which thers is data need to read after get response from card. Should be a value of
@ref SDIOH_Data_Present */
} SDIOH_CmdTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SDIOH_Exported_Constants SDIOH Exported Constants
* @{
*/
/** @defgroup SDIOH_Working_Mode
* @{
*/
#define SDIOH_NORMAL_WRITE 0
#define SDIOH_AUTO_WRITE3 1
#define SDIOH_AUTO_WRITE4 2
#define SDIOH_AUTO_READ3 5
#define SDIOH_AUTO_READ4 6
#define SDIOH_SEND_CMD_GET_RSP 8
#define SDIOH_AUTO_WRITE1 9
#define SDIOH_AUTO_WRITE2 10
#define SDIOH_NORMAL_READ 12
#define SDIOH_AUTO_READ1 13
#define SDIOH_AUTO_READ2 14
#define SDIOH_TUNING 15
/**
* @}
*/
/** @defgroup SDIOH_Card_Response_Type
* @{
*/
#define SDIOH_NO_RESP 0
#define SDIOH_RESP_R1 1
#define SDIOH_RESP_R2 2
#define SDIOH_RESP_R3 3
#define SDIOH_RESP_R6 4
#define SDIOH_RESP_R7 5
/**
* @}
*/
/** @defgroup SDIOH_Card_Response_Classification
* @{
*/
#define SDIOH_NO_RESP 0
#define SDIOH_RSP_6B 1
#define SDIOH_RSP_17B 2
/**
* @}
*/
/** @defgroup SDIOH_Data_Present
* @{
*/
#define SDIOH_NO_DATA 0
#define SDIOH_DATA_EXIST 1
/**
* @}
*/
/** @defgroup SDIOH_DMA_Transfer_Type
* @{
*/
#define SDIOH_DMA_NORMAL 0
#define SDIOH_DMA_64B 1
#define SDIOH_DMA_R2 2
/**
* @}
*/
/** @defgroup SDIOH_Mode_Definition
* @{
*/
#define SDIOH_SD20_MODE 0
#define SDIOH_DDR_MODE 1
#define SDIOH_SD30_MODE 2
/**
* @}
*/
/** @defgroup SDIOH_Bus_Width
* @{
*/
#define SDIOH_BUS_WIDTH_1BIT 0
#define SDIOH_BUS_WIDTH_4BIT 1
/**
* @}
*/
/** @defgroup SDIOH_DMA_Operation
* @{
*/
#define SDIOH_DMA_WRITE 0
#define SDIOH_DMA_READ 1
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SDIOH_Exported_Functions SDIOH Exported Functions
* @{
*/
/** @defgroup SDIO_HOST_Functions SDIO Host Functions
* @{
*/
_LONG_CALL_ u32 SDIOH_Busy(void);
_LONG_CALL_ u32 SDIOH_CheckTxError(u16 *status);
_LONG_CALL_ u32 SDIOH_WaitTxDone(u32 timeout_us);
_LONG_CALL_ u32 SDIOH_WaitDMADone(u32 timeout_us);
_LONG_CALL_ u32 SDIOH_GetISR(void);
_LONG_CALL_ void SDIOH_INTConfig(u8 SDIO_IT, u32 newState);
_LONG_CALL_ void SDIOH_INTClearPendingBit(u8 SDIO_IT);
_LONG_CALL_ u32 SDIOH_CheckBusState(u8 status, u32 timeout_us);
_LONG_CALL_ u8 SDIOH_GetBusWidth(void);
_LONG_CALL_ void SDIOH_SetBusWidth(u8 width);
_LONG_CALL_ void SDIOH_DMAConfig(SDIOH_DmaCtl *dma_ctl);
_LONG_CALL_ void SDIOH_DMAReset(void);
_LONG_CALL_ u32 SDIOH_SendCommand(SDIOH_CmdTypeDef *cmd_attrib, u32 timeout_us);
_LONG_CALL_ u8 SDIOH_GetResponse(u8 byte_index);
_LONG_CALL_ void SDIOH_SwitchSpeed(u8 clk_div, u8 mode);
_LONG_CALL_ u32 SDIOH_InitialModeCmd(u8 NewState, u8 Level);
_LONG_CALL_ u32 SDIOH_Init (u8 BusBitMode);
_LONG_CALL_ void SDIOH_DeInit (void);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup SDIOH_Register_Definitions SDIOH Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup SDIOH_SRAM_CRL
* @{
*****************************************************************************/
#define SDIOH_SHIFT_LX_BURST_SIZE 6
#define SDIOH_LX_BURST_SIZE_64B (0 << SDIOH_SHIFT_LX_BURST_SIZE)
#define SDIOH_SHIFT_MAP_SEL 5
#define SDIOH_MAP_SEL_DEC (1 << SDIOH_SHIFT_MAP_SEL)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_DMA_CRL1
* @{
*****************************************************************************/
#define SDIOH_MASK_DRAM_SA 0x0FFFFFFF
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_DMA_CRL2
* @{
*****************************************************************************/
#define SDIOH_MASK_DMA_LEN 0x0000FFFF
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_DMA_CRL3
* @{
*****************************************************************************/
#define SDIOH_DAT64_SEL BIT(5)
#define SDIOH_RSP17_SEL BIT(4)
#define SDIOH_SHIFT_DDR_WR 1
#define SDIOH_DMA_XFER BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_ISR
* @{
*****************************************************************************/
#define SDIOH_DMA_TRANSFER_DONE BIT(4)
#define SDIOH_CARD_ERROR BIT(2)
#define SDIOH_CARD_END BIT(1)
#define SDIOH_SD_ISR_ALL (0x16)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_ISREN
* @{
*****************************************************************************/
#define SDIOH_DMA_CTL_INT_EN BIT(4)
#define SDIOH_CARD_ERR_INT_EN BIT(2)
#define SDIOH_CARD_END_INT_EN BIT(1)
#define SDIOH_WRITE_DATA BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_CKGEN_CTL
* @{
*****************************************************************************/
#define SDIOH_SHIFT_SD30_SAMP_CLK_SRC 12
#define SDIOH_SHIFT_SD30_PUSH_CLK_SRC 8
#define SDIOH_SHIFT_CRC_CLK_SRC 4
#define SDIOH_SD30_SAMP_CLK_VP1 (2 << SDIOH_SHIFT_SD30_SAMP_CLK_SRC)
#define SDIOH_SD30_PUSH_CLK_VP0 (1 << SDIOH_SHIFT_SD30_PUSH_CLK_SRC)
#define SDIOH_CRC_CLK_SSC (0 << SDIOH_SHIFT_CRC_CLK_SRC)
#define SDIOH_MASK_CLKDIV (0x7)
#define SDIOH_CLK_DIV1 0
#define SDIOH_CLK_DIV2 1
#define SDIOH_CLK_DIV4 2
#define SDIOH_CLK_DIV8 3
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_CARD_STOP
* @{
*****************************************************************************/
#define SDIOH_TARGET_MODULE_SD BIT(2)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_CARD_SELECT
* @{
*****************************************************************************/
#define SDIOH_CARD_SEL_SD_MODULE 0x2
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_CARD_EXIST
* @{
*****************************************************************************/
#define SDIOH_SD_WP BIT(5)
#define SDIOH_SD_EXIST BIT(2)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_CARD_INT_EN
* @{
*****************************************************************************/
#define SDIOH_SDMMC_INT_EN BIT(2)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_CARD_INT_PEND
* @{
*****************************************************************************/
#define SDIOH_SDMMC_INT_PEND BIT(2)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_CARD_CLK_EN_CTL
* @{
*****************************************************************************/
#define SDIOH_SD_CARD_MOUDLE_EN BIT(2)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_CONFIG1
* @{
*****************************************************************************/
#define SDIOH_INITIAL_MODE BIT(7)
#define SDIOH_CLK_DIV_BY_128 0
#define SDIOH_CLK_DIV_BY_256 BIT(6)
#define SDIOH_SD30_ASYNC_FIFO_RST_N BIT(4)
#define SDIOH_SHIFT_MODE_SEL 2
#define SDIOH_MASK_MODE_SEL 0xc
#define SDIOH_SHIFT_BUS_WIDTH 0
#define SDIOH_MASK_BUS_WIDTH 0x3
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_CONFIG2
* @{
*****************************************************************************/
#define SDIOH_CRC7_CAL_EN 0
#define SDIOH_CRC7_CAL_DIS BIT(7)
#define SDIOH_CRC16_CHK_EN 0
#define SDIOH_CRC16_CHK_DIS BIT(6)
#define SDIOH_WAIT_WR_CRCSTA_TO_EN 0
#define SDIOH_WAIT_WR_CRCSTA_TO_DIS BIT(5)
#define SDIOH_IGNORE_WR_CRC_ERR_EN 0
#define SDIOH_IGNORE_WR_CRC_ERR_DIS BIT(4)
#define SDIOH_WAIT_BUSY_END_DIS 0
#define SDIOH_WAIT_BUSY_END_EN BIT(3)
#define SDIOH_CRC7_CHK_EN 0
#define SDIOH_CRC7_CHK_DIS BIT(2)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_CONFIG3
* @{
*****************************************************************************/
#define SDIOH_STOP_STA_WAIT_BUSY_EN 0
#define SDIOH_STOP_STA_WAIT_BUSY_DIS BIT(7)
#define SDIOH_CMD_STA_WAIT_BUSY_EN 0
#define SDIOH_CMD_STA_WAIT_BUSY_DIS BIT(6)
#define SDIOH_DATA_PHA_WAIT_BUSY_EN BIT(5)
#define SDIOH_DATA_PHA_WAIT_BUSY_DIS 0
#define SDIOH_SD30_CLK_STOP_EN BIT(4)
#define SDIOH_SD30_CLK_STOP_DIS 0
#define SDIOH_SD20_CLK_STOP_EN BIT(3)
#define SDIOH_SD20_CLK_STOP_DIS 0
#define SDIOH_SD_CMD_RESP_CHK_EN BIT(2)
#define SDIOH_SD_CMD_RESP_CHK_DIS 0
#define SDIOH_ADDR_MODE_SECTOR 0
#define SDIOH_ADDR_MODE_BYTE BIT(1)
#define SDIOH_CMD_RESP_TO_EN BIT(0)
#define SDIOH_CMD_RESP_TO_DIS 0
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_STATUS1_2
* @{
*****************************************************************************/
#define SDIOH_SD_TUNNING_PAT_COMP_ERR BIT(0)
#define SDIOH_GET_WRCRC_STA_TO_ERR BIT(1)
#define SDIOH_MASK_WR_CRC_STA 0x1C
#define SDIOH_WR_CRC_ERR BIT(5)
#define SDIOH_CRC16_ERR BIT(6)
#define SDIOH_CRC7_ERR BIT(7)
#define SDIOH_SD_CMD_RSP_TO_ERR BIT(8)
#define SDIOH_SD_CMD_RSP_INVALID BIT(9)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_BLOCK_CNT_L
* @{
*****************************************************************************/
#define SDIOH_MASK_BLOCL_CNT_L 0xFF
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_BLOCK_CNT_H
* @{
*****************************************************************************/
#define SDIOH_MASK_BLOCL_CNT_H 0x7F
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_TRANSFER
* @{
*****************************************************************************/
#define SDIOH_START_TRANSFER BIT(7)
#define SDIOH_TRANSFER_END BIT(6)
#define SDIOH_SD_MODULE_FSM_IDLE BIT(5)
#define SDIOH_ERR_OCCUR BIT(4)
#define SDIOH_MASK_COM_CODE 0xF
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_CMD_STATE
* @{
*****************************************************************************/
#define SDIOH_CMD_FSM_IDLE BIT(7)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_DATA_STATE
* @{
*****************************************************************************/
#define SDIOH_DATA_FSM_IDLE BIT(7)
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
#undef SDIOH_SUPPORT_SD30
#define SDIOH_CMD_CPLT_TIMEOUT 5000 /* Max. timeout value when checking the flag of command complete, unit: us */
#define SDIOH_XFER_CPLT_TIMEOUT 1000000 /* Max. timeout value when checking the flag of transfer complete, unit: us */
#define SDIOH_READ_TIMEOUT 100000
#define SDIOH_WRITE_TIMEOUT 250000
#define SDIOH_ERASE_TIMEOUT 2000000//250000
#define HOST_COMMAND BIT(6) /* Transmission bit of register "SD_CMD0", indicating the direction of transmission (host = 1)*/
#define SDIOH_CMD_IDX_MASK 0x3F /* Command index mask of register "SD_CMD0" */
#define SDIOH_CMD8_VHS 0x1 /* Value of "VHS" field in CMD8, 2.7-3.6V */
#define SDIOH_CMD8_CHK_PATN 0xAA /* Value of "Check pattern" field in CMD8 */
#define SDIOH_OCR_VDD_WIN 0xFF8000 /* Value of "OCR" field in ACMD41, OCR bit[23:0] */
#define SDIOH_C6R2_BUF_LEN 64 /* Buffer for CMD6, R2, etc.*/
#define SDIOH_CSD_LEN 16
/* SDIOH_Card_Response_Byte_Index */
#define SDIO_RESP0 0
#define SDIO_RESP1 1
#define SDIO_RESP2 2
#define SDIO_RESP3 3
#define SDIO_RESP4 4
#define SDIO_RESP5 5
/* SDIOH_Signal_Level */
#define SDIOH_SIG_VOL_33 0
#define SDIOH_SIG_VOL_18 1
#endif

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sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_sgpio.h Normal file
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#ifndef _RTL8721D_SIMULATION_H_
#define _RTL8721D_SIMULATION_H_
/* CPUID */
#define SIMULATION_KM0_CPUID 0
#define SIMULATION_KM4_CPUID 1
/* REG */
#define KM0_SIMULATION_STAGE_REG 0x144
#define KM4_SIMULATION_STAGE_REG 0x148
/* KM0 STAGE */
#define BIT_KM0_RUN_INTO_FLASH BIT(0) /* boot into flash */
#define BIT_KM0_IMG1_BSS_CLR BIT(1) /* img1 bss clear done */
#define BIT_KM0_FLASH_CLK_PLL_EN BIT(2) /* flash clk change from xtal to pll */
#define BIT_KM0_FLASH_QIO_EN BIT(3) /* flash Qaurd IO EN */
#define BIT_KM0_FLASH_CALI_START BIT(4) /* flash Calibration start */
#define BIT_KM0_FLASH_CALI_END BIT(5) /* flash Calibration end */
#define BIT_KM0_FUNCTIONS_EN BIT(6) /* Enable KM0 periperals clock & function ok */
#define BIT_KM0_SYSTIMER_EN BIT(7) /* Enable KM0 systimer ok */
#define BIT_KM0_KM4_FREERUN BIT(8) /* Let KM4 Free run into flash */
#define BIT_KM0_IMG2_VALID BIT(9) /* check image2 valid done */
#define BIT_KM0_IMG2_LOAD BIT(10) /* image2 load done */
#define BIT_KM0_TO_IMG2 BIT(11) /* image1 call image2 entry */
#define BIT_KM0_ENTER_IMG2 BIT(12) /* image2 enter */
#define BIT_KM0_IMG2_BSS_CLR BIT(13) /* image2 bss clear done */
#define BIT_KM0_OSC_CALI_START BIT(14) /* osc calibration start */
#define BIT_KM0_OSC_CALI_END BIT(15) /* osc calibration end */
#define BIT_KM0_RTC_INIT_DONE BIT(16) /* RC init done */
#define BIT_KM0_APP_ENTER BIT(17) /* app enter */
#define BIT_KM0_MAIN_ENTER BIT(18) /* main enter */
#define BIT_KM0_WIFIFW_INIT_START BIT(19) /* wififw init start */
#define BIT_KM0_WIFIFW_INIT_END BIT(20) /* wififw init end */
#define BIT_KM0_SIMULATION_START BIT(21) /* simulation start */
#define BIT_KM0_SIMULATION_END BIT(22) /* simulation end */
/* KM4 STAGE */
#define BIT_KM4_RUN_INTO_FLASH BIT(0)
#define BIT_KM4_IMG1_BSS_CLR BIT(1) /* img1 bss clear done */
#define BIT_KM4_IMG2_VALID BIT(2) /* check image2 valid done */
#define BIT_KM4_IMG2_LOAD BIT(3) /* image2 load done */
#define BIT_KM4_IMG3_LOAD_START BIT(4) /* img3 load start */
#define BIT_KM4_IMG3_LOAD_END BIT(5) /* img3 load end */
#define BIT_KM4_TZ_CFG_DONE BIT(6) /* trustzone config done */
#define BIT_KM4_TO_IMG2 BIT(7) /* image1 call image2 entry */
#define BIT_KM4_ENTER_IMG2 BIT(8) /* image2 enter */
#define BIT_KM4_IMG2_BSS_CLR BIT(9) /* image2 bss clear done */
#define BIT_KM4_ENTER_IMG3 BIT(10) /* image2 enter */
#define BIT_KM4_IMG3_BSS_CLR BIT(11) /* image2 bss clear done */
#define BIT_KM4_APP_ENTER BIT(12) /* app enter */
#define BIT_KM4_MAIN_ENTER BIT(13) /* main enter */
#define BIT_KM4_WIFI_INIT_START BIT(14) /* wififw init start */
#define BIT_KM4_WIFI_INIT_END BIT(15) /* wififw init end */
#define BIT_KM4_SIMULATION_START BIT(16) /* simulation start */
#define BIT_KM4_SIMULATION_END BIT(17) /* simulation end */
/* FUNCTION */
u32 simulation_stage_set(u32 cpuid, u32 sim_stage_bit);
#endif /* _RTL8721D_SIMULATION_H_ */

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#ifndef _HAL_SOCPS_H_
#define _HAL_SOCPS_H_
typedef struct
{
u32 Module;
u32 Status;
} PWRCFG_TypeDef;
typedef struct
{
u32 Pinmux; /* PINMUX_S0/S1/S2 based on aon_wakepin */
u32 Status;
u32 Polarity; /* 1 is high, 0 is low */
} WAKEPIN_TypeDef;
typedef struct
{
u32 Module;
u32 Event;
u32 Status;
} HSWAKEEVENT_TypeDef;
extern u8 aon_wakepin[4][3];
extern PWRCFG_TypeDef sleep_wevent_config[];
extern PWRCFG_TypeDef sleep_aon_wevent_config[];
extern PWRCFG_TypeDef sleep_hsram_config[];
extern PWRCFG_TypeDef sleep_lsram_config[];
extern PWRCFG_TypeDef dsleep_lsram_config[];
extern WAKEPIN_TypeDef sleep_wakepin_config[];
extern PWRCFG_TypeDef km0_pwrmgt_config[];
extern PWRCFG_TypeDef dsleep_aon_wevent_config[];
extern HSWAKEEVENT_TypeDef hs_wakeevent_config[];
extern void SOCPS_InitSYSIRQ_HP(void);
extern void SOCPS_CPUReset(void);
extern void SOCPS_SleepPG(void);
extern void SOCPS_SleepCG(void);
extern void SOCPS_InitSYSIRQ(void);
extern void SOCPS_SleepInit(void);
extern void SOCPS_DsleepInit(void);
extern void SOCPS_SleepDeInit(void);
extern void SOCPS_DsleepWakeStatusSet(u32 DslpWake);
extern u32 SOCPS_DsleepWakeStatusGet(void);
extern void SOCPS_ClearWakeEvent_HP(void);
extern void SOCPS_SetWakeEvent_HP(u32 Option, u32 NewStatus);
extern void SOCPS_AONTimerCmd(u32 NewStatus);
extern int SOCPS_AONWakeReason(void);
extern void SOCPS_AONWakeClear(u32 BitMask);
extern void SOCPS_AONTimer(u32 SDuration);
extern void SOCPS_AONTSF(u32 EarlyBcnUs, u32 WakeIntvalUs);
extern VOID SOCPS_MMUReFill(VOID);
extern void SOCPS_SetWakeEvent(u32 Option, u32 NewStatus);
extern void SOCPS_SetWakeEventAON(u32 Option, u32 NewStatus);
extern void SOCPS_ClearWakePin(void);
extern void SOCPS_ClearWakeEvent(void);
extern void SOCPS_AudioLDO(u32 NewStatus);
extern void SOCPS_SWRLDO_Suspend(u32 new_status);
extern void SOCPS_OSC2M_Cmd(u32 new_status);
extern void SOCPS_SleepCG_RAM(void);
extern void SOCPS_SleepPG_RAM(void);
extern void SOCPS_DeepSleep_RAM(void);
extern int SOCPS_WakePinCheck(void);
#endif //_HAL_SOCPS_H_

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/**
******************************************************************************
* @file rtl8721d_ssi.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the SPI firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_SPI_H_
#define _RTL8710B_SPI_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup SPI
* @brief SPI driver modules
* @{
*/
/** @addtogroup SPI
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* SPI0:
* - Support Motorola SPI interface
* - Role: Master or Slave
* - Base Address: SPI0_DEV
* - Bus Clk: 100MHz
* - BaudRate: less than or equal to 50M
* - Transfer mode:Tx,Rx,TRx,EEPROM Read when configured as Master; TRx when configured as Slave
* - Data Frame Size: 4-16 bits supported
* - IRQ Number: SPI0_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI0_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI0_RX
*
* SPI1:
* - Support Motorola SPI interface
* - Role: Master
* - Base Address: SPI1_DEV
* - Bus Clk: 50MHz
* - BaudRate: less than or equal to 25M
* - Transfer mode:Tx,Rx,TRx,EEPROM Read
* - Data Frame Size: 4-16 bits supported
* - IRQ Number: SPI1_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI1_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI1_RX
*
*****************************************************************************************
* How to use Normal SPI
*****************************************************************************************
* To use the SPI in DMA mode, the following steps are mandatory:
*
* 1. Enable peripheral clock using the following functions:
* -RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE) for SPI0;
* -RCC_PeriphClockCmd(APBPeriph_SPI1, APBPeriph_SPI1_CLOCK, ENABLE) for SPI1;
*
* 2. Configure the SPIx pinmux:
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIM) when configured as Master;
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIS) when configured as Slave;
*
* 3. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize,
* Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using
* SSI_StructInit() and change some parameters if needed
*
* 4. Init Hardware use step3 parameters:
* SSI_Init(SPI_TypeDef *spi_dev, SSI_InitTypeDef *SSI_InitStruct)
*
* 5. Enable the SPI:
* SSI_Cmd()
*
* 6. When using poll:
* -Using SSI_Writeable() function to make sure that the transmit FIFO is not full,
* then using SSI_WriteData() function to send data
*
* -Using SSI_Readable() function to make sure that the receive FIFO is not empty,
* then using SSI_ReadData() function to receive data
*
* 7. Enable the NVIC and the corresponding interrupt using following function if you need
* to use interrupt mode.
* -SSI_INTConfig(): SPI IRQ Mask set
* -InterruptRegister(): register the SPI irq handler
* -InterruptEn(): Enable the NVIC interrupt and set irq priority
*
*
* @note in SPI_Exported_Functions group, these functions below are about Interrupts
* and flags management:
* -SSI_GetIsr()
* -SSI_GetRawIsr()
* -SSI_INTConfig()
* -SSI_SetRxFifoLevel()
* -SSI_SetTxFifoLevel()
* -SSI_SetIsrClean()
*
*
*****************************************************************************************
* How to use SPI in DMA mode
*****************************************************************************************
* To use the SPI in DMA mode, the following steps are mandatory:
*
* 1. Enable peripheral clock using the following functions:
* -RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE) for SPI0;
* -RCC_PeriphClockCmd(APBPeriph_SPI1, APBPeriph_SPI1_CLOCK, ENABLE) for SPI1;
*
* 2. Configure the SPIx pinmux:
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIM) when configured as Master;
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIS) when configured as Slave;
*
* 3. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize,
* Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using
* SSI_StructInit() and change some parameters if needed
*
* 4. Init Hardware use step3 parameters:
* SSI_Init(SPI_TypeDef *spi_dev, SSI_InitTypeDef *SSI_InitStruct)
*
* 5. Enable the SPI:
* SSI_Cmd()
*
* 6. GDMA related configurations(DMA burst size/source address/destination address/block size etc).
*
* 7. Active the SPI DMA TX/RX using SSI_SetDmaEnable() function.
*
* @note in SPI_Exported_Functions group, these functions below are about DMA:
* -SSI_SetDmaEnable()
* -SSI_SetDmaLevel()
*
*****************************************************************************************
* @endverbatim
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup SPI_Exported_Types SPI Exported Types
* @{
*/
/**
* @brief SPI Init structure definition
*/
typedef struct
{
u32 SPI_DmaRxDataLevel; /*!< Specifies the DMA receive data level.
The dma_rx_req is generated when the number of valid data entries in the
receive FIFO is equal to or above this field value+1,and RDMAE=1.
@note For Amebaz, the value range of this parameter should be 0 to 63,because
the depth of Rx FIFO is 64. */
u32 SPI_DmaTxDataLevel; /*!< Specifies the DMA transmit data level.
The dma_tx_req is generated when the number of valid data entries in the
transmit FIFO is equal to or below this field value,and TDMAE=1.
@note For Amebaz, the value range of this parameter should be 0 to 63,because
the depth of Rx FIFO is 64. */
u32 SPI_RxThresholdLevel; /*!< Specifies the receive FIFO threshold level.
This Parameter controls the level of entries(or above) at which the receive FIFO controller
triggers an interrupt.When the number of receive FIFO entries is greater than or equal to this
value +1,the receive FIFO full interrupt is triggered.
@note For Amebaz, the value range of this parameter should be 0 to 63,because the depth
of Rx FIFO is 64. */
u32 SPI_TxThresholdLevel; /*!< Specifies the transmit FIFO threshold level.
This Parameter controls the level of entries (or below) at which the transmit FIFO controller
triggers an interrupt.When the number of transmit FIFO entries is less than or equal to this
value,the transmit FIFO empty interrupt is triggered.
@note For Amebaz, the value range of this parameter should be 0 to 63,because of the depth
of Rx FIFO is 64. */
u32 SPI_SlaveSelectEnable; /*!< Set the slave select enable flag.
This Parameter controls which slave to be selected by master,each bit in SER register
corresponds to a slave select line(ss_x_n) from spi master.
@note The default vlaue of this parameter is 0,and one slave is selected.if more slaves to be selected,
you may use SW way to do this.And this parameter is used only when the device is master. */
u32 SPI_ClockDivider; /*!< Specifies the SPI Baud Rate.
The value of sclk_out equals to ssi_clk devides the value of this parameter
@note The LSB for this field is always set to 0 and is unaffected by a write operation,which ensures
an even value is held. */
u32 SPI_DataFrameNumber; /*!< Specifies the number of data frames master wants to receive .
When TMOD=10 or TMOD=11,Ctrl1 register uses this value to set the number of data frames to
be continuous received.
@note The value of this parameter should be set to the number of data frames that to be received
minus one.And this parameter is used only when the device is master. */
u32 SPI_DataFrameFormat; /*!< Selects which serial protocol transfers the data .
This parameter can be a value of @ref SPI_Frame_Format_definitions. */
u32 SPI_DataFrameSize; /*!< Selects the data frame length .
This parameter can be a value of @ref SPI_Data_Frame_Size_definitions.
@note Need to right-justify transmit data before writting into the transmit FIFO
The transmit logic ignores the upper unused bits when transmitting the data. */
u32 SPI_InterruptMask; /*!< Specifies which interrupt to be enable.
Each bit in this parameter corresponds to a specific interrupt.*/
u32 SPI_Role; /*!< Specifies the role of SPI device.
This parameter can be a value of @ref SPI_ROLE_definitions. . */
u32 SPI_SclkPhase; /*!< Specifies the serial clock phase.
When SPI_SclkPhase = 0, data are captured on the first edge of the serial clock. When SPI_SclkPhase = 1,
the serial clock starts toggling one cycle after the slave select line is activated, and data
are captured on the second edge of the serial clock.
This parameter can be a value of @ref SPI_SCPH_definitions.
@note Valid when the frame format(FRF) is set to Motorola SPI. */
u32 SPI_SclkPolarity; /*!< Specifies the serial clock polarity.
When SPI_SclkPolarity = 0, the serial clock remains low when idle. When SPI_SclkPolarity = 1,
the serial clock remains high when idle.
This parameter can be a value of @ref SPI_SCPOL_definitions.
@note Valid when the frame format(FRF) is set to Motorola SPI.*/
u32 SPI_TransferMode; /*!< Selects the mode of transfer for serial communication.
This parameter can be a value of @ref SPI_TMOD_definitions.
@note This transfer mode is only valid when the DW_apb_ssi is configured as a master device.*/
u32 SPI_MicrowireControlFrameSize; /*!< Selects the length of the control word for the Microwire frame format.
This parameter can be a value of @ref SPI_MW_Control_Frame_Size_definitions. */
u32 SPI_MicrowireDirection; /*!< Specifies of the data word when the Microwire serial protocol is used.
This parameter can be a value of @ref SPI_MW_Direction_definitions. */
u32 SPI_MicrowireHandshaking; /*!< Specifies Microwire Handshaking.
This parameter can be a value of @ref SPI_MW_Handshake_Enable_definitions. */
u32 SPI_MicrowireTransferMode; /*!< Specifies Microwire Transfer Mode.
This parameter can be a value of @ref SPI_MW_TMOD_definitions. */
}SSI_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPI_Exported_Constants SPI Exported Constants
* @{
*/
/** @defgroup SPI_TMOD_definitions
* @{
*/
#define TMOD_TR (0)
#define TMOD_TO (1)
#define TMOD_RO (2)
#define TMOD_EEPROM_R (3)
/**
* @}
*/
/** @defgroup SPI_SCPOL_definitions
* @{
*/
#define SCPOL_INACTIVE_IS_LOW (0)
#define SCPOL_INACTIVE_IS_HIGH (1)
/**
* @}
*/
/** @defgroup SPI_SCPH_definitions
* @{
*/
#define SCPH_TOGGLES_IN_MIDDLE (0)
#define SCPH_TOGGLES_AT_START (1)
/**
* @}
*/
/** @defgroup SPI_Data_Frame_Size_definitions
* @{
*/
#define DFS_4_BITS (3)
#define DFS_5_BITS (4)
#define DFS_6_BITS (5)
#define DFS_7_BITS (6)
#define DFS_8_BITS (7)
#define DFS_9_BITS (8)
#define DFS_10_BITS (9)
#define DFS_11_BITS (10)
#define DFS_12_BITS (11)
#define DFS_13_BITS (12)
#define DFS_14_BITS (13)
#define DFS_15_BITS (14)
#define DFS_16_BITS (15)
/**
* @}
*/
/** @defgroup SPI_SS_TOGGLE_PHASE_definitions
* @{
*/
#define SPI_SS_NOT_TOGGLE (0)
#define SPI_SS_TOGGLE (1)
/**
* @}
*/
/** @defgroup SPI_MW_Control_Frame_Size_definitions
* @{
*/
#define CFS_1_BIT (0)
#define CFS_2_BITS (1)
#define CFS_3_BITS (2)
#define CFS_4_BITS (3)
#define CFS_5_BITS (4)
#define CFS_6_BITS (5)
#define CFS_7_BITS (6)
#define CFS_8_BITS (7)
#define CFS_9_BITS (8)
#define CFS_10_BITS (9)
#define CFS_11_BITS (10)
#define CFS_12_BITS (11)
#define CFS_13_BITS (12)
#define CFS_14_BITS (13)
#define CFS_15_BITS (14)
#define CFS_16_BITS (15)
/**
* @}
*/
/** @defgroup SPI_ROLE_definitions
* @{
*/
#define SSI_SLAVE (0)
#define SSI_MASTER (1)
/**
* @}
*/
/** @defgroup SPI_Frame_Format_definitions
* @{
*/
#define FRF_MOTOROLA_SPI (0)
#define FRF_TI_SSP (1)
#define FRF_NS_MICROWIRE (2)
#define FRF_RSVD (3)
/**
* @}
*/
/** @defgroup SPI_DMA_Control_definitions
* @{
*/
#define SSI_NODMA (0)
#define SSI_RXDMA_ENABLE (1)
#define SSI_TXDMA_ENABLE (2)
#define SSI_TRDMA_ENABLE (3)
/**
* @}
*/
/** @defgroup SPI_MW_Handshake_Enable_definitions
* @{
*/
#define MW_HANDSHAKE_DISABLE (0)
#define MW_HANDSHAKE_ENABLE (1)
/**
* @}
*/
/** @defgroup SPI_MW_Direction_definitions
* @{
*/
#define MW_DIRECTION_SLAVE_TO_MASTER (0)
#define MW_DIRECTION_MASTER_TO_SLAVE (1)
/**
* @}
*/
/** @defgroup SPI_MW_TMOD_definitions
* @{
*/
#define MW_TMOD_NONSEQUENTIAL (0)
#define MW_TMOD_SEQUENTIAL (1)
/**
* @}
*/
/** @defgroup SPI_FIFO_depth_definitions
* @{
*/
#define SSI_TX_FIFO_DEPTH (64)
#define SSI_RX_FIFO_DEPTH (64)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SPI_Exported_Functions SPI Exported Functions
* @{
*/
/** @defgroup SPI_Exported_Normal_Functions SPI Exported Normal Functions
* @{
*/
_LONG_CALL_ void SSI_Cmd(SPI_TypeDef *spi_dev, u32 NewStaus);
_LONG_CALL_ void SSI_SetSclkPolarity(SPI_TypeDef *spi_dev, u32 SclkPolarity);
_LONG_CALL_ void SSI_SetSclkPhase(SPI_TypeDef *spi_dev, u32 SclkPhase);
_LONG_CALL_ void SSI_WriteData(SPI_TypeDef *spi_dev, u32 value);
_LONG_CALL_ VOID SSI_INTConfig(SPI_TypeDef* spi_dev, u32 SSI_IT, u32 newState);
_LONG_CALL_ void SSI_SetRxFifoLevel(SPI_TypeDef *spi_dev, u32 RxThresholdLevel);
_LONG_CALL_ void SSI_SetTxFifoLevel(SPI_TypeDef *spi_dev, u32 TxThresholdLevel);
_LONG_CALL_ void SSI_SetSlaveEnable(SPI_TypeDef *spi_dev, u32 SlaveIndex);
_LONG_CALL_ u32 SSI_Busy(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_Writeable(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_Readable(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_GetRxCount(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_GetTxCount(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_GetStatus(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_GetIsr(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_ReadData(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_ReceiveData(SPI_TypeDef *spi_dev, void* RxData, u32 Length);
_LONG_CALL_ u32 SSI_SendData(SPI_TypeDef *spi_dev, void* TxData, u32 Length, u32 Role);
_LONG_CALL_ u32 SSI_GetRawIsr(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_GetSlaveEnable(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_GetDataFrameSize(SPI_TypeDef *spi_dev);
_LONG_CALL_ void SSI_SetSampleDelay(SPI_TypeDef *spi_dev, u32 SampleDelay);
_LONG_CALL_ void SSI_Init(SPI_TypeDef *spi_dev, SSI_InitTypeDef *SSI_InitStruct);
_LONG_CALL_ void SSI_StructInit(SSI_InitTypeDef* SSI_InitStruct);
_LONG_CALL_ void SSI_SetDataFrameSize(SPI_TypeDef *spi_dev, u32 DataFrameSize);
_LONG_CALL_ void SSI_SetBaud(SPI_TypeDef *SPIx, u32 BaudRate, u32 IpClk);
_LONG_CALL_ void SSI_SetIsrClean(SPI_TypeDef *spi_dev, u32 InterruptStatus);
_LONG_CALL_ void SSI_SetReadLen(SPI_TypeDef *spi_dev, u32 DataFrameNumber);
/**
* @}
*/
/** @defgroup SPI_Exported_DMA_Functions SPI Exported DMA Functions
* @{
*/
_LONG_CALL_ BOOL SSI_TXGDMA_Init(u32 Index, PGDMA_InitTypeDef GDMA_InitStruct, void *CallbackData,
IRQ_FUN CallbackFunc, u8 *pTxData, u32 Length);
_LONG_CALL_ BOOL SSI_RXGDMA_Init(u8 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData,
IRQ_FUN CallbackFunc, u8 *pRxData, u32 Length);
_LONG_CALL_ void SSI_SetDmaEnable(SPI_TypeDef *spi_dev, u32 newState, u32 Mask);
_LONG_CALL_ void SSI_SetDmaLevel(SPI_TypeDef *spi_dev, u32 TxLeve, u32 RxLevel);
_LONG_CALL_ void SSI_SetBaudDiv(SPI_TypeDef *spi_dev, u32 ClockDivider);
_LONG_CALL_ void SSI_SetRole(SPI_TypeDef *spi_dev, u32 role);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup SPI_Register_Definitions SPI Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup SPI_CTRLR0
* @{
*****************************************************************************/
#define BIT_CTRLR0_DFS ((u32)0x0000000F)
#define BIT_CTRLR0_FRF ((u32)0x00000003 << 4)
#define BIT_CTRLR0_SCPH ((u32)0x00000001 << 6)
#define BIT_CTRLR0_SCPOL ((u32)0x00000001 << 7)
#define BIT_CTRLR0_TMOD ((u32)0x00000003 << 8)
#define BIT_CTRLR0_SLV_OE ((u32)0x00000001 << 10)
#define BIT_CTRLR0_SRL ((u32)0x00000001 << 11)
#define BIT_CTRLR0_CFS ((u32)0x0000000F << 12)
#define BIT_CTRLR0_TXBYTESWP ((u32)0x00000001 << 21)
#define BIT_CTRLR0_TXBITSWP ((u32)0x00000001 << 22)
#define BIT_CTRLR0_RXBYTESWP ((u32)0x00000001 << 23)
#define BIT_CTRLR0_RXBITSWP ((u32)0x00000001 << 24)
#define BIT_CTRLR0_SSTOGGLE ((u32)0x00000001 << 31)
/** @} */
/**************************************************************************//**
* @defgroup SPI_CTRLR1
* @{
*****************************************************************************/
#define BIT_CTRLR1_NDF ((u32)0x0000FFFF)
/** @} */
/**************************************************************************//**
* @defgroup SPI_SSIENR
* @{
*****************************************************************************/
#define BIT_SSIENR_SSI_EN ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup SPI_MWCR
* @{
*****************************************************************************/
#define BIT_MWCR_MWMOD ((u32)0x00000001)
#define BIT_MWCR_MDD ((u32)0x00000001 << 1)
#define BIT_MWCR_MHS ((u32)0x00000001 << 2)
/** @} */
/**************************************************************************//**
* @defgroup SPI_SER
* @{
*****************************************************************************/
#define BIT_SER_SER ((u32)0x0000FFFF)
/** @} */
/**************************************************************************//**
* @defgroup SPI_BAUDR
* @{
*****************************************************************************/
#define BIT_BAUDR_SCKDV ((u32)0x0000FFFF)
/** @} */
/**************************************************************************//**
* @defgroup SPI_TXFLTR
* @{
*****************************************************************************/
#define BIT_TXFTLR_TFT ((u32)0x0000003F)//(TX_ABW-1):0
/** @} */
/**************************************************************************//**
* @defgroup SPI_RXFLTR
* @{
*****************************************************************************/
#define BIT_RXFTLR_RFT ((u32)0x0000003F) // (RX_ABW-1):0
/** @} */
/**************************************************************************//**
* @defgroup SPI_TXFLR
* @{
*****************************************************************************/
#define BIT_MASK_TXFLR_TXTFL ((u32)0x0000007F) // (TX_ABW):0
/** @} */
/**************************************************************************//**
* @defgroup SPI_RXFLR
* @{
*****************************************************************************/
#define BIT_MASK_RXFLR_RXTFL ((u32)0x0000007F) // (RX_ABW):0
/** @} */
/**************************************************************************//**
* @defgroup SPI_SR
* @{
*****************************************************************************/
#define BIT_SR_BUSY ((u32)0x00000001)
#define BIT_SR_TFNF ((u32)0x00000001 << 1)
#define BIT_SR_TFE ((u32)0x00000001 << 2)
#define BIT_SR_RFNE ((u32)0x00000001 << 3)
#define BIT_SR_RFF ((u32)0x00000001 << 4)
#define BIT_SR_TXE ((u32)0x00000001 << 5)
#define BIT_SR_DCOL ((u32)0x00000001 << 6)
/** @} */
/**************************************************************************//**
* @defgroup SPI_IMR
* @{
*****************************************************************************/
#define BIT_IMR_TXEIM ((u32)0x00000001)
#define BIT_IMR_TXOIM ((u32)0x00000001 << 1)
#define BIT_IMR_RXUIM ((u32)0x00000001 << 2)
#define BIT_IMR_RXOIM ((u32)0x00000001 << 3)
#define BIT_IMR_RXFIM ((u32)0x00000001 << 4)
#define BIT_IMR_MSTIM ((u32)0x00000001 << 5) /*Master only*/
#define BIT_IMR_FAEIM ((u32)0x00000001 << 5) /*Slave only*/
#define BIT_IMR_TXUIM ((u32)0x00000001 << 6) /*Slave only*/
#define BIT_IMR_SSRIM ((u32)0x00000001 << 7) /*Slave only*/
/** @} */
/**************************************************************************//**
* @defgroup SPI_ISR
* @{
*****************************************************************************/
#define BIT_ISR_TXEIS ((u32)0x00000001)
#define BIT_ISR_TXOIS ((u32)0x00000001 << 1)
#define BIT_ISR_RXUIS ((u32)0x00000001 << 2)
#define BIT_ISR_RXOIS ((u32)0x00000001 << 3)
#define BIT_ISR_RXFIS ((u32)0x00000001 << 4)
#define BIT_ISR_MSTIS ((u32)0x00000001 << 5) /*Master only*/
#define BIT_ISR_FAEIS ((u32)0x00000001 << 5) /*Slave only*/
#define BIT_ISR_TXUIS ((u32)0x00000001 << 6) /*Slave only*/
#define BIT_ISR_SSRIS ((u32)0x00000001 << 7) /*Slave only*/
/** @} */
/**************************************************************************//**
* @defgroup SPI_RISR
* @{
*****************************************************************************/
#define BIT_RISR_TXEIR ((u32)0x00000001)
#define BIT_RISR_TXOIR ((u32)0x00000001 << 1)
#define BIT_RISR_RXUIR ((u32)0x00000001 << 2)
#define BIT_RISR_RXOIR ((u32)0x00000001 << 3)
#define BIT_RISR_RXFIR ((u32)0x00000001 << 4)
#define BIT_RISR_MSTIR ((u32)0x00000001 << 5) /*Master only*/
#define BIT_RISR_FAEIS ((u32)0x00000001 << 5) /*Slave only*/
#define BIT_RISR_TXUIS ((u32)0x00000001 << 6) /*Slave only*/
#define BIT_RISR_SSRIS ((u32)0x00000001 << 7) /*Slave only*/
/** @} */
/**************************************************************************//**
* @defgroup SPI_DMACR
* @{
*****************************************************************************/
#define BIT_SHIFT_DMACR_RDMAE ((u32)0x00000001)
#define BIT_SHIFT_DMACR_TDMAE ((u32)0x00000001 << 1)
/** @} */
/**************************************************************************//**
* @defgroup SPI_DMATDLR
* @{
*****************************************************************************/
#define BIT_DMATDLR_DMATDL ((u32)0x0000003F) // (TX_ABW-1):0
/** @} */
/**************************************************************************//**
* @defgroup SPI_DMARDLR
* @{
*****************************************************************************/
#define BIT_DMARDLR_DMARDL ((u32)0x0000003F )// (RX_ABW-1):0
/** @} */
/**************************************************************************//**
* @defgroup SPI_DR
* @{
*****************************************************************************/
#define BIT_DR_DR ((u32)0x0000FFFF)
/** @} */
/**************************************************************************//**
* @defgroup SPI_RX_SAMPLE_DELAY
* @{
*****************************************************************************/
#define BIT_RX_SAMPLE_DELAY ((u32)0x000000FF)
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
typedef struct
{
SPI_TypeDef* SPIx;
u32 Tx_HandshakeInterface;
u32 Rx_HandshakeInterface;
IRQn_Type IrqNum;
} SPI_DevTable;
extern const SPI_DevTable SPI_DEV_TABLE[2];
#define SPI_SLAVE_TXERR_WORK_AROUND 1
#endif //_RTL8710B_SPI_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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#ifndef __INC_RTL8721D_SYS_ON_BIT_H
#define __INC_RTL8721D_SYS_ON_BIT_H
//================= SYSON Register Address Definition =====================//
#define REG_SYS_NORESET_FF 0x0138
#endif //__INC_RTL8721D_SYS_ON_BIT_H

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/**
******************************************************************************
* @file rtl8721d_syscfg.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for SYSCFG firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_SYSCFG_H_
#define _RTL8710B_SYSCFG_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup SYSCFG
* @brief SYSCFG driver modules
* @{
*/
/** @addtogroup SYSCFG
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* Used for system, user can not used it if not needed.
*
*****************************************************************************************
* REG_SYS_SYSTEM_CFG0 Introduction
*****************************************************************************************
*
* BIT[31] Trapped PKG_ENG_SEL value 0: normal package; 1: engineering mode
* BIT[30] CHIP_EN PIN input value
* BIT[27:24] BD info
* BIT[16] 1: Test chip; 0:MP
* BIT[11:8] Vendor ID
* BIT[7:4] Chip version
* BIT[3:0] Vendor ID defined in RF
*
*****************************************************************************************
* REG_LP_SYSTEM_CFG1 Introduction
*****************************************************************************************
*
* BIT[31:28] is BIT_SYSCFG_TRP_ICFG, value is load from following trap pin:
* ICFG[0]/ICFG[1]/ICFG[2]/ICFG[3] when trap pin TSET_MODE_SEL = 1
* BIT[27] is BIT_SYSCFG_TRP_BOOT_SEL
* 0: boot normal, 1: uart flash download
* value load from trap pin UART_DOWNLOAD_IMAGE
* BIT[25] is BIT_SYSCFG_TRP_SPSLDO_SEL, Trapped Selection for SPS
* 0: SWR mode; 1: LDO mode
* load from trap pin SPS_LDO_SEL
* BIT[8] BIT_SYS_XCLK_VLD Xtal Clock Stable, 1: Clock Stable
* BIT[0] BIT_SYSCFG_ALDN_STS 1: SYS CFG autoload done; 0; SYSCFG autoload not ready
*
*****************************************************************************************
* REG_LP_SYSTEM_CFG2 Introduction
*****************************************************************************************
*
* BIT[7:0] ROM Information
*
*
*****************************************************************************************
* trap pins
*****************************************************************************************
*
* GPIOA_0:
* TEST_MODE_SEL
* default PD
*
* GPIOA_3:
* SPS_LDO_SEL
* default PU, internal PU
* 0: SWR 1: LDO
* load to 0x1F4[25]
*
* GPIOA_30:
* UART_DOWNLOAD_IMAGE
* default PU
* load to 0x1F4[27]
*
*****************************************************************************************
* @endverbatim
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
* @{
*/
/** @defgroup SYSCFG_Bounding_Option_definitions
* @{
*/
#define SYSCFG_BD_QFN32 ((u32)0x000000000)
#define SYSCFG_BD_QFN48_MCM_8MBFlash ((u32)0x000000001)
#define SYSCFG_BD_QFN48 ((u32)0x000000002)
#define SYSCFG_BD_QFN48_NEW ((u32)0x000000000)
#define SYSCFG_BD_QFN68 ((u32)0x000000007)
#define SYSCFG_BD_QFN68_NEW ((u32)0x000000005)
#define SYSCFG_BD_TFBGA_MCM_8761A ((u32)0x000000004)
/**
* @}
*/
/** @defgroup SYSCFG_CUT_Version_definitions
* @{
*/
#define SYSCFG_CUT_VERSION_A 0
#define SYSCFG_CUT_VERSION_B 1
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SYSCFG_Exported_Functions SYSCFG Exported Functions
* @{
*/
_LONG_CALL_ u32 SYSCFG_GetChipInfo(void);
//_LONG_CALL_ u32 SYSCFG_CUTVersion(void);
_LONG_CALL_ u32 SYSCFG_TRP_LDOMode(void);
_LONG_CALL_ u32 SYSCFG_TRP_UARTImage(void);
_LONG_CALL_ u32 SYSCFG_TRP_ICFG(void);
_LONG_CALL_ u32 SYSCFG_ROMINFO_Get(void);
_LONG_CALL_ void SYSCFG_ROMINFO_Set(void);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
static inline u32
SYSCFG_CUTVersion(void)
{
u32 tmp = (HAL_READ32(0x48000000, 0x000C) >> 8) & 0xF; //get chip version from REG_AON_BOOT_REASON1
if(0 == tmp) {
return SYSCFG_CUT_VERSION_A; /*A-Cut*/
} else {
tmp = HAL_READ32(0x48000000, 0x03F0) & 0xF; //confirm chip version according to REG_LP_SYSTEM_CFG0
if(0 == tmp)
return SYSCFG_CUT_VERSION_B;
else
return tmp;
}
}
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other definations --------------------------------------------------------*/
/******************* Macro definition for TRP_ICFG ********************/
#define SYSCFG_TRP_ICFG_STOP_IN_ROMBOOT 2
#define SYSCFG_TRP_ICFG_FLASH_LOCATION 3 /* Ameba1 used, AmebaZ not use */
#endif //_RTL8710B_SYSCFG_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**************************************************************************//**
* @file system_ARMCM3.h
* @brief CMSIS Device System Header File for
* ARMCM3 Device Series
* @version V1.08
* @date 23. November 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef _SYSTEM_8195A_H
#define _SYSTEM_8195A_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
extern u32 SystemGetCpuClk(void);
extern void SystemSetCpuClk(u8 CpuClk);
/**
* @brief Generate random seed
* @param none
* @return value: random seed value
*/
u32 Gen_RandomSeed(VOID);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_8195A_H */

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/**
******************************************************************************
* @file rtl8721d_tim.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the Timer firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_TIMER_H_
#define _RTL8721D_TIMER_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup Timer
* @brief Timer driver modules
* @{
*/
/** @addtogroup Timer
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* TIM0/TIM1/TIM2/TIM3: used as generic timers for time-base generation
* - Base Address: TIMM00/TIMM01/TIMM02/TIMM03/TIM0/TIM1/TIM2/TIM3
* - Clock Source: 32kHz
* - Resolution: 32bit
* - Count Mode: Upcounting
* - Interrupt Generation
* - Support Upcounting mode
* TIM4:
* - Base Address: TIMM04/TIM4
* - Channels: 1
* - Clock Source: XTAL, normally is 40MHz
* - Resolution: 16bit
* - Prescaler: 8bit
* - Count Mode: Upcounting
* - Input Pin: 1 input capture
* - Interrupt Generation
* - Support Upcounting mode/Statistic Pulse Width mode/Statistic Pulse Number mode
* TIM5:
* - Base Address: TIMM05/TIM5
* - Channels: 6(KM0)/18(KM4)
* - Clock Source: XTAL, normally is 40MHz
* - Resolution: 16bit
* - Prescaler: 8bit
* - Count Mode: Upcounting
* - Interrup Generation
* - Input Pin: 1 input capture
* - Ouput Pin: 6(KM0)/18(KM4) PWM out
* - Support Upcounting mode/Input capture mode/PWM mode/One Pulse mode
*
*****************************************************************************************
* Sys Timer
*****************************************************************************************
* - TIMM00 is used as systimer, so TIMM00 can not be used for other purpose
*
*****************************************************************************************
* Upcounting mode
*****************************************************************************************
* TIMM00~5/TIM0~5 support
* The counter counts from 0 to the auto-reload value (content of the TIMx_ARR register),
* then restarts from 0 and generates a counter overflow interrupt.
*
*****************************************************************************************
* Statistic Pulse Width mode
*****************************************************************************************
* Only TIMM04/TIM4 support
* TIMM04/TIM4 can statistic the width of active level of TRGI. When the TRGI is transferred from
* inactive level to active level, the counter is enabled automatically and counter starts
* from 0. When the TRGI is transferred from active level to inactive level , the counter
* is disabled automatically, the current counter value will be copied to CCR0 field of
* TIMx_CCR0, the CCxIF will be set and an interrupt can be sent if they are enabled.
*
*****************************************************************************************
* Statistic Pulse Number mode
*****************************************************************************************
* Only TIMM04/TIM4 support
* TIM4 can statistic the number of active edge of TRGI in the given period. When the
* counter overflow, the number will be copied to CCR0 field of TIMx_CCR0, the CCxIF will
* be set and an interrupt can be sent if they are enabled
*
*****************************************************************************************
* Input capture mode
*****************************************************************************************
* Only TIMM05/TIM5 supports
* In input capture mode, the CCRx field of TIMx_CCRx are used to latch the value of the
* counter after a transition detected by the TRGI signal. When a capture occurs, the
* corresponding CCXIF flag (TIMx_SR register) is set and an interrupt can be sent if they are enabled.
*
*****************************************************************************************
* PWM mode
*****************************************************************************************
* Only TIMM05/TIM5 supports
* Pulse Width Modulation mode allows you to generate a signal with a frequency determined
* by the value of the TIMx_ARR register and a duty cycle determined by the value of the
* CCRx field of TIMx_CCRx register.
* Period = (ARR + 1)*Tcnt, Duty cycle = CCRx*Tcnt/Period, where Tcnt = Txtal *(PSC+1).
*
*****************************************************************************************
* One Pulse mode
*****************************************************************************************
* Only TIM5 supports
* This mode allows the counter to be started in response to a stimulus and to generate
* a pulse with a programmable length after a programmable delay. Starting the counter can
* be controlled through the active edge of TRGI. Generating the waveform can be done in PWM
* mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR register. This makes
* the counter stop automatically at the next update event.
*
* NOTICE: you shoud pull up/down the pwm pin (PAD_PullCtrl) when you use one pulse mode based on polarity
*
*****************************************************************************************
* How to use Base Timer
*****************************************************************************************
* To use the Timer in Timing(Time base) mode, the following steps are mandatory:
*
* 1. Enable TIM clock :
* RCC_PeriphClockCmd(APBPeriph_GTIMER, APBPeriph_GTIMER_CLOCK, ENABLE)
*
* 2. Fill the TIM_InitStruct with default parameters using:
* RTIM_TimeBaseStructInit(&TIM_InitStruct)
* or setting the desired parameters manually.
*
* 3. Configure the Time Base unit with the corresponding configurations, register TimerIRQHandler
* and enable the NVIC if you need to generate the update interrupt.
* RTIM_TimeBaseInit(TIMx, &TIM_InitStruct, IrqNum, UserCB, UserCBData)
*
* 4. Enable the corresponding interrupt using :
* RTIM_INTConfig(TIMx, TIM_IT_Update, ENABLE)
*
* 5. Enable the TIM counter.
* RTIM_Cmd(TIMx, ENABLE)
*
* Note1: All other functions can be used separately to modify, if needed,
* a specific feature of the Timer.
*
*****************************************************************************************
* How to use Timer in Capture Compare Mode
*****************************************************************************************
* To use the Timer in CC mode, the following steps are mandatory:
*
* 1. Enable TIM clock :
* RCC_PeriphClockCmd(APBPeriph_GTIMER, APBPeriph_GTIMER_CLOCK, ENABLE)
*
* 2. Configure the TIM pinmux:
* Pinmux_Config(PinName, PinFunc)
*
* 3. Configure the Time base unit as described in the first part of this driver if needed,
* else the Timer will run with the default configuration:
* - Autoreload value = 0xFFFF
* - Prescaler value = 0x0000
*
* 4. Fill the TIM_CCInitStruct with the desired parameters including:
* - The TIM Output Compare mode: TIM_CCMode
* - TIM Output Compare Pulse value: TIM_OCMPulse
* - TIM Output Compare Polarity : TIM_CCPolarity
* - TIM Output Compare value update protection: TIM_OCProtection
*
* 5. Configure the desired channel with the corresponding configuration
* RTIM_CCxInit(TIMx, &TIM_CCInitStruct, TIM_Channel)
*
* 6. Enable corresponding TIM channel.
* RTIM_CCxCmd(TIMx, TIM_Channel, TIM_CCx_Enable)
*
* 7. Enable the TIM counter.
* RTIM_Cmd(TIMx, ENABLE)
*
* Note1: All other functions can be used separately to modify, if needed,
* a specific feature of the Timer.
*
* Note2: In case of PWM mode, the TIMx peripheral Preload register on CCRx(TIM_OCProtection)
* should be enabled.
*
* Note3: If the corresponding interrupt is needed, the user should:
* 1. Enable the NVIC to use the TIM interrupts.
* 2. Enable the corresponding interrupt using the function
* RTIM_ITConfig(TIMx, TIM_IT_CCx, ENABLE)
*
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIM_Exported_Types TIM Exported Types
* @{
*/
/**
* @brief TIM Basic Init structure definition
*/
typedef struct {
u32 TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between 0x00 and 0xFF, basic timer dont care */
u32 TIM_Period; /*!< Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter is 16bits for TIM4-5, and 32bits for TIM0-TIM3
you can get it from SourceClock & TIM_Prescaler */
u32 TIM_UpdateEvent; /*!< Specifies whether or not to enable update event(UEV).
This parameter can be ENABLE or DISABLE. ENABLE means UEV Enable, DISABLE means UEV Disable*/
u32 TIM_UpdateSource; /*!< Specifies the update request source. This parameter can be
TIM_UpdateSource_Overflow or TIM_UpdateSource_Global.
TIM_UpdateSource_Overflow means counter overflow generates an update event(UEV).
TIM_UpdateSource_Global means both counter overflow and setting the UG bit can generate UEV.*/
u32 TIM_ARRProtection; /*!< DISABLE or ENABLE, when ENABLE: period will update when cnt = 0(counter overflow, an UEV happens),
or period will update immediatly */
u8 TIM_Idx; /*!< 0~5 */
} RTIM_TimeBaseInitTypeDef;
/**
* @brief TIM Output Compare Init structure definition
*/
typedef struct
{
u32 TIM_CCMode; /*!< Specifies the TIM5 mode. This parameter can be a value of TIM_CCMode_PWM or TIM_CCMode_Inputcapture */
u32 TIM_CCPolarity; /*!< Specifies the polarity. This parameter can be TIM_CCPolarity_High/TIM_CCPolarity_Low.
If CCx channel is configured as output:
TIM_CCPolarity_High means OCx active high.
TIM_CCPolarity_Low means OCx active low.
If CCx channel is configured as input:
TIM_CCPolarity_High means positive edge of TRGI is active for capture.
TIM_CCPolarity_Low means negative edge of TRGI is active for capture. */
u32 TIM_OCProtection; /*!< Output Compare value update protection. TIM_OCPreload_Enable/TIM_OCPreload_Disable.
TIM_OCPreload_Enable means duty cycle will update when UEV happens if write to CCRx field in TIMx_CCRX.
TIM_OCPreload_Disable means duty cycle will update immediately if write to CCRx field in TIMx_CCRX.*/
u32 TIM_OCPulse; /*!< Specifies the output pulse value to be loaded into the CCRx Register, which decides the duty cycle.
This parameter can be a number between 0x0000 and 0xFFFF */
u32 TIM_ICPulseMode; /*!< Specifies the TIM4 mode, TIM_CCMode_PulseWidth or TIM_CCMode_PulseNumber */
} TIM_CCInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIM_Exported_constants TIM Exported constants
* @{
*/
/** @defgroup TIM_Type_definitions
* @{
*/
#define IS_TIM_ALL_TIM(PERIPH) (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIMM00) || \
((PERIPH) == TIMM01) || \
((PERIPH) == TIMM02) || \
((PERIPH) == TIMM03) || \
((PERIPH) == TIMM04) || \
((PERIPH) == TIMM05))
#define IS_TIM_ONE_PULSE_TIM(PERIPH) ((PERIPH) == TIM5 || (PERIPH) == TIMM05)
#define IS_TIM_CCM_TIM(PERIPH) (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIMM04) || \
((PERIPH) == TIMM05))
#define IS_TIM_PWM_TIM(PERIPH) ((PERIPH) == TIM5 || (PERIPH) == TIMM05)
#define IS_TIM_INPULSE_TIM(PERIPH) ((PERIPH) == TIM4 || (PERIPH) == TIMM04)
#define IS_TIM_40M_TIM(PERIPH) (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIMM04) || \
((PERIPH) == TIMM05))
/**
* @}
*/
/** @defgroup TIM_Channel_definitions
* @note TIMM0x: 0~5, TIMx: 0~17
* @{
*/
#define TIM_Channel_0 ((u16)0x0000)
#define TIM_Channel_1 ((u16)0x0001)
#define TIM_Channel_2 ((u16)0x0002)
#define TIM_Channel_3 ((u16)0x0003)
#define TIM_Channel_4 ((u16)0x0004)
#define TIM_Channel_5 ((u16)0x0005)
#define TIM_Channel_6 ((u16)0x0006)
#define TIM_Channel_7 ((u16)0x0007)
#define TIM_Channel_8 ((u16)0x0008)
#define TIM_Channel_9 ((u16)0x0009)
#define TIM_Channel_10 ((u16)0x000a)
#define TIM_Channel_11 ((u16)0x000b)
#define TIM_Channel_12 ((u16)0x000c)
#define TIM_Channel_13 ((u16)0x000d)
#define TIM_Channel_14 ((u16)0x000e)
#define TIM_Channel_15 ((u16)0x000f)
#define TIM_Channel_16 ((u16)0x0010)
#define TIM_Channel_17 ((u16)0x0011)
#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5) || \
((CHANNEL) == TIM_Channel_6) || \
((CHANNEL) == TIM_Channel_7) || \
((CHANNEL) == TIM_Channel_8) || \
((CHANNEL) == TIM_Channel_9) || \
((CHANNEL) == TIM_Channel_10) || \
((CHANNEL) == TIM_Channel_11) || \
((CHANNEL) == TIM_Channel_12) || \
((CHANNEL) == TIM_Channel_13) || \
((CHANNEL) == TIM_Channel_14) || \
((CHANNEL) == TIM_Channel_15) || \
((CHANNEL) == TIM_Channel_16) || \
((CHANNEL) == TIM_Channel_17))
/**
* @}
*/
/** @defgroup TIMx_Prescaler_definitons
* @{
*/
#define IS_TIM_PSC(VAL) (VAL <= 0xFF)
/**
* @}
*/
/** @defgroup TIMx_Control_Bit_definitions
* @{
*/
#define TIM_OPMode_ETP_positive ((u32)0x00000000)
#define TIM_OPMode_ETP_negative ((u32)0x00000100)
#define IS_TIM_OPM_ETP_MODE(MODE) (((MODE) == TIM_OPMode_ETP_positive) || \
((MODE) == TIM_OPMode_ETP_negative))
#define TIM_OPMode_Single ((u32)0x00000008)
#define TIM_OPMode_Repetitive ((u32)0x00000000) /* repeative is PWM mode */
#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
((MODE) == TIM_OPMode_Repetitive))
#define TIM_UpdateSource_Global ((u32)0x00000000) /*!< Source of update is the counter overflow or the setting of UG bit. */
#define TIM_UpdateSource_Overflow ((u32)0x00000004) /*!< Source of update is counter overflow. */
#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
((SOURCE) == TIM_UpdateSource_Overflow))
/**
* @}
*/
/** @defgroup TIMx_Interrupt_Enable_definitions
* @{
*/
#define TIM_IT_Update ((u32)0x00000001)
#define TIM_IT_CC0 ((u32)0x00000002)
#define TIM_IT_CC1 ((u32)0x00000004)
#define TIM_IT_CC2 ((u32)0x00000008)
#define TIM_IT_CC3 ((u32)0x00000010)
#define TIM_IT_CC4 ((u32)0x00000020)
#define TIM_IT_CC5 ((u32)0x00000040)
#define TIM_IT_CC6 ((u32)0x00000080)
#define TIM_IT_CC7 ((u32)0x00000100)
#define TIM_IT_CC8 ((u32)0x00000200)
#define TIM_IT_CC9 ((u32)0x00000400)
#define TIM_IT_CC10 ((u32)0x00000800)
#define TIM_IT_CC11 ((u32)0x00001000)
#define TIM_IT_CC12 ((u32)0x00002000)
#define TIM_IT_CC13 ((u32)0x00004000)
#define TIM_IT_CC14 ((u32)0x00008000)
#define TIM_IT_CC15 ((u32)0x00010000)
#define TIM_IT_CC16 ((u32)0x00020000)
#define TIM_IT_CC17 ((u32)0x00040000)
#define IS_TIM_IT(IT) ((((IT) & (u32)0xFFF80000) == 0x0000) && (((IT) & (u32)0x7FFFF) != 0x0000))
#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_CC6) || \
((IT) == TIM_IT_CC7) || \
((IT) == TIM_IT_CC8) || \
((IT) == TIM_IT_CC9) || \
((IT) == TIM_IT_CC10) || \
((IT) == TIM_IT_CC11) || \
((IT) == TIM_IT_CC12) || \
((IT) == TIM_IT_CC13) || \
((IT) == TIM_IT_CC14) || \
((IT) == TIM_IT_CC15) || \
((IT) == TIM_IT_CC16) || \
((IT) == TIM_IT_CC17))
/**
* @}
*/
/** @defgroup TIMx_PSC_Reload_Mode_definitons
* @{
*/
#define TIM_PSCReloadMode_Update ((u32)0x00000000)
#define TIM_PSCReloadMode_Immediate ((u32)0x00000001)
#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
((RELOAD) == TIM_PSCReloadMode_Immediate))
/**
* @}
*/
/** @defgroup TIMx_Event_Generation_definitons
* @{
*/
#define TIM_EventSource_Update ((u32)0x00000001)
#define TIM_EventSource_CC0 ((u32)0x00000002)
#define TIM_EventSource_CC1 ((u32)0x00000004)
#define TIM_EventSource_CC2 ((u32)0x00000008)
#define TIM_EventSource_CC3 ((u32)0x00000010)
#define TIM_EventSource_CC4 ((u32)0x00000020)
#define TIM_EventSource_CC5 ((u32)0x00000040)
#define TIM_EventSource_CC6 ((u32)0x00000080)
#define TIM_EventSource_CC7 ((u32)0x00000100)
#define TIM_EventSource_CC8 ((u32)0x00000200)
#define TIM_EventSource_CC9 ((u32)0x00000400)
#define TIM_EventSource_CC10 ((u32)0x00000800)
#define TIM_EventSource_CC11 ((u32)0x00001000)
#define TIM_EventSource_CC12 ((u32)0x00002000)
#define TIM_EventSource_CC13 ((u32)0x00004000)
#define TIM_EventSource_CC14 ((u32)0x00008000)
#define TIM_EventSource_CC15 ((u32)0x00010000)
#define TIM_EventSource_CC16 ((u32)0x00020000)
#define TIM_EventSource_CC17 ((u32)0x00040000)
#define IS_LP_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF80) == 0x0000) && \
(((SOURCE) & 0x7F) != 0x0000))
#define IS_HP_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFF80000) == 0x0000) && \
(((SOURCE) & 0x7FFFF) != 0x0000))
/**
* @}
*/
/** @defgroup TIMx_Capture_Compare_definitions
* @{
*/
#define TIM_CCx_Enable ((u32)0x01000000)
#define TIM_CCx_Disable ((u32)0x00000000)
#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || ((CCX) == TIM_CCx_Disable))
#define TIM_OCPreload_Enable ((u32)0x02000000)
#define TIM_OCPreload_Disable ((u32)0x00000000)
#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
((STATE) == TIM_OCPreload_Disable))
#define TIM_CCPolarity_High ((u32)0x00000000) /*!< if input is set : Positive edge of TRGI is active for capture */
#define TIM_CCPolarity_Low ((u32)0x04000000) /*!< if input is set : negative edge of TRGI is active for capture */
#define IS_TIM_CC_POLARITY(POLARITY) (((POLARITY) == TIM_CCPolarity_High) || \
((POLARITY) == TIM_CCPolarity_Low))
/* TIM5 PWM or Inputcapture mode */
#define TIM_CCMode_PWM ((u32)0x00000000)
#define TIM_CCMode_Inputcapture ((u32)0x08000000)
#define IS_TIM_CC_MODE(MODE) (((MODE) == TIM_CCMode_PWM) || \
((MODE) == TIM_CCMode_Inputcapture))
/* TIM4 pulse mode */
#define TIM_CCMode_PulseWidth ((u32)0x00000000)
#define TIM_CCMode_PulseNumber ((u32)0x10000000)
#define IS_TIM_CC_PULSEMODE(MODE) (((MODE) == TIM_CCMode_PulseWidth) || \
((MODE) == TIM_CCMode_PulseNumber))
#define TIM_CCMode_CCR ((u32)0x0000FFFF)
#define IS_TIM_CC_PULSEWIDTH(Compare) ((Compare) <= TIM_CCMode_CCR)
/**
* @}
*/
/**
* @}
*/
/** @defgroup TIM_Exported_Functions TIM Exported Functions
* @{
*/
/** @defgroup TimeBase_Management_Functions TimeBase Management Functions
* @{
*/
_LONG_CALL_ void RTIM_TimeBaseStructInit(RTIM_TimeBaseInitTypeDef* TIM_InitStruct);
_LONG_CALL_ void RTIM_TimeBaseInit(RTIM_TypeDef* TIMx, RTIM_TimeBaseInitTypeDef* TIM_InitStruct, IRQn_Type IrqNum, IRQ_FUN UserCB, u32 UserCBData);
_LONG_CALL_ void RTIM_Cmd(RTIM_TypeDef* TIMx, u32 NewState);
_LONG_CALL_ void RTIM_DeInit(RTIM_TypeDef* TIMx);
_LONG_CALL_ u32 RTIM_GetCount(RTIM_TypeDef* TIMx);
_LONG_CALL_ void RTIM_UpdateDisableConfig(RTIM_TypeDef* TIMx, u32 NewState);
_LONG_CALL_ void RTIM_ARRPreloadConfig(RTIM_TypeDef* TIMx, u32 NewState);
_LONG_CALL_ void RTIM_UpdateRequestConfig(RTIM_TypeDef* TIMx, u32 TIM_UpdateSource);
_LONG_CALL_ void RTIM_PrescalerConfig(RTIM_TypeDef* TIMx, u32 Prescaler, u32 TIM_PSCReloadMode);
_LONG_CALL_ void RTIM_GenerateEvent(RTIM_TypeDef* TIMx, u32 TIM_EventSource);
_LONG_CALL_ void RTIM_ChangePeriod(RTIM_TypeDef* TIMx, u32 Autoreload);
_LONG_CALL_ void RTIM_ChangePeriodImmediate(RTIM_TypeDef* TIMx, u32 Autoreload);
_LONG_CALL_ void RTIM_Reset(RTIM_TypeDef* TIMx);
/**
* @}
*/
/** @defgroup Capture_Compare_Management_Functions Capture Compare Management Functions
* @{
*/
_LONG_CALL_ void RTIM_CCStructInit(TIM_CCInitTypeDef* TIM_CCInitStruct);
_LONG_CALL_ void RTIM_CCxInit(RTIM_TypeDef* TIMx, TIM_CCInitTypeDef* TIM_CCInitStruct, u16 TIM_Channel);
_LONG_CALL_ void RTIM_CCRxMode(RTIM_TypeDef* TIMx, u16 TIM_Channel, u32 TIM_CCMode);
_LONG_CALL_ void RTIM_CCRxSet(RTIM_TypeDef* TIMx, u32 Compare, u16 TIM_Channel);
_LONG_CALL_ u32 RTIM_CCRxGet(RTIM_TypeDef* TIMx, u16 TIM_Channel);
_LONG_CALL_ void RTIM_OCxPreloadConfig(RTIM_TypeDef* TIMx, u32 TIM_OCProtection, u16 TIM_Channel);
_LONG_CALL_ void RTIM_CCxPolarityConfig(RTIM_TypeDef* TIMx, u32 TIM_OCPolarity, u16 TIM_Channel);
_LONG_CALL_ void RTIM_CCxCmd(RTIM_TypeDef* TIMx, u16 TIM_Channel, u32 TIM_CCx);
_LONG_CALL_ void RTIM_SetOnePulseOutputMode(RTIM_TypeDef* TIMx, u32 TIM_OPMode, u32 TrigerPolarity);
/**
* @}
*/
/** @defgroup Interrupt_Management_Functions Interrupt Management Functions
* @{
*/
_LONG_CALL_ void RTIM_INTConfig(RTIM_TypeDef* TIMx, u32 TIM_IT, u32 NewState);
_LONG_CALL_ void RTIM_INTClear(RTIM_TypeDef* TIMx);
_LONG_CALL_ void RTIM_INTClearPendingBit(RTIM_TypeDef* TIMx, u16 TIM_IT);
_LONG_CALL_ u32 RTIM_GetFlagStatus(RTIM_TypeDef* TIMx, u32 TIM_FLAG);
_LONG_CALL_ u32 RTIM_GetINTStatus(RTIM_TypeDef* TIMx, u32 TIM_IT);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup TIM_Register_Definitions TIM Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup TIM_EN
* @{
*****************************************************************************/
#define TIM_CR_CNT_START ((u32)0x00000001) /*!<Counter start */
#define TIM_CR_CNT_STOP ((u32)0x00000002) /*!<Counter stop */
#define TIM_CR_CNT_RUN ((u32)0x00000100) /*!<Counter run status. polling bit */
#define TIM_CR_CNT_STS ((u32)0x00010000) /*!<Counter working status, polling bit */
/** @} */
/**************************************************************************//**
* @defgroup TIM_CR
* @{
*****************************************************************************/
#define TIM_CR_UDIS ((u32)0x00000002) /*!<Update disable */
#define TIM_CR_URS ((u32)0x00000004) /*!<Update request source */
#define TIM_CR_OPM ((u32)0x00000008) /*!<One pulse mode */
#define TIM_CR_ARPE ((u32)0x00000010) /*!<Auto-reload preload enable */
#define TIM_CR_ETP ((u32)0x00000100) /*!<External trigger polarity for one pulse mode (TRGI). */
/** @} */
/**************************************************************************//**
* @defgroup TIM_DIER
* @{
*****************************************************************************/
/* Interrupt EN */
#define TIM_DIER_UIE ((u32)0x00000001) /*!<Update interrupt enable */
#define TIM_DIER_CC0IE ((u32)0x00000002) /*!<Capture/Compare 0 interrupt enable */
#define TIM_DIER_CC1IE ((u32)0x00000004) /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE ((u32)0x00000008) /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE ((u32)0x00000010) /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE ((u32)0x00000020) /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_CC5IE ((u32)0x00000040) /*!<Capture/Compare 5 interrupt enable */
#define TIM_DIER_CC6IE ((u32)0x00000080) /*!<Capture/Compare 6 interrupt enable */
#define TIM_DIER_CC7IE ((u32)0x00000100) /*!<Capture/Compare 7 interrupt enable */
#define TIM_DIER_CC8IE ((u32)0x00000200) /*!<Capture/Compare 8 interrupt enable */
#define TIM_DIER_CC9IE ((u32)0x00000400) /*!<Capture/Compare 9 interrupt enable */
#define TIM_DIER_CC10IE ((u32)0x00000800) /*!<Capture/Compare 10 interrupt enable */
#define TIM_DIER_CC11IE ((u32)0x00001000) /*!<Capture/Compare 11 interrupt enable */
#define TIM_DIER_CC12IE ((u32)0x00002000) /*!<Capture/Compare 12 interrupt enable */
#define TIM_DIER_CC13IE ((u32)0x00004000) /*!<Capture/Compare 13 interrupt enable */
#define TIM_DIER_CC14IE ((u32)0x00008000) /*!<Capture/Compare 14 interrupt enable */
#define TIM_DIER_CC15IE ((u32)0x00010000) /*!<Capture/Compare 15 interrupt enable */
#define TIM_DIER_CC16IE ((u32)0x00020000) /*!<Capture/Compare 16 interrupt enable */
#define TIM_DIER_CC17IE ((u32)0x00040000) /*!<Capture/Compare 17 interrupt enable */
/** @} */
/**************************************************************************//**
* @defgroup TIM_SR
* @{
*****************************************************************************/
#define TIM_SR_UIF ((u32)0x00000001) /*!<Update interrupt Flag */
#define TIM_SR_CC0IF ((u32)0x00000002) /*!<Capture/Compare 0 interrupt Flag */
#define TIM_SR_CC1IF ((u32)0x00000004) /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF ((u32)0x00000008) /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF ((u32)0x00000010) /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF ((u32)0x00000020) /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_CC5IF ((u32)0x00000040) /*!<Capture/Compare 5 interrupt Flag */
#define TIM_SR_CC6IF ((u32)0x00000080) /*!<Capture/Compare 6 interrupt Flag */
#define TIM_SR_CC7IF ((u32)0x00000100) /*!<Capture/Compare 7 interrupt Flag */
#define TIM_SR_CC8IF ((u32)0x00000200) /*!<Capture/Compare 8 interrupt Flag */
#define TIM_SR_CC9IF ((u32)0x00000400) /*!<Capture/Compare 9 interrupt Flag */
#define TIM_SR_CC10IF ((u32)0x00000800) /*!<Capture/Compare 10 interrupt Flag */
#define TIM_SR_CC11IF ((u32)0x00001000) /*!<Capture/Compare 11 interrupt Flag */
#define TIM_SR_CC12IF ((u32)0x00002000) /*!<Capture/Compare 12 interrupt Flag */
#define TIM_SR_CC13IF ((u32)0x00004000) /*!<Capture/Compare 13 interrupt Flag */
#define TIM_SR_CC14IF ((u32)0x00008000) /*!<Capture/Compare 14 interrupt Flag */
#define TIM_SR_CC15IF ((u32)0x00010000) /*!<Capture/Compare 15 interrupt Flag */
#define TIM_SR_CC16IF ((u32)0x00020000) /*!<Capture/Compare 16 interrupt Flag */
#define TIM_SR_CC17IF ((u32)0x00040000) /*!<Capture/Compare 17 interrupt Flag */
#define TIM_SR_UG_DONE ((u32)0x80000000) /*!<UG operation status for TIMx_EGR UG bit, polling bit */
/** @} */
/**************************************************************************//**
* @defgroup TIM_EGR
* @{
*****************************************************************************/
#define TIM_EGR_UG ((u32)0x00000001) /*!<Update Generation */
#define TIM_EGR_CC0G ((u32)0x00000002) /*!<Capture/Compare 0 Generation */
#define TIM_EGR_CC1G ((u32)0x00000004) /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G ((u32)0x00000008) /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G ((u32)0x00000010) /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G ((u32)0x00000020) /*!<Capture/Compare 4 Generation */
#define TIM_EGR_CC5G ((u32)0x00000040) /*!<Capture/Compare 5 Generation */
#define TIM_EGR_CC6G ((u32)0x00000080) /*!<Capture/Compare 6 Generation */
#define TIM_EGR_CC7G ((u32)0x00000100) /*!<Capture/Compare 7 Generation */
#define TIM_EGR_CC8G ((u32)0x00000200) /*!<Capture/Compare 8 Generation */
#define TIM_EGR_CC9G ((u32)0x00000400) /*!<Capture/Compare 9 Generation */
#define TIM_EGR_CC10G ((u32)0x00000800) /*!<Capture/Compare 10 Generation */
#define TIM_EGR_CC11G ((u32)0x00001000) /*!<Capture/Compare 11 Generation */
#define TIM_EGR_CC12G ((u32)0x00002000) /*!<Capture/Compare 12 Generation */
#define TIM_EGR_CC13G ((u32)0x00004000) /*!<Capture/Compare 13 Generation */
#define TIM_EGR_CC14G ((u32)0x00008000) /*!<Capture/Compare 14 Generation */
#define TIM_EGR_CC15G ((u32)0x00010000) /*!<Capture/Compare 15 Generation */
#define TIM_EGR_CC16G ((u32)0x00020000) /*!<Capture/Compare 16 Generation */
#define TIM_EGR_CC17G ((u32)0x00040000) /*!<Capture/Compare 17 Generation */
/** @} */
/**************************************************************************//**
* @defgroup TIM_CCMR
* @{
*****************************************************************************/
#define TIM_CCER_CCxE ((u32)0x01 << 24) /*!<Capture/Compare x input/output enable */
#define TIM_OCER_CCxPE ((u32)0x02 << 24) /*!<Output Compare x Preload enable */
#define TIM_CCER_CCxP ((u32)0x04 << 24) /*!<Capture/Compare x input/output Polarity */
#define TIM_CCER_CCxM ((u32)0x08 << 24) /*!<CCx working mode input or output mode */
#define TIM_ICER_CCxPULSE_MODE ((u32)0x10 << 24) /*!<CCx input pulse mode: width or num, just CC1 valid */
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
typedef struct
{
u32 PWM_CHANNEL;
u32 KM0_CHAN_STATUS;
u32 KM4_CHAN_STATUS;
} PWMCHANCFG_TypeDef;
extern PWMCHANCFG_TypeDef pwmchannel_config[];
extern int TIMx_irq[6];
extern int TIMx_irq_LP[6];
extern RTIM_TypeDef* TIMx[6];
extern RTIM_TypeDef* TIMx_LP[6];
extern u32 TIM_IT_CCx_LP[6];
extern u32 TIM_IT_CCx[18];
#define TIMER_TICK_US 31
#define TIMER_TICK_US_X4 (4*1000000/32000) //32k clock, 31.25us every timer_tick
#endif //_RTL8721D_TIMER_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_trustzone.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the definations of trustzone.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _TRUSTZONE_H_
#define _TRUSTZONE_H_
typedef struct
{
u32 Start;
u32 End;
u32 NSC;
} TZ_CFG_TypeDef;
/*
* <q> Enable SAU
* <i> Value for SAU->CTRL register bit ENABLE
*/
#define SAU_INIT_CTRL_ENABLE 1
/*
* <o> When SAU is disabled
* <0=> All Memory is Secure
* <1=> All Memory is Non-Secure
* <i> Value for SAU->CTRL register bit ALLNS
* <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
*/
#define SAU_INIT_CTRL_ALLNS 0
#define SAU_ENTRYS_NUM 8
#define IDAU_ENTRYS_NUM 8
void BOOT_RAM_TZCfg(void);
/* The TT instruction takes a memory address and returns the configuration of the Memory Protection Unit (MPU) at that address.
The cmse_address_info_t is declared as following:
typedef union {
struct cmse_address_info {
unsigned mpu_region:8;
unsigned :8;
unsigned mpu_region_valid:1;
unsigned :1;
unsigned read_ok:1;
unsigned readwrite_ok:1;
unsigned :12;
} flags;
unsigned value;
} cmse_address_info_t;
When executed in the secure state the result of TT instruction is extended to return the SAU and IDAU configurations at the specific address.
The extended cmse_address_info_t is declared as following:
typedef union {
struct cmse_address_info {
unsigned mpu_region:8;
unsigned sau_region:8;
unsigned mpu_region_valid:1;
unsigned sau_region_valid:1;
unsigned read_ok:1;
unsigned readwrite_ok:1;
unsigned nonsecure_read_ok:1;
unsigned nonsecure_readwrite_ok:1;
unsigned secure:1;
unsigned idau_region_valid:1;
unsigned idau_region:8;
} flags;
unsigned value;
} cmse_address_info_t;
As a result, these extended bits are only valid when executing in Secure state, and are UNDEFINED if used from Non-secure state.
*/
__STATIC_INLINE u32 TrustZone_IsSecure(void)
{
#if defined (ARM_CORE_CM4)
cmse_address_info_t cmse_address_info = cmse_TT((void *)DiagPrintf);
return cmse_address_info.flags.secure;
#else
return 0;
#endif
}
#endif //_TRUSTZONE_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_uart.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the UART firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_UART_H_
#define _RTL8710B_UART_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup UART
* @{
*/
/** @addtogroup UART
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* KM4 UART0:
* - Base Address: UART0_DEV
* - IPclk: XTAL, normally is 40MHz
* - BaudRate: 110~6000000
* - Low Power Rx: Support
* - SocPs: SleepMode (clock gating & power gating)
* - Boot From UART without Flash
* - IRQ: UART0_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART0_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART0_RX
*
* KM4 UART1_BT: The same as KM4 UART0 except following
* - Base Address: UART1_DEV
* - IRQ: UART1_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART1_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART1_RX
*
* KM0 LUART: The same as KM4 UART0 except following
* - Base Address: UART3_DEV
* - IRQ: UARTLP_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART3_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART3_RX
*
* KM0 LOG UART: Used as loguart
* - Base Address: UART2_DEV
* - IPclk: XTAL, normally is 40MHz
* - BaudRate: 110~6000000, default set 115200 for log
* - Low Power Rx: Support
* - Flash Program use LOGUART
* - IRQ: UART_LOG_IRQ
*
*****************************************************************************************
* Low Power Rx
*****************************************************************************************
* All UART support
* UART can receive data when soc enter power save mode
* baudrate: 110~115200
*
*****************************************************************************************
* How to use Normal Uart
*****************************************************************************************
* To use the normal uart mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power(it is enable default):
* RCC_PeriphClockCmd(APBPeriph_UARTx, APBPeriph_UARTx_CLOCK, ENABLE);
*
* 2. configure the UART pinmux
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_UART)
*
* 3. Set default parameters, change some parameter if needed
* UART_StructInit(UART_InitTypeDef* UART_InitStruct)
*
* 4. init hardware use step3 parameters.
* UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef *UART_InitStruct)
*
* 5. Set Baud Rate.
* UART_SetBaud(UART_TypeDef* UARTx, u32 BaudRate)
*
* 6. Enable IRQ using following function if needed
* UART_INTConfig(): UART IRQ Mask set
* InterruptRegister(): register the uart irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 7. Enable uart rx path:
* UART_RxCmd().
*
* @note in UART_Normal_functions group, these functions below are about Interrupts
* and flags management.
* UART_INTConfig()
* UART_IntStatus()
* UART_LineStatusGet()
*
*****************************************************************************************
* How to use uart in DMA mode
*****************************************************************************************
* To use the uart in DMA mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power(it is enable default):
* RCC_PeriphClockCmd(APBPeriph_UARTx, APBPeriph_UARTx_CLOCK, ENABLE);
*
* 2. configure the UART pinmux
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_UART)
*
* 3. Set default parameters, and change DMA mode open UART_InitStruct
* UART_StructInit(UART_InitTypeDef* UART_InitStruct)
*
* 4. init hardware use step3 parameters.
* UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef *UART_InitStruct)
*
* 5. Set Baud Rate.
* UART_SetBaud(UART_TypeDef* UARTx, u32 BaudRate)
*
* 6. Enable uart rx path:
* UART_RxCmd().
*
* 7. Configure the uart DMA burst size:
* UART_TXDMAConfig()
* UART_RXDMAConfig().
*
* 8. Active the UART TX/RX DMA Request:
* UART_TXDMACmd()
* UART_RXDMACmd().
*
* 9. GDMA related configurations(source address/destination address/block size etc.).
* UART_TXGDMA_Init()
* UART_RXGDMA_Init()
*
*****************************************************************************************
* How to use uart in Low Power mode
*****************************************************************************************
* To use the uart in Low Power mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power(it is enable default):
* RCC_PeriphClockCmd(APBPeriph_UARTx, APBPeriph_UARTx_CLOCK, ENABLE);
*
* 2. configure the UART pinmux
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_UART)
*
* 3. Set default parameters, change some parameter if needed
* UART_StructInit(UART_InitTypeDef* UART_InitStruct)
*
* 4. init hardware use step3 parameters.
* UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef *UART_InitStruct)
*
* 5. Set Baud Rate.
* UART_SetBaud(UART_TypeDef* UARTx, u32 BaudRate)
*
* 6. Enable IRQ using following function if needed
* UART_INTConfig(): UART IRQ Mask set
* InterruptRegister(): register the uart irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 7. Configure monitor parameters:
* UART_MonitorParaConfig();
*
* 8. Enable monitor function if needed.
* UART_RxMonitorCmd()
*
* 9. Set lower power clock source
* RCC_PeriphClockSource_UART (UART_TypeDef* UARTx, u32 Source)
*
* 10. Set the low power RX Baud Rate
* UART_LPRxBaudSet(UART_TypeDef* UARTx, u32 BaudRate, u32 RxIPClockHz)
*
* 11. Enable uart rx path:
* UART_RxCmd().
*
* @note when uart work in low power rx mode, clock source can switch between
* XTAL and OSC. As for how and when to excute switching action,
* refer to related uart specifications for more details.
*
* @note Besides, if more details about the uart low power rx path contens is needed,
* please refer to uart specifications.
*
*****************************************************************************************
* How to use uart in IrDA mode
*****************************************************************************************
* To use the uart in IrDA mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power(it is enable default):
* RCC_PeriphClockCmd(APBPeriph_UARTx, APBPeriph_UARTx_CLOCK, ENABLE);
*
* 2. configure the pinmux:
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_UART)
*
* 3. Disable rx path:
* UART_RxCmd().
*
* 4. Program the IrDA tx pulse width and location and IrDA rx pulse filter:
* UART_IrDAStructInit(IrDA_InitTypeDef * IrDA_InitStruct)
*
* 5. Init Hardware:
* UART_IrDAInit(UART_TypeDef* UARTx, IrDA_InitTypeDef * IrDA_InitStruct).
*
* 6. Enable the IrDA function:
* UART_IrDACmd().
*
* 7. According to the IrDA SIR protocol data format requrement, program Word Length,
* Stop Bit, Parity and DMA Mode(ENABLE/DISABLE):
* UART_StructInit(UART_InitTypeDef* UART_InitStruct)
* UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef *UART_InitStruct)
*
* 8. Program the Baud Rate:
* UART_SetBaud().
*
* 9. Enable IRQ if needed:
* UART_INTConfig(): UART IRQ Mask set
* InterruptRegister(): register the uart irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 10. Enable uart rx path:
* UART_RxCmd().
*
* @note AmebaD IrDA just support IrDA SIR protocol, setting baud rate is no more than
* 115200 bps.
*
* @note because IrDA transfers data using infrared carrier and for the property of the
* IrDA transceiver, IrDA just work in half duplex mode. For details, refer to the IrDA
* protocol specification.
*****************************************************************************************
* @endverbatim
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup UART_Exported_Types UART Exported Types
* @{
*/
/**
* @brief UART Init structure definition
*/
typedef struct
{
u32 DmaModeCtrl; /*!< Specifies the uart DMA mode state.
This parameter can be ENABLE or DISABLE. */
u32 WordLen; /*!< Specifies the UART word length.
This parameter can be a value of @ref UART_Word_length_define. */
u32 StopBit; /*!< Specifies the UART stop bit number.
This parameter can be a value of @ref UART_Stop_Bit_define. */
u32 Parity; /*!< Specifies the UART parity.
This parameter can be a value of @ref UART_Parity_Enable_define. */
u32 ParityType; /*!< Specifies the UART parity type.
This parameter can be a value of @ref UART_Parity_Type_define. */
u32 StickParity; /*!< Specifies the UART stick parity.
This parameter can be a value of @ref UART_Stick_Parity_Type_define. */
u32 FlowControl; /*!< Specifies the UART auto flow control.
This parameter can be ENABLE or DISABLE. */
u32 RxFifoTrigLevel; /*!< Specifies the UART rx fifo trigger level.
This parameter can be a value of @ref UART_RX_FIFO_TRIGGER_LEVEL_define. */
u32 RxErReportCtrl; /*!< Specifies the UART rx error report control.
This parameter can be a value of @ref UART_Rx_Err_Report_define. */
u32 RxTimeOutCnt; /*!< Specifies the UART rx time out counter.
This parameter can be a number between 0x00 and 0xffff.. */
} UART_InitTypeDef;
/**
* @brief UART IRDA Init structure definition
*
*/
typedef struct
{
u32 UART_IrDARxInv; /*!< Specifies the uart irda rx invert control.
This parameter can be ENABLE or DISABLE.
ENABLE: invert the irda input signal.
DISABLE: does't invert the irda input signal.
@note This parameter is only used in IrDA mode. */
u32 UART_IrDATxInv; /*!< Specifies the uart irda tx invert control.
This parameter can be ENABLE or DISABLE.
ENABLE: invert the irda output signal.
DISABLE: does't invert the irda output signal.
@note This parameter is only used in IrDA mode. */
u32 UART_UpperShift; /*!< Specifies the uart irda tx pulse right edge shift direction.
This parameter can be a value of @ref UART_IRDA_PULSE_SHIFT_define. */
u32 UART_UpperShiftVal; /*!< Specifies the uart irda tx pulse right edge shift value in the given direction.
This parameter can be a number between 0x0000 and 0x7fff. */
u32 UART_LowShift; /*!< Specifies the uart irda tx pulse left edge shift direction.
This parameter can be a value of @ref UART_IRDA_PULSE_SHIFT_define. */
u32 UART_LowShiftVal; /*!< Specifies the uart irda tx pulse left edge shift value in the given direction.
This parameter can be a number between 0x0000 and 0x7fff. */
u32 UART_RxFilterThres; /*!< Specifies the uart irda rx filter threshold.
This parameter can be a number between 0x0000 and 0x7fff
@note This parameter is only used in IrDA mode. */
u32 UART_RxFilterCmd; /*!< Specifies the uart irda rx filter control.
This parameter can be ENABLE or DISABLE.
ENABLE: uart IrDA rx filter is used.
DISABLE: uart IrDA rx filter is not used.
@note This parameter is only used in IrDA mode. */
}IrDA_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UART_Exported_Constants UART Exported Constants
* @{
*/
/** @defgroup UART_IRDA_PULSE_SHIFT_define
* @{
*/
#define UART_IRDA_PULSE_LEFT_SHIFT ((u32)0x00000000)
#define UART_IRDA_PULSE_RIGHT_SHIFT ((u32)0x00000001)
#define IS_IRDA_PUL_SHIFT(SHIFT) (((SHIFT) == UART_IRDA_PULSE_LEFT_SHIFT) || \
((SHIFT) == UART_IRDA_PULSE_RIGHT_SHIFT))
/**
* @}
*/
/** @defgroup UART_RX_FIFO_TRIGGER_LEVEL_define
* @{
*/
#define UART_RX_FIFOTRIG_LEVEL_1BYTES ((u32)0x00000000)
#define UART_RX_FIFOTRIG_LEVEL_4BYTES ((u32)0x00000040)
#define UART_RX_FIFOTRIG_LEVEL_8BYTES ((u32)0x00000080)
#define UART_RX_FIFOTRIG_LEVEL_14BYTES ((u32)0x000000c0)
#define IS_UART_RXFIFO_LEVEL(LEVEL) (((LEVEL) == UART_RX_FIFOTRIG_LEVEL_1BYTES) || \
((LEVEL) == UART_RX_FIFOTRIG_LEVEL_4BYTES) || \
((LEVEL) == UART_RX_FIFOTRIG_LEVEL_8BYTES) || \
((LEVEL) == UART_RX_FIFOTRIG_LEVEL_14BYTES))
/**
* @}
*/
/** @defgroup UART_Word_length_define
* @{
*/
#define RUART_WLS_7BITS ((u32)0x00000000)
#define RUART_WLS_8BITS ((u32)0x00000001)
#define IS_UART_WLS(VAL) (((VAL) == RUART_WLS_7BITS) || \
((VAL) == RUART_WLS_8BITS))
/**
* @}
*/
/** @defgroup UART_Stop_Bit_define
* @{
*/
#define RUART_STOP_BIT_1 ((u32)0x00000000)
#define RUART_STOP_BIT_2 ((u32)0x00000001)
#define IS_UART_STOP_BIT(VAL) (((VAL) == RUART_STOP_BIT_1) || \
((VAL) == RUART_STOP_BIT_2))
/**
* @}
*/
/** @defgroup UART_Parity_Enable_define
* @{
*/
#define RUART_PARITY_DISABLE ((u32)0x00000000)
#define RUART_PARITY_ENABLE ((u32)0x00000001)
#define IS_UART_PARITY_ENABLE(VAL) (((VAL) == RUART_PARITY_DISABLE) || \
((VAL) == RUART_PARITY_ENABLE))
/**
* @}
*/
/** @defgroup UART_Parity_Type_define
* @{
*/
#define RUART_ODD_PARITY ((u32)0x00000000)
#define RUART_EVEN_PARITY ((u32)0x00000001)
#define IS_UART_PARITY_TYPE(VAL) (((VAL) == RUART_ODD_PARITY) || \
((VAL) == RUART_EVEN_PARITY))
/**
* @}
*/
/** @defgroup UART_Stick_Parity_Type_define
* @{
*/
#define RUART_STICK_PARITY_DISABLE ((u32)0x00000000)
#define RUART_STICK_PARITY_ENABLE ((u32)0x00000001)
#define IS_UART_STICK_PARITY_ENABLE(VAL) (((VAL) == RUART_STICK_PARITY_DISABLE) || \
((VAL) == RUART_STICK_PARITY_ENABLE))
/**
* @}
*/
/** @defgroup UART_Interrupt_ID_define
* @{
*/
#define RUART_MODEM_STATUS ((u32)0x00000000)
#define RUART_TX_FIFO_EMPTY ((u32)0x00000001)
#define RUART_RECEIVER_DATA_AVAILABLE ((u32)0x00000002)
#define RUART_RECEIVE_LINE_STATUS ((u32)0x00000003)
#define RUART_LP_RX_MONITOR_DONE ((u32)0x00000004)
#define RUART_TIME_OUT_INDICATION ((u32)0x00000006)
/**
* @}
*/
/** @defgroup UART_RX_Clock_Source_define
* @{
*/
#define UART_RX_CLK_XTAL_40M ((u32)0x00000000)
#define UART_RX_CLK_OSC_LP ((u32)0x00000001)
#define UART_RX_CLK_XTAL_LP ((u32)0x00000002)
#define IS_UART_RX_CLK(CLK) (((CLK) == UART_RX_CLK_XTAL_40M) || \
((CLK) == UART_RX_CLK_XTAL_LP) || \
((CLK) == UART_RX_CLK_OSC_LP))
/**
* @}
*/
/** @defgroup UART_Rx_Err_Report_define
* @{
*/
#define UART_RX_EEROR_REPORT_DISABLE ((u32)0x00000000)
#define UART_RX_EEROR_REPORT_ENABLE ((u32)0x00000001)
#define IS_UART_RX_ERROR_REPORT(REPORT) (((REPORT) == UART_RX_EEROR_REPORT_DISABLE) || \
((REPORT) == UART_RX_EEROR_REPORT_ENABLE) )
/**
* @}
*/
/** @defgroup UART_Low_Power_Peripheral_define
* @{
*/
#define IS_LPUART_PERIPH(PERIPH) (((PERIPH) == UART0_DEV) || ((PERIPH) == UART2_DEV) || ((PERIPH) == UART3_DEV))
/**
* @}
*/
/** @defgroup UART_SoftWare_Status_define
* @{
*/
#define STATETX_DMA 1
#define STATETX_INT 2
#define STATETX_POLL 3
#define STATERX_DMA 1
#define STATERX_INT 2
#define STATERX_POLL 3
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UART_Exported_Functions UART Exported Functions
* @{
*/
/** @defgroup UART_Normal_functions
* @{
*/
_LONG_CALL_ void UART_DeInit(UART_TypeDef* UARTx);
_LONG_CALL_ void UART_StructInit(UART_InitTypeDef* UART_InitStruct);
_LONG_CALL_ void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef *UART_InitStruct);
_LONG_CALL_ u32 UART_BaudParaGet(u32 baudrate, u32 *ovsr, u32 *ovsr_adj);
_LONG_CALL_ void UART_BaudParaGetFull(u32 IPclk, u32 baudrate, u32 *ovsr, u32 *ovsr_adj);
_LONG_CALL_ void UART_SetBaudExt(UART_TypeDef* UARTx, u32 Ovsr, u32 Ovsr_adj);
_LONG_CALL_ void UART_SetBaud(UART_TypeDef* UARTx, u32 BaudRate);
_LONG_CALL_ void UART_SetRxLevel(UART_TypeDef* UARTx, u32 FifoLv);
_LONG_CALL_ void UART_RxCmd(UART_TypeDef* UARTx, u32 NewState);
_LONG_CALL_ u32 UART_Writable(UART_TypeDef* UARTx);
_LONG_CALL_ u32 UART_Readable(UART_TypeDef* UARTx);
_LONG_CALL_ void UART_CharPut(UART_TypeDef* UARTx, u8 TxData);
_LONG_CALL_ void UART_CharGet(UART_TypeDef* UARTx, u8 *pRxByte);
_LONG_CALL_ void UART_ReceiveData(UART_TypeDef* UARTx, u8* OutBuf, u32 Count);
_LONG_CALL_ void UART_SendData(UART_TypeDef* UARTx, u8* InBuf, u32 Count);
_LONG_CALL_ u32 UART_ReceiveDataTO(UART_TypeDef* UARTx, u8* OutBuf, u32 Count, u32 Times);
_LONG_CALL_ u32 UART_SendDataTO(UART_TypeDef* UARTx,u8* InBuf,u32 Count, u32 Times);
_LONG_CALL_ void UART_RxByteCntClear(UART_TypeDef* UARTx);
_LONG_CALL_ u32 UART_RxByteCntGet(UART_TypeDef* UARTx);
_LONG_CALL_ void UART_BreakCtl(UART_TypeDef* UARTx, u32 NewState);
_LONG_CALL_ u32 UART_ClearRxFifo(UART_TypeDef* UARTx);
_LONG_CALL_ void UART_ClearTxFifo(UART_TypeDef* UARTx);
_LONG_CALL_ void UART_INTConfig(UART_TypeDef* UARTx, u32 UART_IT, u32 newState);
_LONG_CALL_ u32 UART_IntStatus(UART_TypeDef* UARTx);
_LONG_CALL_ u32 UART_ModemStatusGet(UART_TypeDef* UARTx);
_LONG_CALL_ u32 UART_LineStatusGet(UART_TypeDef* UARTx);
_LONG_CALL_ void UART_WaitBusy(UART_TypeDef* UARTx, u32 PollTimes);
/**
* @}
*/
/** @defgroup UART_DMA_functions
* @{
*/
_LONG_CALL_ void UART_TXDMAConfig(UART_TypeDef* UARTx, u32 TxDmaBurstSize);
_LONG_CALL_ void UART_RXDMAConfig(UART_TypeDef* UARTx, u32 RxDmaBurstSize);
_LONG_CALL_ void UART_TXDMACmd(UART_TypeDef* UARTx, u32 NewState);
_LONG_CALL_ void UART_RXDMACmd(UART_TypeDef* UARTx, u32 NewState);
_LONG_CALL_ BOOL UART_TXGDMA_Init(u8 UartIndex, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pTxBuf, int TxCount);
_LONG_CALL_ BOOL UART_RXGDMA_Init(u8 UartIndex, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pRxBuf, int RxCount);
/**
* @}
*/
/** @defgroup UART_Low_Power_functions
* @{
*/
_LONG_CALL_ void UART_MonitorParaConfig(UART_TypeDef* UARTx, u32 BitNumThres, u32 OscPerbitUpdCtrl);
_LONG_CALL_ void UART_LPRxBaudSet(UART_TypeDef* UARTx, u32 BaudRate, u32 RxIPClockHz);
_LONG_CALL_ void UART_RxMonitorCmd(UART_TypeDef* UARTx, u32 NewState);
_LONG_CALL_ u32 UART_RxMonBaudCtrlRegGet(UART_TypeDef* UARTx);
_LONG_CALL_ u32 UART_RxMonitorSatusGet(UART_TypeDef* UARTx);
/**
* @}
*/
/** @defgroup UART_IRDA_functions
* @{
*/
_LONG_CALL_ void UART_IrDAStructInit(IrDA_InitTypeDef * IrDA_InitStruct);
_LONG_CALL_ void UART_IrDAInit(UART_TypeDef* UARTx, IrDA_InitTypeDef * IrDA_InitStruct);
_LONG_CALL_ void UART_IrDACmd(UART_TypeDef* UARTx, u32 NewState);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup UART_Register_Definitions UART Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup UART_DLH_INTCR
* @{
*****************************************************************************/
#define RUART_IER_ERBI ((u32)0x00000001) /*BIT[0], Enable received data available interrupt (rx trigger)*/
#define RUART_IER_ETBEI ((u32)0x00000001<<1) /*BIT[1], Enable transmitter FIFO empty interrupt (tx fifo empty)*/
#define RUART_IER_ELSI ((u32)0x00000001<<2) /*BIT[2], Enable receiver line status interrupt (receiver line status)*/
#define RUART_IER_EDSSI ((u32)0x00000001<<3) /*BIT[3], Enable modem status interrupt (modem status transition)*/
#define RUART_IER_EDMI ((u32)0x00000001<<4) /*BIT[4], Enable low power rx monitor done interrupt (monitor done)*/
#define RUART_IER_ETOI ((u32)0x00000001<<5) /*BIT[5], Enable rx time out interrupt*/
/** @} */
/**************************************************************************//**
* @defgroup UART_INTID
* @{
*****************************************************************************/
#define RUART_IIR_INT_PEND ((u32)0x00000001) /*uart interrupt global status*/
#define RUART_IIR_INT_ID ((u32)0x00000007<<1) /*Uart Interrupt ID mask, register INTID[3:1]*/
/** @} */
/**************************************************************************//**
* @defgroup UART_FCR
* @{
*****************************************************************************/
#define RUART_FIFO_CTL_RX_ERR_RPT ((u32)0x00000001) /*BIT[0], 0x01, RX error report control bit*/
#define RUART_FIFO_CTL_REG_CLEAR_RXFIFO ((u32)0x00000001<<1) /*BIT[1], 0x02, Write 1 clear*/
#define RUART_FIFO_CTL_REG_CLEAR_TXFIFO ((u32)0x00000001<<2) /*BIT[2], 0x04, Write 1 clear*/
#define RUART_FIFO_CTL_REG_DMA_ENABLE ((u32)0x00000001<<3) /*BIT[3], 0x08, Uart DMA control bit*/
#define RUART_FIFO_CTL_REG_RX_TRG_LEV ((u32)0x00000003<<6) /*BIT[7:6], 0xc0, Uart rx trigger level field*/
/** @} */
/**************************************************************************//**
* @defgroup UART_MCR
* @{
*****************************************************************************/
#define RUART_MCL_FLOW_ENABLE ((u32)((0x00000001 << 5) | (0x00000001 << 1))) /*BIT[1],BIT[5],Uart auto flow control enable bit*/
/** @} */
/**************************************************************************//**
* @defgroup UART_LCR
* @{
*****************************************************************************/
#define BIT_UART_LCR_BREAK_CTRL ((u32)0x00000001<<6) /*BIT[6], Uart break control function enable bit*/
#define RUART_LINE_CTL_REG_DLAB_ENABLE ((u32)0x00000001<<7) /*BIT[7], 0x80*/
/** @} */
/**************************************************************************//**
* @defgroup UART_LSR
* @{
*****************************************************************************/
#define RUART_LINE_STATUS_REG_DR ((u32)0x00000001) /*BIT[0], Data ready indicator*/
#define RUART_LINE_STATUS_ERR_OVERRUN ((u32)0x00000001<<1) /*BIT[1], Over run*/
#define RUART_LINE_STATUS_ERR_PARITY ((u32)0x00000001<<2) /*BIT[2], Parity error*/
#define RUART_LINE_STATUS_ERR_FRAMING ((u32)0x00000001<<3) /*BIT[3], Framing error*/
#define RUART_LINE_STATUS_ERR_BREAK ((u32)0x00000001<<4) /*BIT[4], Break interrupt error*/
#define RUART_LINE_STATUS_REG_THRE ((u32)0x00000001<<5) /*BIT[5], 0x20, Transmit holding register empty interrupt enable*/
#define RUART_LINE_STATUS_REG_TEMT ((u32)0x00000001<<6) /*BIT[6], 0x40, Transmitter empty indicator(bit)*/
#define RUART_LINE_STATUS_ERR_RXFIFO ((u32)0x00000001<<7) /*BIT[7], RX FIFO error*/
#define RUART_LINE_STATUS_ERR (RUART_LINE_STATUS_ERR_OVERRUN |RUART_LINE_STATUS_ERR_PARITY| \
RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \
RUART_LINE_STATUS_ERR_RXFIFO) /*Line status error*/
/** @} */
/**************************************************************************//**
* @defgroup UART_SPR
* @{
*****************************************************************************/
#define RUART_SP_REG_RXBREAK_INT_STATUS ((u32)0x00000001<<7) /*BIT[7], 0x80, Write 1 clear*/
#define RUART_SP_REG_DBG_SEL ((u32)0x0000000F<<8) /*BIT[11:8], Debug port selection*/
#define RUART_SP_REG_XFACTOR_ADJ ((u32)0x000007FF<<16) /*BIT[26:16], ovsr_adj parameter field*/
/** @} */
/**************************************************************************//**
* @defgroup UART_STSR
* @{
*****************************************************************************/
//#define RUART_STS_REG_RESET_RCV ((u32)0x00000001<<3) /*BIT[3], 0x08, Reset uart receiver*/
#define RUART_STS_REG_XFACTOR ((u32)0x000FFFFF<<4) /*BIT[23:4]ovsr parameter field*/
/** @} */
/**************************************************************************//**
* @defgroup UART_MISCR
* @{
*****************************************************************************/
#define RUART_IRDA_ENABLE ((u32)0x00000001) /*BIT[0], Enable IrDA*/
#define RUART_IRDA_TX_INVERT ((u32)0x00000001 << 13) /*BIT[13], Enable IrDA tx invert*/
#define RUART_IRDA_RX_INVERT ((u32)0x00000001 << 14) /*BIT[14], Enable IrDA rx invert*/
#define RUART_TXDMA_BURSTSIZE_MASK ((u32)0x0000001F << 3) /*BIT[7:3], Uart tx DMA burst size mask.
This field value must be no more than 16.
Because tx fifo depth is 16 in UART IP hardware*/
#define RUART_RXDMA_BURSTSIZE_MASK ((u32)0x0000001F << 8) /*BIT[12:8], Uart rx DMA burst size mask.
This field value must be no more than 16.
Because rx fifo depth is 16 in uart IP hardware*/
#define RUART_TXDMA_ENABLE ((u32)0x00000001 << 1) /*BIT[1], Uart tx DMA enable bit*/
#define RUART_RXDMA_ENABLE ((u32)0x00000001 << 2) /*BIT[2], Uart rx DMA enable bit*/
#define RUART_RXDMA_OWNER ((u32)0x00000001 << 15) /*BIT[15], the DMA flow controller selection(UART or DMA)*/
#define RUART_RXDMA_DUMMY_DATA ((u32)0x000000FF << 16) /*BIT[23:16], dummy data when uart is the flow controller*/
#define RUART_RXDMA_DUMMY_FLAG ((u32)0x00000001 << 24) /*BIT[24], this bit is set when master read dummy data from UART RX FIFO, it can be cleared by software
by writing 1 to this bit*/
/** @} */
/**************************************************************************//**
* @defgroup UART_TXPLSR
* @{
*****************************************************************************/
#define RUART_IRDA_TX_PUL_LOW_BUND_VAL ((u32)0x00007FFF) /*BIT[14:0], IrDA tx pulse low bound edge shift value*/
#define RUART_IRDA_TX_PUL_LOW_BUND_SHIFT ((u32)0x00000001 << 15) /*BIT[15], IrDA tx pulse low bound edge shift direction*/
#define RUART_IRDA_TX_PUL_UP_BUND_VAL ((u32)0x00007FFF << 16) /*BIT[30:16], IrDA tx pulse upper bound edge shift value*/
#define RUART_IRDA_TX_PUL_UP_BUND_SHIFT ((u32)0x00000001 << 31) /*BIT[31], IrDA tx pulse upper bound edge shift direction*/
/** @} */
/**************************************************************************//**
* @defgroup UART_RXPLSR
* @{
*****************************************************************************/
#define RUART_IRDA_RX_FILTER_ENABLE ((u32)0x00000001) /*BIT[0], IrDA rx filter enable*/
#define RUART_IRDA_RX_FILTER_THRES ((u32)0x00007FFF << 1) /*BIT[15:1], IrDA rx filter threshold field*/
/** @} */
/**************************************************************************//**
* @defgroup UART_REG_RX_PATH_CTRL
* @{
*****************************************************************************/
#define RUART_REG_LP_RX_PATH_SELECT ((u32)0x00000001) /*BIT[0], 0x01, Select uart low power rx path*/
#define RUART_REG_LP_RX_PATH_RESET ((u32)0x00000001 << 2) /*BIT[2], 0x40, Reset uart low power rx path receiver*/
#define RUART_REG_RX_XFACTOR_ADJ ((u32)0x000007FF << 3) /*BIT[13:3], One factor of Baud rate calculation for rx path, similar with xfactor_adj */
#define RUART_REG_RX_TO_THRES ((u32)0x0000FFFF<<16) /*BIT[31:16], rx timeout threshold, unit is one bit period*/
/** @} */
/**************************************************************************//**
* @defgroup UART_REG_MON_BAUD_CTRL
* @{
*****************************************************************************/
#define RUART_LP_RX_MON_ENABLE ((u32)0x00000001) /*BIT[0], 0x01, Enable low power rx monitor function*/
#define RUART_LP_RX_BIT_NUM_THRES ((u32)0x000000FF << 1) /*BIT[8:1], Bit Number threshold of one monitor period*/
#define RUART_LP_RX_OSC_CYCNUM_PERBIT ((u32)0x000FFFFF << 9) /*BIT[28:9], Cycle number perbit for osc clock */
#define RUART_LP_RX_OSC_UPD_IN_XTAL ((u32)0x00000001 << 29) /*BIT[29], Control bit for osc monitor parameter update */
/** @} */
/**************************************************************************//**
* @defgroup UART_REG_MON_BAUD_STS
* @{
*****************************************************************************/
#define RUART_LP_RX_XTAL_CYCNUM_PERBIT ((u32)0x000FFFFF) /*BIT[19:0], Cycle number perbit for xtal clock */
#define RUART_LP_RX_MON_RDY ((u32)0x00000001 << 20) /*BIT[20], Monitor ready status*/
#define RUART_LP_RX_MON_TOTAL_BITS ((u32)0x0000000F << 21) /*BIT[28:21], Actualy monitor bit number */
/** @} */
/**************************************************************************//**
* @defgroup UART_REG_RX_BYTE_CNT
* @{
*****************************************************************************/
/******************** Bits definition for register *******************/
#define RUART_RX_READ_BYTE_CNTER ((u32)0x0000FFFF) /*BIT[15:0], Byte number of data read from rx fifo */
#define RUART_RX_BYTE_CNTER_CLEAR ((u32)0x00000001 << 16) /*BIT[16], Write 1 clear rx byte counter*/
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
typedef struct
{
u32 LOW_POWER_RX_ENABLE; /*Enable low power RX*/
} UARTCFG_TypeDef;
typedef struct
{
UART_TypeDef* UARTx;
u32 Tx_HandshakeInterface;
u32 Rx_HandshakeInterface;
IRQn_Type IrqNum;
} UART_DevTable;
extern UARTCFG_TypeDef uart_config[];
extern const UART_DevTable UART_DEV_TABLE[4];
extern u32 UART_StateTx[4];
extern u32 UART_StateRx[4];
#define MAX_UART_INDEX (4)
static inline void
UART_SetTxFlag(u32 UartIdx, u32 Flag)
{
UART_StateTx[UartIdx] = Flag;
}
static inline void
UART_SetRxFlag(u32 UartIdx, u32 Flag)
{
UART_StateRx[UartIdx] = Flag;
}
static inline u32
UART_GetTxFlag(u32 UartIdx)
{
return (UART_StateTx[UartIdx]);
}
static inline u32
UART_GetRxFlag(u32 UartIdx)
{
return (UART_StateRx[UartIdx]);
}
#endif
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_usi.h
* @author
* @version V1.0.0
* @date 2017-09-26
* @brief This file contains all the functions prototypes for the USI firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_USI_H_
#define _RTL8721D_USI_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup USI_Register_Definitions USI Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup USI_MODE_CTRL
* @{
*****************************************************************************/
#define USI_SERIAL_MODE ((u32)0x00000007) /*BIT[2:0], USI serial mode control*/
#define USI_SERIAL_ALL_MODE_DISABLE ((u32)0x00000000) /*BIT[2:0] = 000B, USI all serial mode disable*/
#define USI_SERIAL_UART_MODE ((u32)0x00000001) /*BIT[2:0] = 001B, USI serial UART mode*/
#define USI_SERIAL_SPI_MODE ((u32)0x00000002) /*BIT[2:0] = 010B, USI serial SPI mode*/
#define USI_SERIAL_I2C_MODE ((u32)0x00000004) /*BIT[2:0] = 100B, USI serial I2C mode*/
#define USI_TX_BIT_SWAP ((u32)0x00000010) /*BIT[4], USI TX bit swap */
#define USI_RX_BIT_SWAP ((u32)0x00000020) /*BIT[5], USI RX bit swap */
#define USI_TX_BYTE_SWAP ((u32)0x00000040) /*BIT[6], USI tx byte swap */
#define USI_RX_BYTE_SWAP ((u32)0x00000080) /*BIT[7], USI rx byte swap */
/** @} */
/**************************************************************************//**
* @defgroup SW_RESET
* @{
*****************************************************************************/
#define USI_SW_RESET_RSTB ((u32)0x00000001) /*BIT[0], USI reset/release all logic*/
#define USI_SW_RESET_TX_RSTB ((u32)0x00000002) /*BIT[1], USI reset TX path*/
#define USI_SW_RESET_RX_RSTB ((u32)0x00000004) /*BIT[2], USI reset RX path*/
#define USI_SW_RESET_TXFIFO_RSTB ((u32)0x00000008) /*BIT[3], USI reset tx FIFO*/
#define USI_SW_RESET_RXFIFO_RSTB ((u32)0x00000010) /*BIT[4], USI reset rx FIFO*/
/** @} */
/**************************************************************************//**
* @defgroup DMA_ENABLE
* @{
*****************************************************************************/
#define USI_TX_DMA_ENABLE ((u32)0x00000001) /*BIT[0], USI tx path enable*/
#define USI_RX_DMA_ENABLE ((u32)0x00000002) /*BIT[1], USI rx path enable*/
/** @} */
/**************************************************************************//**
* @defgroup DMA_REQ_SIZE
* @{
*****************************************************************************/
#define USI_TX_DMA_BURST_SIZE ((u32)0x0000007F) /*BIT[6:0], TX DMA burst size*/
#define USI_TX_DMA_SINGLE_SIZE ((u32)0x00007F00) /*BIT[14:8], TX DMA single size*/
#define USI_RX_DMA_BURST_SIZE ((u32)0x007F0000) /*BIT[22:16], RX DMA burst size*/
#define USI_RX_DMA_SINGLE_SIZE ((u32)0x7F000000) /*BIT[30:24], RX DMA single size*/
/** @} */
/**************************************************************************//**
* @defgroup TX_FIFO_WRITE
* @{
*****************************************************************************/
#define USI_TX_FIFO_WRITE_DATA ((u32)0x0000FFFF) /*BIT[15:0], TX FIFO WRITE DATA mask*/
#define USI_TX_FIFO_DATA ((u32)0x000000FF) /*BIT[7:0], TX DATA*/
#define USI_TX_FIFO_CMD_RW ((u32)0x00000001<<8) /*BIT[8], this bit controls whether a read or write is performed*/
#define USI_TX_FIFO_CMD_STOP ((u32)0x00000001<<9) /*BIT[9], this bit controls whether a STOP is issued after the byte is sent or received*/
#define USI_TX_FIFO_CMD_RESTART ((u32)0x00000001<<10) /*BIT[10], this bit controls whether a RESTART is issued after the byte is sent or received*/
#define USI_TX_FIFO_NULL_DATA ((u32)0x00000001<<11) /*BIT[11], NULL_DATA condition*/
/** @} */
/**************************************************************************//**
* @defgroup TX_FIFO_CTRL
* @{
*****************************************************************************/
#define USI_TXFIFO_ALMOST_EMPTY_TH ((u32)0x0000007F) /*BIT[6:0], Tx FIFO almost empty threshold, when Tx FIFO empty space >=
txfifo_almost_empty_th, then txfifo_almost_empty will be "1" and report almost empty*/
/** @} */
/**************************************************************************//**
* @defgroup TX_FIFO_STATUS
* @{
*****************************************************************************/
#define USI_TXFIFO_FULL ((u32)0x00000001) /*BIT[0], TX FIFO FULL status*/
#define USI_TXFIFO_EMPTY ((u32)0x00000001<<1) /*BIT[1], TX FIFO EMPTY status*/
#define USI_TXFIFO_ALMOST_EMPTY_COPY ((u32)0x00000001<<2) /*BIT[2], TX FIFO ALMOST EMPTY status*/
#define USI_TXFIFO_EMPTY_SPACE ((u32)0x0000007F<<8) /*BIT[14:8], Tx FIFO empty space(unpush unit number)*/
/** @} */
/**************************************************************************//**
* @defgroup RX_FIFO_READ
* @{
*****************************************************************************/
#define USI_RX_FIFO_RD_DATA ((u32)0x0000FFFF) /*BIT[15:0], read RX FIFO DATA mask*/
#define USI_RX_FIFO_DATA ((u32)0x000000FF) /*BIT[7:0], TX DATA*/
#define USI_RX_FIFO_PARITY_ERR ((u32)0x00000001<<8) /*BIT[8], parity error status in current character*/
#define USI_RX_FIFO_STOP_ERR ((u32)0x00000001<<9) /*BIT[9], stop error status in current character*/
#define USI_RX_FIFO_BREAK_FLAG ((u32)0x00000001<<10) /*BIT[10], break event status in current character*/
/** @} */
/**************************************************************************//**
* @defgroup TX_FIFO_CTRL
* @{
*****************************************************************************/
#define USI_RXFIFO_ALMOST_FULL_TH ((u32)0x0000007F) /*BIT[6:0], Rx FIFO almost full threshold, when Rx FIFO valid cnt >=
rxfifo_almost_full_th, then rxfifo_almost_full will be "1" and report almost full*/
/** @} */
/**************************************************************************//**
* @defgroup RX_FIFO_STATUS
* @{
*****************************************************************************/
#define USI_RXFIFO_FULL ((u32)0x00000001) /*BIT[0], RX FIFO FULL status*/
#define USI_RXFIFO_EMPTY ((u32)0x00000001<<1) /*BIT[1], RX FIFO EMPTY status*/
#define USI_RXFIFO_ALMOST_FULL_COPY ((u32)0x00000001<<2) /*BIT[2], RX FIFO ALMOST FULL status*/
#define USI_RXFIFO_VALID_CNT ((u32)0x0000007F<<8) /*BIT[14:8], Rx FIFO valid cnt(pushed unit number which can be read)*/
/** @} */
/**************************************************************************//**
* @defgroup RX_FIFO_RD_CNT
* @{
*****************************************************************************/
#define USI_RX_FIFO_RD_CNT ((u32)0x0000FFFF) /*BIT[15:0], mask for counting the byte number of data read from Rx FIFO*/
#define USI_RX_FIFO_RD_CNT_CLR ((u32)0x00010000) /*BIT[16], write 1 to clear rxfifo_rd_cnt*/
/** @} */
/**************************************************************************//**
* @defgroup INTERRUPT_ENABLE
* @{
*****************************************************************************/
#define USI_TXFIFO_ALMOST_EMTY_INTR_EN ((u32)0x00000001) /*BIT[0], txfifo_almost_empty_intr_en*/
#define USI_TXFIFO_OVERFLOW_INTR_EN ((u32)0x00000001<<1) /*BIT[1], txfifo_overflow_intr_en*/
#define USI_TXFIFO_UNDERFLOW_INTR_EN ((u32)0x00000001<<2) /*BIT[2], txfifo_underflow_intr_en*/
#define USI_RXFIFO_ALMOST_FULL_INTR_EN ((u32)0x00000001<<4) /*BIT[4], rxfifo_almost_full_intr_en*/
#define USI_RXFIFO_OVERFLOW_INTR_EN ((u32)0x00000001<<5) /*BIT[5], rxfifo_overflow_intr_en*/
#define USI_RXFIFO_UNDERFLOW_INTR_EN ((u32)0x00000001<<6) /*BIT[6], rxfifo_underflow_intr_en*/
#define USI_RX_PARITY_ERR_INTR_EN ((u32)0x00000001<<8) /*BIT[8], uart_rx_parity_err_intr_en*/
#define USI_RX_STOP_ERR_INTR_EN ((u32)0x00000001<<9) /*BIT[9], uart_rx_stop_err_intr_en*/
#define USI_RX_BREAK_INTR_EN ((u32)0x00000001<<10) /*BIT[10], uart_rx_break_intr_en*/
#define USI_RXFIFO_TM_OUT_INTR_EN ((u32)0x00000001<<11) /*BIT[11], uart_rxfifo_timeout_intr_en*/
#define USI_RX_BAUDMON_DONE_INTR_EN ((u32)0x00000001<<12) /*BIT[12], uart_rx_baudmon_done_intr_en*/
#define USI_TX_CTS_CHANGE_INTR_EN ((u32)0x00000001<<13) /*BIT[13], uart_tx_cts_change_intr_en*/
#define USI_SPI_RX_DATA_FRM_ERR_INTER_EN ((u32)0x00000001<<16) /*BIT[16], spi_rx_data_frame_err_intr_en*/
#define USI_I2C_RD_REQ_INTER_EN ((u32)0x00000001<<20) /*BIT[20], i2c_rd_req_intr_en*/
#define USI_I2C_TX_ABRT_INTER_EN ((u32)0x00000001<<21) /*BIT[21], i2c_tx_abrt_intr_en*/
#define USI_I2C_RX_DONE_INTER_EN ((u32)0x00000001<<22) /*BIT[22], i2c_rx_done_intr_en*/
#define USI_I2C_ACTIVITY_INTER_EN ((u32)0x00000001<<23) /*BIT[23], i2c_activity_intr_en*/
#define USI_I2C_STOP_DET_INTER_EN ((u32)0x00000001<<24) /*BIT[24], i2c_stop_det_intr_en*/
#define USI_I2C_START_DET_INTER_EN ((u32)0x00000001<<25) /*BIT[25], i2c_stop_det_intr_en*/
#define USI_I2C_GEN_CALL_INTER_EN ((u32)0x00000001<<26) /*BIT[26], i2c_gen_call_intr_en*/
#define USI_I2C_LP_WAKE_INTER_EN ((u32)0x00000001<<27) /*BIT[27], i2c_lp_wake_intr_en*/
#define USI_I2C_DMA_DONE_INTER_EN ((u32)0x00000001<<28) /*BIT[28], i2c_dma_done_intr_en*/
/** @} */
/**************************************************************************//**
* @defgroup INTERRUPT_STATUS
* @{
*****************************************************************************/
#define USI_TXFIFO_ALMOST_EMTY_INTS ((u32)0x00000001) /*BIT[0], txfifo_almost_empty_intr*/
#define USI_TXFIFO_OVERFLOW_INTS ((u32)0x00000001<<1) /*BIT[1], txfifo_overflow_intr*/
#define USI_TXFIFO_UNDERFLOW_INTS ((u32)0x00000001<<2) /*BIT[2], txfifo_underflow_intr*/
#define USI_RXFIFO_ALMOST_FULL_INTS ((u32)0x00000001<<4) /*BIT[4], rxfifo_almost_full_intr*/
#define USI_RXFIFO_OVERFLOW_INTS ((u32)0x00000001<<5) /*BIT[5], rxfifo_overflow_intr*/
#define USI_RXFIFO_UNDERFLOW_INTS ((u32)0x00000001<<6) /*BIT[6], rxfifo_underflow_intr*/
#define USI_RX_PARITY_ERR_INTS ((u32)0x00000001<<8) /*BIT[8], uart_rx_parity_err_intr*/
#define USI_RX_STOP_ERR_INTS ((u32)0x00000001<<9) /*BIT[9], uart_rx_stop_err_intr*/
#define USI_RX_BREAK_INTS ((u32)0x00000001<<10) /*BIT[10], uart_rx_break_intr*/
#define USI_RXFIFO_TM_OUT_INTS ((u32)0x00000001<<11) /*BIT[11], uart_rxfifo_timeout_intr*/
#define USI_RX_BAUDMON_DONE_INTS ((u32)0x00000001<<12) /*BIT[12], uart_rx_baudmon_done_intr*/
#define USI_TX_CTS_CHANGE_INTS ((u32)0x00000001<<13) /*BIT[13], uart_tx_cts_change_intr*/
#define USI_SPI_RX_DATA_FRM_ERR_INTS ((u32)0x00000001<<16) /*BIT[16], spi_rx_data_frame_err_intr*/
#define USI_I2C_RD_REQ_INTS ((u32)0x00000001<<20) /*BIT[20], i2c_rd_req_intr*/
#define USI_I2C_TX_ABRT_INTS ((u32)0x00000001<<21) /*BIT[21], i2c_tx_abrt_intr*/
#define USI_I2C_RX_DONE_INTS ((u32)0x00000001<<22) /*BIT[22], i2c_rx_done_intr*/
#define USI_I2C_ACTIVITY_INTS ((u32)0x00000001<<23) /*BIT[23], i2c_activity_intr*/
#define USI_I2C_STOP_DET_INTS ((u32)0x00000001<<24) /*BIT[24], i2c_stop_det_intr*/
#define USI_I2C_START_DET_INTS ((u32)0x00000001<<25) /*BIT[25], i2c_stop_det_intr*/
#define USI_I2C_GEN_CALL_INTS ((u32)0x00000001<<26) /*BIT[26], i2c_gen_call_intr*/
#define USI_I2C_LP_WAKE_INTS ((u32)0x00000001<<27) /*BIT[27], i2c_lp_wake_intr*/
#define USI_I2C_DMA_DONE_INTS ((u32)0x00000001<<28) /*BIT[28], i2c_dma_done_intr*/
/** @} */
/**************************************************************************//**
* @defgroup INTERRUPT_RAW_STATUS
* @{
*****************************************************************************/
#define USI_TXFIFO_ALMOST_EMTY_RSTS ((u32)0x00000001) /*BIT[0], txfifo_almost_empty*/
#define USI_TXFIFO_OVERFLOW_RSTS ((u32)0x00000001<<1) /*BIT[1], txfifo_overflow*/
#define USI_TXFIFO_UNDERFLOW_RSTS ((u32)0x00000001<<2) /*BIT[2], txfifo_underflow*/
#define USI_RXFIFO_ALMOST_FULL_RSTS ((u32)0x00000001<<4) /*BIT[4], rxfifo_almost_full*/
#define USI_RXFIFO_OVERFLOW_RSTS ((u32)0x00000001<<5) /*BIT[5], rxfifo_overflow*/
#define USI_RXFIFO_UNDERFLOW_RSTS ((u32)0x00000001<<6) /*BIT[6], rxfifo_underflow*/
#define USI_RX_PARITY_ERR_RSTS ((u32)0x00000001<<8) /*BIT[8], uart_rx_parity_err*/
#define USI_RX_STOP_ERR_RSTS ((u32)0x00000001<<9) /*BIT[9], uart_rx_stop_err*/
#define USI_RX_BREAK_RSTS ((u32)0x00000001<<10) /*BIT[10], uart_rx_break_intr*/
#define USI_RXFIFO_TM_OUT_RSTS ((u32)0x00000001<<11) /*BIT[11], uart_rxfifo_timeout*/
#define USI_RX_BAUDMON_DONE_RSTS ((u32)0x00000001<<12) /*BIT[12], uart_rx_baudmon_done*/
#define USI_TX_CTS_CHANGE_RSTS ((u32)0x00000001<<13) /*BIT[13], uart_tx_cts_change*/
#define USI_SPI_RX_DATA_FRM_ERR_RSTS ((u32)0x00000001<<16) /*BIT[16], spi_rx_data_frame_err*/
#define USI_I2C_RD_REQ_RSTS ((u32)0x00000001<<20) /*BIT[20], i2c_rd_req*/
#define USI_I2C_TX_ABRT_RSTS ((u32)0x00000001<<21) /*BIT[21], i2c_tx_abrt*/
#define USI_I2C_RX_DONE_RSTS ((u32)0x00000001<<22) /*BIT[22], i2c_rx_done*/
#define USI_I2C_ACTIVITY_RSTS ((u32)0x00000001<<23) /*BIT[23], i2c_activity*/
#define USI_I2C_STOP_DET_RSTS ((u32)0x00000001<<24) /*BIT[24], i2c_stop_det*/
#define USI_I2C_START_DET_RSTS ((u32)0x00000001<<25) /*BIT[25], i2c_stop_det*/
#define USI_I2C_GEN_CALL_RSTS ((u32)0x00000001<<26) /*BIT[26], i2c_gen_call*/
#define USI_I2C_LP_WAKE_RSTS ((u32)0x00000001<<27) /*BIT[27], i2c_lp_wake*/
#define USI_I2C_DMA_DONE_RSTS ((u32)0x00000001<<28) /*BIT[28], i2c_dma_done*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_TX_ABRT_SOURCE
* @{
*****************************************************************************/
#define USI_I2C_ABRT_7B_ADDR_NOACK ((u32)0x00000001) /*BIT[0], Master is in 7-bit addressing mode and the address sent was
not acknowledged by any slave. Role is Master*/
#define USI_I2C_ABRT_10ADDR1_NOACK ((u32)0x00000001<<1) /*BIT[1], Master is in 10-bit address mode and the first 10-bit address
byte was not acknowledged by any slave. Role is Master.*/
#define USI_I2C_ABRT_10ADDR2_NOACK ((u32)0x00000001<<2) /*BIT[2], Master is in 10-bit address mode and the second byte of the
10-bit address was not acknowledged by any slave. Role is Master.*/
#define USI_I2C_ABRT_TXDATA_NOACK ((u32)0x00000001<<3) /*BIT[3], This is a master-mode only bit. Master has received an acknowledgement
for the address, but when it sent data byte(s) following the address, it did not
receive an acknowledge from the remote slave(s). Role is Master-Transmitter.*/
#define USI_I2C_ABRT_GCALL_NOACK ((u32)0x00000001<<4) /*BIT[4], I2C in master mode sent a General Call and no slave on the bus acknowledged
the General Call. Role is Master-Transmitter.*/
#define USI_I2C_ABRT_GCALL_READ ((u32)0x00000001<<5) /*BIT[5], I2C in master mode sent a General Call but the user programmed the byte following
the General Call to be a read from the bus. Role is Master-Transmitter.*/
#define USI_I2C_ABRT_HS_ACKDET ((u32)0x00000001<<6) /*BIT[6], Master is in High Speed mode and the High Speed Master code was acknowledged
(wrong behavior). Role is Master.*/
#define USI_I2C_ABRT_SBYTE_ACKDET ((u32)0x00000001<<7) /*BIT[7], Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
Role is Master.*/
#define USI_I2C_ABRT_HS_NORSTRT ((u32)0x00000001<<8) /*BIT[8], The restart is disabled and the user is trying to use the master to transfer data in High
Speed mode. Role is Master.*/
#define USI_I2C_ABRT_SBYTE_NORSTRT ((u32)0x00000001<<9) /*BIT[9], The restart is disabled and the user is trying to send a START Byte. Role is Master.*/
#define USI_I2C_ABRT_10B_RD_NORSTRT ((u32)0x00000001<<10) /*BIT[10], The restart is disabled and the master sends a read command in 10-bit addressing mode.
Role is Master-Receiver.*/
#define USI_I2C_ABRT_MASTER_DIS ((u32)0x00000001<<11) /*BIT[11], User tries to initiate a Master operation with the Master mode disabled. Role is Master.*/
#define USI_I2C_ARBT_LOST ((u32)0x00000001<<12) /*BIT[12], Master has lost arbitration, or if i2c_tx_abrt_source [14] is also set, then the slave transmitter
has lost arbitration. Role is Master-Transmitter or Slave-Transmitter.*/
#define USI_I2C_ABRT_SLVFLUSH_TXFIFO ((u32)0x00000001<<13) /*BIT[13], Slave has received a read command and some data exists in the TxFIFO so the slave issues a
TX_ABRT interrupt to flush old data in TxFIFO. Role is Slave-Transmitter*/
#define USI_I2C_ABRT_SLV_ARBLOST ((u32)0x00000001<<14) /*BIT[14], Slave lost the bus while transmitting data to a remote master. i2c_tx_abrt_source [12] is set
at the same time. Role is Slave-Transmitter.*/
/** @} */
/**************************************************************************//**
* @defgroup INTERRUPT_ALL_CLR
* @{
*****************************************************************************/
#define USI_INT_ALL_CLEAR ((u32)0x00000001) /*BIT[0], Write "1" to this register to clear the combined interrupt, all individual interrupts, interrupt
status register and raw interrupt status register. This bit does not clear hardware clearable
interrupts but software dis-clearable interrupts, and the relate register (include txfifo_almost_empty,
rxfifo_almost_full, uart_rxfifo_timeout)*/
/** @} */
/**************************************************************************//**
* @defgroup INTERRUPT_STATUS_CLR
* @{
*****************************************************************************/
#define USI_TXFIFO_OVERFLOW_CLR ((u32)0x00000001<<1) /*BIT[1], clear txfifo_overflow interrupt and related register*/
#define USI_TXFIFO_UNDERFLOW_CLR ((u32)0x00000001<<2) /*BIT[2], clear txfifo_underflow interrupt and related register*/
#define USI_RXFIFO_OVERFLOW_CLR ((u32)0x00000001<<5) /*BIT[5], clear rxfifo_overflow interrupt and related register*/
#define USI_RXFIFO_UNDERFLOW_CLR ((u32)0x00000001<<6) /*BIT[6], clear rxfifo_underflow interrupt and related register*/
#define USI_RX_PARITY_ERR_CLR ((u32)0x00000001<<8) /*BIT[8], clear uart_rx_parity_err interrupt and related register*/
#define USI_RX_STOP_ERR_CLR ((u32)0x00000001<<9) /*BIT[9], clear uart_rx_stop_err interrupt and related register*/
#define USI_RX_BREAK_CLR ((u32)0x00000001<<10) /*BIT[10], clear uart_rx_break interrupt and related register*/
#define USI_RX_BAUDMON_DONE_CLR ((u32)0x00000001<<12) /*BIT[12], clear uart_rx_baudmon_done interrupt and related register*/
#define USI_TX_CTS_CHANGE_CLR ((u32)0x00000001<<13) /*BIT[13], clear uart_tx_cts_change interrupt and related register*/
#define USI_SPI_RX_DATA_FRM_ERR_CLR ((u32)0x00000001<<16) /*BIT[16], clear spi_rx_data_frame_err interrupt and related register*/
#define USI_I2C_RD_REQ_CLR ((u32)0x00000001<<20) /*BIT[20], clear i2c_rd_req interrupt and related register*/
#define USI_I2C_TX_ABRT_CLR ((u32)0x00000001<<21) /*BIT[21], clear i2c_tx_abrt interrupt and related register, this is also releases
the Tx FIFO from the flushed/reset state, allowing more writes to the Tx FIFO.*/
#define USI_I2C_RX_DONE_CLR ((u32)0x00000001<<22) /*BIT[22], clear i2c_rx_done interrupt and related register*/
#define USI_I2C_ACTIVITY_CLR ((u32)0x00000001<<23) /*BIT[23], clear i2c_activity interrupt and related register if the I2C is not active anymore. If the
I2C module is still active on the bus, the i2c_activity will continues to be set. It is automatically
cleared by hardware if the module is disabled and if there is no further activity on the bus. */
#define USI_I2C_STOP_DET_CLR ((u32)0x00000001<<24) /*BIT[24], clear i2c_stop_det interrupt and related register*/
#define USI_I2C_START_DET_CLR ((u32)0x00000001<<25) /*BIT[25], clear i2c_start_det interrupt and related register*/
#define USI_I2C_GEN_CALL_CLR ((u32)0x00000001<<26) /*BIT[26], clear i2c_gen_call interrupt and related register*/
#define USI_I2C_LP_WAKE_CLR ((u32)0x00000001<<27) /*BIT[27], clear i2c_lp_wake interrupt and related register*/
#define USI_I2C_DMA_DONE_CLR ((u32)0x00000001<<28) /*BIT[28], clear i2c_dma_done interrupt and related register*/
/** @} */
/**************************************************************************//**
* @defgroup DEBUG_SEL
* @{
*****************************************************************************/
#define USI_DBG_SEL ((u32)0x0000001F) /*BIT[4:0], USI DEBUG SELECT MASK */
#define USI_DBG_UART_CLKRST ((u32)0x00000000) /*BIT[4:0]=0X00, dbg_uart_clkrst*/
#define USI_DBG_SPI_CLKRST ((u32)0x00000001) /*BIT[4:0]=0X01, dbg_spi_clkrst*/
#define USI_DBG_I2C_CLKRST ((u32)0x00000002) /*BIT[4:0]=0X02, dbg_i2c_clkrst*/
#define USI_DBG_TXFIFO_CLKRST ((u32)0x00000003) /*BIT[4:0]=0X03, dbg_txfifo_clkrst*/
#define USI_DBG_RXFIFO_CLKRST ((u32)0x00000004) /*BIT[4:0]=0X04, dbg_rxfifo_clkrst*/
#define USI_DBG_APBSLV ((u32)0x00000005) /*BIT[4:0]=0X05, dbg_apbslv*/
#define USI_DBG_DMAIF ((u32)0x00000006) /*BIT[4:0]=0X06, dbg_dmaif*/
#define USI_DBG_INTR ((u32)0x00000007) /*BIT[4:0]=0X07, dbg_intr*/
#define USI_DBG_I2C_DMODE ((u32)0x00000008) /*BIT[4:0]=0X08, dbg_i2c_dmode*/
#define USI_DBG_TRXFIFO ((u32)0x00000009) /*BIT[4:0]=0X09, dbg_trxfifo*/
#define USI_DBG_UART_TXCTRL ((u32)0x0000000A) /*BIT[4:0]=0X0A, dbg_uart_txctrl*/
#define USI_DBG_UART_RXCTRL ((u32)0x0000000B) /*BIT[4:0]=0X0B, dbg_uart_rxctrl*/
#define USI_DBG_UART_RXMON ((u32)0x0000000C) /*BIT[4:0]=0X0C, dbg_uart_rxmon*/
#define USI_DBG_UART_IRDA_DEC1 ((u32)0x0000000D) /*BIT[4:0]=0X0D, dbg_uart_irda_dec1*/
#define USI_DBG_UART_IRDA_DEC2 ((u32)0x0000000E) /*BIT[4:0]=0X0E, dbg_uart_irda_dec2*/
#define USI_DBG_UART_IRDA_DEC3 ((u32)0x0000000F) /*BIT[4:0]=0X0F, dbg_uart_irda_dec3*/
#define USI_DBG_UART_IRDA_DEC4 ((u32)0x00000010) /*BIT[4:0]=0X10, dbg_uart_irda_dec4*/
#define USI_DBG_UART_IRDA_ENC1 ((u32)0x00000011) /*BIT[4:0]=0X11, dbg_uart_irda_enc1*/
#define USI_DBG_UART_IRDA_ENC2 ((u32)0x00000012) /*BIT[4:0]=0X12, dbg_uart_irda_enc2*/
#define USI_DBG_UART_IRDA_ENC3 ((u32)0x00000013) /*BIT[4:0]=0X13, dbg_uart_irda_enc3*/
#define USI_DBG_UART_IRDA_ENC4 ((u32)0x00000014) /*BIT[4:0]=0X14, dbg_uart_irda_enc4*/
#define USI_DBG_UART_TOPCTRL ((u32)0x00000015) /*BIT[4:0]=0X15, dbg_uart_topctrl*/
#define USI_DBG_SPI_MST_TXCTRL ((u32)0x00000016) /*BIT[4:0]=0X16, dbg_spi_mst_txctrl*/
#define USI_DBG_SPI_MST_RXCTRL ((u32)0x00000017) /*BIT[4:0]=0X17, dbg_spi_mst_rxctrl*/
#define USI_DBG_SPI_MST_CLKREQ ((u32)0x00000018) /*BIT[4:0]=0X18, dbg_spi_mst_clkreq*/
#define USI_DBG_SPI_SLV_TXCTRL ((u32)0x00000019) /*BIT[4:0]=0X19, dbg_spi_slv_txctrl*/
#define USI_DBG_SPI_SLV_RXCTRL ((u32)0x0000001A) /*BIT[4:0]=0X1A, dbg_spi_slv_rxctrl*/
#define USI_DBG_I2C_FIFO ((u32)0x0000001B) /*BIT[4:0]=0X1B, dbg_i2c_fifo*/
#define USI_DBG_I2C_BUS ((u32)0x0000001C) /*BIT[4:0]=0X1C, dbg_i2c_bus*/
#define USI_DBG_I2C_INTR ((u32)0x0000001D) /*BIT[4:0]=0X1D, dbg_i2c_intr*/
/** @} */
/**************************************************************************//**
* @defgroup UART_CTRL
* @{
*****************************************************************************/
#define USI_UART_WORD_LEN_MD ((u32)0x00000001) /*BIT[0], Word length selection , 0: data is 7 bit word length; 1: data is 8 bit word length.*/
#define USI_UART_STOP_BIT_MD ((u32)0x00000001<<1) /*BIT[1], This is bit specifies the number of Stop bits transmitted and received in each serial character. */
#define USI_UART_PARITY_ENABLE ((u32)0x00000001<<4) /*BIT[4], Parity Enable*/
#define USI_UART_PARITY_EVEN ((u32)0x00000001<<5) /*BIT[5], Even Parity select*/
#define USI_UART_STICK_PARITY_BIT ((u32)0x00000001<<6) /*BIT[6], Stick Parity bit.*/
#define USI_UART_LOOPBACK_MD_EN ((u32)0x00000001<<8) /*BIT[8], LoopBack mode*/
#define USI_UART_PIN_LOOPBACK_TEST_EN ((u32)0x00000001<<9) /*BIT[9], For uart IP txd/rxd/rts/cts pin loopback test*/
#define USI_UART_BREAK_CTRL ((u32)0x00000001<<12) /*BIT[12], Break Control bit*/
/** @} */
/**************************************************************************//**
* @defgroup UART_IRDA_CTRL
* @{
*****************************************************************************/
#define USI_UART_IRDA_ENABLE ((u32)0x00000001) /*BIT[0], UART IRDA ENABLE.*/
#define USI_UART_IRDA_TX_INV ((u32)0x00000001<<1) /*BIT[1], Invert irda_tx_o when 1.*/
#define USI_UART_IRDA_RX_INV ((u32)0x00000001<<2) /*BIT[2], Invert irda_rx_i when 1.*/
/** @} */
/**************************************************************************//**
* @defgroup UART_IRDA_TX_PULSE_WD
* @{
*****************************************************************************/
#define USI_UART_IRDA_TX_PUL_LOW_BUND_VAL ((u32)0x00007FFF) /*BIT[14:0], IrDA tx pulse low bound edge shift value*/
#define USI_UART_IRDA_TX_PUL_LOW_BUND_SHIFT ((u32)0x00000001 << 15) /*BIT[15], IrDA tx pulse low bound edge shift direction*/
#define USI_UART_IRDA_TX_PUL_UP_BUND_VAL ((u32)0x00007FFF << 16) /*BIT[30:16], IrDA tx pulse upper bound edge shift value*/
#define USI_UART_IRDA_TX_PUL_UP_BUND_SHIFT ((u32)0x00000001 << 31) /*BIT[31], IrDA tx pulse upper bound edge shift direction*/
/** @} */
/**************************************************************************//**
* @defgroup UART_IRDA_RX_PULSE_WD
* @{
*****************************************************************************/
#define USI_UART_IRDA_RX_FILTER_ENABLE ((u32)0x00000001) /*BIT[0], IrDA rx filter enable*/
#define USI_UART_IRDA_RX_FILTER_THRES ((u32)0x00007FFF << 1) /*BIT[15:1], IrDA rx filter threshold field*/
/** @} */
/**************************************************************************//**
* @defgroup UART_TX_FRACTION_BAUD
* @{
*****************************************************************************/
#define USI_UART_TX_XFACTOR ((u32)0x000FFFFF) /*BIT[19:0], USI UART Factor of Baud rate calculation*/
#define USI_UART_TX_XFACTOR_ADJ ((u32)0x000007FF<<20) /*BIT[30:20], USI UART fractional factor of Baud rate calculation*/
/** @} */
/**************************************************************************//**
* @defgroup UART_RX_BAUD_OSC
* @{
*****************************************************************************/
#define USI_UART_LPRX_OSC_CYCNUM_PERBIT ((u32)0x000FFFFF) /*BIT[19:0], Average OSC clock cycle number of one bit, for integral baud rate(new rx path) osc clk
SW set the initial value, HW update it depend on the monitor result*/
/** @} */
/**************************************************************************//**
* @defgroup UART_RX_BAUD_XTAL
* @{
*****************************************************************************/
#define USI_RUART_LPRX_XTAL_CYCNUM_PERBIT ((u32)0x000FFFFF) /*BIT[19:0], Average fractional xtal clock cycle number of one bit, for integral baud rate(new rx path) xtal clk
SW set the initial value, HW update it depend on the monitor result*/
/** @} */
/**************************************************************************//**
* @defgroup UART_RX_FRACTION_BAUD_CTRL
* @{
*****************************************************************************/
#define USI_UART_RX_XFACTOR_ADJ ((u32)0x000007FF) /*BIT[10:0], USI UART RX fractional factor of Baud rate calculation*/
/** @} */
/**************************************************************************//**
* @defgroup UART_BAUD_MON_CTRL
* @{
*****************************************************************************/
#define USI_UART_LP_RX_MON_ENABLE ((u32)0x00000001) /*BIT[0], 0x01, Enable low power rx monitor function*/
#define USI_UART_LP_RX_OSC_UPD_IN_XTAL ((u32)0x00000001 << 1) /*BIT[1], Control bit for osc monitor parameter update */
#define USI_UART_LP_RX_BIT_NUM_THRES ((u32)0x000000FF << 8) /*BIT[15:8], Bit Number threshold of one monitor period*/
/** @} */
/**************************************************************************//**
* @defgroup UART_BAUD_MON_STATUS0
* @{
*****************************************************************************/
#define USI_UART_LP_RX_BAUDMON_VALID ((u32)0x00000001) /*BIT[0], Monitor VALID status*/
#define USI_UART_LP_RX_MON_TOTAL_BITS ((u32)0x000000FF << 8) /*BIT[15:8], Actualy monitor bit number */
/** @} */
/**************************************************************************//**
* @defgroup UART_BAUD_MON_STATUS1
* @{
*****************************************************************************/
#define USI_UART_RX_BAUDMON_TOTAL_CYCLE ((u32)0x0FFFFFFF) /*BIT[27:0], actually monitored clk cycle*/
/** @} */
/**************************************************************************//**
* @defgroup UART_FLOW_CTRL
* @{
*****************************************************************************/
#define USI_UART_RX_RTS ((u32)0x00000001) /*BIT[0], Request to Send (RTS) signal control*/
#define USI_UART_TX_CTS ((u32)0x00000001<<1) /*BIT[1], Complement of the CTS input or equals to RTS in loopback mode.*/
#define USI_UART_AUTO_FLOW_EN ((u32)0x00000001<<4) /*BIT[4], AutoFlow Enable .*/
#define USI_UART_RX_HOLD_THRD ((u32)0x0000007F<<8) /*BIT[14:8], when uart_auto_flowctrl_en = 1 and Rx FIFO unpushed space >= uart_rx_hold_thres,
hardware will auto hold Rx path RTS (send uart_rx_rts_oe output to 1).*/
/** @} */
/**************************************************************************//**
* @defgroup UART_RXFIFO_TO_TH
* @{
*****************************************************************************/
#define USI_UART_RXFIFO_TO_TH ((u32)0x0000FFFF) /*BIT[15:0], UART RXFIFO timeout threshold*/
/** @} */
/**************************************************************************//**
* @defgroup UART_RXDMA_FLOW_CTRL
* @{
*****************************************************************************/
#define USI_UART_RXDMA_RXDMA_OWNER ((u32)0x00000001) /*BIT[0], UART RXFIFO FLOW OWNER*/
#define USI_UART_RXDMA_DUMMY_DATA ((u32)0x0000FF00) /*BIT[15:8], UART RXDMA dummy data*/
#define USI_UART_RXDMA_DUMMY_FLAG ((u32)0x00010000) /*BIT[16], UART RXDMA dummy flag*/
/** @} */
/**************************************************************************//**
* @defgroup SPI_CTRL
* @{
*****************************************************************************/
#define USI_SPI_DAT_FRM_SIZE ((u32)0x0000000F) /*BIT[3:0], data frame size*/
#define USI_SPI_MASTER_MODE ((u32)0x00000001<<4) /*BIT[4], spi master mode.*/
#define USI_SPI_SS_TOG_PHASE ((u32)0x00000001<<5) /*BIT[5], only used by master mode, RSVD for slave mode. .*/
#define USI_SPI_CPH ((u32)0x00000001<<6) /*BIT[6], clock phase.*/
#define USI_SPI_CPOL ((u32)0x00000001<<7) /*BIT[7], clock polarity.*/
#define USI_SPI_RX_SAMPLE_DLY ((u32)0x000000FF<<8) /*BIT[15:8], Receive Data (rxd) Sample Delay*/
#define USI_SPI_MST_BAUD ((u32)0x0000FFFF<<16) /*BIT[15:8], spi_mst_clk Divider*/
/** @} */
/**************************************************************************//**
* @defgroup SPI_TRANS_EN
* @{
*****************************************************************************/
#define USI_SPI_TX_ENABLE ((u32)0x00000001) /*BIT[0], SPI TX path enable/disable*/
#define USI_SPI_RX_ENABLE ((u32)0x00000001<<1) /*BIT[1], SPI RX path enable/disable*/
#define USI_SPI_RXONLY_NUM ((u32)0x0000FFFF<<16) /*BIT[16:31], Valid only in SPI Master Rx only (Tx disable) mode, otherwise has no affect.
Set this register and then write a dummy Tx data into Tx FIFO, SPI Master hardware will
automatically start Rx spi_rxonly_num+1 frames data from SPI Slave*/
/** @} */
/**************************************************************************//**
* @defgroup SPI_TRANS_STATUS
* @{
*****************************************************************************/
#define USI_SPI_ACTIVITY ((u32)0x00000001) /*BIT[0], SPI activity/idle status*/
#define USI_SPI_MST_TX_ACTIVITY ((u32)0x00000001<<1) /*BIT[1], SPI MASTER TX PATH activity/idle status*/
#define USI_SPI_MST_RX_ACTIVITY ((u32)0x00000001<<2) /*BIT[2], SPI MASTER RX PATH activity/idle status*/
#define USI_SPI_SLV_TX_ACTIVITY ((u32)0x00000001<<3) /*BIT[3], SPI SLAVE TX PATH activity/idle status*/
#define USI_SPI_SLV_RX_ACTIVITY ((u32)0x00000001<<4) /*BIT[4], SPI SLAVE RX PATH activity/idle status*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_CTRL
* @{
*****************************************************************************/
#define USI_I2C_MODE ((u32)0x00000001) /*BIT[0], I2C master mode*/
#define USI_I2C_RESTART_EN ((u32)0x00000001<<1) /*BIT[1], Determine whether RESTART conditions may be sent when acting as a master.*/
#define USI_I2C_SPEED ((u32)0x00000003<<2) /*BIT[3:2], this setting is relevant only if operating in I2C master mode.*/
#define USI_I2C_HS_MAR ((u32)0x00000007<<4) /*BIT[6:4], the value of the I2C HS(high speed) mode master mode. */
#define USI_I2C_SLV_DISABLE ((u32)0x00000001<<8) /*BIT[8], This bit controls whether I2C has its slave (7-bit or 10-bit address) disabled*/
#define USI_I2C_10BITADDR_SLAVE ((u32)0x00000001<<9) /*BIT[9], When acting as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses.*/
#define USI_I2C_SAR ((u32)0x000003FF<<12) /*BIT[21:12], slave address when the I2C is operating as slave*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_SS_SCL_CNT
* @{
*****************************************************************************/
#define USI_I2C_SS_SCL_HCNT ((u32)0x0000FFFF) /*BIT[15:0], sets the SCL clock high-period count for standard speed. */
#define USI_I2C_SS_SCL_LCNT ((u32)0x0000FFFF<<16) /*BIT[31:16], sets the SCL clock low-period count for standard speed. */
/** @} */
/**************************************************************************//**
* @defgroup I2C_FS_SCL_CNT
* @{
*****************************************************************************/
#define USI_I2C_FS_SCL_HCNT ((u32)0x0000FFFF) /*BIT[15:0], sets the SCL clock high-period count for fast speed. */
#define USI_I2C_FS_SCL_LCNT ((u32)0x0000FFFF<<16) /*BIT[31:16], This register sets the SCL clock low-period count for fast speed.*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_FS_SCL_CNT
* @{
*****************************************************************************/
#define USI_I2C_HS_SCL_HCNT ((u32)0x0000FFFF) /*BIT[15:0], This register sets the SCL clock high-period count for high speed. */
#define USI_I2C_HS_SCL_LCNT ((u32)0x0000FFFF<<16) /*BIT[31:16], This register sets the SCL clock low-period count for high speed. */
/** @} */
/**************************************************************************//**
* @defgroup I2C_SDA_TIMING
* @{
*****************************************************************************/
#define USI_I2C_SDA_SETUP ((u32)0x000000FF) /*BIT[7:0], Set the required SDA setup time in units of i2c_clk period. */
#define USI_I2C_SDA_HOLD ((u32)0x0000FFFF<<16) /*BIT[31:16], This register controls the amount of hold time on the SDA signal after
a negative edge of SCL in both master and slave mode, in units of i2c_clk period.*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_DIG_FILTER
* @{
*****************************************************************************/
#define USI_I2C_DIG_FLTR_DEG ((u32)0x0000000F) /*BIT[3:0], DIG_FLTR_DEG is to define frequency range of filter */
#define USI_I2C_DIG_FLTR_SEL ((u32)0x00000001<<4) /*BIT[4], Enable filter*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_SLV_ACK_CTRL
* @{
*****************************************************************************/
#define USI_I2C_SLV_DATA_NACK_ONLY ((u32)0x00000001) /*BIT[0], Generate NACK*/
#define USI_I2C_ACK_GENERAL_CALL ((u32)0x00000001<<1) /*BIT[1], This register controls whether I2C responds with a ACK or NACK when it receives an I2C General Call address.*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_ENABLE
* @{
*****************************************************************************/
#define USI_I2C_ENABLE ((u32)0x00000001) /*BIT[0], Control whether the I2C is enabled.*/
#define USI_I2C_FORCE ((u32)0x00000001<<1) /*BIT[1], copy from I2C IP, used by i2c master*/
#define USI_I2C_SLEEP ((u32)0x00000001<<4) /*BIT[4], I2C clock contro*/
#define USI_I2C_CLK_IS_GATED ((u32)0x00000001<<8) /*BIT[8], Clock-gated I2C clock domain for address matching interrupts wake up.*/
#define USI_I2C_OUT_SMP_DLY ((u32)0x00000007<<9) /*BIT[11:9], I2C output delay sample*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_TAR
* @{
*****************************************************************************/
#define USI_I2C_IC_TAR ((u32)0x000003FF) /*BIT[9:0], target address for any master transaction.*/
#define USI_I2C_GC_OR_START ((u32)0x00000001<<10) /*BIT[10], If i2c_special is set to 1, then this bit indicates whether a General Call or START BYTE
command is to be performed by I2C. 0: General Call ¨C after issuing a General Call, only write may be performed. 1: START BYTE*/
#define USI_I2C_SPECIAL ((u32)0x00000001<<11) /*BIT[11], This bit indicates whether software performs a General Call or START BYTE command.*/
#define USI_I2C_10BITADDR_MST ((u32)0x00000001<<12) /*BIT[12], Control whether I2C starts its transfers in 7- or 10-bit addressing mode when acting as a master. */
/** @} */
/**************************************************************************//**
* @defgroup I2C_DMA_CMD
* @{
*****************************************************************************/
#define USI_I2C_DMODE_ENABLE ((u32)0x00000001) /*BIT[0], 1: Set to enable dma mode, clear when transfer is done*/
#define USI_I2C_DMA_MODE ((u32)0x00000003<<1) /*BIT[2:1], DMA mode MASK*/
#define USI_I2C_DMA_LEGACY_MODE ((u32)0x00000000<<1) /*BIT[2:1]=0, DWC DMA legacy mode*/
#define USI_I2C_DMA_CTRL_REG_MODE ((u32)0x00000001<<1) /*BIT[2:1]=1, DMA with control register*/
#define USI_I2C_DMA_DESC_MODE ((u32)0x00000002<<1) /*BIT[2:1]=2, DMA with transfer descriptor*/
#define USI_I2C_DMODE_READ_CMD ((u32)0x00000001<<4) /*BIT[4], This bit controls a read operation is performed in DMA mode.*/
#define USI_I2C_DMODE_WRITE_CMD ((u32)0x00000000<<4) /*BIT[4], This bit controls a write operation is performed in DMA mode.*/
#define USI_I2C_DMODE_STOP ((u32)0x00000001<<5) /*BIT[5], This bit controls whether a STOP is issued after the byte is sent or received in DMA mode.*/
#define USI_I2C_DMODE_RESTART ((u32)0x00000001<<6) /*BIT[6], This bit controls whether a RESTART is issued after the byte is sent or received in DMA mode.*/
#define USI_I2C_DMA_DAT_LEN ((u32)0x0000FFFF<<16) /*BIT[31:16], DMA transfer data length*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_STATUS
* @{
*****************************************************************************/
#define USI_I2C_ENABLE_COPY ((u32)0x00000001) /*BIT[0], i2c_enable copy to here*/
#define USI_I2C_ACTIVITY_COMB ((u32)0x00000001<<4) /*BIT[4], I2C Activity Status, i2c_mst_activity or i2c_slv_activity is "1"*/
#define USI_I2C_MST_ACTIVITY ((u32)0x00000001<<5) /*BIT[5], Master FSM Activity Status. When the Master FSM is not in the IDLE state, this bit is set.*/
#define USI_I2C_SLV_ACTIVITY ((u32)0x00000001<<6) /*BIT[6], Slave FSM Activity Status. When the Slave FSM is not in the IDLE state, this bit is set.*/
#define USI_I2C_BUS_ACTIVITY ((u32)0x00000001<<7) /*BIT[7], BUS FSM Activity Status. When the BUS FSM is not in the IDLE state, this bit is set.*/
#define USI_I2C_SLV_DIS_WHL_BUSY ((u32)0x00000001<<8) /*BIT[8], Slave Disabled While Busy (Transmit, Receive)*/
#define USI_I2C_DMA_DIS_WHL_BUSY ((u32)0x00000003<<9) /*BIT[10:9], DMA disable While Busy mask*/
#define USI_I2C_DMA_DIS_WHL_BUSY_DMA ((u32)0x00000001<<9) /*BIT[9], I2C is disable while busy in DMA mode*/
#define USI_I2C_DMA_DIS_WHL_BUSY_DESC ((u32)0x00000002<<9) /*BIT[10], I2C is disable while busy in Descriptor mode*/
#define USI_I2C_DMA_TRANS_LEN ((u32)0x0000FFFF<<16) /*BIT[31:16], DMA mode transfer bytes*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_ANA_FILTER1
* @{
*****************************************************************************/
#define USI_I2C_ANA_DATA_DEG_RL ((u32)0x000FFFFF) /*BIT[19:0]*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_ANA_FILTER2
* @{
*****************************************************************************/
#define USI_I2C_ANA_DATA_DEG_RM ((u32)0x000FFFFF) /*BIT[19:0]*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_ANA_FILTER3
* @{
*****************************************************************************/
#define USI_I2C_ANA_CLK_DEG_RL ((u32)0x000FFFFF) /*BIT[19:0]*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_ANA_FILTER4
* @{
*****************************************************************************/
#define USI_I2C_ANA_CLK_DEG_RM ((u32)0x000FFFFF) /*BIT[19:0]*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_ANA_FILTER5
* @{
*****************************************************************************/
#define USI_I2C_ANA_DATA_DEG_CL ((u32)0x000FFFFF) /*BIT[19:0]*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_ANA_FILTER6
* @{
*****************************************************************************/
#define USI_I2C_ANA_DATA_DEG_CM ((u32)0x0000001F) /*BIT[4:0]*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_ANA_FILTER7
* @{
*****************************************************************************/
#define USI_I2C_ANA_CLK_DEG_CL ((u32)0x000FFFFF) /*BIT[19:0]*/
/** @} */
/**************************************************************************//**
* @defgroup I2C_ANA_FILTER8
* @{
*****************************************************************************/
#define USI_I2C_ANA_CLK_DEG_CM ((u32)0x0000001F) /*BIT[4:0]*/
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
/*----------------------global---------------------*/
typedef struct
{
USI_TypeDef* USIx;
u32 Tx_HandshakeInterface;
u32 Rx_HandshakeInterface;
IRQn_Type IrqNum;
} USI_DevTable;
extern const USI_DevTable USI_DEV_TABLE[1];
#define MAX_USI_INDEX (1)
#endif
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_usi_i2c.h
* @author
* @version V1.0.0
* @date 2017-12-18
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_USI_I2C_H_
#define _RTL8721D_USI_I2C_H_
#include "rtl8721d_usi.h"
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @addtogroup USI-I2C
* @{
*/
/** @addtogroup USI-I2C
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* USI_I2C:
* - Base Address: USI0_DEV
* - IPclk: 50Mhz
* - Speed: Standard (up to 100 kHz) , Fast (up to 400 kHz), High (up to 3.33 MHz) mode
* - Address: 7/10-bit Address Mode
* - IRQ: USI_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_USI0_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_USI0_RX
*
*****************************************************************************************
* How to use USI_I2C
*****************************************************************************************
* To use the normal USI_I2C mode, the following steps are mandatory:
*
* 1. Enable peripheral clock using the follwoing functions.(it is enabled by default)
* RCC_PeriphClockCmd(APBPeriph_USI_REG, APBPeriph_USI_CLOCK, ENABLE);
*
* 2. configure the I2C pinmux.
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_I2C)
*
* 3. Program Role, Address Mode, Speed Mode, USI_I2C CLK, Slave address, Threshold, Feature Supports
* USI_I2C_StructInit()
*
* 4. Init Hardware use step3 parameters:
* USI_I2C_Init(USI_TypeDef *USIx, USI_I2C_InitTypeDef* USI_I2C_InitStruct)
*
* 5. Enable the NVIC and the corresponding interrupt using following function if you need
* to use interrupt mode.
* USI_I2C_INTConfig(): USI_I2C IRQ Mask set
* InterruptRegister(): register the i2c irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 6. Enable USI_I2C module using USI_I2C_Cmd().
*
*****************************************************************************************
* How to use USI_I2C in DMA Register mode
*****************************************************************************************
* To use the USI_I2C in DMA Register mode, the following steps are mandatory:
*
* 1. Enable peripheral clock using the follwoing functions.(it is enabled by default)
* RCC_PeriphClockCmd(APBPeriph_USI_REG, APBPeriph_USI_CLOCK, ENABLE);
*
* 2. configure the I2C pinmux.
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_I2C)
*
* 3. Program Role, Address Mode, Speed Mode, USI_I2C CLK, Slave address, Threshold, Feature Supports
* USI_I2C_StructInit()
*
* 4. Init Hardware use step3 parameters:
* USI_I2C_Init(USI_TypeDef *USIx, USI_I2C_InitTypeDef* USI_I2C_InitStruct)
*
* 5. Enable USI_I2C module using USI_I2C_Cmd().
*
* 6. GDMA related configurations(source address/destination address/block size etc.)
* USI_I2C_TXGDMA_Init():Init and Enable USI_I2C TX GDMA
* USI_I2C_RXGDMA_Init():Init and Enable USI_I2C RX GDMA
*
* 7. USI_I2C DMA Register Mode set.
* USI_I2C_DmaRegModeConfig():Configures the USI_I2C Control Register DMA mode
*
* 8. Active the USI_I2C TX/RX DMA Request using USI_I2C_DMAControl().
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types --------------------------------------------------------*/
/** @defgroup USI_I2C_Exported_Types USI-I2C Exported Types
* @{
*/
/**
* @brief USI_I2C Init structure definition
*/
typedef struct {
u32 USI_I2CIdx; /*!< Specifies the USI_I2C Device Index.
This parameter can be a value of @ref USI_I2C_Peripheral_definitions */
u32 USI_I2CMaster; /*!< Specifies the USI_I2C Role.
This parameter can be a value of @ref USI_I2C_Role_definitions */
u32 USI_I2CAddrMod; /*!< Specifies the USI_I2C Addressing Mode.
This parameter can be a value of @ref USI_I2C_Addr_Mode_definitions */
u32 USI_I2CSpdMod; /*!< Specifies the USI_I2C Speed Mode.
This parameter can be a value of @ref USI_I2C_Speed_Mode_definitions */
u32 USI_I2CRXTL; /*!< Specifies the USI_I2C RX FIFO Threshold. It controls the level of
entries(or above) that triggers the RX_FULL interrupt.
This parameter must be set to a value in the 0-255 range. A value of 0 sets
the threshold for 1 entry, and a value of 255 sets the threshold for 256 entry*/
u32 USI_I2CTXTL; /*!< Specifies the I2C TX FIFO Threshold.It controls the level of
entries(or below) that triggers the TX_EMPTY interrupt.
This parameter must be set to a value in the 0-255 range. A value of 0 sets
the threshold for 0 entry, and a value of 255 sets the threshold for 255 entry*/
u32 USI_I2CMstReSTR; /*!< Specifies the USI_I2C Restart Support of Master. */
u32 USI_I2CMstGC; /*!< Specifies the USI_I2C General Call Support of Master. */
u32 USI_I2CMstStartB; /*!< Specifies the USI_I2C Start Byte Support of Master. */
u32 USI_I2CSlvNoAck; /*!< Specifies the USI_I2C Slave No Ack Support. */
u32 USI_I2CSlvAckGC; /*!< Specifies the USI_I2C Slave Acks to General Call. */
u32 USI_I2CAckAddr; /*!< Specifies the USI_I2C Target Address in I2C Master Mode or
Ack Address in USI_I2C Slave0 Mode.
This parameter must be set to a value in the 0-127 range if the USI_I2C_ADDR_7BIT
is selected or 0-1023 range if the USI_I2C_ADDR_10BIT is selected. */
u32 USI_I2CSlvSetup; /*!< Specifies the USI_I2C SDA Setup Time. It controls the amount of time delay
introduced in the rising edge of SCL¡ªrelative to SDA changing¡ªby holding SCL low
when USI_I2C Device operating as a slave transmitter, in units of ic_clk period.
This parameter must be set to a value in the 0-255 range, it must be set larger than USI_I2CSdaHd*/
u32 USI_I2CSdaHd; /*!< Specifies the USI_I2C SDA Hold Time. It controls the amount of
hold time on the SDA signal after a negative edge of SCL in both master
and slave mode, in units of ic_clk period.
This parameter must be set to a value in the 0-0xFFFF range. */
u32 USI_I2CClk; /*!< Specifies the USI_I2C Bus Clock (in kHz). It is closely related to USI_I2CSpdMod */
u32 USI_I2CIPClk; /*!< Specifies the USI_I2C IP Clock (in Hz). */
u32 USI_I2CFilter; /*!< Specifies the USI_I2C SCL/SDA Spike Filter. */
u32 USI_I2CTxDMARqLv; /*!< Specifies the USI_I2C TX DMA Empty Level. dma_tx_req signal is generated when
the number of valid data entries in the transmit FIFO is equal to or below the DMA
Transmit Data Level Register. The value of DMA Transmit Data Level Register is equal
to this value. This parameter must be set to a value in the 0-31 range. */
u32 USI_I2CRxDMARqLv; /*!< Specifies the USI_I2C RX DMA Full Level. dma_rx_req signal is generated when
the number of valid data entries in the transmit FIFO is equal to or above the DMA
Receive Data Level Register. The value of DMA Receive Data Level Register is equal to
this value+1. This parameter must be set to a value in the 0-31 range. */
u32 USI_I2CDMAMod; /*!< Specifies the USI_I2C DMA Mode.
This parameter can be a value of @ref USI_I2C_DMA_Mode_definitions */
}USI_I2C_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup USI_I2C_Exported_Constants USI-I2C Exported Constants
* @{
*/
/** @defgroup USI_I2C_Peripheral_definitions
* @{
*/
#define IS_USI_I2C_ALL_PERIPH(PERIPH) ((PERIPH) == USI0_DEV)
/**
* @}
*/
/** @defgroup USI_I2C_Addr_Mode_definitions
* @{
*/
#define USI_I2C_ADDR_7BIT ((u32)0x00000000)
#define USI_I2C_ADDR_10BIT ((u32)0x00000001)
#define IS_USI_I2C_ADDR_MODE(MODE) (((MODE) == USI_I2C_ADDR_7BIT) || \
((MODE) == USI_I2C_ADDR_10BIT))
/**
* @}
*/
/** @defgroup USI_I2C_Speed_Mode_definitions
* @{
*/
#define USI_I2C_SS_MODE ((u32)0x00000001)
#define USI_I2C_FS_MODE ((u32)0x00000002)
#define USI_I2C_HS_MODE ((u32)0x00000003)
#define IS_USI_I2C_SPEED_MODE(MODE) (((MODE) == USI_I2C_SS_MODE) || \
((MODE) == USI_I2C_FS_MODE) || \
((MODE) == USI_I2C_HS_MODE))
/**
* @}
*/
/** @defgroup USI_I2C_Role_definitions
* @{
*/
#define USI_I2C_SLAVE_MODE ((u32)0x00000000)
#define USI_I2C_MASTER_MODE ((u32)0x00000001)
/**
* @}
*/
/** @defgroup USI_I2C_DMA_Mode_definitions
* @{
*/
#define USI_I2C_DMA_LEGACY ((u32)0x00000000)
#define USI_I2C_DMA_REGISTER ((u32)0x00000001)
#define USI_I2C_DMA_DESCRIPTOR ((u32)0x00000002)
#define IS_USI_I2C_DMA_MODE(MODE) (((MODE) == USI_I2C_DMA_LEGACY) || \
((MODE) == USI_I2C_DMA_REGISTER) || \
((MODE) == USI_I2C_DMA_DESCRIPTOR))
/**
* @}
*/
/** @defgroup USI_I2C_DMA_DATA_LENGTH
* @{
*/
#define IS_USI_I2C_DMA_DATA_LEN(LENGTH) ((LENGTH) <= 0xFFFF)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup USI_I2C_Exported_Functions USI-I2C Exported Functions
* @{
*/
/** @defgroup USI_I2C_Exported_Normal_Functions USI-I2C Exported Normal Functions
* @{
*/
_LONG_CALL_ void USI_I2C_StructInit(USI_I2C_InitTypeDef* USI_I2C_InitStruct);
_LONG_CALL_ void USI_I2C_Init(USI_TypeDef *USIx, USI_I2C_InitTypeDef* USI_I2C_InitStruct);
_LONG_CALL_ void USI_I2C_SetSpeed(USI_TypeDef *USIx, u32 SpdMd, u32 I2Clk, u32 I2CIPClk);
_LONG_CALL_ void USI_I2C_SetSlaveAddress(USI_TypeDef *USIx, u16 Address);
_LONG_CALL_ u8 USI_I2C_CheckFlagState(USI_TypeDef *USIx, u32 USI_I2C_FLAG);
_LONG_CALL_ u8 USI_I2C_CheckTXFIFOState(USI_TypeDef *USIx, u32 USI_I2C_TXFIFO_FLAG);
_LONG_CALL_ u8 USI_I2C_CheckRXFIFOState(USI_TypeDef *USIx, u32 USI_I2C_RXFIFO_FLAG);
_LONG_CALL_ void USI_I2C_INTConfig(USI_TypeDef *USIx, u32 USI_I2C_IT, u32 NewState);
_LONG_CALL_ void USI_I2C_ClearINT(USI_TypeDef *USIx, u32 INTrBit);
_LONG_CALL_ void USI_I2C_ClearAllINT(USI_TypeDef *USIx);
_LONG_CALL_ u32 USI_I2C_GetRawINT(USI_TypeDef *USIx);
_LONG_CALL_ u32 USI_I2C_GetINT(USI_TypeDef *USIx);
_LONG_CALL_ void USI_I2C_Cmd(USI_TypeDef *USIx, u8 NewState);
_LONG_CALL_ u8 USI_I2C_ReceiveData(USI_TypeDef *USIx);
/**
* @}
*/
/** @defgroup USI_I2C_Exported_Master_Functions USI-I2C Exported Master Functions
* @{
*/
_LONG_CALL_ void USI_I2C_MasterSendNullData(USI_TypeDef *USIx, u8* pBuf, u8 I2CCmd, u8 I2CStop, u8 I2CReSTR);
_LONG_CALL_ void USI_I2C_MasterSend(USI_TypeDef *USIx, u8* pBuf, u8 I2CCmd, u8 I2CStop, u8 I2CReSTR);
_LONG_CALL_ u8 USI_I2C_MasterWrite(USI_TypeDef *USIx, u8* pBuf, u8 len);
_LONG_CALL_ u8 USI_I2C_MasterRead(USI_TypeDef *USIx, u8* pBuf, u8 len);
_LONG_CALL_ void USI_I2C_MasterRepeatRead(USI_TypeDef* USIx, u8* pWriteBuf, u8 Writelen, u8* pReadBuf, u8 Readlen);
_LONG_CALL_ void USI_I2C_SetSlaveAddress(USI_TypeDef *USIx, u16 Address);
/**
* @}
*/
/** @defgroup USI_I2C_Exported_Slave_Functions USI-I2C Exported Slave Functions
* @{
*/
_LONG_CALL_ void USI_I2C_SlaveWrite(USI_TypeDef *USIx, u8* pBuf, u8 len);
_LONG_CALL_ void USI_I2C_SlaveRead(USI_TypeDef *USIx, u8* pBuf, u8 len);
_LONG_CALL_ void USI_I2C_SlaveSend(USI_TypeDef *USIx, u8 Data);
/**
* @}
*/
/** @defgroup USI_I2C_Exported_DMA_Functions USI-I2C Exported DMA Functions
* @{
*/
_LONG_CALL_ void USI_I2C_DMAControl(USI_TypeDef *USIx, u32 DmaCtrl, u8 NewState);
_LONG_CALL_ void USI_I2C_DmaRegModeConfig(USI_TypeDef *USIx, u32 USI_I2C_DmaCmd, u32 USI_I2C_DmaBLen);
_LONG_CALL_ BOOL USI_I2C_TXGDMA_Init(u8 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pTxBuf, int TxCount);
_LONG_CALL_ BOOL USI_I2C_RXGDMA_Init(u8 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pRxBuf, int RxCount);
/**
* @}
*/
/** @defgroup USI_I2C_Exported_PowerSave_Functions USI-I2C Exported PowerSave Functions
* @{
*/
_LONG_CALL_ void USI_I2C_Sleep_Cmd(USI_TypeDef *USIx, u32 NewStatus);
_LONG_CALL_ void USI_I2C_WakeUp(USI_TypeDef *USIx);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
//USI_I2C Timing Parameters
#define USI_I2C_SS_MIN_SCL_HTIME 4000 //the unit is ns.
#define USI_I2C_SS_MIN_SCL_LTIME 4700 //the unit is ns.
#define USI_I2C_FS_MIN_SCL_HTIME 600 //the unit is ns.
#define USI_I2C_FS_MIN_SCL_LTIME 1300 //the unit is ns.
#define USI_I2C_HS_MIN_SCL_HTIME_100 60 //the unit is ns, with bus loading = 100pf
#define USI_I2C_HS_MIN_SCL_LTIME_100 100 //the unit is ns., with bus loading = 100pf
#define USI_I2C_HS_MIN_SCL_HTIME_400 160 //the unit is ns, with bus loading = 400pf
#define USI_I2C_HS_MIN_SCL_LTIME_400 320 //the unit is ns., with bus loading = 400pf
extern u32 USI_I2C_SLAVEWRITE_PATCH;
extern u32 USI_IC_FS_SCL_HCNT_TRIM;
extern u32 USI_IC_FS_SCL_LCNT_TRIM;
#endif
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_usi_ssi.h
* @author
* @version V1.0.0
* @date 2017-11-27
* @brief This file contains all the functions prototypes for the SPI firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_USI_SSI_H_
#define _RTL8721D_USI_SSI_H_
#include "rtl8721d_usi.h"
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup USI-SPI
* @brief USI-SPI driver modules
* @{
*/
/** @addtogroup USI-SPI
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* USI-SPI:
* - Support Motorola SPI interface
* - Role: Master or Slave
* - Base Address: USI0_DEV
* - Bus Clk: 50MHz
* - BaudRate: less than or equal to 25M
* - Transfer mode: Tx,Rx,TRx when configured as Master; TRx when configured as Slave
* - Data Frame Size: 4-16 bits supported
* - IRQ Number: USI_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_USI0_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_USI0_RX
*
*****************************************************************************************
* How to use Normal USI SPI
*****************************************************************************************
* To use the SPI in normal mode, the following steps are mandatory:
*
* 1. Enable peripheral clock using the following functions:
* -RCC_PeriphClockCmd(APBPeriph_USI_REG, APBPeriph_USI_CLOCK, ENABLE);
*
* 2. Configure the SPIx pinmux:
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIM) when configured as Master;
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIS) when configured as Slave;
*
* 3. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize,
* Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using
* USI_SSI_StructInit() and change some parameters if needed
*
* 4. Init Hardware use step3 parameters:
* USI_SSI_Init(USI_TypeDef *usi_dev, USI_SSI_InitTypeDef *USI_SSI_InitStruct)
*
* 5. Enable the SPI:
* USI_SSI_Cmd()
*
* 6. When using poll:
* -Using USI_SSI_Writeable() function to make sure that the transmit FIFO is not full,
* then using USI_SSI_WriteData() function to send data
*
* -Using USI_SSI_Readable() function to make sure that the receive FIFO is not empty,
* then using USI_SSI_ReadData() function to receive data
*
* 7. Enable the NVIC and the corresponding interrupt using following function if you need
* to use interrupt mode.
* -USI_SSI_INTConfig(): SPI IRQ Mask set
* -InterruptRegister(): register the SPI irq handler
* -InterruptEn(): Enable the NVIC interrupt and set irq priority
*
*
* @note in SPI_Exported_Functions group, these functions below are about Interrupts
* and flags management:
* -USI_SSI_GetIsr()
* -USI_SSI_GetRawIsr()
* -USI_SSI_INTConfig()
* -USI_SSI_SetRxFifoLevel()
* -USI_SSI_SetTxFifoLevel()
* -USI_SSI_SetIsrClean()
*
*
*****************************************************************************************
* How to use USI SPI in DMA mode
*****************************************************************************************
* To use the USI SPI in DMA mode, the following steps are mandatory:
*
* 1. Enable peripheral clock using the following functions:
* -RCC_PeriphClockCmd(APBPeriph_USI_REG, APBPeriph_USI_CLOCK, ENABLE);
*
* 2. Configure the SPIx pinmux:
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIM) when configured as Master;
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIS) when configured as Slave;
*
* 3. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize,
* Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using
* USI_SSI_StructInit() and change some parameters if needed
*
* 4. Init Hardware use step3 parameters:
* USI_SSI_Init(USI_TypeDef *usi_dev, USI_SSI_InitTypeDef *USI_SSI_InitStruct)
*
* 5. Enable the SPI:
* USI_SSI_Cmd()
*
* 6. GDMA related configurations(DMA burst size/source address/destination address/block size etc).
*
* 7. Active the SPI DMA TX/RX using USI_SSI_SetDmaEnable() function.
*
* @note in SPI_Exported_Functions group, these functions below are about DMA:
* -USI_SSI_SetDmaEnable()
* -USI_SSI_SetDmaLevel()
*
*****************************************************************************************
* @endverbatim
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup USI_SPI_Exported_Types USI-SPI Exported Types
* @{
*/
/**
* @brief USI-SPI Init structure definition
*/
typedef struct
{
u32 USI_SPI_DmaRxDataLevel; /*!< Specifies the DMA receive data level.
The dma_rx_req is generated when the number of valid data entries in the
receive FIFO is equal to or above this field value+1,and rxdma_en =1.
@note For AmebaD, the value range of this parameter should be 0 to 63,because
the depth of Rx FIFO is 64. */
u32 USI_SPI_DmaTxDataLevel; /*!< Specifies the DMA transmit data level.
The dma_tx_req is generated when the number of valid data entries in the
transmit FIFO is equal to or below this field value,and txdma_en =1.
@note For AmebaD, the value range of this parameter should be 0 to 63,because
the depth of Rx FIFO is 64. */
u32 USI_SPI_RxThresholdLevel; /*!< Specifies the receive FIFO threshold level.
This Parameter controls the level of entries(or above) at which the receive FIFO controller
triggers an interrupt.When the number of receive FIFO entries is greater than or equal to this
value +1,the receive FIFO full interrupt is triggered.
@note For AmebaD, the value range of this parameter should be 0 to 63,because the depth
of Rx FIFO is 64. */
u32 USI_SPI_TxThresholdLevel; /*!< Specifies the transmit FIFO threshold level.
This Parameter controls the level of entries (or below) at which the transmit FIFO controller
triggers an interrupt.When the number of transmit FIFO entries is less than or equal to this
value,the transmit FIFO empty interrupt is triggered.
@note For AmebaD, the value range of this parameter should be 0 to 63,because of the depth
of Rx FIFO is 64. */
u32 USI_SPI_ClockDivider; /*!< Specifies the SPI Baud Rate.
The value of sclk_out equals to ssi_clk devides the value of this parameter
@note The LSB for this field is always set to 0 and is unaffected by a write operation,which ensures
an even value is held. */
u32 USI_SPI_DataFrameNumber; /*!< Specifies the number of data frames master wants to receive.
When TMOD=10, SPI uses this value to set the number of data frames to
be continuous received.
@note The value of this parameter should be set to the number of data frames that to be received
minus one.And this parameter is used only when the device is master. */
u32 USI_SPI_DataFrameSize; /*!< Selects the data frame length .
This parameter can be a value of @ref USI_SPI_Data_Frame_Size_definitions.
@note Need to right-justify transmit data before writting into the transmit FIFO
The transmit logic ignores the upper unused bits when transmitting the data. */
u32 USI_SPI_InterruptMask; /*!< Specifies which interrupt to enable.
Each bit in this parameter corresponds to a specific interrupt.*/
u32 USI_SPI_Role; /*!< Specifies the role of SPI device.
This parameter can be a value of @ref USI_SPI_ROLE_definitions. . */
u32 USI_SPI_SclkPhase; /*!< Specifies the serial clock phase.
When USI_SPI_SclkPhase = 0, data are captured on the first edge of the serial clock.
When USI_SPI_SclkPhase = 1, the serial clock starts toggling one cycle after the slave select line is activated,
and data are captured on the second edge of the serial clock.
This parameter can be a value of @ref USI_SPI_SCPH_definitions. */
u32 USI_SPI_SclkPolarity; /*!< Specifies the serial clock polarity.
When USI_SPI_SclkPolarity = 0, the serial clock remains low when idle.
When USI_SPI_SclkPolarity = 1, the serial clock remains high when idle.
This parameter can be a value of @ref USI_SPI_SCPOL_definitions. */
u32 USI_SPI_TransferMode; /*!< Selects the mode of transfer for serial communication.
This parameter can be a value of @ref USI_SPI_TMOD_definitions.
@note This transfer mode is only valid when the DW_apb_ssi is configured as a master device.*/
u32 USI_SPI_RxSampleDelay; /*!< Specifies the sample delay time of receive data input signal.The unit is spi_mst_clk.
@note This configuration is only valid when the DW_apb_ssi is configured as a master device.
For AmebaD, the value range of this parameter should be 0 to 0xFF */
u32 USI_SPI_SSTogglePhase; /*!< Specifies whether CS needs to toggle between transmissions when USI_SPI_SclkPhase = 0.
This parameter can be a value of @ref USI_SPI_SS_Toggle_Phase_definitions.
@note This configuration is only valid when the DW_apb_ssi is configured as a master device. */
}USI_SSI_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup USI_SPI_Exported_Constants USI-SPI Exported Constants
* @{
*/
/** @defgroup USI_SPI_TMOD_definitions
* @{
*/
#define USI_SPI_TMOD_TR (0)
#define USI_SPI_TMOD_TO (1)
#define USI_SPI_TMOD_RO (2)
/**
* @}
*/
/** @defgroup USI_SPI_SCPOL_definitions
* @{
*/
#define USI_SPI_SCPOL_INACTIVE_IS_LOW (0)
#define USI_SPI_SCPOL_INACTIVE_IS_HIGH (1)
/**
* @}
*/
/** @defgroup USI_SPI_SCPH_definitions
* @{
*/
#define USI_SPI_SCPH_TOGGLES_IN_MIDDLE (0)
#define USI_SPI_SCPH_TOGGLES_AT_START (1)
/**
* @}
*/
/** @defgroup USI_SPI_SS_Toggle_Phase_definitions
* @{
*/
#define USI_SPI_SS_NOT_TOGGLE (0)
#define USI_SPI_SS_TOGGLE (1)
/**
* @}
*/
/** @defgroup USI_SPI_Data_Frame_Size_definitions
* @{
*/
#define USI_SPI_DFS_4_BITS (3)
#define USI_SPI_DFS_5_BITS (4)
#define USI_SPI_DFS_6_BITS (5)
#define USI_SPI_DFS_7_BITS (6)
#define USI_SPI_DFS_8_BITS (7)
#define USI_SPI_DFS_9_BITS (8)
#define USI_SPI_DFS_10_BITS (9)
#define USI_SPI_DFS_11_BITS (10)
#define USI_SPI_DFS_12_BITS (11)
#define USI_SPI_DFS_13_BITS (12)
#define USI_SPI_DFS_14_BITS (13)
#define USI_SPI_DFS_15_BITS (14)
#define USI_SPI_DFS_16_BITS (15)
/**
* @}
*/
/** @defgroup USI_SPI_ROLE_definitions
* @{
*/
#define USI_SPI_SLAVE (0)
#define USI_SPI_MASTER (1)
/**
* @}
*/
/** @defgroup USI_SPI_DMA_Control_definitions
* @{
*/
#define USI_SPI_NODMA (0)
#define USI_SPI_RXDMA_ENABLE (1)
#define USI_SPI_TXDMA_ENABLE (2)
#define USI_SPI_TRDMA_ENABLE (3)
/**
* @}
*/
/** @defgroup USI_SPI_FIFO_depth_definitions
* @{
*/
#define USI_SPI_TX_FIFO_DEPTH (64)
#define USI_SPI_RX_FIFO_DEPTH (64)
/**
* @}
*/
/** @defgroup USI_SPI_Interrupt_definitions
* @{
*/
#define USI_SPI_INTERRUPT_MASK (USI_TXFIFO_ALMOST_EMTY_INTR_EN | \
USI_TXFIFO_OVERFLOW_INTR_EN | \
USI_TXFIFO_UNDERFLOW_INTR_EN | \
USI_RXFIFO_ALMOST_FULL_INTR_EN | \
USI_RXFIFO_OVERFLOW_INTR_EN | \
USI_RXFIFO_UNDERFLOW_INTR_EN | \
USI_SPI_RX_DATA_FRM_ERR_INTER_EN)
#define USI_SPI_INTERRUPT_CLEAR_MASK (USI_TXFIFO_OVERFLOW_CLR | \
USI_TXFIFO_UNDERFLOW_CLR | \
USI_RXFIFO_OVERFLOW_CLR | \
USI_RXFIFO_UNDERFLOW_CLR | \
USI_SPI_RX_DATA_FRM_ERR_CLR)
/**
* @}
*/
/** @defgroup USI_TRX_Threshold_Level_definitions
* @{
*/
#define IS_USI_SPI_RxThresholdLevel(value) (value <= 63)
#define IS_USI_SPI_TxThresholdLevel(value) (value <= 63)
/**
* @}
*/
/** @defgroup USI_TRX_DMA_Level_definitions
* @{
*/
#define IS_USI_SPI_RxDMALevel(value) (value <= 63)
#define IS_USI_SPI_TxDMALevel(value) (value <= 63)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup USI_SPI_Exported_Functions USI-SPI Exported Functions
* @{
*/
/** @defgroup USI_SPI_Exported_Normal_Functions USI-SPI Exported Normal Functions
* @{
*/
_LONG_CALL_ void USI_SSI_StructInit(USI_SSI_InitTypeDef* USI_SSI_InitStruct);
_LONG_CALL_ void USI_SSI_Init(USI_TypeDef *usi_dev, USI_SSI_InitTypeDef *USI_SSI_InitStruct);
_LONG_CALL_ void USI_SSI_Cmd(USI_TypeDef *usi_dev, u32 NewStatus);
_LONG_CALL_ void USI_SSI_TRxPath_Cmd(USI_TypeDef *usi_dev, u32 path, u32 NewStatus);
_LONG_CALL_ u32 USI_SSI_GetTRxPath(USI_TypeDef *usi_dev);
_LONG_CALL_ void USI_SSI_INTConfig(USI_TypeDef* usi_dev, u32 USI_SSI_IT, u32 newState);
_LONG_CALL_ void USI_SSI_SetSclkPolarity(USI_TypeDef *usi_dev, u32 SclkPolarity);
_LONG_CALL_ void USI_SSI_SetSclkPhase(USI_TypeDef *usi_dev, u32 SclkPhase);
_LONG_CALL_ void USI_SSI_SetSSTogglePhase(USI_TypeDef *usi_dev, u32 TogglePhase);
_LONG_CALL_ void USI_SSI_SetDataFrameSize(USI_TypeDef *usi_dev, u32 DataFrameSize);
_LONG_CALL_ void USI_SSI_SetSampleDelay(USI_TypeDef *usi_dev, u32 SampleDelay);
_LONG_CALL_ void USI_SSI_SetReadLen(USI_TypeDef *usi_dev, u32 DataFrameNumber);
_LONG_CALL_ void USI_SSI_SetBaudDiv(USI_TypeDef *usi_dev, u32 ClockDivider);
_LONG_CALL_ void USI_SSI_SetBaud(USI_TypeDef *USIx, u32 BaudRate, u32 IpClk);
_LONG_CALL_ void USI_SSI_SetIsrClean(USI_TypeDef *usi_dev, u32 InterruptStatus);
_LONG_CALL_ void USI_SSI_WriteData(USI_TypeDef *usi_dev, u32 value);
_LONG_CALL_ void USI_SSI_SetRxFifoLevel(USI_TypeDef *usi_dev, u32 RxThresholdLevel);
_LONG_CALL_ void USI_SSI_SetTxFifoLevel(USI_TypeDef *usi_dev, u32 TxThresholdLevel);
_LONG_CALL_ u32 USI_SSI_Writeable(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_Writeable(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_ReadData(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_ReceiveData(USI_TypeDef *usi_dev, void* RxData, u32 Length);
_LONG_CALL_ u32 USI_SSI_SendData(USI_TypeDef *usi_dev, void* TxData, u32 Length, u32 Role);
_LONG_CALL_ u32 USI_SSI_GetRxCount(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_GetTxCount(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_GetTxFIFOStatus(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_GetRxFIFOStatus(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_GetTransStatus(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_GetDataFrameSize(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_Busy(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_GetIsr(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_GetRawIsr(USI_TypeDef *usi_dev);
/**
* @}
*/
/** @defgroup USI_SPI_Exported_DMA_Functions USI-SPI Exported DMA Functions
* @{
*/
_LONG_CALL_ BOOL USI_SSI_TXGDMA_Init(u32 Index, PGDMA_InitTypeDef GDMA_InitStruct, void *CallbackData,
IRQ_FUN CallbackFunc, u8 *pTxData, u32 Length);
_LONG_CALL_ BOOL USI_SSI_RXGDMA_Init(u8 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData,
IRQ_FUN CallbackFunc, u8 *pRxData, u32 Length);
_LONG_CALL_ void USI_SSI_SetDmaEnable(USI_TypeDef *usi_dev, u32 newState, u32 Mask);
_LONG_CALL_ void USI_SSI_SetDmaLevel(USI_TypeDef *usi_dev, u32 TxLevel, u32 RxLevel);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
#endif //_RTL8721D_USI_SSI_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_usi_uart.h
* @author
* @version V1.0.0
* @date 2017-09-26
* @brief This file contains all the functions prototypes for the USI firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_USI_UART_H_
#define _RTL8721D_USI_UART_H_
#include "rtl8721d_usi.h"
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup USI-UART
* @{
*/
/** @addtogroup USI-UART
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* USI0-UART:
* - Base Address: USI0_DEV
* - IPclk: XTAL, normally is 40MHz
* - BaudRate: 110~6000000
* - Low Power Rx: Support
* - Boot From UART without Flash
* - IRQ: USI_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_USI0_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_USI0_RX
*
*****************************************************************************************
* USI UART Low Power Rx
*****************************************************************************************
* USI0-UART support
* UART can receive data when soc enter power save mode
* baudrate: 110~500000
*
*****************************************************************************************
* How to use USI Normal Uart
*****************************************************************************************
* To use the normal uart mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power:
*
* 2. configure the USI UART pinmux
*
* 3. Set default parameters, change some parameter if needed
* USI_UARTStructInit(USI_UARTInitTypeDef* USI_UARTInitStruct)
*
* 4. init hardware use step3 parameters.
* USI_UARTInit(USI_TypeDef* USIx, USI_UARTInitTypeDef *USI_UARTInitStruct)
*
* 5. Set Baud Rate.
* USI_UARTSetBaud(USI_TypeDef* USIx, u32 BaudRate)
*
* 6. Enable IRQ using following function if needed
* USI_UARTINTConfig(): USI UART IRQ Mask set
* InterruptRegister(): register the uart irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 7. Enable uart rx path:
* USI_UARTRxCmd().
*
*****************************************************************************************
* How to use USI uart in DMA mode
*****************************************************************************************
* To use the uart in DMA mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power:
*
* 2. configure the USI UART pinmux
*
* 3. Set default parameters, and change DMA mode open USI_UARTInitStruct
* USI_UARTStructInit(USI_UARTInitTypeDef* USI_UARTInitStruct)
*
* 4. init hardware use step3 parameters.
* USI_UARTInit(USI_TypeDef* USIx, USI_UARTInitTypeDef *USI_UARTInitStruct)
*
* 5. Set Baud Rate.
* USI_UARTSetBaud(USI_TypeDef* USIx, u32 BaudRate)
*
* 6. Enable uart rx path:
* USI_UARTRxCmd().
*
* 7. Configure the uart DMA burst size:
* USI_UARTTXDMAConfig()
* USI_UARTRXDMAConfig().
*
* 8. Active the UART TX/RX DMA Request:
* USI_UARTTXDMACmd()
* USI_UARTRXDMACmd().
*
* 9. GDMA related configurations(source address/destination address/block size etc.).
* USI_UARTTXGDMA_Init()
* USI_UARTRXGDMA_Init()
*
*****************************************************************************************
* How to use USI uart in Low Power mode
*****************************************************************************************
* To use the uart in Low Power mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power:
*
* 2. configure the USI UART pinmux
*
* 3. Set default parameters, change some parameter if needed
* USI_UARTStructInit(USI_UARTInitTypeDef* USI_UARTInitStruct)
*
* 4. init hardware use step3 parameters.
* USI_UARTInit(USI_TypeDef* USIx, USI_UARTInitTypeDef *USI_UARTInitStruct)
*
* 5. Set Baud Rate.
* USI_UARTSetBaud(USI_TypeDef* USIx, u32 BaudRate)
*
* 6. Enable IRQ using following function if needed
* USI_UARTINTConfig(): USI UART IRQ Mask set
* InterruptRegister(): register the uart irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 6. Init Low power RX:
* USI_UARTLPRxStructInit(USI_LPUARTInitTypeDef* USI_LPUARTInitStruct)
* USI_UARTLPRxInit(USI_TypeDef* USIx, USI_LPUARTInitTypeDef *USI_LPUARTInitTypeDef)
*
* 7. Set the low power RX Baud Rate
* USI_UARTLPRxBaudSet(USI_TypeDef* USIx, u32 BaudRate, u32 RxIPClockHz)
*
* 8. Enable monitor function if needed.
* USI_UARTLPRxMonitorCmd()
*
* 9. Enable low power rx path:
* USI_UARTLPRxCmd().
*
* @note when uart work in low power rx mode, clock source can switch between
* XTAL and OSC. As for how and when to excute switching action,
* refer to related uart specifications for more details.
*
* @note Besides, if more details about the uart low power rx path contens is needed,
* please refer to uart specifications.
*
*****************************************************************************************
* How to use USI uart in IrDA mode
*****************************************************************************************
* To use the uart in IrDA mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power:
*
* 2. configure the pinmux:
*
* 3. Disable rx path:
* USI_UARTRxCmd().
*
* 4. Program the IrDA tx pulse width and location and IrDA rx pulse filter:
* USI_UARTIrDAStructInit(USI_UartIrDAInitTypeDef * IrDA_InitStruct)
*
* 5. Init Hardware:
* USI_UARTIrDAInit(USI_TypeDef* USIx, USI_UartIrDAInitTypeDef * IrDA_InitStruct).
*
* 6. Enable the IrDA function:
* USI_UARTIrDACmd().
*
* 7. According to the IrDA SIR protocol data format requrement, program Word Length,
* Stop Bit, Parity and DMA Mode(ENABLE/DISABLE):
* USI_UARTStructInit(USI_UARTInitTypeDef* USI_UARTInitStruct)
* USI_UARTInit(USI_TypeDef* USIx, USI_UARTInitTypeDef *USI_UARTInitStruct)
*
* 8. Program the Baud Rate:
* USI_UARTSetBaud().
*
* 9. Enable IRQ if needed:
* USI_UARTINTConfig(): USI UART IRQ Mask set
* InterruptRegister(): register the uart irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 10. Enable uart rx path:
* USI_UARTRxCmd().
*
* @note AmebaD IrDA just support IrDA SIR protocol, setting baud rate is no more than
* 115200 bps.
*
* @note because IrDA transfers data using infrared carrier and for the property of the
* IrDA transceiver, IrDA just work in half duplex mode. For details, refer to the IrDA
* protocol specification.
*****************************************************************************************
* @endverbatim
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup USI_UART_Exported_Types USI-UART Exported Types
* @{
*/
/**
* @brief USI_UART Init structure definition
*/
typedef struct
{
u32 USI_UARTDmaModeCtrl; /*!< Specifies the uart DMA mode state.
This parameter can be ENABLE or DISABLE. */
u32 USI_UARTWordLen; /*!< Specifies the USI UART word length.
This parameter can be a value of @ref USI_UART_Word_length_define. */
u32 USI_UARTStopBit; /*!< Specifies the USI UART stop bit number.
This parameter can be a value of @ref USI_UART_Stop_Bit_define. */
u32 USI_UARTParity; /*!< Specifies the USI UART parity.
This parameter can be a value of @ref USI_UART_Parity_Enable_define. */
u32 USI_UARTParityType; /*!< Specifies the USI UART parity type.
This parameter can be a value of @ref USI_UART_Parity_Type_define. */
u32 USI_UARTStickParity; /*!< Specifies the USI UART stick parity.
This parameter can be a value of @ref USI_UART_Stick_Parity_Type_define. */
u32 USI_UARTFlowControl; /*!< Specifies the USI UART auto flow control.
This parameter can be ENABLE or DISABLE. */
u32 USI_UARTFlwCtrlRxHoldThd; /*!< Specifies the USI UART uart auto flow control rx hold threshold.
This parameter can be a value of 0 ~ 64. */
u32 USI_UARTRxFifoTrigLevel; /*!< Specifies the USI UART rx fifo trigger level.
This parameter can be a value of 0 ~ 64 . */
u32 USI_UARTTxFifoTrigLevel; /*!< Specifies the USI UART rx error report control.
This parameter can be a value of 0 ~ 64 . */
u32 USI_UARTRxTimeOutCnt; /*!< Specifies the USI UART rx time out counter.
This parameter can be a number between 0x00 and 0xffff.. */
} USI_UARTInitTypeDef;
/**
* @brief USI UART Low Power Init structure definition
*/
typedef struct
{
u32 USI_LPUARTOscPerbitUpdCtrl; /*!< Specifies the OSC perbit update control when use xtal 8M.
This parameter can be ENABLE or DISABLE.
ENABLE: osc perbit updates with xtal perbit when use xtal 8M.
DISABLE: osc perbit does't update with xtal perbit when use xtal 8M.
@note This parameter is only used in low power rx path with xtal 8M.
@note osc perbit will update when use osc 8M, even if USI_LPUARTOscPerbitUpdCtrl is disable */
u32 USI_LPUARTBitNumThres; /*!< Specifies the bit number threshold of one monitor period.
This parameter is used to get the average clock cycles of one bit
and can be a number between 0x00 and 0x7f.
@note This parameter is only used in low power rx path. */
} USI_LPUARTInitTypeDef;
/**
* @brief USI UART IRDA Init structure definition
*/
typedef struct
{
u32 USI_UARTIrDARxInv; /*!< Specifies the uart irda rx invert control.
This parameter can be ENABLE or DISABLE.
ENABLE: invert the irda input signal.
DISABLE: does't invert the irda input signal.
@note This parameter is only used in IrDA mode. */
u32 USI_UARTIrDATxInv; /*!< Specifies the uart irda tx invert control.
This parameter can be ENABLE or DISABLE.
ENABLE: invert the irda output signal.
DISABLE: does't invert the irda output signal.
@note This parameter is only used in IrDA mode. */
u32 USI_UARTUpperShift; /*!< Specifies the USI uart irda tx pulse right edge shift direction.
This parameter can be a value of @ref USI_UART_IRDA_PULSE_SHIFT_define. */
u32 USI_UARTUpperShiftVal; /*!< Specifies the USI uart irda tx pulse right edge shift value in the given direction.
This parameter can be a number between 0x0000 and 0x7fff. */
u32 USI_UARTLowShift; /*!< Specifies the USI uart irda tx pulse left edge shift direction.
This parameter can be a value of @ref USI_UART_IRDA_PULSE_SHIFT_define. */
u32 USI_UARTLowShiftVal; /*!< Specifies the USI uart irda tx pulse left edge shift value in the given direction.
This parameter can be a number between 0x0000 and 0x7fff. */
u32 USI_UARTRxFilterThres; /*!< Specifies the USI uart irda rx filter threshold.
This parameter can be a number between 0x0000 and 0x7fff
@note This parameter is only used in IrDA mode. */
u32 USI_UARTRxFilterCmd; /*!< Specifies the USI uart irda rx filter control.
This parameter can be ENABLE or DISABLE.
ENABLE: USI uart IrDA rx filter is used.
DISABLE: USI uart IrDA rx filter is not used.
@note This parameter is only used in IrDA mode. */
}USI_UartIrDAInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup USI_UART_Exported_Constants USI-UART Exported Constants
* @{
*/
/** @defgroup USI_UART_IRDA_PULSE_SHIFT_define
* @{
*/
#define USI_UART_IRDA_PULSE_LEFT_SHIFT ((u32)0x00000000)
#define USI_UART_IRDA_PULSE_RIGHT_SHIFT ((u32)0x00000001)
#define IS_USI_IRDA_PUL_SHIFT(SHIFT) (((SHIFT) == USI_UART_IRDA_PULSE_LEFT_SHIFT) || \
((SHIFT) == USI_UART_IRDA_PULSE_RIGHT_SHIFT))
/**
* @}
*/
/** @defgroup USI_UART_Word_length_define
* @{
*/
#define USI_RUART_WLS_7BITS ((u32)0x00000000)
#define USI_RUART_WLS_8BITS ((u32)0x00000001)
#define IS_USI_UART_WLS(VAL) (((VAL) == USI_RUART_WLS_7BITS) || \
((VAL) == USI_RUART_WLS_8BITS))
/**
* @}
*/
/** @defgroup USI_UART_Stop_Bit_define
* @{
*/
#define USI_RUART_STOP_BIT_1 ((u32)0x00000000)
#define USI_RUART_STOP_BIT_2 ((u32)0x00000002)
#define IS_USI_UART_STOP_BIT(VAL) (((VAL) == USI_RUART_STOP_BIT_1) || \
((VAL) == USI_RUART_STOP_BIT_2))
/**
* @}
*/
/** @defgroup USI_UART_Parity_Enable_define
* @{
*/
#define USI_RUART_PARITY_DISABLE ((u32)0x00000000)
#define USI_RUART_PARITY_ENABLE ((u32)0x00000010)
#define IS_USI_UART_PARITY_ENABLE(VAL) (((VAL) == USI_RUART_PARITY_DISABLE) || \
((VAL) == USI_RUART_PARITY_ENABLE))
/**
* @}
*/
/** @defgroup USI_UART_Parity_Type_define
* @{
*/
#define USI_RUART_ODD_PARITY ((u32)0x00000000)
#define USI_RUART_EVEN_PARITY ((u32)0x00000020)
#define IS_USI_UART_PARITY_TYPE(VAL) (((VAL) == USI_RUART_ODD_PARITY) || \
((VAL) == USI_RUART_EVEN_PARITY))
/**
* @}
*/
/** @defgroup USI_UART_Stick_Parity_Type_define
* @{
*/
#define USI_RUART_STICK_PARITY_DISABLE ((u32)0x00000000)
#define USI_RUART_STICK_PARITY_ENABLE ((u32)0x00000040)
#define IS_USI_UART_STICK_PARITY_ENABLE(VAL) (((VAL) == USI_RUART_STICK_PARITY_DISABLE) || \
((VAL) == USI_RUART_STICK_PARITY_ENABLE))
/**
* @}
*/
/** @defgroup USI_UART_Interrupt_ID_define
* @{
*/
/*TX FIFO (UART, I2C, SPI)*/
#define USI_TX_FIFO_ALMOST_EMPTY_INTER ((u32)0x00000001)
#define USI_TX_FIFO_OVERFLOW_INTER ((u32)0x00000002)
#define USI_TX_FIFO_UNDERFLOW_INTER ((u32)0x00000004) /*USI UART do not have this type interrupt*/
/*RX FIFO (UART, I2C, SPI)*/
#define USI_RX_FIFO_ALMOST_FULL_INTER ((u32)0x00000010)
#define USI_RX_FIFO_OVERFLOW_INTER ((u32)0x00000020)
#define USI_RX_FIFO_UNDERFLOW_INTER ((u32)0x00000040)
/*UART related interrupt*/
#define USI_UART_PARITY_ERROR_INTER ((u32)0x00000100)
#define USI_UART_STOP_ERROR_INTER ((u32)0x00000200)
#define USI_UART_BREAK_INTER ((u32)0x00000400)
#define USI_RX_FIFO_TIMEOUT_INTER ((u32)0x00000800)
#define USI_RX_BAUDMON_DONE_INTER ((u32)0x00001000)
#define USI_TX_CTS_CHANGE_INTER ((u32)0x00002000)
/*JUST FOR USI UART USE*/
#define IS_USI_UART_GET_IT(IT) (((IT) == USI_TX_FIFO_ALMOST_EMPTY_INTER) || \
((IT) == USI_TX_FIFO_OVERFLOW_INTER) || \
((IT) == USI_RX_FIFO_ALMOST_FULL_INTER)|| \
((IT) == USI_RX_FIFO_OVERFLOW_INTER)|| \
((IT) == USI_RX_FIFO_UNDERFLOW_INTER)|| \
((IT) == USI_UART_PARITY_ERROR_INTER)|| \
((IT) == USI_UART_STOP_ERROR_INTER)|| \
((IT) == USI_UART_BREAK_INTER)|| \
((IT) == USI_RX_FIFO_TIMEOUT_INTER)|| \
((IT) == USI_RX_BAUDMON_DONE_INTER)|| \
((IT) == USI_TX_CTS_CHANGE_INTER))
#define IS_USI_UART_IT(IT) ((((IT) & (u32)0xFFFFC08C) == 0x00) && ((IT) != 0x00))
#define IS_USI_UART_CLEAR_IT(IT) ((((IT) & (u32)0xFFFFC89D) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup USI_UART_Rx_DMA_mode_define
* @{
*/
#define USI_UART_RX_UART_IS_DMA_FLOW_CTRL ((u32)0x00000001)
#define USI_UART_RX_GDMA_IS_DMA_FLOW_CTRL ((u32)0x00000000)
#define IS_USI_UART_RX_DMA_MODE(MODE) (((MODE) == USI_UART_RX_UART_IS_DMA_FLOW_CTRL) || \
((MODE) == USI_UART_RX_GDMA_IS_DMA_FLOW_CTRL) )
/**
* @}
*/
/** @defgroup USI_Peripheral_define
* @{
*/
#define IS_ALL_USI_PERIPH(PERIPH) (((PERIPH) == USI0_DEV))
#define IS_ALL_USI_LP_PERIPH(PERIPH) (((PERIPH) == USI0_DEV))
/**
* @}
*/
/** @defgroup USI_UART_SoftWare_Status_define
* @{
*/
#define USI_UART_STATETX_DMA 1
#define USI_UART_STATETX_INT 2
#define USI_UART_STATETX_POLL 3
#define USI_UART_STATERX_DMA 1
#define USI_UART_STATERX_INT 2
#define USI_UART_STATERX_POLL 3
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup USI_UART_Exported_Functions USI-UART Exported Functions
* @{
*/
/** @defgroup USI_UART_Normal_functions
* @{
*/
_LONG_CALL_ void USI_UARTDeInit(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTStructInit(USI_UARTInitTypeDef* USI_UARTInitStruct);
_LONG_CALL_ void USI_UARTInit(USI_TypeDef* USIx, USI_UARTInitTypeDef* USI_UARTInitStruct);
_LONG_CALL_ u32 USI_UARTBaudParaGet(u32 baudrate, u32 *ovsr, u32 *ovsr_adj);
_LONG_CALL_ void USI_UARTBaudParaGetFull(u32 IPclk, u32 baudrate, u32 *ovsr, u32 *ovsr_adj);
_LONG_CALL_ void USI_UARTSetBaudExt(USI_TypeDef* USIx, u32 Ovsr, u32 Ovsr_adj);
_LONG_CALL_ void USI_UARTSetBaud(USI_TypeDef* USIx, u32 BaudRate);
_LONG_CALL_ void USI_UARTSetRxLevel(USI_TypeDef* USIx, u32 FifoLv);
_LONG_CALL_ void USI_UARTRxCmd(USI_TypeDef* USIx, u32 NewState);
_LONG_CALL_ u32 USI_UARTWritable(USI_TypeDef* USIx);
_LONG_CALL_ u32 USI_UARTReadable(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTCharPut(USI_TypeDef* USIx, u8 TxData);
_LONG_CALL_ void USI_UARTCharGet(USI_TypeDef* USIx, u8 *pRxByte);
_LONG_CALL_ void USI_UARTReceiveData(USI_TypeDef* USIx, u8* OutBuf, u32 Count);
_LONG_CALL_ void USI_UARTSendData(USI_TypeDef* USIx, u8* InBuf, u32 Count);
_LONG_CALL_ u32 USI_UARTReceiveDataTO(USI_TypeDef* USIx, u8* OutBuf, u32 Count, u32 Times);
_LONG_CALL_ u32 USI_UARTSendDataTO(USI_TypeDef* USIx,u8* InBuf,u32 Count, u32 Times);
_LONG_CALL_ void USI_UARTRxByteCntClear(USI_TypeDef* USIx);
_LONG_CALL_ u32 USI_UARTRxByteCntGet(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTBreakCtl(USI_TypeDef* USIx, u32 NewState);
_LONG_CALL_ u32 USI_UARTClearRxFifo(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTClearTxFifo(USI_TypeDef* USIx);
_LONG_CALL_ u32 USI_UARTGetRxFifoValidCnt(USI_TypeDef* USIx);
_LONG_CALL_ u32 USI_UARTGetTxFifoEmptyCnt(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTINTConfig(USI_TypeDef* USIx, u32 UART_IT, u32 newState);
_LONG_CALL_ u32 USI_UARTIntStatus(USI_TypeDef* USIx);
_LONG_CALL_ u32 USI_UARTGetRawIntStatus(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTClearAllIntStatus(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTClearIntStatus(USI_TypeDef* USIx, u32 USIUART_IT);
_LONG_CALL_ void USI_UARTWaitBusy(USI_TypeDef* USIx, u32 PollTimes);
_LONG_CALL_ void USI_UARTRxTimeOutConfig(USI_TypeDef* USIx, u32 TimeOutCnt);
_LONG_CALL_ void USI_UARTRxDMAModeConfig(USI_TypeDef* USIx, u32 Mode);
_LONG_CALL_ void USI_UARTRxDMADummyDataConfig(USI_TypeDef* USIx, u8 Byte);
_LONG_CALL_ u32 USI_UARTGetRxDMADummyFlag(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTRxClearDMADummyFlag(USI_TypeDef* USIx);
/**
* @}
*/
/** @defgroup USI_UART_DMA_functions
* @{
*/
_LONG_CALL_ void USI_UARTTXDMAConfig(USI_TypeDef* USIx, u32 TxDmaBurstSize);
_LONG_CALL_ void USI_UARTRXDMAConfig(USI_TypeDef* USIx, u32 RxDmaBurstSize);
_LONG_CALL_ void USI_UARTTXDMACmd(USI_TypeDef* USIx, u32 NewState);
_LONG_CALL_ void USI_UARTRXDMACmd(USI_TypeDef* USIx, u32 NewState);
_LONG_CALL_ BOOL USI_UARTTXGDMA_Init(u8 USIIndex, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pTxBuf, int TxCount);
_LONG_CALL_ BOOL USI_UARTRXGDMA_Init(u8 USIIndex, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pRxBuf, int RxCount);
/**
* @}
*/
/** @defgroup USI_UART_Low_Power_functions
* @{
*/
_LONG_CALL_ void USI_UARTLPRxStructInit(USI_LPUARTInitTypeDef* USI_UARTInitStruct);
_LONG_CALL_ void USI_UARTLPRxInit(USI_TypeDef* USIx, USI_LPUARTInitTypeDef *USI_UARTInitStruct);
_LONG_CALL_ void USI_UARTLPRxBaudSet(USI_TypeDef* USIx, u32 BaudRate, u32 RxIPClockHz);
_LONG_CALL_ void USI_UART_LPRxMonitorCmd(USI_TypeDef* USIx, u32 NewState);
_LONG_CALL_ void USI_UARTLPRxpathSet(USI_TypeDef* USIx, u32 LPRxpath);
_LONG_CALL_ void USI_UARTLPRxIPClockSet(USI_TypeDef* USIx, u32 RxIPClock);
_LONG_CALL_ void USI_UARTLPRxCmd(USI_TypeDef* USIx, u32 NewState);
/**
* @}
*/
/** @defgroup USI_UART_IRDA_functions
* @{
*/
_LONG_CALL_ void USI_UARTIrDAStructInit(USI_UartIrDAInitTypeDef * IrDA_InitStruct);
_LONG_CALL_ void USI_UARTIrDAInit(USI_TypeDef* USIx, USI_UartIrDAInitTypeDef * IrDA_InitStruct);
_LONG_CALL_ void USI_UARTIrDACmd(USI_TypeDef* USIx, u32 NewState);
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
/*----------------USI UART definations---------------*/
typedef struct
{
u32 LOW_POWER_RX_ENABLE; /*Enable low power RX*/
} USI_UARTCFG_TypeDef;
extern USI_UARTCFG_TypeDef usi_uart_config[];
extern u32 USI_UART_StateTx[1];
extern u32 USI_UART_StateRx[1];
static inline void
USI_UART_SetTxFlag(u32 USIIdx, u32 Flag)
{
USI_UART_StateTx[USIIdx] = Flag;
}
static inline void
USI_UART_SetRxFlag(u32 USIIdx, u32 Flag)
{
USI_UART_StateRx[USIIdx] = Flag;
}
static inline u32
USI_UART_GetTxFlag(u32 USIIdx)
{
return (USI_UART_StateTx[USIIdx]);
}
static inline u32
USI_UART_GetRxFlag(u32 USIIdx)
{
return (USI_UART_StateRx[USIIdx]);
}
#endif
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_vector.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the IRQ firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_VECTOR_TABLE_H_
#define _RTL8710B_VECTOR_TABLE_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup IRQ
* @brief IRQ modules
* @{
*/
/** @addtogroup IRQ
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* IRQ table, please refer to IRQ Exported Constants->IRQn_enum->IRQn
*
*****************************************************************************************
* how to use
*****************************************************************************************
* 1. register/unregister IRQ use: InterruptRegister/InterruptUnRegister
* 2. enable/disable IRQ use: InterruptEn/InterruptDis
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup IRQ_Exported_Types IRQ Exported Types
* @{
*/
typedef s32 IRQn_Type;
typedef void (*HAL_VECTOR_FUN) (void);
typedef u32 (*IRQ_FUN)(void *Data);
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IRQ_Exported_Constants IRQ Exported Constants
* @{
*/
/** @defgroup IRQn_enum
* @{
*/
enum IRQn {
/****** Cortex-M4 Processor Exceptions Numbers ********/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/****** RTL8710B Specific Interrupt Numbers ************/
SYSTEM_ON_IRQ = 0, /*!< 0 SYS Interrupt for wakeup from power save */
WDG_IRQ = 1, /*!< 1 Watch dog global insterrupt */
RXI300_IRQ = 2, /*!< 2 RXI300 interrupt */
UART_LOG_IRQ = 3, /*!< 3 log uart intr */
GPIOA_IRQ = 4, /*!< 4 GPIOA portA global interrupt */
RTC_IRQ = 5, /*!< 5 rtc timer interrupt */
I2C0_IRQ = 6, /*!< 6 I2C0 global interrupt */
SPI_FLASH_IRQ = 7, /*!< 7 SPI Flash global interrupt */
GPIOB_IRQ = 8, /*!< 8 GPIOB portA global interrupt */
UARTLP_IRQ = 9, /*!< 9 UART0 global interrupt */
KEYSCAN_IRQ = 10, /*!< 10 KEYSCAN interrupt */
CTOUCH_IRQ = 11, /*!< 11 Cap-Touch interrupt */
BOR2_IRQ = 12, /*!< 12 BOR2 interrupt */
SGPIO_IRQ = 13, /*!< 13 SGPIO interrupt */
IPC_IRQ = 14, /*!< 14 IPC_KM0 interrupt */
ADC_IRQ = 15, /*!< 15 adc interrupt */
QDECODER_IRQ = 16, /*!< 16 Q-DECODER interrupt */
TIMER0_IRQ = 17, /*!< 17 Timer0 global interrupt */
TIMER1_IRQ = 18, /*!< 18 Timer1 global interrupt */
TIMER2_IRQ = 19, /*!< 19 Timer2 global interrupt */
TIMER3_IRQ = 20, /*!< 20 Timer3 global interrupt */
TIMER4_IRQ = 21, /*!< 21 Timer4 global interrupt */
TIMER5_IRQ = 22, /*!< 22 Timer5 global interrupt */
LCDC_IRQ = 23, /*!< 23 LCDC interrupt */
USB_OTG_IRQ = 24, /*!< 24 USOC interrupt */
SDIO_DEVICE_IRQ = 25, /*!< 25 SDIO device global interrupt */
SDIO_HOST_IRQ = 26, /*!< 26 SDIO host global interrupt */
CRYPTO_IRQ = 27, /*!< 27 IPsec global interrupt */
I2S0_PCM0_IRQ = 28, /*!< 28 I2S0 global interrupt */
PWR_DOWN_IRQ = 29, /*!< 29 power down enable interrupt */
ADC_COMP_IRQ = 30, /*!< 30 ADC compare interrupt */
WL_DMA_IRQ = 31, /*!< 31 Wlan Host global interrupt */
WL_PROTOCOL_IRQ = 32, /*!< 32 Wlan Firmware Wlan global interrupt */
PSRAMC_IRQ = 33, /*!< 33 PSRAM controller interrupt */
UART0_IRQ = 34, /*!< 34 UART0 global interrupt */
UART1_IRQ = 35, /*!< 35 UART1 BT UART global interrupt */
SPI0_IRQ = 36, /*!< 36 SPI0 global interrupt for communication spi */
SPI1_IRQ = 37, /*!< 37 SPI1 global interrupt for communication spi */
USI_IRQ = 38, /*!< 38 USI global interrupt */
IR_IRQ = 39, /*!< 39 IR global interrupt */
BT2WL_STS_IRQ = 40, /*!< 40 BT to WL Status Interrupt */
GDMA0_CHANNEL0_IRQ = 41, /*!< 41 GDMA0 channel 0 global interrupt */
GDMA0_CHANNEL1_IRQ = 42, /*!< 42 GDMA0 channel 1 global interrupt */
GDMA0_CHANNEL2_IRQ = 43, /*!< 43 GDMA0 channel 2 global interrupt */
GDMA0_CHANNEL3_IRQ = 44, /*!< 44 GDMA0 channel 3 global interrupt */
GDMA0_CHANNEL4_IRQ = 45, /*!< 45 GDMA0 channel 4 global interrupt */
GDMA0_CHANNEL5_IRQ = 46, /*!< 46 GDMA0 channel 5 global interrupt */
CRYPTO_IRQ_S = 50, /*!< 50 IPsec global interrupt */
RXI300_IRQ_S = 51, /*!< 51 RXI300 interrupt */
GDMA0_CHANNEL0_IRQ_S = 52, /*!< 52 GDMA0 channel 0 global interrupt */
GDMA0_CHANNEL1_IRQ_S = 53, /*!< 53 GDMA0 channel 1 global interrupt */
GDMA0_CHANNEL2_IRQ_S = 54, /*!< 54 GDMA0 channel 2 global interrupt */
GDMA0_CHANNEL3_IRQ_S = 55, /*!< 55 GDMA0 channel 3 global interrupt */
GDMA0_CHANNEL4_IRQ_S = 56, /*!< 56 GDMA0 channel 4 global interrupt */
GDMA0_CHANNEL5_IRQ_S = 57, /*!< 57 GDMA0 channel 5 global interrupt */
};
/**
* @}
*/
/** @defgroup LPIRQn_enum
* @{
*/
enum LPIRQn {
/****** Cortex-M4 Processor Exceptions Numbers ********/
NonMaskableInt_IRQn_LP = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn_LP = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn_LP = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn_LP = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn_LP = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn_LP = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn_LP = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn_LP = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn_LP = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/****** RTL8710B Specific Interrupt Numbers ************/
SYSTEM_ON_IRQ_LP = 0, /*!< 0 SYS Interrupt for wakeup from power save */
WDG_IRQ_LP = 1, /*!< 1 Watch dog global insterrupt */
RXI300_IRQ_LP = 2, /*!< 2 RXI300 interrupt */
UART_LOG_IRQ_LP = 3, /*!< 3 log uart intr */
GPIOA_IRQ_LP = 4, /*!< 4 GPIOA portA global interrupt */
RTC_IRQ_LP = 5, /*!< 5 rtc timer interrupt */
I2C0_IRQ_LP = 6, /*!< 6 I2C0 global interrupt */
SPI_FLASH_IRQ_LP = 7, /*!< 7 SPI Flash global interrupt */
GPIOB_IRQ_LP = 8, /*!< 8 GPIOB portA global interrupt */
UARTLP_IRQ_LP = 9, /*!< 9 UART0 global interrupt */
KEYSCAN_IRQ_LP = 10, /*!< 10 KEYSCAN interrupt */
CTOUCH_IRQ_LP = 11, /*!< 11 Cap-Touch interrupt */
BOR2_IRQ_LP = 12, /*!< 12 BOR2 interrupt */
SGPIO_IRQ_LP = 13, /*!< 13 SGPIO interrupt */
IPC_IRQ_LP = 14, /*!< 14 IPC_KM4 interrupt */
ADC_IRQ_LP = 15, /*!< 15 adc interrupt */
QDECODER_IRQ_LP = 16, /*!< 16 Q-DECODER interrupt */
TIMER0_IRQ_LP = 17, /*!< 17 Timer0 global interrupt */
TIMER1_IRQ_LP = 18, /*!< 18 Timer1 global interrupt */
TIMER2_IRQ_LP = 19, /*!< 19 Timer2 global interrupt */
TIMER3_IRQ_LP = 20, /*!< 20 Timer3 global interrupt */
TIMER4_IRQ_LP = 21, /*!< 21 Timer4 global interrupt */
TIMER5_IRQ_LP = 22, /*!< 22 Timer5 global interrupt */
GDMA0_CHANNEL0_IRQ_LP = 23, /*!< 23 GDMA channel 0 global interrupt */
GDMA0_CHANNEL1_IRQ_LP = 24, /*!< 24 GDMA channel 1 global interrupt */
GDMA0_CHANNEL2_IRQ_LP = 25, /*!< 25 GDMA channel 2 global interrupt */
WIFI_FISR_FESR = 26, /*!< 26 WIFI_FISR_FESR interrupt */
WIFI_FTSR_MAILBOX = 27, /*!< 27 WIFI_FTSR_MAILBOX interrupt */
GDMA0_CHANNEL3_IRQ_LP = 28, /*!< 28 GDMA channel 3 global interrupt */
PWR_DOWN_IRQ_LP = 29, /*!< 29 power down enable interrupt */
ADC_COMP_IRQ_LP = 30, /*!< 30 ADC compare interrupt */
KM4_WAKE_EVENT_IRQ_LP = 31, /*!< 31 KM4 peripherals wakeup CPU event interrupt */
};
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IRQ_Exported_Functions IRQ Exported Functions
* @{
*/
extern _LONG_CALL_ void irq_table_init(u32 StackP);
extern _LONG_CALL_ BOOL irq_register(IRQ_FUN IrqFun, IRQn_Type IrqNum, u32 Data, u32 Priority);
extern _LONG_CALL_ BOOL irq_unregister(IRQn_Type IrqNum);
extern _LONG_CALL_ void irq_enable(IRQn_Type IrqNum);
extern _LONG_CALL_ void irq_disable(IRQn_Type IrqNum);
#define InterruptRegister irq_register_check
#define InterruptUnRegister irq_unregister
#define InterruptEn(a,b) irq_enable(a)
#define InterruptDis(a) irq_disable(a)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
extern IRQ_FUN UserIrqFunTable[];
extern u32 UserIrqDataTable[];
extern HAL_VECTOR_FUN NewVectorTable[];
#if defined (ARM_CORE_CM4)
#define MAX_VECTOR_TABLE_NUM (64+16)
#define MAX_PERIPHERAL_IRQ_NUM 64
#define MAX_IRQ_PRIORITY_VALUE 7
#define IRQ_PRIORITY_SHIFT 1
#else
#define MAX_VECTOR_TABLE_NUM (16+32)
#define MAX_PERIPHERAL_IRQ_NUM 32
#define MAX_IRQ_PRIORITY_VALUE 3
#define IRQ_PRIORITY_SHIFT 2
#endif
#define MSP_RAM_LP 0x0008FFFC
#define VCT_RAM_LP 0x00080000
#define MSP_RAM_HP 0x1007EFFC
#define MSP_RAM_HP_NS 0x10004FFC
static inline BOOL irq_register_check(IRQ_FUN IrqFun, IRQn_Type IrqNum, u32 Data, u32 Priority) {
if(Priority > MAX_IRQ_PRIORITY_VALUE) {
Priority = MAX_IRQ_PRIORITY_VALUE;
}
Priority = (Priority << IRQ_PRIORITY_SHIFT);
return irq_register(IrqFun, IrqNum, Data, Priority);
}
#endif //_RTL8710B_VECTOR_TABLE_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721d_wdg.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the WDG firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_WDG_H_
#define _RTL8721D_WDG_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup WDG
* @brief WDG driver modules
* @{
*/
/** @addtogroup WDG
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* WDG:
* - Base Address: VENDOR_REG_BASE
* - Timer clk: SDM 32k
* - Generates MCU reset or WDG interrupt on expiry of a programmed time period,
* unless the program refreshes the watchdog
* - IRQ: WDG_IRQ
*
*****************************************************************************************
* WDG Register
*****************************************************************************************
* [31] R/W1C Wdt_to Watch dog timer timeout. 1 cycle pulse
* [30] R/W Wdt_mode 1: Reset system, 0: Interrupt CPU
* [29] R/W RSVD
* [28:25] R/W Cnt_limit 0: 0x001
* 1: 0x003
* 2: 0x007
* 3: 0x00F
* 4: 0x01F
* 5: 0x03F
* 6: 0x07F
* 7: 0x0FF
* 8: 0x1FF
* 9: 0x3FF
* 10: 0x7FF
* 11~15: 0xFFF
* [24] W Wdt_clear Write 1 to clear timer
* [23:17] R/W RSVD
* [16] R/W Wdt_en_byte Set 0x1 to enable watch dog timer
* [15:0] R/W BIT_VNDR_divfactor "Dividing factor.Watch dog timer is count with 32.768KHz/(divfactor+1).
* Minimum dividing factor is 1."
*
*****************************************************************************************
* How to use WGD
*****************************************************************************************
* To use WDG peripheral, the following steps are mandatory:
*
* 1. Get count ID and divisor factor according to WDG timeout period using
* WDG_Scalar(WDG_TEST_TIMEOUT, &CountProcess, &DivFacProcess);
*
* 2. Configure WDG with the corresponding configuration.
* WDG_Init(&WDG_InitStruct)
*
* 3. Activate the WDG peripheral:
WDG_Cmd(ENABLE).
*
* @note In interrupt mode, call WDG_IrqInit() function after WDG_Init()
*
* @note WDG_Refresh() function is used to clear timer, if call this function before timeout period,
* then MCU reset or WDG interrupt won't generate
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup WDG_Exported_Types WDG Exported Types
* @{
*/
/**
* @brief WDG Init structure definition
*/
typedef struct
{
u32 CountProcess; /*!< WDG parameter get from WDG_Scalar, Specifies count id of WDG
This parameter must be set to a value in the 0-11 range */
u32 DivFacProcess; /*!< WDG parameter get from WDG_Scalar, Specifies WDG timeout count divisor factor
This parameter must be set to a value in the 1-65535 range */
u32 RstAllPERI; /*!< WDG parameter, Specifies WDG reset all the PERIs in HS or not
This parameter must be set to a value of 0 or 1 */
} WDG_InitTypeDef;
/**
* @}
*/
/** @defgroup WDG_Exported_Functions WDG Exported Functions
* @{
*/
_LONG_CALL_ void WDG_Scalar(u32 Period, u32 *pCountProcess, u32 *pDivFacProcess);
_LONG_CALL_ void WDG_Init(WDG_InitTypeDef *WDG_InitStruct);
_LONG_CALL_ void WDG_IrqInit(void *handler, u32 Id);
_LONG_CALL_ void WDG_Cmd(u32 NewState);
_LONG_CALL_ void WDG_Refresh(void);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup WDG_Register_Definitions WDG Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup WDG_REG
* @{
*****************************************************************************/
#define WDG_BIT_ENABLE ((u32)0x00000001 << 16)
#define WDG_BIT_CLEAR ((u32)0x00000001 << 24)
#define WDG_BIT_RST_MODE ((u32)0x00000001 << 30)
#define WDG_BIT_ISR_CLEAR ((u32)0x00000001 << 31)
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
#endif //_RTL8721D_WDG_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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#ifndef __INC_RTL8711B_WL_ON_H
#define __INC_RTL8711B_WL_ON_H
/* this is a subset of hal_com_reg.h */
/* BIT_WL_PMC_OFFMAC 0x0020 */
#define BIT_WL_PMC_OFFMAC (0x00000001 << 1) /*!< Auto FSM to Turn On, include clock, isolation, power control for MAC only
(auto set by ICFG, and clear when Power Ready) */
#define BIT_WL_APMC_ONMAC (0x00000001 << 0) /*!< Auto FSM to Turn On, include clock, isolation, power control for MAC only */
/* REG_WL_RF_PSS 0x005c */
#define BIT_AFE_POWER_MODE_SEL (0x00000001 << 8) /*!< AFE power mode selection:1: LDO mode 0: Power-cut mode */
#define BIT_SEL_LDO_RF (0x00000001 << 2) /*!< Power source selection1: LDO mode (power source is 3.3V,VD33PAD); 0: Power Cut mode (Power source is 1.2V,VDTR). */
#define BIT_SEL_LDO_SYN (0x00000001 << 1) /*!< Power source selection1: LDO mode (power source is 3.3V,VD33SYN); 0: Power Cut mode (Power source is 1.2V,VDSYN). */
#define BIT_SEL_LDO_BUF (0x00000001 << 0) /*!< Power source selection1: LDO mode (power source is 3.3V,VD33SYN); 0: Power Cut mode (Power source is 1.2V,VDSYN). */
/* REG_USB_INDIRECT_CTRL 0x006c */
#define BIT_USB_HOST_INT_REQ (0x00000001 << 31) /*!< For USB doggle mode, USB Host write this bit to 1 will trigger interrupt to CM4. After CM4 finishes handling this interrupt , CM4 will clear this bit to 0 */
//#define BIT_USB_HOST_INT_TYPE (0x00000001 << 30) /*!< 0: read efuse, 1: write efuse, 2: host cmd */
#define BIT_USB_HOST_CMD (0x0000001F << 24) /*!< host cmd val */
/* REG_USB_SIE_IMR 0x0078 */
#define BIT_EFUSE_RD_MSK_CM4 (0x00000001 << 23) /*!< USB host indirect read efuse interrupt mask for cm4 */
#define BIT_USB_SUS_MSK_CM4 (0x00000001 << 22) /*!< USB suspend interrupt mask for cm4 */
#define BIT_USB_RES_MSK_CM4 (0x00000001 << 21) /*!< USB resume interrupt mask for cm4 */
#define BIT_SE0_RST_MSK_CM4 (0x00000001 << 20) /*!< SE0 reset interrupt mask for cm4 */
#define BIT_SIE_ACK_DONE_MSK_CM4 (0x00000001 << 19) /*!< SIE ACK done interrupt mask for cm4 */
#define BIT_SIE_NAK_DONE_MSK_CM4 (0x00000001 << 18) /*!< SIE NAK done interrupt mask for cm4 */
#define BIT_LPM_RSM_MSK_CM4 (0x00000001 << 17) /*!< SIE resume from LPM interrupt mask for cm4 */
#define BIT_LPM_ACT_MSK_CM4 (0x00000001 << 16) /*!< SIE enter LPM interrupt mask for cm4 */
#define BIT_EFUSE_RD_MSK_DW8051 (0x00000001 << 7) /*!< USB host indirect read efuse interrupt mask for dw8051 */
#define BIT_USB_SUS_MSK_DW8051 (0x00000001 << 6) /*!< USB suspend interrupt mask for dw8051 */
#define BIT_USB_RES_MSK_DW8051 (0x00000001 << 5) /*!< USB resume interrupt mask for dw8051 */
#define BIT_SE0_RST_MSK_DW8051 (0x00000001 << 4) /*!< SE0 reset interrupt mask for dw8051 */
#define BIT_SIE_ACK_DONE_MSK_DW8051 (0x00000001 << 3) /*!< SIE ACK done interrupt mask for dw8051 */
#define BIT_SIE_NAK_DONE_MSK_DW8051 (0x00000001 << 2) /*!< SIE NAK done interrupt mask for dw8051 */
#define BIT_LPM_RSM_MSK_DW8051 (0x00000001 << 1) /*!< SIE resume from LPM interrupt mask for dw8051 */
#define BIT_LPM_ACT_MSK_DW8051 (0x00000001 << 0) /*!< SIE enter LPM interrupt mask for dw8051 */
/* REG_USB_SIE_INT 0x007c */
#define BIT_USB_CMD_INT ((u32)(0x00000001 << 7)) /*!< USB host indirect read/write efuse or host cmd interrupt */
#define BIT_USB_SUS_INT ((u32)(0x00000001 << 6)) /*!< USB suspend interrupt */
#define BIT_USB_RES_INT ((u32)(0x00000001 << 5)) /*!< USB resume interrupt */
#define BIT_SE0_RST_INT ((u32)(0x00000001 << 4)) /*!< SE0 reset interrupt */
#define BIT_SIE_ACK_DONE_INT ((u32)(0x00000001 << 3)) /*!< SIE ACK done interrupt */
#define BIT_SIE_NAK_DONE_INT ((u32)(0x00000001 << 2)) /*!< SIE NAK done interrupt */
#define BIT_LPM_RSM_INT ((u32)(0x00000001 << 1)) /*!< SIE resume from LPM interrupt */
#define BIT_LPM_ACT_INT ((u32)(0x00000001 << 0)) /*!< IE enter LPM interrupt */
/* REG_USB_PWR_OPT 0x0088 */
#define BIT_CM4_WAKE_USB ((u32)(0x00000001 << 6)) /*!< R/W 0 cm4 wakeup usb device, 1: wakeup 0: not wakeup */
#define BIT_HOST_WAKE_DEV_EN ((u32)(0x00000001 << 5)) /*!< R/W 0 usb host wake device function enable, 1: Enable, 0:Disable */
#define BIT_HOST_WAKE_DEV ((u32)(0x00000001 << 4)) /*!< R/W 0 usb host wake device, 1: wake */
#define BIT_USB_LPS_BLOCK ((u32)(0x00000001 << 3)) /*!< R/W 0 Block USB RX for wlan is in LPS, 1: Block RX ; 0: Not block */
#define BIT_USB_LPM_NY ((u32)(0x00000001 << 2)) /*!< R/W 0 USB LPM Not Yet */
#define BIT_USB_SUS_DIS ((u32)(0x00000001 << 1)) /*!< R/W 0 Disable USB enter suspend, 1: Disable, 0: enable */
#define BIT_USB_LPMACT_EN ((u32)(0x00000001 << 0)) /*!< R/W 0 Enable USB enter LPM , 1: Enable, 0: Disable */
/* REG_SYS_CFG_8710B 0xF0 */
#define BIT_USB_DOGGLE_MODE ((u32)(0x00000001 << 1)) /*!< 1: enable usb host access wifi mac, this bit should set by host driver */
#define BIT_MCLK_VLD ((u32)(0x00000001 << 0)) /*!< 1: MAC clock ready flag */
#define REG_WL_PMC_CTRL 0x0020
#define REG_WL_RF_PSS 0x005C /*!< select RF power source: LDO:3.3V, PC: 1.2V*/
#define REG_SYS_CFG_8710B 0x00F0
#define REG_USB_INDIRECT_CTRL 0x006C
#define REG_USB_SIE_IMR 0x0078
#define REG_USB_SIE_INT 0x007c
#define REG_WL_PMC_ISR_8711B 0x0084
#define REG_USB_PWR_OPT 0x0088
#define REG_USB_HOST_RW_DATA 0x009C
#define REG_USB_HOST_RW_ADDR 0x00F8
#endif //__INC_RTL8711B_WL_ON_H

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/**
******************************************************************************
* @file rtl8721dhp_rcc.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for peripheral reset and clock control driver.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_HP_RCC_H_
#define _RTL8721D_HP_RCC_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup RCC
* @brief RCC driver modules
* @{
*/
/** @defgroup HS_RCC
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* - functions prototypes for peripheral reset and clock control driver.
*
*****************************************************************************************
*
*****************************************************************************************
* how to use
*****************************************************************************************
* use UART0 as example:
* RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
*
*****************************************************************************************
* @endverbatim
*/
/** @addtogroup HS_RCC
* @brief HS_RCC driver modules
* @{
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HS_RCC_CLK_Exported_Constants HS_RCC CLK Exported Constants
* @{
*/
#define SYS_CLK_CTRL1 0x03U //0x210
#define SYS_CLK_CTRL2 0x02U
#define SYS_CLK_CTRL3 0x01U
#define SYS_CLK_CTRL4 0x00U
#define APBPeriph_CLOCK_NULL 0 //if you dont want to set any clock, you can use this
#define APBPeriph_PSRAM_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HSYS_PSRAM_CKE | BIT_SHIFT_HSYS_PSRAM_CKSL_100)
#define APBPeriph_AUDIOC_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HSYS_AC_CK)
#define APBPeriph_VENDOR_REG_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_VNDR_CKE)
#define APBPeriph_USI_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_USI_CKE)
#define APBPeriph_IRDA_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_IRDA_CKE)
#define APBPeriph_IPC_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_IPC_CKE)
#define APBPeriph_GTIMER_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_TIMER0_CKE)
#define APBPeriph_SPI1_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_SPI1_CKE)
#define APBPeriph_SPI0_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_SPI0_CKE)
#define APBPeriph_UART1_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_UART1_CKE)
#define APBPeriph_UART0_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_UART0_CKE)
#define APBPeriph_BT_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_BT_CKE)
#define APBPeriph_WL_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_WLAN_CKSL_AXIF | BIT_HSYS_WLAN_CKE_AXIF)
#define APBPeriph_GDMA0_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_GDMA0_CKE)
#define APBPeriph_LCDC_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_LCDC_CKE)
#define APBPeriph_I2S0_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_I2S0_CKE)
#define APBPeriph_SEC_ENG_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_IPSEC_CKE)
#define APBPeriph_LXBUS_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_LX1BUS_CKE)
#define APBPeriph_SPORT_CLOCK (SYS_CLK_CTRL3 << 30 | BIT_HSYS_SPORT_CKE)
#define APBPeriph_OTG_CLOCK (SYS_CLK_CTRL3 << 30 | BIT_HSYS_USBOTG_CKE)
#define APBPeriph_SDIOH_CLOCK (SYS_CLK_CTRL3 << 30 | BIT_HSYS_SDH_CKE_SCLK | BIT_HSYS_SDH_CKE_BCLK)
#define APBPeriph_SDIOD_CLOCK (SYS_CLK_CTRL3 << 30 | BIT_HSYS_SDD_CKE)
/**
* @}
*/
/** @defgroup AON_RCC_CLK_Exported_Constants Exported Constants
* @{
*/
#define APBPeriph_RTC_CLOCK (BIT_AON_RTC_CKE)
#define APBPeriph_CTOUCH_CLOCK (BIT_AON_CTOUCH_CKE)
#define APBPeriph_CK32KGEN_CLOCK (BIT_AON_CK32KGEN_CKE)
#define APBPeriph_KEYSCAN_CLOCK (BIT_AON_KEYSCAN_CKE)
#define APBPeriph_TSF_CLOCK (BIT_AON_TSF_CKE)
/**
* @}
*/
/** @defgroup HS_RCC_FUNC_Exported_Constants HS_RCC FUNC Exported Constants
* @{
*/
#define SYS_FUNC_EN1 0x03U //0x200
#define SYS_FUNC_EN2 0x02U //0x204
#define SYS_FUNC_EN3 0x01U //0x208
#define SYS_FUNC_EN4 0x00U //0x
#define APBPeriph_NULL 0 //if you dont want to set any function, you can use this
#define APBPeriph_PSRAM (SYS_FUNC_EN1 << 30 | BIT_HSYS_PSRAM_FEN)
#define APBPeriph_AUDIOC (SYS_FUNC_EN1 << 30 | BIT_HSYS_AC_FEN)
#define APBPeriph_VENDOR_REG (SYS_FUNC_EN1 << 30 | BIT_HS_VNDR_FEN)
#define APBPeriph_USI_REG (SYS_FUNC_EN1 << 30 | BIT_HS_USI_FEN)
#define APBPeriph_IRDA_REG (SYS_FUNC_EN1 << 30 | BIT_HS_IRDA_FEN)
#define APBPeriph_IPC (SYS_FUNC_EN1 << 30 | BIT_HS_IPC_FEN)
#define APBPeriph_GTIMER (SYS_FUNC_EN1 << 30 | BIT_HS_TIMER0_FEN)
#define APBPeriph_SPI1 (SYS_FUNC_EN1 << 30 | BIT_HS_SPI1_FEN)
#define APBPeriph_SPI0 (SYS_FUNC_EN1 << 30 | BIT_HS_SPI0_FEN)
#define APBPeriph_UART1 (SYS_FUNC_EN1 << 30 | BIT_HS_UART1_FEN_FUN | BIT_HS_UART1_FEN_GLB)
#define APBPeriph_UART0 (SYS_FUNC_EN1 << 30 | BIT_HS_UART0_FEN_FUN | BIT_HS_UART0_FEN_GLB)
#define APBPeriph_BT (SYS_FUNC_EN2 << 30 | BIT_HSYS_BT_FEN)
#define APBPeriph_WL (SYS_FUNC_EN2 << 30 | BIT_HSYS_WLAN_FEN_AXIF)
#define APBPeriph_GDMA0 (SYS_FUNC_EN2 << 30 | BIT_HSYS_GDMA0_FEN)
#define APBPeriph_LCDC (SYS_FUNC_EN2 << 30 | BIT_HSYS_LCDC_FEN)
#define APBPeriph_I2S0 (SYS_FUNC_EN2 << 30 | BIT_HSYS_I2S0_FEN)
#define APBPeriph_SECURITY_ENGINE (SYS_FUNC_EN2 << 30 | BIT_HSYS_IPSEC_FEN)
#define APBPeriph_LXBUS (SYS_FUNC_EN2 << 30 | BIT_HSYS_LX1BUS_FEN)
#define APBPeriph_SPORT (SYS_FUNC_EN3 << 30 | BIT_HSYS_SPORT_FEN)
#define APBPeriph_OTG (SYS_FUNC_EN3 << 30 | BIT_HSYS_USBOTG_FEN)
#define APBPeriph_SDIOH (SYS_FUNC_EN3 << 30 | BIT_HSYS_SDH_FEN_SCKGEN | BIT_HSYS_SDH_FEN)
#define APBPeriph_SDIOD (SYS_FUNC_EN3 << 30 | BIT_HSYS_SDD_FEN_OFF | BIT_HSYS_SDD_FEN_ON)
/**
* @}
*/
/** @defgroup AON_RCC_FUNC_Exported_Constants Exported Constants
* @{
*/
#define APBPeriph_RTC (BIT_AON_RTC_FEN)
#define APBPeriph_CTOUCH (BIT_AON_CTOUCH_FEN)
#define APBPeriph_CK32KGEN (BIT_AON_CK32KGEN_FEN)
#define APBPeriph_KEYSCAN (BIT_AON_KEYSCAN_FEN)
#define APBPeriph_TSF (BIT_AON_TSF_FEN)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HS_RCC_Exported_Functions HS_RCC Exported Functions
* @{
*/
_LONG_CALL_ void RCC_PeriphClockCmd(u32 APBPeriph, u32 APBPeriph_Clock, u8 NewState);
_LONG_CALL_ void RCC_WIFIClockCmd(u8 NewState);
_LONG_CALL_ void RCC_PeriphClockSource_RTC(u32 Xtal);
_LONG_CALL_ void RCC_PeriphClockSource_I2C(UNUSED_WARN_DIS u32 Idx, u32 Source);
_LONG_CALL_ void RCC_PeriphClockSource_QDEC(UNUSED_WARN_DIS u32 Idx, u32 Source);
_LONG_CALL_ void RCC_PeriphClockSource_UART (UART_TypeDef* UARTx, u32 Source);
/**
* @brief Enables or disables the AON APB peripheral clock and function
* @param APBPeriph: specifies the APB peripheral to gates its clock.
* this parameter can be one of @ref AON_RCC_FUNC_Exported_Constants
* @param APBPeriph_Clock: specifies the APB peripheral clock config.
* this parameter can be one of @ref AON_RCC_CLK_Exported_Constants
* @param NewState: new state of the specified peripheral clock.
* This parameter can be: ENABLE or DISABLE.
*/
__STATIC_INLINE void RCC_PeriphClockCmd_AON(u32 APBPeriph, u32 APBPeriph_Clock, u8 NewState)
{
u32 TempVal = 0;
//clock
if (APBPeriph_Clock != APBPeriph_CLOCK_NULL) {
if(NewState == ENABLE)
{
TempVal = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL);
TempVal |= APBPeriph_Clock;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL, TempVal);
} else {
TempVal = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL);
TempVal &= ~APBPeriph_Clock;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL, TempVal);
}
}
if (APBPeriph == APBPeriph_NULL)
return;
//function
if(NewState == ENABLE)
{
TempVal = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL);
TempVal |= APBPeriph;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL, TempVal);
} else {
TempVal = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL);
TempVal &= ~APBPeriph;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL, TempVal);
}
return;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/* Other definations --------------------------------------------------------*/
#endif /* _RTL8721D_HP_RCC_H_ */
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721dhp_sd.h
* @author
* @version V1.0.0
* @date 2018-06-29
* @brief This file contains all the functions prototypes for the SDIOH firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_SDIO_SD_H
#define _RTL8721D_SDIO_SD_H
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @addtogroup SDIOH
* @brief SDIOH driver modules
* @{
*/
/** @addtogroup SDIOH
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* SDIOH:
* - Base Address: SDIOH_BASE
* - IP Clock: 100MHz
* - Support SD Spec. Version 2.0
* - High Voltage SD Memory Card
* – Operating voltage range: 2.7-3.6 V
* - Support 1/4-bit mode SD
* – Bus Speed Mode (using 4 parallel data lines)
* -Default Speed mode: 3.3V signaling, Frequency up to 25 MHz, up to 12.5 MB/sec
* -High Speed mode: 3.3V signaling, Frequency up to 50 MHz, up to 25 MB/sec
* - Support hardware CRC function for SD
*
*****************************************************************************************
* How to use SDIO Host Controller
*****************************************************************************************
* To use the SDIO Host Controller, the following steps are mandatory.
*
* 1. Insert SD card to card slot.
*
* 2. Call SD_Init() function to initialize SDIOH and SD card, in which the following operations are executed:
* (1) Enable SDIOH peripheral clock.
* (2) Configure the SDIOH pinmux.
* (3) Initialize SDIO Host to initial-mode and enable card interrupt.
* (4) If card insert is detected, card identification is started.
* (5) When card identification is successful, card enters into data transfer mode (Default Speed Mode).
* (6) Set SDIOH and card to 4-bit bus width or High Speed mode if needed according to configure parameters.
*
* 3. After initialization, users can call the following functions to read or write blocks.
* SD_RESULT SD_ReadBlocks(u32 sector,u8 *data,u32 count);
* SD_RESULT SD_WriteBlocks(u32 sector,const u8 *data,u32 count);
*
* Note that if users access SD card through FATFS, then the above steps don't need to be implemented manually.
* They are already porting to FATFS low-level driver, and users can call FATFS API directly.
* Details can be found in FATFS example.
*
*****************************************************************************************
* @endverbatim
*/
#define SD 0
#define EMMC 1
#define SDIO SD
/* Exported constants --------------------------------------------------------*/
/** @defgroup SDIOH_Exported_Constants SDIOH Exported Constants
* @{
*/
/** @defgroup SD_Command_Index
* @{
*/
typedef enum
{
SD_CMD_GoIdleSte = 0,
EMMC_CMD_SendOpCond = 1, // CMD only for EMMC
SD_CMD_AllSendCid = 2,
SD_CMD_SendRelAddr = 3,
SD_CMD_SetDsr = 4,
SD_CMD_SwitchFunc = 6,
SD_CMD_SetBusWidth = 6, // ACMD6
SD_CMD_SelDeselCard = 7,
SD_CMD_SendIfCond = 8, // CMD only for SD card
EMMC_CMD_SendExtCsd = 8, // CMD only for EMMC
SD_CMD_SendCsd = 9,
SD_CMD_SendCid = 10,
SD_CMD_VolSwitch = 11, // CMD only for SD card
SD_CMD_StopXsmission = 12,
SD_CMD_SendSts = 13,
SD_CMD_SetBlklen = 16,
SD_CMD_RdSingleBlk = 17,
SD_CMD_RdMulBlk = 18,
SD_CMD_SendTuningBlk = 19, // CMD only for SD card
SD_CMD_SendNumWrBlks = 22, // ACMD22
SD_CMD_SetBlkCnt = 23,
SD_CMD_SetWrBlkEraseCnt = 23, // ACMD23
SD_CMD_WrBlk = 24,
SD_CMD_WrMulBlk = 25,
SD_CMD_ProgCsd = 27,
SD_CMD_EraseBlkSt = 32, // CMD only for SD card
SD_CMD_EraseBlkEd = 33, // CMD only for SD card
EMMC_CMD_EraseAddrSt = 35, // CMD only for EMMC
EMMC_CMD_EraseAddrEd = 36, // CMD only for EMMC
SD_CMD_Erase = 38,
SD_CMD_SdSendOpCond = 41, // ACMD41 cmd only for SD card
SD_CMD_SendScr = 51, // ACMD51 cmd only for SD card
SD_CMD_AppCmd = 55 // CMD only for SD card
} SD_COMMAND;
/**
* @}
*/
/** @defgroup SD_Result
* @{
*/
typedef enum
{
SD_OK = 0,
SD_NODISK,
SD_INSERT,
SD_INITERR,
SD_PROTECTED,
SD_ERROR,
} SD_RESULT;
/**
* @}
*/
/** @defgroup SD_Card_States
* @{
*/
#define SD_CARD_READY 0x00000001
#define SD_CARD_IDENTIFICATION 0x00000002
#define SD_CARD_STANDBY 0x00000003
#define SD_CARD_TRANSFER 0x00000004
#define SD_CARD_SENDING 0x00000005
#define SD_CARD_RECEIVING 0x00000006
#define SD_CARD_PROGRAMMING 0x00000007
#define SD_CARD_DISCONNECTED 0x00000008
#define SD_CARD_ERROR 0x000000FF
/**
* @}
*/
/** @defgroup SD_Specification_Version SD_Specification_Version
* @{
*/
#define SD_SPEC_V101 0
#define SD_SPEC_V110 1
#define SD_SPEC_V200 2
#define SD_SPEC_V300 3
/**
* @}
*/
/** @defgroup SD_Access_Mode SD_Access_Mode
* @{
*/
#define SD_SPEED_DS 0 // 3.3V Function 0
#define SD_SPEED_HS 1 // 3.3V Function 1
#define SD_SPEED_SDR12 2 // 1.8V Function 0
#define SD_SPEED_SDR25 3 // 1.8V Function 1
#define SD_SPEED_SDR50 4 // 1.8V Function 2
#define SD_SPEED_SDR104 5 // 1.8V Function 3
#define SD_SPEED_DDR50 6 // 1.8V Function 4
#define SD_KEEP_CUR_SPEED 15
/**
* @}
*/
/**
* @}
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup SDIOH_Exported_Types SDIOH Exported Types
* @{
*/
/**
* @brief SD card info structure definition
*/
typedef struct {
u8 csd[SDIOH_CSD_LEN]; /*!< Store the card-specific data(CSD) of the current SD card. */
u16 rca; /*!< Store the relative address(RCA) of the current SD card. */
u8 is_sdhc_sdxc; /*!< Specify the current card is SDSC or SDHC/SDXC. */
u8 sd_spec_ver; /*!< Specify the physical layer specification version of current
card, which would be a value of @ref SD_Specification_Version */
u32 capaticy; /*!< Specify the capacity of current card. Unit: KByte */
u32 read_bl_len; /*!< Specify max. read data block length of current card. Unit: byte */
u32 write_bl_len; /*!< Specify max. write data block length. Unit: byte */
u8 sig_level; /*!< Specify current signal level, 0: 3.3v, 1: 1.8v */
u8 bus_spd; /*!< Specify current bus speed, which would be a value of @ref SD_Access_Mode */
SD_RESULT sd_status; /*!< Specify current sd status, which would be a value of @ref SD_Result */
u8 dma_buf[SDIOH_C6R2_BUF_LEN] __attribute__((aligned(32))); /*!< DMA buffer, 32 byte-alignment */
} SD_CardInfo;
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SDIOH_Exported_Functions SDIOH Exported Functions
* @{
*/
/** @defgroup SD_Card_Functions SD Card Functions
* @{
*/
_LONG_CALL_ SD_RESULT SD_Init(void);
_LONG_CALL_ SD_RESULT SD_DeInit(void);
_LONG_CALL_ SD_RESULT SD_GetCapacity(u32* sector_count);
_LONG_CALL_ SD_RESULT SD_ReadBlocks(u32 sector,u8 *data,u32 count);
_LONG_CALL_ SD_RESULT SD_WriteBlocks(u32 sector,const u8 *data,u32 count);
_LONG_CALL_ SD_RESULT SD_Status(void);
_LONG_CALL_ SD_RESULT SD_GetEXTCSD(u8 *pbuf);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#define SD_BLOCK_SIZE 512 //Bytes
/* SDIO_RESP4 */
#define SD_APP_CMD BIT(5)
/* SDIO_RESP0 */
#define SD_ADDRESS_ERROR BIT(6)
#define SD_BLOCK_LEN_ERROR BIT(5)
#define SD_WP_VIOLATION BIT(2)
/* SDXC_Power_Control SDXC_Power_Control used in ACMD41*/
#define SD_POWER_SAVING 0
#define SD_MAX_PERFORM 1
/* SD_Switch_1.8v_Request used in ACMD41 */
#define SD_USE_CUR_VOL 0
#define SD_SWITCH_18V 1
/* SD_operation_mode used in CMD6 */
#define SD_CMD6_CHECK_MODE 0
#define SD_CMD6_SWITCH_MODE 1
/* SD_Capacity_Support in ACMD41 */
#define SD_SUPPORT_SDSC_ONLY 0
#define SD_SUPPORT_SDHC_SDXC 1
typedef struct {
u8 sdioh_bus_speed; /*!< Specify SDIO Host bus speed, should be SD_SPEED_DS or SD_SPEED_HS*/
u8 sdioh_bus_width; /*!< Specify SDIO Host bus width, should be a value of @ref SDIOH_Bus_Width */
u32 sdioh_cd_pin; /*!< Specify Card Detect pin, should be a value of _PB_25/_PA_6/_PNC */
u32 sdioh_wp_pin; /*!< Specify Write Protection pin, should be a value of _PB_25/_PA_6/_PNC */
} SDIOHCFG_TypeDef;
#endif

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#ifndef __INC_RTL8721D_HP_SYS_ON_BIT_H
#define __INC_RTL8721D_HP_SYS_ON_BIT_H
/* REG_HS_PWR_ISO_CTRL 0x0000 */
#define BIT_HSYS_ISO_AUXPLL_PCM BIT(19) /* R/W 1 1: isolation signal from PCM 45.1584MHz PLL When this PLL is power off; 0: release isolation */
#define BIT_HSYS_ISO_AUXPLL_I2S BIT(18) /* R/W 1 1: isolation signal from I2S 98.304MHz PLL When this PLL is power off; 0: release isolation */
#define BIT_HSYS_ISO_BT_EN BIT(16) /* R/W 1 1: isolation signal from BT When BT is power off; 0: release isolation */
#define BIT_HSYS_PWC_BT_EN_BIT1 BIT(1) /* R/W 0 "2'b11: Enable BT power cut 2'b00: Disable. Note: When enable this power cut, bit0 should be set to 1'b1 first, then delay 100us set bit1 to 1'b1" */
#define BIT_HSYS_PWC_BT_EN_BIT0 BIT(0)
/* REG_HS_PLATFORM_PARA 0x000C */
#define BIT_HSYS_PLFM_WDTRST_OPT BIT(23) /* R/W 0 HS watchdog reset option, 0: watchdog reset hs platform only, 1: reset hs/ls/spic platform */
#define BIT_HSYS_GDMA_CLK_ALWAYS_DISABLE BIT(22) /* R/W 0 Disable dmac clk all the time. if clk_always_enable=0 and clk_always_disable=1, the whole dmac¡¯s clk will be shut down to save power. */
#define BIT_HSYS_GDMA_CLK_ALWAYS_ENABLE BIT(21) /* R/W 0 "Enable dmac clk all the time. It has the highest priority. If clk_always_enable=0 and clk_always_disable=0, dmac can shut any channel¡¯s clk when this channel has no job to save power. If clk_always_enable=1, all the channel¡¯s clk will be valid." */
#define BIT_HSYS_PSRAM_SPDUPSIM BIT(20) /* R/W 0 */
#define BIT_HSYS_PLFM_AUTO_ICG_EN BIT(19) /* R/W 0 1: Enable HS platform auto clock gating for power saving */
#define BIT_HSYS_SHARE_BT_MEM BIT(18) /* R/W 0 1: Enable KM4 to share BT memory */
#define BIT_HSYS_SHARE_WL_MEM BIT(17) /* R/W 0 1: Enable KM4 to share WL memory */
#define BIT_KM4_RETENTION_MODE BIT(16) /* R/W 0 "1: enable, when KM4 reset, Cache will not be clear 0: Disable, when KM4 reset, Cache will be clear by HW" */
#define BIT_KM4_DBGRESTARTED_STATUS BIT(3) /* R 0 BIT_KM4_DBGRESTARTED_STATUS KM4 debug restart status */
#define BIT_KM4_HALTED_STATUS BIT(2) /* R 0 KM4 halt status */
#define BIT_KM4_LOCKUP_STATUS BIT(1) /* R 0 KM4 lockup status */
#define BIT_KM4_SLEEP_STATUS BIT(0) /* R 0 KM4 sleep status used for __WFE, tm_sl_sleepsys_r */
/* #define REG_HS_RFAFE_IND_VIO1833 0x0020 */
#define BIT_RFAFE_IND_VIO1833 BIT(0) /* R/W 0 "RFAFE voltage indication: 0: 1.8v 1: 3.3v" */
/* REG_HS_PLL_I2S_CTRL0 0x0080 */
#define BIT_PLL_I2S_POWCUT_EN BIT(31) /* R/W 0 erc enable. */
#define BIT_PLL_I2S_DIV_EN BIT(30) /* R/W 0 input divider enable (need pwl signal) 0->1 */
#define BIT_PLL_I2S_EN BIT(29) /* R/W 0 (need pwl signal) 0->1 */
#define BIT_PLL_SHIFT_I2S_CPC_SEL 26 /* R/W 000 "charge pump current selection . Default=5u CP current select : 000: Icp=5uA, 001: Icp=10uA, 010: Icp=15uA, 011: Icp=20uA; 100:Icp=25uA, 101: Icp=30uA, 110: Icp=35uA, 111: Icp=40uA; " */
#define BIT_PLL_MASK_I2S_CPC_SEL 0x07 /* R/W 000 "charge pump current selection . Default=5u CP current select : 000: Icp=5uA, 001: Icp=10uA, 010: Icp=15uA, 011: Icp=20uA; 100:Icp=25uA, 101: Icp=30uA, 110: Icp=35uA, 111: Icp=40uA; " */
#define BIT_PLL_I2S_WDG_EN BIT(25) /* R/W 1 0: watch dog on ,1: watch dog off */
#define BIT_PLL_SHIFT_I2SS_PS_SEL 22
#define BIT_PLL_MASK_I2SS_PS_SEL 0x07 /* R/W 000 */
#define BIT_PLL_SHIFT_I2S_CP_SEL 20
#define BIT_PLL_MASK_I2S_CP_SEL 0x03 /* R/W 00 "Cp selection. Default=3p 00: Cp=3p, 01: Cp=4p, 10: Cp=5p, 11: Cp=6p" */
#define BIT_PLL_SHIFT_I2S_RS_SEL 17
#define BIT_PLL_MASK_I2S_RS_SEL 0x07 /* R/W 110 "Rs selection. Default=14k 000: Rs=2k, 001: Rs=4k, 010: Rs=6k, 011: Rs=8k, 100: Rs=10k, 101: Rs=12k, 110: Rs=14k, 111: Rs=16k; " */
#define BIT_PLL_SHIFT_I2S_CS_SEL 15
#define BIT_PLL_MASK_I2S_CS_SEL 0x03 /* R/W 10 "Cs selection. Default=50p 00: Cs=30p, 01: Cs=40p, 10: Cs=50p, 11: Cs=60p" */
#define BIT_PLL_SHIFT_I2S_R3_SEL 12
#define BIT_PLL_MASK_I2S_R3_SEL 0x07 /* R/W 010 "R3 selection. Default=1k 000: R3=0k, 001: R3=0.5k, 010: R3=1k, 011: R3=1.5k, 100: R3=2k, 101: R3=2.5k, 110: R3=3k, 111: R3=3.5k; " */
#define BIT_PLL_SHIFT_I2S_C3_SET 10
#define BIT_PLL_MASK_I2S_C3_SET 0x03 /* R/W 10 "Cp selection. Default=5p 00: Cp=3p, 01: Cp=4p, 10: Cp=5p, 11: Cp=6p" */
#define BIT_PLL_I2S_FREF_EDGE_SEL BIT(9) /* R/W 1 0:fref,1:frefb */
#define BIT_PLL_I2S_CLK_EN BIT(8) /* R/W 0 output clk enable */
#define BIT_PLL_I2S_DIV2_EN BIT(7) /* R/W 0 output clk div 2 enable */
#define BIT_PLL_I2S_PS_EN BIT(6) /* R/W 0 phase selector enable */
#define BIT_PLL_SHIFT_I2S_DIV_SEL 3
#define BIT_PLL_MASK_I2S_DIV_SEL 0x07 /* R/W 110 output divider selection. Default=000, 000=/1, 100=/4, 110=/8, 111=/16 */
/* REG_HS_PLL_I2S_CTRL1 0x0084 */
#define BIT_PLL_SHIFT_I2S_XTAL_SEL 28
#define BIT_PLL_MASK_I2S_XTAL_SEL 0x0F /* R/W 0 "xtal selection, Default=40MHz 0000: 40MHz, 0001: 25MHz,0010: 13MHz, 0011: 19.2MHz0100: 20MHz, 0101: 26MHz,0110: 38.4MHz, 0111: 17.664MHz1000: 16MHz, 1001: 14.138MHz1010: 12MHz, 1011: 52MHz1100: 48MHz, 1101: 27MHz,1110: 24MHz, 1111: none " */
#define BIT_PLL_SHIFT_I2S_FREQ_SEL 24
#define BIT_PLL_MASK_I2S_FREQ_SEL 0x0F /* R/W 0101 output clk selection, Default=98.304MHz/24.576MHz */
#define BIT_PLL_SHIFT_I2S_TBASE_FREQ_SEL 20
#define BIT_PLL_MASK_I2S_TBASE_FREQ_SEL 0x0F /* R/W 1000 for output clk step up or step down */
#define BIT_PLL_SHIFT_I2S_STEP_FREQ_SEL 16
#define BIT_PLL_MASK_I2S_STEP_FREQ_SEL 0x0F /* R/W 0101 step size selection for switching freq. */
#define BIT_PLL_I2S_TRIG_RREQ_EN BIT(15) /* R/W 0 freq. step up or step down enable */
#define BIT_PLL_SHIFT_I2S_BB_DBG_SEL_AFE_SDM 11
#define BIT_PLL_MASK_I2S_BB_DBG_SEL_AFE_SDM 0x0F /* R/W 0 */
#define BIT_PLL_SHIFT_I2S_DIVN_SDM 5
#define BIT_PLL_MASK_I2S_DIVN_SDM 0x3F /* R/W 011100 */
#define BIT_PLL_I2S_POW_SDM_FCODE BIT(0)
/* REG_HS_PLL_I2S_CTRL2 0x0088 */
#define BIT_PLL_SHIFT_I2S_SSC_STEP_SEL 19
#define BIT_PLL_MASK_I2S_SSC_STEP_SEL 0x1FFF /* R/W 0 ssc step size selection. */
#define BIT_PLL_SHIFT_I2S_SSC_FREQ_SEL 6
#define BIT_PLL_MASK_I2S_SSC_FREQ_SEL 0x1FFF /* R/W 0 ssc freq selection */
#define BIT_PLL_I2S_SSC_EN BIT(5) /* R/W 0 ssc enable. Default=0 */
/* REG_HS_PLL_I2S_CTRL3 0x008C */
#define BIT_PLL_SHIFT_I2S_SDM_FOF 19
#define BIT_PLL_MASK_I2S_SDM_FOF 0x1FFF /* R/W 0 F code, feedback divider number 1for 1/8*1/2^13 */
#define BIT_PLL_SHIFT_I2S_SDM_FON 16
#define BIT_PLL_MASK_I2S_SDM_FON 0x07 /* R/W 0 N code, feedback divider number 1 for 1/8 */
#define BIT_PLL_I2S_SDM_ORDER_SEL BIT(15) /* R/W 0 SDM order: 0:2nd order, 1:3rd order */
/* REG_HS_PLL_PCM_CTRL0 0x0090 */
#define BIT_PLL_PCM_POWCUT_EN BIT(31)
#define BIT_PLL_PCM_DIV_EN BIT(30)
#define BIT_PLL_PCM_EN BIT(29)
#define BIT_PLL_PCM_CLK_EN BIT(8)
#define BIT_PLL_PCM_DIV2_EN BIT(7)
/* REG_HS_PLL_PCM_CTRL1 0x0094 */
#define BIT_PLL_PCM_TRIG_RREQ_EN BIT(15) /* R/W 0 freq. step up or step down enable */
#define BIT_PLL_SHIFT_PCM_DIVN_SDM 5
#define BIT_PLL_MASK_PCM_DIVN_SDM 0x3F /* R/W 011100 */
#define BIT_PLL_PCM_POW_SDM_FCODE BIT(0)
/* REG_HS_PLL_PCM_CTRL3 0x009C */
#define BIT_PLL_SHIFT_PCM_SDM_FOF 19
#define BIT_PLL_MASK_PCM_SDM_FOF 0x1FFF /* R/W 0 F code, feedback divider number 1for 1/8*1/2^13 */
#define BIT_PLL_SHIFT_PCM_SDM_FON 16
#define BIT_PLL_MASK_PCM_SDM_FON 0x07 /* R/W 0 N code, feedback divider number 1 for 1/8 */
/* REG_HS_PLL_TEST 0x00A0 */
#define BIT_PLL_PCM_RDY BIT(30) /* PCM PLL ready(45.1584MHz) */
#define BIT_PLL_I2S_RDY BIT(29) /* I2S PLL ready(98.304MHz) */
/*REG_HS_WAKE_EVENT_MSK0 0x120*/
#define BIT_HS_WEVT_BT_MSK BIT(24) /* [24] R/W "1: enable BT Wakeup event; 0: disable TIMER wakeup event" */
#define BIT_HS_WEVT_UART_MSK BIT(20) /* [20] R/W "1: enable UART Wakeup event; 0: disable UART wakeup event" */
#define BIT_HS_WEVT_USB_MSK BIT(16) /* [16] R/W "1: enable USB Wakeup event; 0: disable UART wakeup event" */
#define BIT_HS_WEVT_SDIO_MSK BIT(14) /* [14] R/W "1: enable SDIO Wakeup event; 0: disable UART wakeup event" */
#define BIT_HS_WEVT_TIMER_MSK BIT(1) /* [1] R/W "1: enable TIMER Wakeup event; 0: disable TIMER wakeup event" */
/*REG_HS_WAKE_EVENT_STATUS0 0x124*/
#define BIT_HS_WEVT_BT_STATUS BIT(24) /* [24] R/W "1: indicate BT Wakeup event" */
#define BIT_HS_WEVT_UART_STATUS BIT(20) /* [20] R/W "1: indicate UART Wakeup event" */
#define BIT_HS_WEVT_USB_STATUS BIT(16) /* [16] R/W "1: indicate USB Wakeup event" */
#define BIT_HS_WEVT_SDIO_STATUS BIT(14) /* [14] R/W "1: indicate SDIO Wakeup event" */
#define BIT_HS_WEVT_TIMER_STATUS BIT(1) /* [1] R/W "1: indicate TIMER Wakeup event" */
/* REG_HS_WAKE_EVENT_STATUS0 SW define register 0x012C */
#define BIT_HP_WEVT_MISC_STS BIT(7) /* [7] R/W 0 1: Indicate MISC Wakeup event */
#define BIT_HP_WEVT_CAPTOUCH_STS BIT(6) /* [6] R/W 0 1: Indicate captouch Wakeup event */
#define BIT_HP_WEVT_KEYSCAN_STS BIT(5) /* [5] R/W 0 1: Indicate keyscan Wakeup event */
#define BIT_HP_WEVT_RTC_STS BIT(4) /* [4] R/W 0 1: Indicate RTC Wakeup event */
#define BIT_HP_WEVT_UART_STS BIT(3) /* [3] R/W 0 1: Indicate UART Wakeup event */
#define BIT_HP_WEVT_WLAN_STS BIT(2) /* [2] R/W 0 1: Indicate WLAN Wakeup event */
#define BIT_HP_WEVT_GPIO_STS BIT(1) /* [1] R/W 0 1: Indicate GPIO Wakeup event */
#define BIT_HP_WEVT_TIMER_STS BIT(0) /* [0] R/W 0 1: Indicate Timer Wakeup event; */
/* REG_HS_PERI_FUNC_CTRL1 0x0200 */
#define BIT_HSYS_PSRAM_FEN BIT(26)
#define BIT_HSYS_AC_FEN BIT(24)
#define BIT_HS_VNDR_FEN BIT(20)
#define BIT_HS_USI_FEN BIT(19)
#define BIT_HS_IRDA_FEN BIT(18)
#define BIT_HS_IPC_FEN BIT(17)
#define BIT_HS_TIMER0_FEN BIT(16)
#define BIT_HS_SPI1_FEN BIT(9)
#define BIT_HS_SPI0_FEN BIT(8)
#define BIT_HS_UART1_FEN_FUN BIT(3)
#define BIT_HS_UART1_FEN_GLB BIT(2)
#define BIT_HS_UART0_FEN_FUN BIT(1)
#define BIT_HS_UART0_FEN_GLB BIT(0)
/* REG_HS_PERI_FUNC_CTRL2 0x0204 */
#define BIT_HSYS_BT_FEN BIT(24)
#define BIT_HSYS_WLAN_FEN_AXIF BIT(16)
#define BIT_HSYS_GDMA0_FEN BIT(9)
#define BIT_HSYS_LCDC_FEN BIT(8)
#define BIT_HSYS_I2S0_FEN BIT(2)
#define BIT_HSYS_IPSEC_FEN BIT(1)
#define BIT_HSYS_LX1BUS_FEN BIT(0)
/* REG_HS_PERI_FUNC_CTRL3 0x0208 */
#define BIT_HSYS_SPORT_FEN BIT(19)
#define BIT_HSYS_USBOTG_FEN BIT(16)
#define BIT_HSYS_SDH_FEN_SCKGEN BIT(9)
#define BIT_HSYS_SDH_FEN BIT(8)
#define BIT_HSYS_SDD_FEN_OFF BIT(1)
#define BIT_HSYS_SDD_FEN_ON BIT(0)
/* REG_HS_PERI_CLK_CTRL1 0x0210 */
#define BIT_MASK_HSYS_PSRAM_CKSL 0x03 /* [28:27] R/W 0 "PSRAM PHY Clock sel2'b00: 100MHz2'b01: 133.3MHz2'b10/2'b11: 200MHz" */
#define BIT_SHIFT_HSYS_PSRAM_CKSL 27
#define BIT_SHIFT_HSYS_PSRAM_CKSL_100 (0 << BIT_SHIFT_HSYS_PSRAM_CKSL)
#define BIT_SHIFT_HSYS_PSRAM_CKSL_133 (1 << BIT_SHIFT_HSYS_PSRAM_CKSL)
#define BIT_SHIFT_HSYS_PSRAM_CKSL_200 (3 << BIT_SHIFT_HSYS_PSRAM_CKSL)
#define BIT_HSYS_PSRAM_CKE BIT(26)
#define BIT_HSYS_AC_CK BIT(24)
#define BIT_HS_VNDR_CKE BIT(20)
#define BIT_HS_USI_CKE BIT(19)
#define BIT_HS_IRDA_CKE BIT(18)
#define BIT_HS_IPC_CKE BIT(17)
#define BIT_HS_TIMER0_CKE BIT(16)
#define BIT_HS_SPI1_CKE BIT(9)
#define BIT_HS_SPI0_CKE BIT(8)
#define BIT_SHIFT_HSUART0_SCLK_SEL 4
#define BIT_MASK_HSUART0_SCLK_SEL 0x03 /* [5:4] lp uart1 rx clock, 00: xtal; 01: osc 2m; 10: xtal 2M */
#define BIT_HS_UART1_CKE BIT(2)
#define BIT_HS_UART0_CKE BIT(0)
/* REG_HS_PERI_CLK_CTRL2 0x0214 */
#define BIT_HSYS_BT_CKE BIT(24)
#define BIT_HSYS_WLAN_CKSL_AXIF BIT(17) /* "WLAN AXI DAM clock sel0: 50MHz1: 100MHz" */
#define BIT_HSYS_WLAN_CKE_AXIF BIT(16)
#define BIT_HSYS_GDMA0_CKE BIT(9)
#define BIT_HSYS_LCDC_CKE BIT(8)
#define BIT_HSYS_I2S0_CKE BIT(2)
#define BIT_HSYS_IPSEC_CKE BIT(1)
#define BIT_HSYS_LX1BUS_CKE BIT(0)
/* REG_HS_PERI_CLK_CTRL3 0x0218 */
#define BIT_MASK_HSYS_AC_SPORT_CKSL 0x03 /* R/W 0 BIT_HSYS_AC_SPORT_CKSL "Audio Codec sport clock selection:2'b00: Divided clock from 98.304MHz PLL2'b01: Divided clock from 45.1584MHz PLL2'b10/2'b11: 40M clock " */
#define BIT_SHIFT_HSYS_AC_SPORT_CKSL 28
#define BIT_MASK_HSYS_I2S_CLKDIV 0x7f
#define BIT_SHIFT_HSYS_I2S_CLKDIV 20
#define BIT_HSYS_SPORT_CKE BIT(19)
#define BIT_HSYS_USBOTG_CKE BIT(16)
#define BIT_MASK_HSYS_SDH_SCK2_PHSEL 0x07 /* [15:13] R/W 0 */
#define BIT_SHIFT_HSYS_SDH_SCK2_PHSEL 13
#define BIT_MASK_HSYS_SDH_SCK1_PHSEL 0x07 /* [12:10] R/W 0 */
#define BIT_SHIFT_HSYS_SDH_SCK1_PHSEL 10
#define BIT_HSYS_SDH_CKE_SCLK BIT(9)
#define BIT_HSYS_SDH_CKE_BCLK BIT(8)
#define BIT_HSYS_SDD_CKE BIT(0)
/* REG_HS_BT_CTRL 0x0228 */
#define BIT_HSYS_BT_I2C_TEST_EN BIT(1) /* R/W 0 1: Enable I2C for BT TEST */
#define BIT_HSYS_HOST_WAKE_BT BIT(0) /* R/W 0 1: Host wake BT request */
/* #define REG_HS_WL_CTRL 0x0240 */
#define BIT_HS_WLAFE_POD33 BIT(24) /* R/W 0 0: power down 33 WLAFE */
/* #define REG_HS_OTG_CTRL 0x0244 */
#define BIT_HS_USB2_DIGOTGPADEN BIT(28) /* R/W 1 1: Enable USB OTG PAD shared as GPIO */
#define BIT_HS_USB_OTGMODE BIT(27) /* R/W 0 */
#define BIT_HS_USB2_DIGPADEN BIT(26) /* R/W 1 1: Enable USB analog PAD shared as GPIO */
#define BIT_HS_ISO_USBA_EN BIT(25) /* R/W 1 1: enable usb analogy isolation */
#define BIT_HS_ISO_USBD_EN BIT(24) /* R/W 1 1: enable usb digital isolation */
#define BIT_HS_USBA_LDO_EN BIT(23) /* R/W 0 1: enable USB APHY LDO */
#define BIT_USB_IBX2USB_EN BIT(21) /* R/W 0 1: enable IBX to USB*/
#define BIT_USB_PDN33 BIT(20) /* R/W 1 1: power down USB (LDOIO power down share it) */
#define BIT_HS_UABG_EN BIT(19) /* R/W 0 1. Enable bandgap */
#define BIT_HS_UAHV_EN BIT(18) /* R/W 0 1: USB PHY analog 3.3V power cut enable */
#define BIT_HS_UALV_EN BIT(17) /* R/W 0 1: Enable USB APHY function */
#define BIT_HS_USBD_EN BIT(16) /* R/W 0 1: Enable USB digital power */
#define BIT_HS_OTG_CLK_EN BIT(4) /* R/W 0 1: Enable OTG clock */
/* REG_HS_SDIO_CTRL 0x248 */
#define BIT_HS_SDIOH_PIN_EN BIT(28) /* R/W 0 SDIO Host Mode PINMUX enable */
#define BIT_HS_SDIOD_PIN_EN BIT(5) /* R/W 0 SDIO Device Mode PINMUX enable (GPIOB_0~5) */
#define BIT_HS_SDIOH_CLK_READY BIT(24)
/* REG_HS_SPI_CTRL 0x268*/
#define BIT_HS_SPI1_ROLE_SEL BIT(11) /* R/W 0 1: master; 0: slave */
#define BIT_HS_SPI0_ROLE_SELECT BIT(3) /* R/W 0 1: master; 0: slave */
/* REG_HS_MEM_CTRL0 0x300*/
#define BIT_HSYS_SNPS_DPRAM_TEST1 BIT(22) /* R/W 0 Vendor Dual-port Memory parameter: TEST1 */
#define BIT_HSYS_SNPS_DPRAM_LS BIT(21) /* R/W 0 "Vendor Dual-port Memory light-sleep enable, 1: enable light-sleep 0: Disable" */
#define BIT_HSYS_SNPS_DPRAM_RME BIT(20) /* R/W 0 Vendor Dual-port Memory parameter */
#define BIT_HSYS_SHIFT_SNPS_DPRAM_RM 16
#define BIT_HSYS_MASK_SNPS_DPRAM_RM 0x0F /* R/W 0000 Vendor Dual-port Memory parameter */
#define BIT_HSYS_SHIFT_SNPS_SPRAM_RA 14
#define BIT_HSYS_MASK_SNPS_SPRAM_RA 0x03 /* R/W 00 Vendor single-port Memory parameter */
#define BIT_HSYS_SHIFT_SNPS_SPRAM_WA 11
#define BIT_HSYS_MASK_SNPS_SPRAM_WA 0x07 /* R/W 100 Vendor single-port Memory parameter */
#define BIT_HSYS_SHIFT_SNPS_SPRAM_WPS 8
#define BIT_HSYS_MASK_SNPS_SPRAM_WPS 0x07 /* R/W 0 Vendor single-port Memory parameter */
#define BIT_HSYS_SNPS_SPRAM_TEST1 BIT(6) /* R/W 0 Vendor single-port Memory parameter: TEST1 */
#define BIT_HSYS_SNPS_SPRAM_RME BIT(4) /* R/W 1 Vendor single-port Memory parameter */
#define BIT_HSYS_SHIFT_SNPS_SPRAM_RM 0
#define BIT_HSYS_MASK_SNPS_SPRAM_RM 0x0F /* R/W 0011 Vendor single-port Memory parameter */
/* REG_HS_MEM_CTRL1 0x304*/
#define BIT_HSYS_SNPS_ROM_TEST1 BIT(30) /* R/W 0 Vendor ROM parameter: TEST1 */
#define BIT_HSYS_SNPS_ROM_LS BIT(29) /* R/W 0 "Vendor ROM parameter: LS (light-sleep) 1: Enable ROM light-sleep 0: Disable" */
#define BIT_HSYS_SNPS_ROM_RME BIT(28) /* R/W 1 Vendor ROM parameter */
#define BIT_HSYS_SHIFT_SNPS_ROM_RM 24
#define BIT_HSYS_MASK_SNPS_ROM_RM 0x0F /* R/W 0011 Vendor ROM parameter */
#define BIT_HSYS_SHIFT_RTK_MEM_RM 16
#define BIT_HSYS_MASK_RTK_MEM_RM 0x0F /* R/W 1000 In-house Memory parameter */
#define BIT_HSYS_SHIFT_RTK_MEM_RA 12
#define BIT_HSYS_MASK_RTK_MEM_RA 0x03 /* R/W 00 In-house Memory parameter */
#define BIT_HSYS_SHIFT_RTK_MEM_WA 9
#define BIT_HSYS_MASK_RTK_MEM_WA 0x07 /* R/W 010 In-house Memory parameter */
#define BIT_HSYS_RTK_MEM_WAE BIT(8) /* R/W 0 In-house Memory parameter */
#define BIT_HSYS_SHIFT_RTK_MEM_SAW 4
#define BIT_HSYS_MASK_RTK_MEM_SAW 0x03 /* R/W 11 In-house Memory parameter */
#define BIT_HSYS_SHIFT_RTK_MEM_WM 0
#define BIT_HSYS_MASK_RTK_MEM_WM 0x0F /* R/W 1000 In-house Memory parameter */
/* REG_HS_MEM_CTRL2 0x308 */
#define BIT_HSYS_RFC_MEM_LS BIT(31) /* R/W 0 1: Enable RFC memory enter into light-sleep mode 0: Disable */
#define BIT_HSYS_RFC_MEM_DS BIT(30) /* R/W 0 1: Enable RFC memory enter into deep-sleep mode 0: Disable */
#define BIT_HSYS_RFC_MEM_SD BIT(29) /* R/W 0 1: Shut-down RFC memory 0: Power on RFC memory */
#define BIT_HSYS_IDCACHE_LS BIT(28) /* R/W 0 1: Enable ICACHE/DCACHE enter light-sleep mode 0: Disable */
#define BIT_HSYS_WL_SHARE_MEM_LS BIT(26) /* R/W 0 1: Enable WL shared memory enter into light-sleep mode, only valid when WL memory shared as KM4 RAM 0: Disable */
#define BIT_HSYS_WL_SHARE_MEM_DS BIT(25) /* R/W 0 1: Enable WL shared memory enter into deep-sleep mode, only valid when WL memory shared as KM4 RAM 0: Disable */
#define BIT_HSYS_WL_SHARE_MEM_SD BIT(24) /* R/W 0 1: Shut-down WL shared memory, only valid when WL memory shared as KM4 RAM 0: Power on WL shared memory, only valid when WL memory shared as KM4 RAM */
#define BIT_HSYS_BT_SHARE_MEM_LS BIT(22) /* R/W 0 1: Enable BT shared memory enter into light-sleep mode, only valid when BT memory shared as KM4 RAM 0: Disable */
#define BIT_HSYS_BT_SHARE_MEM_DS BIT(21) /* R/W 0 1: Enable BT shared memory enter into deep-sleep mode, only valid when BT memory shared as KM4 RAM 0: Disable */
#define BIT_HSYS_BT_SHARE_MEM_SD BIT(20) /* R/W 0 1: Shut-down BT shared memory, only valid when BT memory shared as KM4 RAM 0: Power on BT shared memory, only valid when BT memory shared as KM4 RAM */
#define BIT_HSYS_K4RAM2_LS BIT(18) /* R/W 0 1: Enable KM4 RAM2 enter into light-sleep mode 0: Disable */
#define BIT_HSYS_K4RAM2_DS BIT(17) /* R/W 0 1: Enable KM4 RAM2 enter into deep-sleep mode 0: Disable */
#define BIT_HSYS_K4RMA2_SD BIT(16) /* R/W 0 1: Shut-down KM4 RAM2 0: Power on KM4 RAM2 */
#define BIT_HSYS_K4RAM1_LS BIT(14) /* R/W 0 1: Enable KM4 RAM1 enter into light-sleep mode 0: Disable */
#define BIT_HSYS_K4RAM1_DS BIT(13) /* R/W 0 1: Enable KM4 RAM1 enter into deep-sleep mode 0: Disable */
#define BIT_HSYS_K4RMA1_SD BIT(12) /* R/W 0 1: Shut-down KM4 RAM1 0: Power on KM4 RAM1 */
#define BIT_HSYS_K4RAM0_LS BIT(10) /* R/W 0 1: Enable KM4 RAM0 enter into light-sleep mode 0: Disable */
#define BIT_HSYS_K4RAM0_DS BIT(9) /* R/W 0 1: Enable KM4 RAM0 enter into deep-sleep mode 0: Disable */
#define BIT_HSYS_K4RMA0_SD BIT(8) /* R/W 0 1: Shut-down KM4 RAM0 0: Power on KM4 RAM0 */
#define BIT_HSYS_PERI_MEM_LS BIT(6) /* R/W 0 1: Enable Peripheral memory enter into light-sleep mode 0: Disable */
#define BIT_HSYS_PERI_MEM_DS BIT(5) /* R/W 0 1: Enable Peripheral memory enter into deep-sleep mode 0: Disable */
#define BIT_HSYS_PERI_MEM_SD BIT(4) /* R/W 0 1: Shut-down Peripheral memory 0: Power on Peripheral memory */
#define BIT_HSYS_USB_MEM_LS BIT(2) /* R/W 0 1: Enable USB memory enter into light-sleep mode 0: Disable */
#define BIT_HSYS_USB_MEM_DS BIT(1) /* R/W 0 1: Enable USB memory enter into deep-sleep mode 0: Disable */
#define BIT_HSYS_USB_MEM_SD BIT(0) /* R/W 0 1: Shut-down USB memory 0: Power on USB memory */
/* HP Security Register */
#define BIT_SEC_EF_RWFLAG BIT(31) /* R/W 0 Write "1" for Program; Write "0" for Read Access */
#define BIT_SHIFT_SEC_EF_ADDR 8 /* [17:8] R/W 0 Access Address */
#define BIT_MASK_SEC_EF_ADDR 0x3FF /* [17:8] R/W 0 Access Address */
#define BIT_SHIFT_SEC_EF_DATA 0 /* [7:0] R/W 0 Access Data */
#define BIT_MASK_SEC_EF_DATA 0xFF /* [7:0] R/W 0 Access Data */
/* HS Secure Boot Status Register */
#define BIT_SECURE_BOOT_DONE BIT(0) /* Write Only, Read as 0*/
//================= SYSON Register Address Definition =====================//
#define REG_HS_PWR_ISO_CTRL 0x0000 /*!< 0x00: REG_SYS_PWR_CTRL, 0x02: REG_SYS_ISO_CTRL */
#define REG_HS_PLATFORM_PARA 0x000C
#define REG_HS_RFAFE_IND_VIO1833 0x0020
#define REG_HS_PLL_I2S_CTRL0 0x0080
#define REG_HS_PLL_I2S_CTRL1 0x0084
#define REG_HS_PLL_I2S_CTRL2 0x0088
#define REG_HS_PLL_I2S_CTRL3 0x008C
#define REG_HS_PLL_PCM_CTRL0 0x0090
#define REG_HS_PLL_PCM_CTRL1 0x0094
#define REG_HS_PLL_PCM_CTRL2 0x0098
#define REG_HS_PLL_PCM_CTRL3 0x009C
#define REG_HS_PLL_TEST 0x00A0
#define REG_HS_WAKE_EVENT_MSK0 0x0120
#define REG_HS_WAKE_EVENT_STATUS0 0x0124
#define REG_HS_WAKE_EVENT_MSK1 0x0128
#define REG_HS_WAKE_EVENT_STATUS1 0x012C
/* HP_PER */
#define REG_HS_PERI_FUNC_CTRL1 0x0200
#define REG_HS_PERI_FUNC_CTRL2 0x0204
#define REG_HS_PERI_FUNC_CTRL3 0x0208
#define REG_HS_PERI_FUNC_CTRL4 0x020C
#define REG_HS_PERI_CLK_CTRL1 0x0210
#define REG_HS_PERI_CLK_CTRL2 0x0214
#define REG_HS_PERI_CLK_CTRL3 0x0218
#define REG_HS_BT_CTRL 0x0228
#define REG_HS_WL_CTRL 0x0240
#define REG_HS_OTG_CTRL 0x0244
#define REG_HS_SDIO_CTRL 0x0248
/*SPI Role Select*/
#define REG_HS_SPI_CTRL 0x268
/*HP_MEM_CTRL*/
#define REG_HS_MEM_CTRL0 0x300
#define REG_HS_MEM_CTRL1 0x304
#define REG_HS_MEM_CTRL2 0x308
/* HP Security Register */
#define REG_HS_SEC_EFUSE_CTRL0 0x10000810
/* HS Secure Boot Status Register */
#define REG_HS_SECURE_BOOT_STA 0x0800
#endif //__INC_RTL8721D_HP_SYS_ON_BIT_H

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/**
******************************************************************************
* @file rtl8721dlp_km4.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for km0 control km4.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_LP_KM4_H_
#define _RTL8721D_LP_KM4_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup KM0_CTRL_KM4
* @brief KM0_CTRL_KM4 driver modules
* @{
*/
/** @addtogroup KM0_CTRL_KM4
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* - functions prototypes for for km0 control km4.
*
*****************************************************************************************
*
*****************************************************************************************
* how to use
*****************************************************************************************
*
*****************************************************************************************
* @endverbatim
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup km4_sleep_parameter km4 sleep parameter
* @{
*/
#ifndef CONFIG_BUILD_ROM
typedef struct
{
u8 dlps_enable;
u8 sleep_type;
u32 sleep_time;
} KM4SLEEP_ParamDef;
#endif
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup KM4_CTRL_Exported_Functions KM4_CTRL Exported Functions
* @{
*/
void km4_pm_init(void);
void km4_boot_on(void);
u32 km4_suspend(u32 type);
void km4_resume(void);
u32 km4_status_on(void);
void km4_set_wake_event(u32 wevt);
u32 km4_get_wake_event(void);
void km4_wake_event_update(void);
void km4_tickless_ipc_int(VOID *Data, u32 IrqStatus, u32 ChanNum);
void km4_flash_highspeed_resume(u32 Protection);
void km4_flash_highspeed_suspend(u32 Protection);
void km4_flash_highspeed_init(void);
uint32_t pmu_get_km4sleeptime(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/* Other definations --------------------------------------------------------*/
extern u8 km4_sleep_type;
extern u32 km4_sleep_timeout;
extern void flash_operation_config(void);
#endif /* _RTL8721D_LP_KM4_H_ */
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/**
******************************************************************************
* @file rtl8721dlp_rcc.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for peripheral reset and clock control driver.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_LP_RCC_H_
#define _RTL8721D_LP_RCC_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup RCC
* @brief RCC driver modules
* @{
*/
/** @defgroup LP_RCC
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* - functions prototypes for peripheral reset and clock control driver.
*
*****************************************************************************************
*
*****************************************************************************************
* how to use
*****************************************************************************************
* use UART0 as example:
* RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
*
*****************************************************************************************
* @endverbatim
*/
/** @addtogroup LP_RCC
* @brief LP_RCC driver modules
* @{
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup LP_RCC_CLK_Exported_Constants LP_RCC CLK Exported Constants
* @{
*/
#define SYS_CLK_CTRL0 0x00U //0x210
#define SYS_CLK_CTRL1 0x01U //0x214
#define SYS_CLK_CTRL2 0x02U //0x004 AON
#define SYS_CLK_CTRL3 0x03U //TODO
#define APBPeriph_CLOCK_NULL 0 //if you dont want to set any clock, you can use this
#define APBPeriph_WLON_CLOCK (SYS_CLK_CTRL0 << 30 | BIT_LSYS_WLON_CKE)
#define APBPeriph_FLASH_CLOCK (SYS_CLK_CTRL0 << 30 | BIT_FLASH_CKE)
#define APBPeriph_GDMA0_CLOCK (SYS_CLK_CTRL0 << 30 | BIT_LSYS_GDMA0_CKE)
#define APBPeriph_EFUSE_CLOCK (SYS_CLK_CTRL0 << 30 | BIT_SYSON_CK_EELDR_EN)
#define APBPeriph_GPIO_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_GPIO0_CKE)
#define APBPeriph_QDEC0_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_QDEC0_CKE)
#define APBPeriph_SGPIO_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_SPGIO0_CKE)
#define APBPeriph_I2C0_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_I2C0_CKE)
#define APBPeriph_ADC_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_ADC_CKE)
#define APBPeriph_UART1_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_UART1_CKE)
#define APBPeriph_LOGUART_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_UART0_CKE)
#define APBPeriph_GTIMER_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_TIMER0_CKE)
#define APBPeriph_IPC_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_IPC_CKE)
#define APBPeriph_VENDOR_REG_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_VENDOR_CKE)
#define APBPeriph_RTC_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_AON_RTC_CKE)
#define APBPeriph_CTOUCH_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_AON_CTOUCH_CKE)
#define APBPeriph_CK32KGEN_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_AON_CK32KGEN_CKE)
#define APBPeriph_KEYSCAN_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_AON_KEYSCAN_CKE)
#define APBPeriph_TSF_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_AON_TSF_CKE)
/* Switch SPIC clock using RCC_PeriphClockSource_SPIC(), don't use the following macro. Because SPIC has RCC_PeriphClockCmd has bug. */
#define APBPeriph_FLASH_CLOCK_ANA4M (SYS_CLK_CTRL0 << 30 | BIT_FLASH_CKE | BIT_SHIFT_FLASH_CLK_ANA4M)
#define APBPeriph_FLASH_CLOCK_XTAL (SYS_CLK_CTRL0 << 30 | BIT_FLASH_CKE | BIT_SHIFT_FLASH_CLK_XTAL)
#define APBPeriph_FLASH_CLOCK_PLL (SYS_CLK_CTRL0 << 30 | BIT_FLASH_CKE | BIT_SHIFT_FLASH_CLK_PLL)
/**
* @}
*/
/** @defgroup LP_RCC_FUNC_Exported_Constants LP_RCC FUNC Exported Constants
* @{
*/
#define SYS_FUNC_EN0 0x03U //0x208
#define SYS_FUNC_EN1 0x02U //0x20C
#define SYS_FUNC_EN2 0x01U //0x004 AON
#define SYS_FUNC_EN3 0x00U //TODO
#define APBPeriph_NULL 0 //if you dont want to set any function, you can use this
#define APBPeriph_WLON (SYS_FUNC_EN0 << 30 | BIT_LSYS_WLON_FEN)
#define APBPeriph_FLASH (SYS_FUNC_EN0 << 30 | BIT_FLASH_FUN_EN)
#define APBPeriph_GDMA0 (SYS_FUNC_EN0 << 30 | BIT_LSYS_GDMA0_FEN)
#define APBPeriph_EFUSE (SYS_FUNC_EN0 << 30 | BIT_SYS_FEN_EELDR)
#define APBPeriph_GPIO (SYS_FUNC_EN1 << 30 | BIT_LSYS_GPIO0_FEN)
#define APBPeriph_QDEC0 (SYS_FUNC_EN1 << 30 | BIT_LSYS_QDEC0_FEN)
#define APBPeriph_SGPIO (SYS_FUNC_EN1 << 30 | BIT_LSYS_SPGIO0_FEN)
#define APBPeriph_I2C0 (SYS_FUNC_EN1 << 30 | BIT_LSYS_I2C0_FEN)
#define APBPeriph_ADC (SYS_FUNC_EN1 << 30 | BIT_LSYS_ADC_FEN)
#define APBPeriph_UART1 (SYS_FUNC_EN1 << 30 | BIT_LSYS_UART1_FEN_GLB | BIT_LSYS_UART1_FEN_FUN)
#define APBPeriph_LOGUART (SYS_FUNC_EN1 << 30 | BIT_LSYS_UART0_FEN_GLB | BIT_LSYS_UART0_FEN_FUN)
#define APBPeriph_GTIMER (SYS_FUNC_EN1 << 30 | BIT_LSYS_TIMER0_FEN)
#define APBPeriph_IPC (SYS_FUNC_EN1 << 30 | BIT_LSYS_IPC_FEN)
#define APBPeriph_VENDOR_REG (SYS_FUNC_EN1 << 30 | BIT_VENDOR_EN)
#define APBPeriph_RTC (SYS_FUNC_EN2 << 30 | BIT_AON_RTC_FEN)
#define APBPeriph_CTOUCH (SYS_FUNC_EN2 << 30 | BIT_AON_CTOUCH_FEN)
#define APBPeriph_CK32KGEN (SYS_FUNC_EN2 << 30 | BIT_AON_CK32KGEN_FEN)
#define APBPeriph_KEYSCAN (SYS_FUNC_EN2 << 30 | BIT_AON_KEYSCAN_FEN)
#define APBPeriph_TSF (SYS_FUNC_EN2 << 30 | BIT_AON_TSF_FEN)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LP_RCC_Exported_Functions LP_RCC Exported Functions
* @{
*/
_LONG_CALL_ void RCC_PeriphClockCmd(u32 APBPeriph, u32 APBPeriph_Clock, u8 NewState);
_LONG_CALL_ void RCC_PeriphClockSource_RTC(u32 Xtal);
_LONG_CALL_ void RCC_PeriphClockSource_I2C(UNUSED_WARN_DIS u32 Idx, u32 Source);
_LONG_CALL_ void RCC_PeriphClockSource_QDEC(UNUSED_WARN_DIS u32 Idx, u32 Source);
_LONG_CALL_ void RCC_PeriphClockSource_UART (UART_TypeDef* UARTx, u32 Source);
/**
* @brief Configure SPIC Clock.
* @param Source: This parameter can be one of the following values:
* @arg BIT_SHIFT_FLASH_CLK_ANA4M
* @arg BIT_SHIFT_FLASH_CLK_XTAL
* @arg BIT_SHIFT_FLASH_CLK_PLL
* @retval None
* @note Used to switch SPIC clock
*/
__STATIC_INLINE void RCC_PeriphClockSource_SPIC (u32 Source)
{
u32 Temp = 0;
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_CLK_CTRL0);
Temp &= ~ (BIT_MASK_FLASH_CLK_SEL << BIT_SHIFT_FLASH_CLK_SEL);
Temp |= Source;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_CLK_CTRL0, Temp);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/* Other definations --------------------------------------------------------*/
#endif /* _RTL8721D_LP_RCC_H_ */
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _SECTION_CONFIG_H_
#define _SECTION_CONFIG_H_
#include "basic_types.h"
#define RAM_VECTOR_TABLE1_SECTION \
SECTION(".ram_vector_table1")
#define RAM_VECTOR_TABLE2_SECTION \
SECTION(".ram_vector_table2")
#define RAM_VECTOR_TABLE3_SECTION \
SECTION(".ram_vector_table3")
//3 //3 Hal Section
#define HAL_ROM_TEXT_SECTION \
SECTION(".hal.rom.text")
#define HAL_ROM_ENTRY_NS_SECTION \
SECTION(".hal.rom.entryns.rodata")
#define SIM_ROM_DATA_SECTION \
SECTION(".sim.rom.rodata")
#define HAL_ROM_DATA_SECTION \
SECTION(".hal.rom.rodata")
#define HAL_ROM_BSS_SECTION \
SECTION(".hal.rom.bss")
#define HAL_ROM_BSS_SECTION_BANK \
SECTION(".hal.rom.bank.bss")
#define BOOT_RAM_TEXT_SECTION \
SECTION(".boot.ram.text")
#define BOOT_RAM_RODATA_SECTION \
SECTION(".boot.rodata")
#define BOOT_RAM_DATA_SECTION \
SECTION(".boot.ram.data")
#define BOOT_RAM_BSS_SECTION \
SECTION(".boot.ram.bss")
#define BOOT_RAM_END_BSS_SECTION \
SECTION(".boot.ram.end.bss")
//3 Shell
#if defined (ARM_CORE_CM0)
#define SHELL_ROM_TEXT_SECTION HAL_ROM_TEXT_SECTION
#define SHELL_ROM_BSS_SECTION HAL_ROM_BSS_SECTION
#define SHELL_ROM_DATA_SECTION HAL_ROM_DATA_SECTION
#else
#define SHELL_ROM_TEXT_SECTION
#define SHELL_ROM_BSS_SECTION
#define SHELL_ROM_DATA_SECTION
#endif
#define CMD_TABLE_DATA_SECTION \
SECTION(".cmd.table.data")
//3 Image 1 data
#define IMAGE1_ENTRY_SECTION \
SECTION(".image1.entry.data")
#define IMAGE1_EXPORT_SYMB_SECTION \
SECTION(".image1.export.symb")
#define IMAGE1_VALID_PATTEN_SECTION \
SECTION(".image1.validate.rodata")
#define IMAGE1_DATA_SECTION \
SECTION(".image1.rodata")
#define IMAGE2_VALID_PATTEN_SECTION \
SECTION(".image2.validate.rodata")
//3 SRAM Config Section
#define SRAM_BD_DATA_SECTION \
SECTION(".bdsram.data")
#define SRAM_NOCACHE_DATA_SECTION \
SRAM_BD_DATA_SECTION
#define SRAM_BF_DATA_SECTION \
SECTION(".bfsram.data")
#define IMAGE2_ENTRY_SECTION \
SECTION(".image2.entry.data")
#define IMAGE2_RAM_TEXT_SECTION \
SECTION(".image2.ram.text")
#define SDRAM_DATA_SECTION
#if defined (ARM_CORE_CM4)
#define PSRAM_TEXT_SECTION SECTION(".psram.text")
#define PSRAM_DATA_SECTION SECTION(".psram.data")
#define PSRAM_RODATA_SECTION SECTION(".psram.rodata")
#define PSRAM_BSS_SECTION SECTION(".psram.bss")
#define PSRAM_HEAP_SECTION SECTION(".psram.heap")
#endif
//3 Wlan Section
#define WLAN_ROM_TEXT_SECTION
#define WLAN_ROM_DATA_SECTION
#define WLAN_RAM_MAP_SECTION
#undef CONFIG_WIFI_CRITICAL_CODE_SECTION
#define CONFIG_WIFI_CRITICAL_CODE_SECTION SECTION(".image2.net.ram.text")
#define CONFIG_FW_CRITICAL_CODE_SECTION //IMAGE2_RAM_TEXT_SECTION
//3 Apple Section
#define APPLE_ROM_TEXT_SECTION \
SECTION(".apple.rom.text")
#define APPLE_ROM_DATA_SECTION \
SECTION(".apple.rom.rodata")
//3 Libc Section
#define LIBC_ROM_TEXT_SECTION \
SECTION(".libc.rom.text")
#define LIBC_ROM_DATA_SECTION \
SECTION(".libc.rom.rodata")
#define LIBC_HEAP_SECTION \
SECTION(".heap.stdlib")
//3 SSL Section
#define SSL_ROM_TEXT_SECTION \
SECTION(".ssl.rom.text")
#define SSL_ROM_DATA_SECTION \
SECTION(".ssl.rom.rodata")
#define SSL_RAM_MAP_SECTION \
SECTION(".ssl_ram_map")
//OS Section
#define OS_ROM_TEXT_SECTION \
SECTION(".os.rom.text")
#define OS_ROM_DATA_SECTION \
SECTION(".os.rom.rodata")
//FLASH RUN CODE
#define FLASH_BOOT_TEXT_SECTION SECTION(".flashboot.text")
#define IMAGE2_CUSTOM_SIGNATURE SECTION(".img2_custom_signature") /* 32B: for OTA update */
//RDP (read protect area just text)
#define RDP_TEXT_SECTION SECTION(".rdp.ram.text")
#define RDP_DATA_SECTION SECTION(".rdp.ram.data")
#define RETENTION_TEXT_SECTION SECTION(".retention.ram.text")
#define RETENTION_DATA_SECTION SECTION(".retention.ram.data")
#define RETENTION_ENTRY_SECTION SECTION(".retention.entry.data")
/* rom map */
#define ROM_FUNCTION_MAP SECTION(".rommap.data")
//3 FW Section
#define FW_ROM_TEXT_SECTION \
SECTION(".FW.rom.text")
#define FW_ROM_DATA_SECTION \
SECTION(".FW.rom.rodata")
#define FW_ROM_BSS_SECTION \
SECTION(".FW.rom.bss")
#define FW_RAM_TEXT_SECTION \
SECTION(".FW.ram.text")
#define FW_RAM_DATA_SECTION \
SECTION(".FW.ram.rodata")
#define FW_RAM_BSS_SECTION \
SECTION(".FW.ram.bss")
/* image3 secure image */
#define IMAGE3_ENTRY_SECTION \
SECTION(".image3.nsc_entry.text")
/*USB_OTG define*/
#define OTG_ROM_TEXT_SECTION
#define START_OTG_RAM_FUN_SECTION
#define START_OTG_RAM_DATA_SECTION
#define OTG_ROM_DATA_SECTION
#endif //_SECTION_CONFIG_H_

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