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xidameng 2020-07-31 22:16:12 +08:00
commit 8508ee6139
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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\Project.ewp</path>
</project>
<batchBuild/>
</workspace>

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/* Bootloader symbol list */
define exported symbol BOOT_FLASH_RDP_VALID = 0x08000123;
define exported symbol BOOT_FLASH_SetStatusReg = 0x080003f5;
define exported symbol BOOT_FLASH_Image1 = 0x0800043b;
define exported symbol IMAGE1$$Base = 0x10002001;
define exported symbol RamStartTable = 0x10002001;
define exported symbol RAM_IMG1_VALID_PATTEN = 0x10002019;
define exported symbol boot_export_symbol = 0x10002021;
define exported symbol BOOT_System_Init1 = 0x10002251;
define exported symbol BOOT_System_Init2 = 0x10002263;
define exported symbol BOOT_Swd_Off = 0x10002275;
define exported symbol boot_ram_end = 0x10002455;
define exported symbol IMAGE1$$Limit = 0x10002459;

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
//define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/**/
/**/
include "rom_symbol_v01_iar.icf";
/****************************************
* Memory Regions *
****************************************/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
define symbol __ICFEDIT_region_ROMBSS_RAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_ROMBSS_RAM_end__ = 0x10001FFF;
define symbol __ICFEDIT_region_BOOTLOADER_RAM_start__ = 0x10002000;
define symbol __ICFEDIT_region_BOOTLOADER_RAM_end__ = 0x10004FFF;
define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10005000;
define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1002FFFF;
define symbol __ICFEDIT_region_MSP_RAM_start__ = 0x1003E000;
define symbol __ICFEDIT_region_MSP_RAM_end__ = 0x1003EFFF;
define symbol __ICFEDIT_region_RDP_RAM_start__ = 0x1003F000;
define symbol __ICFEDIT_region_RDP_RAM_end__ = 0x1003FFEF;
define symbol __ICFEDIT_region_IMG2_TEMP_start__ = 0x10006000;
define symbol __ICFEDIT_region_IMG2_TEMP_end__ = 0x1000BFFF;
define symbol __ICFEDIT_region_XIP_BOOT_start__ = 0x08000000+0x20;
define symbol __ICFEDIT_region_XIP_BOOT_end__ = 0x08003FFF;
define symbol __ICFEDIT_region_XIP_OTA1_start__ = 0x0800B000+0x20;
define symbol __ICFEDIT_region_XIP_OTA1_end__ = 0x080FFFFF;
/****************************************
* Sizes *
****************************************/
/*define symbol __ICFEDIT_size_cstack__ = 0x400;*/
/*define symbol __ICFEDIT_size_heap__ = 0x800;*/
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region ROM_BSS_region = mem:[from __ICFEDIT_region_ROMBSS_RAM_start__ to __ICFEDIT_region_ROMBSS_RAM_end__];
define region BOOT_RAM_region = mem:[from __ICFEDIT_region_BOOTLOADER_RAM_start__ to __ICFEDIT_region_BOOTLOADER_RAM_end__];
define region BD_RAM_region = mem:[from __ICFEDIT_region_BD_RAM_start__ to __ICFEDIT_region_BD_RAM_end__];
define region IMG2_TEMP_region = mem:[from __ICFEDIT_region_IMG2_TEMP_start__ to __ICFEDIT_region_IMG2_TEMP_end__];
define region XIP_BOOT_region = mem:[from __ICFEDIT_region_XIP_BOOT_start__ to __ICFEDIT_region_XIP_BOOT_end__];
define region XIP_OTA1_region = mem:[from __ICFEDIT_region_XIP_OTA1_start__ to __ICFEDIT_region_XIP_OTA1_end__];
define region RDP_RAM_region = mem:[from __ICFEDIT_region_RDP_RAM_start__ to __ICFEDIT_region_RDP_RAM_end__];
/*define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };*/
/*define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };*/
//initialize by copy { readwrite };
//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
//do not initialize { section * };
//place at address mem:__ICFEDIT_intvec_start__ { readonly section .vectors_table };
//
/****************************************
* ROM Section config *
****************************************/
keep { section .rom.text };
keep { section .rom.rodata };
place at start of ROM_region { readonly, section .rom.text, section .rom.rodata };
/****************************************
* ROM BSS Section config *
****************************************/
keep { section .ram_vector_table1 };
keep { section .ram_vector_table2 };
keep { section .ram_vector_table3 };
keep { section .hal.rom.bss* };
keep { section .wlan_ram_map* };
keep { section .libc.ram.bss* };
keep { section .ssl_ram_map* };
define block .hal.rom.bss with fixed order{ section .ram_vector_table1,
section .ram_vector_table2,
section .ram_vector_table3,
section .hal.rom.bss*,
section .wlan_ram_map*,
section .libc.ram.bss*,
section .ssl_ram_map*,
};
define block ROM_BSS with fixed order { block .hal.rom.bss};
place at start of ROM_BSS_region { readwrite,
block ROM_BSS,
};
/****************************************
* BOOT RAM Section config *
****************************************/
keep { section .image1.entry.data* };
keep { section .image1.validate.rodata* };
define block .ram_image1.entry with fixed order{section .image1.entry.data*,
section .image1.validate.rodata*,
};
keep { section .boot.ram.text* };
keep { section .boot.rodata* };
define block .ram_image1.text with fixed order{section .boot.ram.text*,
section .boot.rodata*,
};
keep { section .boot.ram.data* };
define block .ram_image1.data with fixed order{section .boot.ram.data*,
};
keep { section .boot.ram.bss* };
define block .ram_image1.bss with fixed order{section .boot.ram.bss*,
};
define block IMAGE1 with fixed order { block .ram_image1.entry, block .ram_image1.text, block .ram_image1.data, block .ram_image1.bss};
place at start of BOOT_RAM_region { readwrite,
block IMAGE1,
};
/****************************************
* BD RAM Section config *
****************************************/
keep { section .image2.entry.data* };
keep { section .image2.validate.rodata* };
define block .ram_image2.entry with fixed order{ section .image2.entry.data*,
section .image2.validate.rodata*,
};
define block SHT$$PREINIT_ARRAY { preinit_array };
define block SHT$$INIT_ARRAY { init_array };
define block CPP_INIT with fixed order { block SHT$$PREINIT_ARRAY,
block SHT$$INIT_ARRAY };
define block .ram.data with fixed order{ section .data*,
section DATA,
section .iar.init_table,
section __DLIB_PERTHREAD,
block CPP_INIT,
section .mdns.data,
section .mdns.text
};
define block .ram.text with fixed order{ section .image2.ram.text*,
};
define block IMAGE2 with fixed order { block .ram_image2.entry,
block .ram.data,
block .ram.text,
};
define block .ram_image2.bss with fixed order{ section .bss*,
section COMMON,
};
define block .ram_image2.skb.bss with fixed order{ section .bdsram.data* };
define block .ram_heap.data with fixed order{ section .bfsram.data* };
place at start of BD_RAM_region { readwrite,
block IMAGE2,
block .ram_image2.bss,
block .ram_image2.skb.bss,
block .ram_heap.data,
section .heap.stdlib,
};
/****************************************
* XIP BOOT Section config *
****************************************/
keep { section .flashboot.text* };
define block .xip_image1.text with fixed order{ section .flashboot.text* };
define block Bootloader with fixed order { section LOADER };
place at start of XIP_BOOT_region { block Bootloader,
readwrite,
block .xip_image1.text };
/****************************************
* XIP OTA1 Section config *
****************************************/
define block .xip_image2.text with fixed order{ section .img2_custom_signature*,
section .text*,
section .rodata*,
section .debug_trace,
section CODE,
section Veneer, // object startup.o,
};
place at start of XIP_OTA1_region { readwrite,
block .xip_image2.text };
/****************************************
* RDP Section config *
****************************************/
keep { section .rdp.ram.text* };
keep { section .rdp.ram.data* };
define block .RDP_RAM with fixed order {
section .rdp.ram.text*,
section .rdp.ram.data* };
place at start of RDP_RAM_region{
readwrite,
block .RDP_RAM };
define exported symbol __ram_start_table_start__= 0x10002000; // use in rom
define exported symbol __image1_validate_code__= 0x10002018; // needed by ram code
define exported symbol __rom_top_4k_start_= 0x1003F000; // needed by ram code
define exported symbol __flash_text_start__= 0x0800b020; // needed by ram code
define exported symbol boot_export_symbol = 0x10002020;

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all: ram_all
OS := $(shell uname)
.PHONY: toolchain
toolchain:
ifeq ($(OS),Linux)
if [ ! -d ../../../tools/arm-none-eabi-gcc/4_8-2014q3 ] ; then tar -jxf ../../../tools/arm-none-eabi-gcc/gcc-arm-none-eabi-4_8-2014q3-20140805-linux.tar.bz2 -C ../../../tools/arm-none-eabi-gcc/ ; mv ../../../tools/arm-none-eabi-gcc/gcc-arm-none-eabi-4_8-2014q3 ../../../tools/arm-none-eabi-gcc/4_8-2014q3 ; fi
else
if [ ! -d ../../../tools/arm-none-eabi-gcc/4_8-2014q3 ] ; then tar -xf ../../../tools/arm-none-eabi-gcc/4_8-2014q3.tar -C ../../../tools/arm-none-eabi-gcc/ ; fi
endif
.PHONY: ram_all
ram_all: toolchain
@$(MAKE) -f application.mk
.PHONY: mp
mp: toolchain
@$(MAKE) -f application.mk mp
.PHONY: clean
clean:
@$(MAKE) -f application.mk clean
.PHONY: flash debug ramdebug setup
setup:
@$(MAKE) -f application.mk $(MAKECMDGOALS)
flash: toolchain
@$(MAKE) -f application.mk flashburn
debug: toolchain
@$(MAKE) -f application.mk debug
ramdebug: toolchain
@$(MAKE) -f application.mk ramdebug

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# Initialize tool chain
# -------------------------------------------------------------------
ARM_GCC_TOOLCHAIN = ../../../tools/arm-none-eabi-gcc/4_8-2014q3/bin/
AMEBA_TOOLDIR = ../../../component/soc/realtek/8711b/misc/iar_utility/common/tools/
FLASH_TOOLDIR = ../../../component/soc/realtek/8195a/misc/gcc_utility/
FLASHDOWNLOAD_TOOLDIR = ../../../component/soc/realtek/8711b/misc/gnu_utility/flash_download/image
DEBUG_TOOLDIR = ../../../component/soc/realtek/8711b/misc/gcc_utility/
CROSS_COMPILE = $(ARM_GCC_TOOLCHAIN)/arm-none-eabi-
ota_idx = 1
# Compilation tools
AR = $(CROSS_COMPILE)ar
CC = $(CROSS_COMPILE)gcc
AS = $(CROSS_COMPILE)as
NM = $(CROSS_COMPILE)nm
LD = $(CROSS_COMPILE)gcc
GDB = $(CROSS_COMPILE)gdb
OBJCOPY = $(CROSS_COMPILE)objcopy
OBJDUMP = $(CROSS_COMPILE)objdump
OS := $(shell uname)
ifeq ($(findstring CYGWIN, $(OS)), CYGWIN)
PICK = $(AMEBA_TOOLDIR)pick.exe
PAD = $(AMEBA_TOOLDIR)padding.exe
CHKSUM = $(AMEBA_TOOLDIR)checksum.exe
OTA = $(AMEBA_TOOLDIR)ota.exe
else
PICK = $(AMEBA_TOOLDIR)pick
PAD = $(AMEBA_TOOLDIR)padding
CHKSUM = $(AMEBA_TOOLDIR)checksum
OTA = $(AMEBA_TOOLDIR)ota
endif
# Initialize target name and target object files
# -------------------------------------------------------------------
all: application manipulate_images
mp: application manipulate_images
TARGET=application
OBJ_DIR=$(TARGET)/Debug/obj
BIN_DIR=$(TARGET)/Debug/bin
# Include folder list
# -------------------------------------------------------------------
INCLUDES =
INCLUDES += -I../inc
INCLUDES += -I../../../component/os/freertos
INCLUDES += -I../../../component/os/freertos/freertos_v8.1.2/Source/include
INCLUDES += -I../../../component/os/freertos/freertos_v8.1.2/Source/portable/GCC/ARM_CM4F
INCLUDES += -I../../../component/os/os_dep/include
INCLUDES += -I../../../component/common/api/network/include
INCLUDES += -I../../../component/common/api
INCLUDES += -I../../../component/common/api/at_cmd
INCLUDES += -I../../../component/common/api/platform
INCLUDES += -I../../../component/common/api/wifi
INCLUDES += -I../../../component/common/api/wifi/rtw_wpa_supplicant/src
INCLUDES += -I../../../component/common/api/wifi/rtw_wowlan
INCLUDES += -I../../../component/common/api/wifi/rtw_wpa_supplicant/wpa_supplicant
INCLUDES += -I../../../component/common/application
INCLUDES += -I../../../component/common/application/mqtt/MQTTClient
INCLUDES += -I../../../component/common/application/mqtt/MQTTPacket
INCLUDES += -I../../../component/common/example
INCLUDES += -I../../../component/common/example/wlan_fast_connect
INCLUDES += -I../../../component/common/drivers/modules
INCLUDES += -I../../../component/common/drivers/sdio/realtek/sdio_host/inc
INCLUDES += -I../../../component/common/drivers/inic/rtl8711b
INCLUDES += -I../../../component/common/drivers/usb_class/device
INCLUDES += -I../../../component/common/drivers/usb_class/device/class
INCLUDES += -I../../../component/common/drivers/wlan/realtek/include
INCLUDES += -I../../../component/common/drivers/wlan/realtek/src/osdep
INCLUDES += -I../../../component/common/drivers/wlan/realtek/src/hci
INCLUDES += -I../../../component/common/drivers/wlan/realtek/src/hal
INCLUDES += -I../../../component/common/drivers/wlan/realtek/src/hal/rtl8711b
INCLUDES += -I../../../component/common/drivers/wlan/realtek/src/hal/OUTSRC
INCLUDES += -I../../../component/common/drivers/wlan/realtek/wlan_ram_map/rom
INCLUDES += -I../../../component/common/file_system
INCLUDES += -I../../../component/common/network
INCLUDES += -I../../../component/common/network/lwip/lwip_v1.4.1/port/realtek/freertos
INCLUDES += -I../../../component/common/network/lwip/lwip_v1.4.1/src/include
INCLUDES += -I../../../component/common/network/lwip/lwip_v1.4.1/src/include/lwip
INCLUDES += -I../../../component/common/network/lwip/lwip_v1.4.1/src/include/ipv4
INCLUDES += -I../../../component/common/network/lwip/lwip_v1.4.1/port/realtek
INCLUDES += -I../../../component/common/network/ssl/polarssl-1.3.8/include
INCLUDES += -I../../../component/common/network/ssl/ssl_ram_map/rom
INCLUDES += -I../../../component/common/test
INCLUDES += -I../../../component/common/utilities
INCLUDES += -I../../../component/soc/realtek/8711b/app/monitor/include
INCLUDES += -I../../../component/soc/realtek/8711b/cmsis
INCLUDES += -I../../../component/soc/realtek/8711b/cmsis/device
INCLUDES += -I../../../component/soc/realtek/8711b/fwlib
INCLUDES += -I../../../component/soc/realtek/8711b/fwlib/include
INCLUDES += -I../../../component/soc/realtek/8711b/fwlib/ram_lib/crypto
INCLUDES += -I../../../component/soc/realtek/8711b/fwlib/rom_lib
INCLUDES += -I../../../component/soc/realtek/8711b/swlib/os_dep/include
INCLUDES += -I../../../component/soc/realtek/8711b/swlib/std_lib/include
INCLUDES += -I../../../component/soc/realtek/8711b/swlib/std_lib/libc/include
INCLUDES += -I../../../component/soc/realtek/8711b/swlib/std_lib/libc/rom/string
INCLUDES += -I../../../component/soc/realtek/8711b/swlib/std_lib/libgcc/rtl8195a/include
INCLUDES += -I../../../component/soc/realtek/8711b/swlib/rtl_lib
INCLUDES += -I../../../component/soc/realtek/8711b/misc
INCLUDES += -I../../../component/soc/realtek/8711b/misc/os
INCLUDES += -I../../../component/common/mbed/api
INCLUDES += -I../../../component/common/mbed/hal
INCLUDES += -I../../../component/common/mbed/hal_ext
INCLUDES += -I../../../component/common/mbed/targets/cmsis/rtl8711b
INCLUDES += -I../../../component/common/mbed/targets/hal/rtl8711b
INCLUDES += -I../../../project/realtek_8195a_gen_project/rtl8195a/sw/lib/sw_lib/mbed/api
INCLUDES += -I../../../component/common/application/mqtt/MQTTClient
INCLUDES += -I../../../component/common/network/websocket
# Source file list
# -------------------------------------------------------------------
SRC_C =
DRAM_C =
#app uart_adapter
SRC_C += ../../../component/common/application/uart_adapter/uart_adapter.c
#cmsis
SRC_C += ../../../component/soc/realtek/8711b/cmsis/device/app_start.c
SRC_C += ../../../component/soc/realtek/8711b/fwlib/ram_lib/startup.c
SRC_C += ../../../component/soc/realtek/8711b/cmsis/device/system_8195a.c
#console
SRC_C += ../../../component/common/api/at_cmd/atcmd_lwip.c
SRC_C += ../../../component/common/api/at_cmd/atcmd_sys.c
SRC_C += ../../../component/common/api/at_cmd/atcmd_wifi.c
SRC_C += ../../../component/common/api/at_cmd/log_service.c
SRC_C += ../../../component/soc/realtek/8711b/app/monitor/ram/low_level_io.c
SRC_C += ../../../component/soc/realtek/8711b/app/monitor/ram/monitor.c
SRC_C += ../../../component/soc/realtek/8711b/app/monitor/ram/rtl_consol.c
SRC_C += ../../../component/soc/realtek/8711b/app/monitor/ram/rtl_trace.c
#lib
#SRC_C += ../../../component/soc/realtek/8711b/misc/bsp/lib/common/IAR/lib_platform.a
#SRC_C += ../../../component/soc/realtek/8711b/misc/bsp/lib/common/IAR/lib_rtlstd.a
#SRC_C += ../../../component/soc/realtek/8711b/misc/bsp/lib/common/IAR/lib_wlan.a
#SRC_C += ../../../component/soc/realtek/8711b/misc/bsp/lib/common/IAR/lib_wlan_mp.a
#SRC_C += ../../../component/soc/realtek/8711b/misc/bsp/lib/common/IAR/lib_wps.a
#network api wifi rtw_wpa_supplicant
SRC_C += ../../../component/common/api/wifi/rtw_wpa_supplicant/wpa_supplicant/wifi_eap_config.c
SRC_C += ../../../component/common/api/wifi/rtw_wpa_supplicant/wpa_supplicant/wifi_wps_config.c
#network api wifi
SRC_C += ../../../component/common/api/wifi/wifi_conf.c
SRC_C += ../../../component/common/api/wifi/wifi_ind.c
SRC_C += ../../../component/common/api/wifi/wifi_promisc.c
SRC_C += ../../../component/common/api/wifi/wifi_simple_config.c
SRC_C += ../../../component/common/api/wifi/wifi_util.c
#network api
SRC_C += ../../../component/common/api/lwip_netconf.c
#network app
SRC_C += ../../../component/common/application/mqtt/MQTTClient/MQTTClient.c
SRC_C += ../../../component/common/application/mqtt/MQTTPacket/MQTTConnectClient.c
SRC_C += ../../../component/common/application/mqtt/MQTTPacket/MQTTConnectServer.c
SRC_C += ../../../component/common/application/mqtt/MQTTPacket/MQTTDeserializePublish.c
SRC_C += ../../../component/common/application/mqtt/MQTTPacket/MQTTFormat.c
SRC_C += ../../../component/common/application/mqtt/MQTTClient/MQTTFreertos.c
SRC_C += ../../../component/common/application/mqtt/MQTTPacket/MQTTPacket.c
SRC_C += ../../../component/common/application/mqtt/MQTTPacket/MQTTSerializePublish.c
SRC_C += ../../../component/common/application/mqtt/MQTTPacket/MQTTSubscribeClient.c
SRC_C += ../../../component/common/application/mqtt/MQTTPacket/MQTTSubscribeServer.c
SRC_C += ../../../component/common/application/mqtt/MQTTPacket/MQTTUnsubscribeClient.c
SRC_C += ../../../component/common/application/mqtt/MQTTPacket/MQTTUnsubscribeServer.c
SRC_C += ../../../component/common/api/network/src/ping_test.c
SRC_C += ../../../component/common/utilities/ssl_client.c
SRC_C += ../../../component/common/utilities/tcptest.c
SRC_C += ../../../component/common/api/network/src/wlan_network.c
#network lwip api
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/api/api_lib.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/api/api_msg.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/api/err.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/api/netbuf.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/api/netdb.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/api/netifapi.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/api/sockets.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/api/tcpip.c
#network lwip core ipv4
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/autoip.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/icmp.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/igmp.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/inet.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/inet_chksum.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/ip.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/ip_addr.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/ip_frag.c
#network lwip core
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/def.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/dhcp.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/dns.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/init.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/lwip_timers.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/mem.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/memp.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/netif.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/pbuf.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/raw.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/stats.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/sys.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/tcp.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/tcp_in.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/tcp_out.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/core/udp.c
#network lwip netif
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/src/netif/etharp.c
#network lwip port
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/port/realtek/freertos/ethernetif.c
SRC_C += ../../../component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c
SRC_C += ../../../component/common/network/lwip/lwip_v1.4.1/port/realtek/freertos/sys_arch.c
#network - wsclient
SRC_C += ../../../component/common/network/websocket/wsclient_tls.c
#network lwip
SRC_C += ../../../component/common/network/dhcp/dhcps.c
SRC_C += ../../../component/common/network/sntp/sntp.c
#network polarssl polarssl
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/aesni.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/blowfish.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/camellia.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/ccm.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/certs.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/cipher.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/cipher_wrap.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/debug.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/ecp_ram.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/entropy.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/entropy_poll.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/error.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/gcm.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/havege.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/md2.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/md4.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/memory_buffer_alloc.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/net.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/padlock.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/pbkdf2.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/pkcs11.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/pkcs12.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/pkcs5.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/pkparse.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/platform.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/ripemd160.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/ssl_cache.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/ssl_ciphersuites.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/ssl_cli.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/ssl_srv.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/ssl_tls.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/threading.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/timing.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/version.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/version_features.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/x509.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/x509_create.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/x509_crl.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/x509_crt.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/x509_csr.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/x509write_crt.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/x509write_csr.c
SRC_C += ../../../component/common/network/ssl/polarssl-1.3.8/library/xtea.c
#network polarssl ssl_ram_map
SRC_C += ../../../component/common/network/ssl/ssl_ram_map/ssl_ram_map.c
#os freertos portable
SRC_C += ../../../component/os/freertos/freertos_v8.1.2/Source/portable/MemMang/heap_5.c
SRC_C += ../../../component/os/freertos/freertos_v8.1.2/Source/portable/GCC/ARM_CM4F/port.c
#SRC_C += ../../../component/os/freertos/freertos_v8.1.2/Source/portable/IAR/ARM_CM4F/portasm.s
#os freertos
SRC_C += ../../../component/os/freertos/cmsis_os.c
SRC_C += ../../../component/os/freertos/freertos_v8.1.2/Source/croutine.c
SRC_C += ../../../component/os/freertos/freertos_v8.1.2/Source/event_groups.c
SRC_C += ../../../component/os/freertos/freertos_service.c
SRC_C += ../../../component/os/freertos/freertos_v8.1.2/Source/list.c
SRC_C += ../../../component/os/freertos/freertos_v8.1.2/Source/queue.c
SRC_C += ../../../component/os/freertos/freertos_v8.1.2/Source/tasks.c
SRC_C += ../../../component/os/freertos/freertos_v8.1.2/Source/timers.c
#os osdep
SRC_C += ../../../component/os/os_dep/device_lock.c
SRC_C += ../../../component/os/os_dep/osdep_service.c
#peripheral api
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/analogin_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/dma_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/efuse_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/flash_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/gpio_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/gpio_irq_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/i2c_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/i2s_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/nfc_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/pinmap.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/pinmap_common.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/port_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/pwmout_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/rtc_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/serial_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/sleep.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/spi_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/sys_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/timer_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/us_ticker.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/us_ticker_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/wait_api.c
SRC_C += ../../../component/common/mbed/targets/hal/rtl8711b/wdt_api.c
#peripheral rtl8710b
SRC_C += ../../../component/soc/realtek/8711b/fwlib/ram_lib/rtl8710b_dsleepcfg.c
SRC_C += ../../../component/soc/realtek/8711b/fwlib/ram_lib/rtl8710b_dstandbycfg.c
SRC_C += ../../../component/soc/realtek/8711b/fwlib/ram_lib/rtl8710b_intfcfg.c
SRC_C += ../../../component/soc/realtek/8711b/misc/rtl8710b_ota.c
SRC_C += ../../../component/soc/realtek/8711b/fwlib/ram_lib/rtl8710b_pinmapcfg.c
SRC_C += ../../../component/soc/realtek/8711b/fwlib/ram_lib/rtl8710b_sleepcfg.c
#utilities example
SRC_C += ../../../component/common/example/bcast/example_bcast.c
SRC_C += ../../../component/common/example/dct/example_dct.c
SRC_C += ../../../component/common/example/eap/example_eap.c
SRC_C += ../../../component/common/example/example_entry.c
SRC_C += ../../../component/common/example/get_beacon_frame/example_get_beacon_frame.c
SRC_C += ../../../component/common/example/high_load_memory_use/example_high_load_memory_use.c
SRC_C += ../../../component/common/example/http_client/example_http_client.c
SRC_C += ../../../component/common/example/http_download/example_http_download.c
SRC_C += ../../../component/common/example/mcast/example_mcast.c
SRC_C += ../../../component/common/example/mdns/example_mdns.c
SRC_C += ../../../component/common/example/mqtt/example_mqtt.c
SRC_C += ../../../component/common/example/nonblock_connect/example_nonblock_connect.c
SRC_C += ../../../component/common/example/rarp/example_rarp.c
SRC_C += ../../../component/common/example/sntp_showtime/example_sntp_showtime.c
SRC_C += ../../../component/common/example/socket_select/example_socket_select.c
SRC_C += ../../../component/common/example/ssl_download/example_ssl_download.c
SRC_C += ../../../component/common/example/ssl_server/example_ssl_server.c
SRC_C += ../../../component/common/example/tcp_keepalive/example_tcp_keepalive.c
SRC_C += ../../../component/common/example/uart_atcmd/example_uart_atcmd.c
SRC_C += ../../../component/common/example/wifi_mac_monitor/example_wifi_mac_monitor.c
SRC_C += ../../../component/common/example/wlan_fast_connect/example_wlan_fast_connect.c
SRC_C += ../../../component/common/example/wlan_scenario/example_wlan_scenario.c
SRC_C += ../../../component/common/example/websocket/example_wsclient.c
SRC_C += ../../../component/common/example/xml/example_xml.c
#utilities
SRC_C += ../../../component/common/utilities/cJSON.c
SRC_C += ../../../component/common/utilities/http_client.c
SRC_C += ../../../component/common/utilities/uart_socket.c
SRC_C += ../../../component/common/utilities/webserver.c
SRC_C += ../../../component/common/utilities/xml.c
#user
SRC_C += ../src/main.c
# Generate obj list
# -------------------------------------------------------------------
SRC_O = $(patsubst %.c,%.o,$(SRC_C))
DRAM_O = $(patsubst %.c,%.o,$(DRAM_C))
SRC_C_LIST = $(notdir $(SRC_C)) $(notdir $(DRAM_C))
OBJ_LIST = $(addprefix $(OBJ_DIR)/,$(patsubst %.c,%.o,$(SRC_C_LIST)))
DEPENDENCY_LIST = $(addprefix $(OBJ_DIR)/,$(patsubst %.c,%.d,$(SRC_C_LIST)))
# Compile options
# -------------------------------------------------------------------
CFLAGS =
CFLAGS += -DM3 -DCONFIG_PLATFORM_8711B
CFLAGS += -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -g2 -w -O2 -Wno-pointer-sign -fno-common -fmessage-length=0 -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-short-enums -DF_CPU=166000000L -std=gnu99 -fsigned-char
LFLAGS =
LFLAGS += -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -g --specs=nano.specs -nostartfiles -Wl,-Map=$(BIN_DIR)/application.map -Os -Wl,--gc-sections -Wl,--cref -Wl,--entry=Reset_Handler -Wl,--no-enum-size-warning -Wl,--no-wchar-size-warning
LFLAGS += -Wl,-wrap,malloc -Wl,-wrap,free -Wl,-wrap,realloc
LIBFLAGS =
all: LIBFLAGS += -L../../../component/soc/realtek/8711b/misc/bsp/lib/common/GCC/ -l_platform -l_wlan -l_wps -l_dct -l_rtlstd -lm -lc -lnosys -lgcc -l_websocket
mp: LIBFLAGS += -L../../../component/soc/realtek/8711b/misc/bsp/lib/common/GCC/ -l_platform -l_wlan_mp -l_wps -l_dct -l_rtlstd -lm -lc -lnosys -lgcc -l_websocket
RAMALL_BIN =
OTA_BIN =
all: RAMALL_BIN = ram_all.bin
all: OTA_BIN = ota.bin
mp: RAMALL_BIN = ram_all_mp.bin
mp: OTA_BIN = ota_mp.bin
IMAGE2_OTA1=
IMAGE2_OTA2=
OTA_ALL=
all:IMAGE2_OTA1 = image2_all_ota1.bin
all:IMAGE2_OTA2 = image2_all_ota2.bin
all:OTA_ALL = ota_all.bin
mp:IMAGE2_OTA1 = image2_all_ota1_mp.bin
mp:IMAGE2_OTA2 = image2_all_ota2_mp.bin
mp:OTA_ALL = ota_all_mp.bin
# Compile
# -------------------------------------------------------------------
.PHONY: application
application: prerequirement build_info $(SRC_O) $(DRAM_O)
ifeq ("${ota_idx}", "1")
$(LD) $(LFLAGS) -o $(BIN_DIR)/$(TARGET).axf $(OBJ_LIST) $(OBJ_DIR)/boot_all.o $(LIBFLAGS) -T./rlx8711B-symbol-v02-img2_xip1.ld
else ifeq ("${ota_idx}", "2")
$(LD) $(LFLAGS) -o $(BIN_DIR)/$(TARGET).axf $(OBJ_LIST) $(OBJ_DIR)/boot_all.o $(LIBFLAGS) -T./rlx8711B-symbol-v02-img2_xip2.ld
else
@echo ===========================================================
@echo ota_idx must be "1" or "2"
@echo ===========================================================
endif
$(OBJDUMP) -d $(BIN_DIR)/$(TARGET).axf > $(BIN_DIR)/$(TARGET).asm
# Manipulate Image
# -------------------------------------------------------------------
.PHONY: manipulate_images
manipulate_images:
@echo ===========================================================
@echo Image manipulating
@echo ===========================================================
$(NM) $(BIN_DIR)/$(TARGET).axf | sort > $(BIN_DIR)/$(TARGET).nmap
$(OBJCOPY) -j .ram_image2.entry -j .ram_image2.data -j .ram_image2.bss -j .ram_image2.skb.bss -j .ram_heap.data -Obinary $(BIN_DIR)/$(TARGET).axf $(BIN_DIR)/ram_2.r.bin
$(OBJCOPY) -j .xip_image2.text -Obinary $(BIN_DIR)/$(TARGET).axf $(BIN_DIR)/xip_image2.bin
$(OBJCOPY) -j .ram_rdp.text -Obinary $(BIN_DIR)/$(TARGET).axf $(BIN_DIR)/rdp.bin
cp ../../../component/soc/realtek/8711b/misc/bsp/image/boot_all.bin $(BIN_DIR)/boot_all.bin
chmod 777 $(BIN_DIR)/boot_all.bin
chmod +rx $(PICK) $(CHKSUM) $(PAD) $(OTA)
$(PICK) 0x`grep __ram_image2_text_start__ $(BIN_DIR)/$(TARGET).nmap | gawk '{print $$1}'` 0x`grep __ram_image2_text_end__ $(BIN_DIR)/$(TARGET).nmap | gawk '{print $$1}'` $(BIN_DIR)/ram_2.r.bin $(BIN_DIR)/ram_2.bin raw
$(PICK) 0x`grep __ram_image2_text_start__ $(BIN_DIR)/$(TARGET).nmap | gawk '{print $$1}'` 0x`grep __ram_image2_text_end__ $(BIN_DIR)/$(TARGET).nmap | gawk '{print $$1}'` $(BIN_DIR)/ram_2.bin $(BIN_DIR)/ram_2.p.bin
$(PICK) 0x`grep __xip_image2_start__ $(BIN_DIR)/$(TARGET).nmap | gawk '{print $$1}'` 0x`grep __xip_image2_start__ $(BIN_DIR)/$(TARGET).nmap | gawk '{print $$1}'` $(BIN_DIR)/xip_image2.bin $(BIN_DIR)/xip_image2.p.bin
ifeq ("${ota_idx}", "1")
cat $(BIN_DIR)/xip_image2.p.bin > $(BIN_DIR)/$(IMAGE2_OTA1)
chmod 777 $(BIN_DIR)/$(IMAGE2_OTA1)
cat $(BIN_DIR)/ram_2.p.bin >> $(BIN_DIR)/$(IMAGE2_OTA1)
$(CHKSUM) $(BIN_DIR)/$(IMAGE2_OTA1) || true
#rm $(BIN_DIR)/xip_image2.p.bin $(BIN_DIR)/ram_2.p.bin
else ifeq ("${ota_idx}", "2")
cat $(BIN_DIR)/xip_image2.p.bin > $(BIN_DIR)/$(IMAGE2_OTA2)
chmod 777 $(BIN_DIR)/$(IMAGE2_OTA2)
cat $(BIN_DIR)/ram_2.p.bin >> $(BIN_DIR)/$(IMAGE2_OTA2)
$(CHKSUM) $(BIN_DIR)/$(IMAGE2_OTA2) || true
$(OTA) $(BIN_DIR)/$(IMAGE2_OTA1) 0x800B000 $(BIN_DIR)/$(IMAGE2_OTA2) 0x08080000 0x20170111 $(BIN_DIR)/$(OTA_ALL)
else
@echo ===========================================================
@echo ota_idx must be "1" or "2"
@echo ===========================================================
endif
# ramall_bin
# $(PAD) 44k 0xFF $(BIN_DIR)/boot_all.bin
# cat $(BIN_DIR)/boot_all.bin > $(BIN_DIR)/$(RAMALL_BIN)
# chmod 777 $(BIN_DIR)/$(RAMALL_BIN)
# cat $(BIN_DIR)/image2_all_ota1.bin >> $(BIN_DIR)/$(RAMALL_BIN)
# cat $(BIN_DIR)/image2_all_ota2.bin >> $(BIN_DIR)/$(RAMALL_BIN)
# Generate build info
# -------------------------------------------------------------------
.PHONY: build_info
build_info:
@echo \#define UTS_VERSION \"`date +%Y/%m/%d-%T`\" > .ver
@echo \#define RTL8195AFW_COMPILE_TIME \"`date +%Y/%m/%d-%T`\" >> .ver
@echo \#define RTL8195AFW_COMPILE_DATE \"`date +%Y%m%d`\" >> .ver
@echo \#define RTL8195AFW_COMPILE_BY \"`id -u -n`\" >> .ver
@echo \#define RTL8195AFW_COMPILE_HOST \"`$(HOSTNAME_APP)`\" >> .ver
@if [ -x /bin/dnsdomainname ]; then \
echo \#define RTL8195AFW_COMPILE_DOMAIN \"`dnsdomainname`\"; \
elif [ -x /bin/domainname ]; then \
echo \#define RTL8195AFW_COMPILE_DOMAIN \"`domainname`\"; \
else \
echo \#define RTL8195AFW_COMPILE_DOMAIN ; \
fi >> .ver
@echo \#define RTL195AFW_COMPILER \"gcc `$(CC) $(CFLAGS) -dumpversion | tr --delete '\r'`\" >> .ver
@mv -f .ver ../inc/$@.h
.PHONY: prerequirement
prerequirement:
@echo ===========================================================
@echo Build $(TARGET)
@echo ===========================================================
mkdir -p $(OBJ_DIR)
mkdir -p $(BIN_DIR)
#cp ../../../component/soc/realtek/8195a/misc/bsp/image/ram_1.r.bin $(OBJ_DIR)/ram_1.r.bin
cp ../../../component/soc/realtek/8711b/misc/bsp/image/boot_all.bin $(OBJ_DIR)/boot_all.bin
#chmod 777 $(OBJ_DIR)/ram_1.r.bin
chmod 777 $(OBJ_DIR)/boot_all.bin
# $(OBJCOPY) --rename-section .data=.loader.data,contents,alloc,load,readonly,data -I binary -O elf32-littlearm -B arm $(OBJ_DIR)/boot_all.bin $(OBJ_DIR)/boot_all.o
$(OBJCOPY) -I binary -O elf32-littlearm -B arm $(OBJ_DIR)/boot_all.bin $(OBJ_DIR)/boot_all.o
$(SRC_O): %.o : %.c
$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $@
$(CC) $(CFLAGS) $(INCLUDES) -c $< -MM -MT $@ -MF $(OBJ_DIR)/$(notdir $(patsubst %.o,%.d,$@))
cp $@ $(OBJ_DIR)/$(notdir $@)
chmod 777 $(OBJ_DIR)/$(notdir $@)
$(DRAM_O): %.o : %.c
$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $@
$(OBJCOPY) --prefix-alloc-sections .sdram $@
$(CC) $(CFLAGS) $(INCLUDES) -c $< -MM -MT $@ -MF $(OBJ_DIR)/$(notdir $(patsubst %.o,%.d,$@))
cp $@ $(OBJ_DIR)/$(notdir $@)
chmod 777 $(OBJ_DIR)/$(notdir $@)
-include $(DEPENDENCY_LIST)
# Generate build info
# -------------------------------------------------------------------
#ifeq (setup,$(firstword $(MAKECMDGOALS)))
# # use the rest as arguments for "run"
# RUN_ARGS := $(wordlist 2,$(words $(MAKECMDGOALS)),$(MAKECMDGOALS))
# # ...and turn them into do-nothing targets
# $(eval $(RUN_ARGS):;@:)
#endif
.PHONY: setup
setup:
@echo "----------------"
@echo Setup $(GDB_SERVER)
@echo "----------------"
ifeq ($(GDB_SERVER), openocd)
cp -p $(FLASH_TOOLDIR)/rtl_gdb_debug_openocd.txt $(FLASH_TOOLDIR)/rtl_gdb_debug.txt
cp -p $(DEBUG_TOOLDIR)/rtl_gdb_debug_openocd.txt $(DEBUG_TOOLDIR)/rtl_gdb_debug.txt
cp -p $(FLASH_TOOLDIR)/rtl_gdb_ramdebug_openocd.txt $(FLASH_TOOLDIR)/rtl_gdb_ramdebug.txt
cp -p $(FLASH_TOOLDIR)/rtl_gdb_flash_write_openocd.txt $(FLASH_TOOLDIR)/rtl_gdb_flash_write.txt
cp -p $(FLASHDOWNLOAD_TOOLDIR)/rtl_gdb_jtag_boot_com_openocd.txt $(FLASHDOWNLOAD_TOOLDIR)/rtl_gdb_jtag_boot_com.txt
else
cp -p $(FLASH_TOOLDIR)/rtl_gdb_debug_jlink.txt $(FLASH_TOOLDIR)/rtl_gdb_debug.txt
cp -p $(DEBUG_TOOLDIR)/rtl_gdb_debug_jlink.txt $(DEBUG_TOOLDIR)/rtl_gdb_debug.txt
cp -p $(FLASH_TOOLDIR)/rtl_gdb_ramdebug_jlink.txt $(FLASH_TOOLDIR)/rtl_gdb_ramdebug.txt
cp -p $(FLASH_TOOLDIR)/rtl_gdb_flash_write_jlink.txt $(FLASH_TOOLDIR)/rtl_gdb_flash_write.txt
cp -p $(FLASHDOWNLOAD_TOOLDIR)/rtl_gdb_jtag_boot_com_jlink.txt $(FLASHDOWNLOAD_TOOLDIR)/rtl_gdb_jtag_boot_com.txt
endif
.PHONY: flashburn
flashburn:
@if [ ! -f $(FLASHDOWNLOAD_TOOLDIR)/rtl_gdb_flash_write.txt ] ; then echo Please do \"make setup GDB_SERVER=[jlink or openocd]\" first; echo && false ; fi
ifeq ($(findstring CYGWIN, $(OS)), CYGWIN)
$(FLASHDOWNLOAD_TOOLDIR)/Check_Jtag.sh
endif
cp $(FLASHDOWNLOAD_TOOLDIR)/target_FPGA.axf $(FLASH_TOOLDIR)/target_NORMAL.axf
# cp $(FLASH_TOOLDIR)/target_NORMALB.axf $(FLASH_TOOLDIR)/target_NORMAL.axf
chmod 777 $(FLASHDOWNLOAD_TOOLDIR)/target_NORMAL.axf
chmod +rx $(FLASHDOWNLOAD_TOOLDIR)/SetupGDB_NORMAL.sh
$(FLASHDOWNLOAD_TOOLDIR)/SetupGDB_NORMAL.sh
$(GDB) -x $(FLASHDOWNLOAD_TOOLDIR)/rtl_gdb_flash_write.txt
.PHONY: debug
debug:
@if [ ! -f $(DEBUG_TOOLDIR)/rtl_gdb_debug.txt ] ; then echo Please do \"make setup GDB_SERVER=[jlink or openocd]\" first; echo && false ; fi
ifeq ($(findstring CYGWIN, $(OS)), CYGWIN)
$(DEBUG_TOOLDIR)/Check_Jtag.sh
cmd /c start $(GDB) -x $(DEBUG_TOOLDIR)/rtl_gdb_debug.txt
else
$(GDB) -x $(DEBUG_TOOLDIR)/rtl_gdb_debug.txt
endif
.PHONY: ramdebug
ramdebug:
@if [ ! -f $(FLASH_TOOLDIR)/rtl_gdb_ramdebug.txt ] ; then echo Please do \"make setup GDB_SERVER=[jlink or openocd]\" first; echo && false ; fi
ifeq ($(findstring CYGWIN, $(OS)), CYGWIN)
$(FLASH_TOOLDIR)/Check_Jtag.sh
cmd /c start $(GDB) -x $(FLASH_TOOLDIR)/rtl_gdb_ramdebug.txt
else
$(GDB) -x $(FLASH_TOOLDIR)/rtl_gdb_ramdebug.txt
endif
.PHONY: clean
clean:
rm -rf $(TARGET)
rm -f $(SRC_O) $(DRAM_O)
rm -f $(patsubst %.o,%.d,$(SRC_O)) $(patsubst %.o,%.d,$(DRAM_O))

1427
project/realtek_amebaz_va0_example/GCC-RELEASE/export-rom_symbol_v01.txt Normal file
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157
project/realtek_amebaz_va0_example/GCC-RELEASE/rlx8711B-symbol-v02-img2_xip1.ld Normal file
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ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x2B000 /* MAIN RAM: 228 */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 32k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x08080000+0x20, LENGTH = 0x75000-0x20 /* XIP2: 468k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
*(.heap.stdlib*)
} > BD_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text*)
*(.rodata*)
*(.debug_trace*)
__flash_text_end__ = .;
. = ALIGN (16);
} > XIP1
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}

157
project/realtek_amebaz_va0_example/GCC-RELEASE/rlx8711B-symbol-v02-img2_xip2.ld Normal file
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ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x2B000 /* MAIN RAM: 228 */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 32k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x08080000+0x20, LENGTH = 0x75000-0x20 /* XIP2: 468k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
*(.heap.stdlib*)
} > BD_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text*)
*(.rodata*)
*(.debug_trace*)
__flash_text_end__ = .;
. = ALIGN (16);
} > XIP2
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}

2
project/realtek_amebaz_va0_example/GCC-RELEASE/run_openocd.bat Normal file
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taskkill /F /IM openocd.exe
openocd -f interface\cmsis-dap.cfg -f ..\..\..\component\soc\realtek\8711b\misc\gcc_utility\openocd\amebaz.cfg

21
project/realtek_amebaz_va0_example/GCC-RELEASE/run_openocd.sh Normal file
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#!/bin/sh
OS=`uname | cut -c 1-6`
PID=`ps aux | grep openocd | gawk '{print $1}'`
if [ ! -z "$PID" -a "$PID" != " " ]; then
echo Found openocd running, Kill it
kill $PID
else
if [ $OS == CYGWIN ]; then
echo Try to search windows process
PID=`ps --windows | grep openocd | gawk '{print $1}'`
if [ -n PID ]; then
echo Found openocd running, Kill it
taskkill /F /pid $PID
fi
fi
fi
openocd -f interface/cmsis-dap.cfg -f ../../../component/soc/realtek/8711b/misc/gcc_utility/openocd/amebaz.cfg

24
project/realtek_amebaz_va0_example/example_sources/adc_one_shot/Makefile Normal file
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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

6
project/realtek_amebaz_va0_example/example_sources/adc_one_shot/readme.txt Normal file
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Example Description
This example describes how to use adc one shot mode.
Requirement Components:
None

52
project/realtek_amebaz_va0_example/example_sources/adc_one_shot/src/Makefile Normal file
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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

71
project/realtek_amebaz_va0_example/example_sources/adc_one_shot/src/main.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "analogin_api.h"
#include <sys_api.h>
void adc_isr(void *Data)
{
u32 buf[30];
u32 isr = 0;
u32 i = 0;
isr = ADC_GetISR();
if (isr & BIT_ADC_FIFO_THRESHOLD) {
for(i = 0; i < 30; i++) {
buf[i] = (u32)ADC_Read();
}
}
ADC_INTClear();
DBG_8195A("0x%08x, 0x%08x\n", buf[0], buf[1]);
}
VOID adc_one_shot (VOID)
{
ADC_InitTypeDef ADCInitStruct;
/* ADC Interrupt Initialization */
InterruptRegister((IRQ_FUN)&adc_isr, ADC_IRQ, (u32)NULL, 5);
InterruptEn(ADC_IRQ, 5);
/* To release ADC delta sigma clock gating */
PLL2_Set(BIT_SYS_SYSPLL_CK_ADC_EN, ENABLE);
/* Turn on ADC active clock */
RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
ADC_InitStruct(&ADCInitStruct);
ADCInitStruct.ADC_BurstSz = 8;
ADCInitStruct.ADC_OneShotTD = 8; /* means 4 times */
ADC_Init(&ADCInitStruct);
ADC_SetOneShot(ENABLE, 100, ADCInitStruct.ADC_OneShotTD); /* 100 will task 200ms */
ADC_INTClear();
ADC_Cmd(ENABLE);
vTaskDelete(NULL);
}
void main(void)
{
if(xTaskCreate( (TaskFunction_t)adc_one_shot, "ADC ONE SHOT DEMO", (2048/4), NULL, (tskIDLE_PRIORITY + 1), NULL)!= pdPASS) {
DBG_8195A("Cannot create ADC one shot demo task\n\r");
}
vTaskStartScheduler();
while(1);
}

24
project/realtek_amebaz_va0_example/example_sources/adc_vbat/Makefile Normal file
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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

8
project/realtek_amebaz_va0_example/example_sources/adc_vbat/readme.txt Normal file
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Example Description
This example describes how to use adc vabt channel to measure 5V vlotage.
Requirement Components:
none

52
project/realtek_amebaz_va0_example/example_sources/adc_vbat/src/Makefile Normal file
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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

67
project/realtek_amebaz_va0_example/example_sources/adc_vbat/src/main.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "analogin_api.h"
#include <sys_api.h>
/*
* OFFSET: value of measuring at 0.000v, value(0.000v)
* GAIN_DIV: value(1.000v)-value(0.000v) or value(2.000v)-value(1.000v) or value(3.000v)-value(2.000v)
*
* MSB 12bit of value is valid, need to truncate LSB 4bit (0xABCD -> 0xABC). OFFSET and GAIN_DIV are truncated values.
*/
/* Vbat channel */
#define OFFSET 0x496
#define GAIN_DIV 0xBA
#define AD2MV(ad,offset,gain) (((ad >> 4) -offset) * 1000 / gain)
void adc_delay(void)
{
int i;
for(i=0;i<1600000;i++)
asm(" nop");
}
void adc_vbat_en(void)
{
uint16_t adc_read = 0;
int32_t voltage;
analogin_t adc_vbat;
analogin_init(&adc_vbat, AD_2);
DBG_8195A("ADC:offset = 0x%x, gain = 0x%x\n", OFFSET, GAIN_DIV);
for (;;){
adc_read = analogin_read_u16(&adc_vbat);
voltage = AD2MV(adc_read, OFFSET, GAIN_DIV);
DBG_8195A("ADC_Vbat: 0x%x = %d mv\n", adc_read, voltage);
adc_delay();
}
analogin_deinit(&adc_vbat);
vTaskDelete(NULL);
}
VOID main (VOID)
{
if(xTaskCreate( (TaskFunction_t)adc_vbat_en, "ADC VBAT DEMO", (2048/4), NULL, (tskIDLE_PRIORITY + 1), NULL)!= pdPASS) {
DBG_8195A("Cannot create ADC Vbat demo task\n\r");
}
vTaskStartScheduler();
while(1);
}

24
project/realtek_amebaz_va0_example/example_sources/adc_wakeup/Makefile Normal file
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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

13
project/realtek_amebaz_va0_example/example_sources/adc_wakeup/readme.txt Normal file
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@ -0,0 +1,13 @@
Example Description
This example describes how to use adc one shot mode wakeup.
Requirement Components:
The following modules in rtl8710b_sleepcfg.c need to be set to ON before compile:
(1) BIT_SYSON_PMOPT_SNZ_XTAL_EN and BIT_SYSON_PMOPT_SNZ_SYSPLL_EN of sleep_pwrmgt_config(global variable)
(2) BIT_SYSON_WEVT_ADC_MSK of sleep_wevent_config(global variable)
Operating process:
- Boot up device, and wait around 1 second, device will enter sleep mode, and the registered suspend function will called automatically.
- ADC scan each channel every 200ms.When adc fifo data size is more than 8, adc wakes up CPU and the registered resume function will be called automatically.
- Then system will enter sleep again until next one shot mode interrupt occurs.

52
project/realtek_amebaz_va0_example/example_sources/adc_wakeup/src/Makefile Normal file
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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

93
project/realtek_amebaz_va0_example/example_sources/adc_wakeup/src/main.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "analogin_api.h"
#include <sys_api.h>
u32 adc_buf[8];
void adc_isr(void *Data)
{
u32 isr = 0;
u32 i = 0;
isr = ADC_GetISR();
if (isr & BIT_ADC_FIFO_THRESHOLD) {
for(i = 0; i < 8; i++) {
adc_buf[i] = (u32)ADC_Read();
}
}
ADC_INTClear();
}
static u32 adc_suspend(u32 expected_idle_time )
{
ADC_INTClear();
ADC_Cmd(ENABLE);
return TRUE;
}
static u32 adc_resume(u32 expected_idle_time)
{
u32 i = 0;
ADC_Cmd(DISABLE);
for (i = 0; i < 8; i += 2) {
DBG_8195A("%08x, %08x\n", adc_buf[i], adc_buf[i + 1]);
adc_buf[i] = 0;
adc_buf[i+1] = 0;
}
return TRUE;
}
VOID adc_wakeup (VOID)
{
ADC_InitTypeDef ADCInitStruct;
/* ADC Interrupt Initialization */
InterruptRegister((IRQ_FUN)&adc_isr, ADC_IRQ, (u32)NULL, 5);
InterruptEn(ADC_IRQ, 5);
/* To release ADC delta sigma clock gating */
PLL2_Set(BIT_SYS_SYSPLL_CK_ADC_EN, ENABLE);
/* Turn on ADC active clock */
RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
ADC_InitStruct(&ADCInitStruct);
ADCInitStruct.ADC_BurstSz = 8;
ADCInitStruct.ADC_OneShotTD = 8; /* means 4 times */
ADC_Init(&ADCInitStruct);
ADC_SetOneShot(ENABLE, 100, ADCInitStruct.ADC_OneShotTD); /* 100 will task 200ms */
pmu_register_sleep_callback(PMU_ADC_DEVICE, (PSM_HOOK_FUN)adc_suspend, (void*)NULL, (PSM_HOOK_FUN)adc_resume, (void*)NULL);
pmu_sysactive_timer_init();
pmu_set_sysactive_time(PMU_ADC_DEVICE, 1000);
pmu_release_wakelock(PMU_OS);
vTaskDelete(NULL);
}
void main(void)
{
if(xTaskCreate( (TaskFunction_t)adc_wakeup, "ADC WAKEUP DEMO", (2048/4), NULL, (tskIDLE_PRIORITY + 1), NULL)!= pdPASS) {
DBG_8195A("Cannot create ADC wakeup demo task\n\r");
}
vTaskStartScheduler();
while(1);
}

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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

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Example Description
This example describes how to use ADC normal channel.
Prcedure:
1.Plug in macro USB to DUT.
2.Run main code for the test.
3.Make connection via DuPont Line as specified in the above figure:
1) AD0 GND: Make a DuPont Line to A19 and ground.
2) AD0 3.3V: Make a DuPont Line to A19 and 3.3V.
3) AD2 GND: Make a DuPont Line to A20 and ground.
4) AD2 3.3V: Make a DuPont Line to A20 and 3.3V.
4.Record the all ADC output values.
AD0:4131 = -5 mv, AD2:8096 = 1209 mv
AD0:4132 = -5 mv, AD2:8090 = 1209 mv
AD0:4133 = -5 mv, AD2:8094 = 1209 mv
AD0:4133 = -5 mv, AD2:8094 = 1209 mv
Results:
1. ADC0 GND:
1) AD0 voltage value approaches 0
2) AD1 voltage value is around 184mv
3) AD2 voltage value is around 1200mv
2. ADC0 3.3v:
1) AD0 voltage value approaches 3300mv
2) AD1 voltage value is around 184mv
3) AD2 voltage value is around 1200mv
3. ADC1 GND:
1) AD0 voltage value is around 1200mv
2) AD1 voltage value is around 184mv
3) AD2 voltage value approaches 0
4. ADC1 3.3v:
1) AD0 voltage value is around 1200mv
2) AD1 voltage value is around 184mv
3) AD2 voltage value approaches 3300mv
NOTE:
1. For 8710BN EVB, AD0 and AD1 are available. AD2 is not avaliable.
For 8711BN EVB, AD0 and AD2 are available. AD1 is not available.
For 8711BG EVB, AD0 and AD1 and AD2 are all avaliable.
2. AD1(VBAT) calibration parameters(gain & offset) are different with normal channel need modify OFFSET and GAIN_DI Vcalibration to get correct voltage value.

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "analogin_api.h"
#include <sys_api.h>
#define ADC_CALIBRATION 0
#if defined (__ICCARM__)
analogin_t adc0;
analogin_t adc2;
#else
volatile analogin_t adc0;
volatile analogin_t adc2;
#endif
void adc_delay(void)
{
int i;
for(i=0;i<1600000;i++)
asm(" nop");
}
uint16_t adcdat0 = 0;
uint16_t adcdat2 = 0;
int32_t v_mv0;
int32_t v_mv2;
/*
* OFFSET: value of measuring at 0.000v, value(0.000v)
* GAIN_DIV: value(1.000v)-value(0.000v) or value(2.000v)-value(1.000v) or value(3.000v)-value(2.000v)
*
* MSB 12bit of value is valid, need to truncate LSB 4bit (0xABCD -> 0xABC). OFFSET and GAIN_DIV are truncated values.
*/
/* Normal channel*/
#define OFFSET 0x0418
#define GAIN_DIV 0x342
#define AD2MV(ad,offset,gain) (((ad/16)-offset)*1000/gain)
VOID
main (
VOID
)
{
uint16_t offset, gain;
analogin_init(&adc0, AD_1);
analogin_init(&adc2, AD_3);
#if ADC_CALIBRATION
sys_adc_calibration(0, &offset, &gain);
printf("ADC:offset = 0x%x, gain = 0x%x\n", offset, gain);
if((offset==0xFFFF) || (gain==0xFFFF))
#endif
{
offset = OFFSET;
gain = GAIN_DIV;
printf("ADC:offset = 0x%x, gain = 0x%x\n", offset, gain);
}
for (;;){
adcdat0 = analogin_read_u16(&adc0);
adcdat2 = analogin_read_u16(&adc2);
v_mv0 = AD2MV(adcdat0, offset, gain);
v_mv2 = AD2MV(adcdat2, offset, gain);
printf("AD0:%x = %d mv, AD2:%x = %d mv\n", adcdat0, v_mv0, adcdat2, v_mv2);
adc_delay();
}
analogin_deinit(&adc0);
analogin_deinit(&adc2);
}

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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

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Example Description
This example describes how to use backup register.
Requirement Components:
none

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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "analogin_api.h"
#include <sys_api.h>
#define TEST_BIT BIT(0)
void backup_register(void)
{
u32 value_bk0 = BKUP_Read(BKUP_REG0);
u32 value_bk3 = BKUP_Read(BKUP_REG3);
if(value_bk0 & BIT_CPU_RESET_HAPPEN){ //system reboot
if(value_bk3 & TEST_BIT){
DBG_8195A("Backup Register function test ok.\n");
BKUP_Clear(BKUP_REG3, TEST_BIT);
}
}
else{
BKUP_Set(BKUP_REG3, TEST_BIT);
DBG_8195A("\nRebooting ...\n");
NVIC_SystemReset();
}
vTaskDelete(NULL);
}
void main(void)
{
if(xTaskCreate( (TaskFunction_t)backup_register, "BACKUP REG DEMO", (2048/4), NULL, (tskIDLE_PRIORITY + 1), NULL)!= pdPASS) {
DBG_8195A("Cannot create Backup register demo task\n\r");
}
vTaskStartScheduler();
while(1);
}

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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

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Example Description
This example describes how to use Bor2 Brown-Out Reset.
Requirement Components:
a USB to TTL Adapter
Operating process:
- Remove R43 on the demo board
- Give 3.3V at pin that near the chip of J34 by power supply.
- Boot up device, and you will see the log"Supply 2.6V-3.0V voltage!!!"
- Change 3.3V to 2.6V-3.0V to trigger Bor2 Interrupt,and will call the registered "bor_intr_Handler"
- Recover voltage to 3.3V
Note:
- Never give 3.3V at the other pin of J34

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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

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/*
* Routines to access hardware
*
* Copyright (c) 2015 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "gpio_api.h" // mbed
#include "gpio_irq_api.h" // mbed
#include "sleep_ex_api.h"
#include "sys_api.h"
#include "diag.h"
#include "main.h"
void bor_intr_Handler(void)
{
DBG_8195A("bor_intr_handler!!!\n");
}
void bor2_test(void)
{
// mbed BOR2 test
BOR2_ModeSet(BOR2_INTR);
BOR2_INTRegister((void *)bor_intr_Handler);
BOR2_INTCmd(ENABLE);
DBG_8195A("Supply 2.6V-3.0V voltage!!!\n");
vTaskDelete(NULL);
}
void main(void)
{
// create demo Task
if(xTaskCreate( (TaskFunction_t)bor2_test, "BOR2 DEMO", (2048/4), NULL, (tskIDLE_PRIORITY + 1), NULL)!= pdPASS) {
DBG_8195A("Cannot create bor2 demo task\n\r");
goto end_demo;
}
#if defined(CONFIG_KERNEL) && !TASK_SCHEDULER_DISABLED
#ifdef PLATFORM_FREERTOS
vTaskStartScheduler();
#endif
#else
#error !!!Need FREERTOS!!!
#endif
end_demo:
while(1);
}

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Example Description
This example describes how to use CRYPTO function, it is based on cutomer requirement modified.
use Arduino board to test, and it will show at console

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "FreeRTOS.h"
#include "task.h"
#include "device.h"
#include "serial_api.h"
#include "hal_crypto.h"
#include "main.h"
#include "diag.h"
#include <polarssl/aes.h>
#define STACKSIZE 2048
//static const u8 plaintext[] = "The quick brown fox jumps over the lazy dog";
//static const u8 md5_digest[] = "\x9e\x10\x7d\x9d\x37\x2b\xb6\x82"
// "\x6b\xd8\x1d\x35\x42\xa4\x19\xd6";
//static const u8 md5_key[] = "key";
static unsigned char plaintext[] = "12345678901234567890123456789012345678901234567890123456789012" \
"345678901234567890";
static const char md5_digest[] = { 0x57, 0xED, 0xF4, 0xA2, 0x2B, 0xE3, 0xC9, 0x55,
0xAC, 0x49, 0xDA, 0x2E, 0x21, 0x07, 0xB6, 0x7A };
static u8 md5_key[] = "key";
static unsigned char md5_test_buf[16][128] =
{
{ "" },
{ "a" },
{ "abc" },
{ "message digest" },
{ "abcdefghijklmnopqrstuvwxyz" },
{ "The quick brown fox jumps over the lazy dog" },
{ "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789" },
{ "12345678901234567890123456789012345678901234567890123456789012" \
"345678901234567890" },
{ "" },
{ "a" },
{ "abc" },
{ "message digest" },
{ "abcdefghijklmnopqrstuvwxyz" },
{ "The quick brown fox jumps over the lazy dog" },
{ "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789" },
{ "12345678901234567890123456789012345678901234567890123456789012" \
"345678901234567890" }
};
static const int md5_test_buflen[16] =
{
0, 1, 3, 14, 26, 43, 62, 80, 0, 1, 3, 14, 26, 43, 62, 80
};
static const unsigned char md5_test_sum[16][16] =
{
{ 0xD4, 0x1D, 0x8C, 0xD9, 0x8F, 0x00, 0xB2, 0x04,
0xE9, 0x80, 0x09, 0x98, 0xEC, 0xF8, 0x42, 0x7E },
{ 0x0C, 0xC1, 0x75, 0xB9, 0xC0, 0xF1, 0xB6, 0xA8,
0x31, 0xC3, 0x99, 0xE2, 0x69, 0x77, 0x26, 0x61 },
{ 0x90, 0x01, 0x50, 0x98, 0x3C, 0xD2, 0x4F, 0xB0,
0xD6, 0x96, 0x3F, 0x7D, 0x28, 0xE1, 0x7F, 0x72 },
{ 0xF9, 0x6B, 0x69, 0x7D, 0x7C, 0xB7, 0x93, 0x8D,
0x52, 0x5A, 0x2F, 0x31, 0xAA, 0xF1, 0x61, 0xD0 },
{ 0xC3, 0xFC, 0xD3, 0xD7, 0x61, 0x92, 0xE4, 0x00,
0x7D, 0xFB, 0x49, 0x6C, 0xCA, 0x67, 0xE1, 0x3B },
{"\x9e\x10\x7d\x9d\x37\x2b\xb6\x82"
"\x6b\xd8\x1d\x35\x42\xa4\x19\xd6"},
{ 0xD1, 0x74, 0xAB, 0x98, 0xD2, 0x77, 0xD9, 0xF5,
0xA5, 0x61, 0x1C, 0x2C, 0x9F, 0x41, 0x9D, 0x9F },
{ 0x57, 0xED, 0xF4, 0xA2, 0x2B, 0xE3, 0xC9, 0x55,
0xAC, 0x49, 0xDA, 0x2E, 0x21, 0x07, 0xB6, 0x7A },
{ 0xD4, 0x1D, 0x8C, 0xD9, 0x8F, 0x00, 0xB2, 0x04,
0xE9, 0x80, 0x09, 0x98, 0xEC, 0xF8, 0x42, 0x7E },
{ 0x0C, 0xC1, 0x75, 0xB9, 0xC0, 0xF1, 0xB6, 0xA8,
0x31, 0xC3, 0x99, 0xE2, 0x69, 0x77, 0x26, 0x61 },
{ 0x90, 0x01, 0x50, 0x98, 0x3C, 0xD2, 0x4F, 0xB0,
0xD6, 0x96, 0x3F, 0x7D, 0x28, 0xE1, 0x7F, 0x72 },
{ 0xF9, 0x6B, 0x69, 0x7D, 0x7C, 0xB7, 0x93, 0x8D,
0x52, 0x5A, 0x2F, 0x31, 0xAA, 0xF1, 0x61, 0xD0 },
{ 0xC3, 0xFC, 0xD3, 0xD7, 0x61, 0x92, 0xE4, 0x00,
0x7D, 0xFB, 0x49, 0x6C, 0xCA, 0x67, 0xE1, 0x3B },
{"\x9e\x10\x7d\x9d\x37\x2b\xb6\x82"
"\x6b\xd8\x1d\x35\x42\xa4\x19\xd6"},
{ 0xD1, 0x74, 0xAB, 0x98, 0xD2, 0x77, 0xD9, 0xF5,
0xA5, 0x61, 0x1C, 0x2C, 0x9F, 0x41, 0x9D, 0x9F },
{ 0x57, 0xED, 0xF4, 0xA2, 0x2B, 0xE3, 0xC9, 0x55,
0xAC, 0x49, 0xDA, 0x2E, 0x21, 0x07, 0xB6, 0x7A },
};
u8 digest[64];
u8 cipher_result[2048];
u8 test_result[1024];
serial_t sobj;
/*
*
*
* This test_md5 function is used to test hardware md5 functoinality
*/
void test_md5(void)
{
int i;
int ret;
u8 md5sum[16];
DiagPrintf("MD5 test\r\n");
ret = rtl_crypto_md5(plaintext, strlen(plaintext), (unsigned char *)&digest); // the length of MD5's digest is 16 bytes.
if ( _memcmp(digest, md5_digest, 16) == 0 ) {
DiagPrintf("MD5 test result is correct, ret=%d\r\n", ret);
} else {
DiagPrintf("MD5 test result is WRONG!!, ret=%d\r\n", ret);
}
for( i = 0; i < 16; i++ )
{
DiagPrintf( " MD5 test #%d: ", i + 1 );
ret = rtl_crypto_md5(md5_test_buf[i], md5_test_buflen[i], md5sum); // the length of MD5's digest is 16 bytes.
DiagPrintf(" MD5 ret=%d\n", ret);
if( _memcmp( md5sum, md5_test_sum[i], 16 ) != 0 )
{
DiagPrintf( "failed\n" );
memset(md5sum,0,16);
}
else{
DiagPrintf( "passed\n" );
memset(md5sum,0,16);}
}
}
//
// vector : AES CBC 128 bit :
// http://www.inconteam.com/software-development/41-encryption/55-aes-test-vectors#aes-cbc-128
//
//#ifdef __ICCARM__
//#pragma data_alignment = 4
//#elif defined (__GNUC__)
//__attribute__ ((aligned (4)))
//#endif
static unsigned char aes_test_key[16] =
{
0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6,
0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c
} ;
//#ifdef __ICCARM__
//#pragma data_alignment = 4
//#elif defined (__GNUC__)
//__attribute__ ((aligned (4)))
//#endif
static unsigned char aes_test_iv_1[16] =
{
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
};
static unsigned char aes_test_buf[16] =
{
0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
};
static unsigned char aes_test_ecb_buf[160] =
{
0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a
};
static const unsigned char aes_test_res_128[16] =
{
0x76, 0x49, 0xab, 0xac, 0x81, 0x19, 0xb2, 0x46,
0xce, 0xe9, 0x8e, 0x9b, 0x12, 0xe9, 0x19, 0x7d
};
static const unsigned char aes_test_ecb_res_128[160] =
{
0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60,
0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97,
0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60,
0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97,
0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60,
0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97,
0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60,
0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97,
0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60,
0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97,
0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60,
0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97,
0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60,
0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97,
0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60,
0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97,
0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60,
0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97,
0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60,
0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97
};
/*
*
* THis test_aes_cbc function is use to directly test hardware aes cbc crypto functionality
*
*/
int test_aes_cbc(void)
{
const u8 *key, *pIv;
u32 keylen= 0;
u32 ivlen = 0;
u8 *message;
u32 msglen;
u8 *pResult;
int ret;
DiagPrintf("AES CBC test\r\n");
key = aes_test_key;
keylen = 16;
pIv = aes_test_iv_1;
ivlen = 16;
pResult = cipher_result;
message = (unsigned char *)aes_test_buf;
msglen = sizeof(aes_test_buf);
ret = rtl_crypto_aes_cbc_init(key,keylen);
if ( ret != 0 ) {
DiagPrintf("AES CBC init failed\r\n");
return ret;
}
ret = rtl_crypto_aes_cbc_encrypt(message, msglen, pIv, ivlen, pResult);
if ( ret != 0 ) {
DiagPrintf("AES CBC encrypt failed\r\n");
return ret;
}
if ( _memcmp(aes_test_res_128, pResult, msglen) == 0 ) {
DiagPrintf("AES CBC encrypt result success\r\n");
} else {
DiagPrintf("AES CBC encrypt result failed\r\n");
}
message = pResult;
ret = rtl_crypto_aes_cbc_decrypt(message, msglen, pIv, ivlen, pResult);
if ( ret != 0 ) {
DiagPrintf("AES CBC decrypt failed, ret=%d\r\n", ret);
return ret;
}
if ( _memcmp(aes_test_buf, pResult, msglen) == 0 ) {
DiagPrintf("AES CBC decrypt result success\r\n");
} else {
DiagPrintf("AES CBC decrypt result failed\r\n");
}
return 0;
}
/*
*
* THis test_aes_ecb function is use to directly test hardware ecb cbc crypto functionality
*
* The input parameter for ecb need to confirm iv is null and ivlen is 0
*/
int test_aes_ecb(void)
{
const u8 *key, *pIv;
u32 keylen= 0;
u32 ivlen = 0;
u8 *message;
u32 msglen;
u8 *pResult;
int ret;
DiagPrintf("AES ECB test\r\n");
key = aes_test_key;
keylen = 16;
pIv = NULL;
ivlen = 0;
pResult = cipher_result;
message = (unsigned char *)aes_test_ecb_buf;
msglen = sizeof(aes_test_buf);
//for(int i=0;i<msglen;i++)
//printf("\r\n first message[%d] = %p,",i,message[i]);
ret = rtl_crypto_aes_ecb_init(key,keylen);
if ( ret != 0 ) {
DiagPrintf("AES ECB init failed\r\n");
return ret;
}
ret = rtl_crypto_aes_ecb_encrypt(message, msglen, pIv, ivlen, pResult);
if ( ret != 0 ) {
DiagPrintf("AES ECB encrypt failed\r\n");
return ret;
}
if ( _memcmp(aes_test_ecb_res_128, pResult, msglen) == 0 )
{
DiagPrintf("AES ECB encrypt result success\r\n");
}
else {
DiagPrintf("AES ECB encrypt result failed\r\n");
}
message = pResult;
//for(int i=0;i<msglen;i++)
//printf("\r\n second message[%d] = %p,",i,message[i]);
ret = rtl_crypto_aes_ecb_decrypt(message, msglen, pIv, ivlen, pResult);
if ( ret != 0 ) {
DiagPrintf("AES ECB decrypt failed, ret=%d\r\n", ret);
return ret;
}
if ( _memcmp(aes_test_ecb_buf, pResult, msglen) == 0 )
{
DiagPrintf("AES ECB decrypt result success\r\n");
}
else {
DiagPrintf("AES ECB decrypt result failed\r\n");
}
//for(int i=0;i<msglen;i++)
//printf("\r\n last message[%d] = %p,",i,message[i]);
return 0;
}
void main(void)
{
// sample text
char rc;
//
int ret;
int loop=0;
u32 keylen= 0;
u32 ivlen = 0;
u8 *pResult;
u8 *message;
u32 *ResultLen;
u32 msglen = 0;
const u8 *key, *pIv;
key = aes_test_key;
keylen = 16;
pIv = aes_test_iv_1;
ivlen = 16;
//
message = (unsigned char *)aes_test_buf;
msglen = sizeof(aes_test_buf);
DiagPrintf("CRYPTO API Demo...\r\n");
if ( rtl_cryptoEngine_init() != 0 ) {
DiagPrintf("crypto engine init failed\r\n");
}
else
printf("init success\n");
pResult = test_result;
test_md5();
test_aes_cbc();
test_aes_ecb();
//aes_test(); //added api combined aes_cbc setkey and cryption into one function
while(1);
}

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project/realtek_amebaz_va0_example/example_sources/crypto/Makefile Normal file
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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

51
project/realtek_amebaz_va0_example/example_sources/crypto/readme.txt Normal file
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Example Description
It basically verifies hardware encryption/decryption functions and show results on the LOG_OUT.
1. Plug in macro USB to DUT.
2. use Arduino board to test, and it will show at console
3. check if the console result is right.
The expected result is in the serial terminal which has logs as below:
sleep 10 sec. to wait for UART console
CRYPTO API Demo...
MD5 test
MD5 test result is correct, ret=0
MD5 test #1: MD5 ret=0
passed
MD5 test #2: MD5 ret=0
passed
MD5 test #3: MD5 ret=0
passed
MD5 test #4: MD5 ret=0
passed
MD5 test #5: MD5 ret=0
passed
MD5 test #6: MD5 ret=0
passed
MD5 test #7: MD5 ret=0
passed
MD5 test #8: MD5 ret=0
passed
MD5 test #9: MD5 ret=0
passed
MD5 test #10: MD5 ret=0
passed
MD5 test #11: MD5 ret=0
passed
MD5 test #12: MD5 ret=0
passed
MD5 test #13: MD5 ret=0
passed
MD5 test #14: MD5 ret=0
passed
MD5 test #15: MD5 ret=0
passed
MD5 test #16: MD5 ret=0
passed
AES CBC test
AES CBC encrypt result success
AES CBC decrypt result success

52
project/realtek_amebaz_va0_example/example_sources/crypto/src/Makefile Normal file
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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "serial_api.h"
#include "hal_crypto.h"
#include "main.h"
#include "diag.h"
//static const u8 plaintext[] = "The quick brown fox jumps over the lazy dog";
//static const u8 md5_digest[] = "\x9e\x10\x7d\x9d\x37\x2b\xb6\x82"
// "\x6b\xd8\x1d\x35\x42\xa4\x19\xd6";
//static const u8 md5_key[] = "key";
static unsigned char plaintext[] = "12345678901234567890123456789012345678901234567890123456789012" \
"345678901234567890";
static const char md5_digest[] = { 0x57, 0xED, 0xF4, 0xA2, 0x2B, 0xE3, 0xC9, 0x55,
0xAC, 0x49, 0xDA, 0x2E, 0x21, 0x07, 0xB6, 0x7A };
static u8 md5_key[] = "key";
static unsigned char md5_test_buf[16][81] =
{
{ "" },
{ "a" },
{ "abc" },
{ "message digest" },
{ "abcdefghijklmnopqrstuvwxyz" },
{ "The quick brown fox jumps over the lazy dog" },
{ "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789" },
{ "12345678901234567890123456789012345678901234567890123456789012" \
"345678901234567890" },
{ "" },
{ "a" },
{ "abc" },
{ "message digest" },
{ "abcdefghijklmnopqrstuvwxyz" },
{ "The quick brown fox jumps over the lazy dog" },
{ "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789" },
{ "12345678901234567890123456789012345678901234567890123456789012" \
"345678901234567890" }
};
static const int md5_test_buflen[16] =
{
0, 1, 3, 14, 26, 43, 62, 80, 0, 1, 3, 14, 26, 43, 62, 80
};
static const unsigned char md5_test_sum[16][16] =
{
{ 0xD4, 0x1D, 0x8C, 0xD9, 0x8F, 0x00, 0xB2, 0x04,
0xE9, 0x80, 0x09, 0x98, 0xEC, 0xF8, 0x42, 0x7E },
{ 0x0C, 0xC1, 0x75, 0xB9, 0xC0, 0xF1, 0xB6, 0xA8,
0x31, 0xC3, 0x99, 0xE2, 0x69, 0x77, 0x26, 0x61 },
{ 0x90, 0x01, 0x50, 0x98, 0x3C, 0xD2, 0x4F, 0xB0,
0xD6, 0x96, 0x3F, 0x7D, 0x28, 0xE1, 0x7F, 0x72 },
{ 0xF9, 0x6B, 0x69, 0x7D, 0x7C, 0xB7, 0x93, 0x8D,
0x52, 0x5A, 0x2F, 0x31, 0xAA, 0xF1, 0x61, 0xD0 },
{ 0xC3, 0xFC, 0xD3, 0xD7, 0x61, 0x92, 0xE4, 0x00,
0x7D, 0xFB, 0x49, 0x6C, 0xCA, 0x67, 0xE1, 0x3B },
{"\x9e\x10\x7d\x9d\x37\x2b\xb6\x82"
"\x6b\xd8\x1d\x35\x42\xa4\x19\xd6"},
{ 0xD1, 0x74, 0xAB, 0x98, 0xD2, 0x77, 0xD9, 0xF5,
0xA5, 0x61, 0x1C, 0x2C, 0x9F, 0x41, 0x9D, 0x9F },
{ 0x57, 0xED, 0xF4, 0xA2, 0x2B, 0xE3, 0xC9, 0x55,
0xAC, 0x49, 0xDA, 0x2E, 0x21, 0x07, 0xB6, 0x7A },
{ 0xD4, 0x1D, 0x8C, 0xD9, 0x8F, 0x00, 0xB2, 0x04,
0xE9, 0x80, 0x09, 0x98, 0xEC, 0xF8, 0x42, 0x7E },
{ 0x0C, 0xC1, 0x75, 0xB9, 0xC0, 0xF1, 0xB6, 0xA8,
0x31, 0xC3, 0x99, 0xE2, 0x69, 0x77, 0x26, 0x61 },
{ 0x90, 0x01, 0x50, 0x98, 0x3C, 0xD2, 0x4F, 0xB0,
0xD6, 0x96, 0x3F, 0x7D, 0x28, 0xE1, 0x7F, 0x72 },
{ 0xF9, 0x6B, 0x69, 0x7D, 0x7C, 0xB7, 0x93, 0x8D,
0x52, 0x5A, 0x2F, 0x31, 0xAA, 0xF1, 0x61, 0xD0 },
{ 0xC3, 0xFC, 0xD3, 0xD7, 0x61, 0x92, 0xE4, 0x00,
0x7D, 0xFB, 0x49, 0x6C, 0xCA, 0x67, 0xE1, 0x3B },
{"\x9e\x10\x7d\x9d\x37\x2b\xb6\x82"
"\x6b\xd8\x1d\x35\x42\xa4\x19\xd6"},
{ 0xD1, 0x74, 0xAB, 0x98, 0xD2, 0x77, 0xD9, 0xF5,
0xA5, 0x61, 0x1C, 0x2C, 0x9F, 0x41, 0x9D, 0x9F },
{ 0x57, 0xED, 0xF4, 0xA2, 0x2B, 0xE3, 0xC9, 0x55,
0xAC, 0x49, 0xDA, 0x2E, 0x21, 0x07, 0xB6, 0x7A }
};
u8 digest[64];
u8 cipher_result[1024];
serial_t sobj;
void test_md5(void)
{
int i;
int ret;
u8 md5sum[16];
DiagPrintf("MD5 test\r\n");
ret = rtl_crypto_md5(plaintext, strlen(plaintext), (unsigned char *)&digest); // the length of MD5's digest is 16 bytes.
if ( _memcmp(digest, md5_digest, 16) == 0 ) {
DiagPrintf("MD5 test result is correct, ret=%d\r\n", ret);
} else {
DiagPrintf("MD5 test result is WRONG!!, ret=%d\r\n", ret);
}
for( i = 0; i < 16; i++ )
{
DiagPrintf( " MD5 test #%d: ", i + 1 );
ret = rtl_crypto_md5(md5_test_buf[i], md5_test_buflen[i], md5sum); // the length of MD5's digest is 16 bytes.
DiagPrintf(" MD5 ret=%d\n", ret);
if( _memcmp( md5sum, md5_test_sum[i], 16 ) != 0 )
{
DiagPrintf( "failed\n" );
memset(md5sum,0,16);
}
else{
DiagPrintf( "passed\n" );
memset(md5sum,0,16);}
}
}
//
// vector : AES CBC 128 bit :
// http://www.inconteam.com/software-development/41-encryption/55-aes-test-vectors#aes-cbc-128
//
#ifdef __ICCARM__
#pragma data_alignment = 4
#elif defined (__GNUC__)
__attribute__ ((aligned (4)))
#endif
static unsigned char aes_test_key[16] =
{
0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6,
0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c
} ;
#ifdef __ICCARM__
#pragma data_alignment = 4
#elif defined (__GNUC__)
__attribute__ ((aligned (4)))
#endif
static unsigned char aes_test_iv_1[16] =
{
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
};
static unsigned char aes_test_buf[16] =
{
0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a
};
static const unsigned char aes_test_res_128[16] =
{
0x76, 0x49, 0xab, 0xac, 0x81, 0x19, 0xb2, 0x46,
0xce, 0xe9, 0x8e, 0x9b, 0x12, 0xe9, 0x19, 0x7d
};
int test_aes_cbc(void)
{
const u8 *key, *pIv;
u32 keylen= 0;
u32 ivlen = 0;
u8 *message;
u32 msglen;
u8 *pResult;
int ret;
DiagPrintf("AES CBC test\r\n");
key = aes_test_key;
keylen = 16;
pIv = aes_test_iv_1;
ivlen = 16;
pResult = cipher_result;
message = (unsigned char *)aes_test_buf;
msglen = sizeof(aes_test_buf);
ret = rtl_crypto_aes_cbc_init(key,keylen);
if ( ret != 0 ) {
DiagPrintf("AES CBC init failed, ret=%d\r\n", ret);
return ret;
}
ret = rtl_crypto_aes_cbc_encrypt(message, msglen, pIv, ivlen, pResult);
if ( ret != 0 ) {
DiagPrintf("AES CBC encrypt failed, ret=%d\r\n", ret);
return ret;
}
if ( _memcmp(aes_test_res_128, pResult, msglen) == 0 ) {
DiagPrintf("AES CBC encrypt result success\r\n");
} else {
DiagPrintf("AES CBC encrypt result failed\r\n");
}
message = pResult;
ret = rtl_crypto_aes_cbc_decrypt(message, msglen, pIv, ivlen, pResult);
if ( ret != 0 ) {
DiagPrintf("AES CBC decrypt failed, ret=%d\r\n", ret);
return ret;
}
if ( _memcmp(aes_test_buf, pResult, msglen) == 0 ) {
DiagPrintf("AES CBC decrypt result success\r\n");
} else {
DiagPrintf("AES CBC decrypt result failed\r\n");
}
return 0;
}
void main(void)
{
// sample text
char rc;
//
int ret;
int loop=0;
//
DiagPrintf("sleep 10 sec. to wait for UART console\n");
//RtlMsleepOS(10000);
DiagPrintf("CRYPTO API Demo...\r\n");
if ( rtl_cryptoEngine_init() != 0 ) {
DiagPrintf("crypto engine init failed\r\n");
}
test_md5();
test_aes_cbc();
for(;;);
}

10
project/realtek_amebaz_va0_example/example_sources/efuse_mtp/readme.txt Normal file
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Example Description
This example describes how to read/write efuse in MTP.
MTP block has 32 bytes.
Requirement Components:
None

72
project/realtek_amebaz_va0_example/example_sources/efuse_mtp/src/main.c Normal file
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#include "FreeRTOS.h"
#include "task.h"
#include "diag.h"
//#include "hal_efuse.h"
#include "efuse_api.h"
#include "osdep_service.h"
#include "device_lock.h"
#define MTP_MAX_LEN 32 // The MTP max length is 32 bytes
static void efuse_mtp_task(void *param)
{
int ret;
u8 i, buf[MTP_MAX_LEN];
DBG_8195A("\nefuse MTP block: Test Start\n");
// read MTP content
_memset(buf, 0xFF, MTP_MAX_LEN);
device_mutex_lock(RT_DEV_LOCK_EFUSE);
efuse_mtp_read(buf);
device_mutex_unlock(RT_DEV_LOCK_EFUSE);
for(i=0; i<MTP_MAX_LEN; i+=8){
DBG_8195A("[%d]\t%02X %02X %02X %02X %02X %02X %02X %02X\n",
i, buf[i], buf[i+1], buf[i+2], buf[i+3], buf[i+4], buf[i+5], buf[i+6], buf[i+7]);
}
// write MTP content
_memset(buf, 0xFF, MTP_MAX_LEN);
if(0){ // fill your data
for(i=0; i<MTP_MAX_LEN; i++)
buf[i] = i;
}
if(0){ // write
device_mutex_lock(RT_DEV_LOCK_EFUSE);
ret = efuse_mtp_write(buf, MTP_MAX_LEN);
device_mutex_unlock(RT_DEV_LOCK_EFUSE);
if(ret < 0){
DBG_8195A("efuse MTP block: write length error\n");
goto exit;
}
DBG_8195A("\nWrite Done\n");
DBG_8195A("Remain %d\n", efuse_get_remaining_length());
}
DBG_8195A("\n");
// read MTP content
_memset(buf, 0xFF, MTP_MAX_LEN);
device_mutex_lock(RT_DEV_LOCK_EFUSE);
efuse_mtp_read(buf);
device_mutex_unlock(RT_DEV_LOCK_EFUSE);
for(i=0; i<MTP_MAX_LEN; i+=8){
DBG_8195A("[%d]\t%02X %02X %02X %02X %02X %02X %02X %02X\n",
i, buf[i], buf[i+1], buf[i+2], buf[i+3], buf[i+4], buf[i+5], buf[i+6], buf[i+7]);
}
DBG_8195A("efuse MTP block: Test Done\n");
vTaskDelete(NULL);
exit:
DBG_8195A("efuse MTP block: Test Fail!\n");
vTaskDelete(NULL);
}
void main(void)
{
if(xTaskCreate(efuse_mtp_task, ((const char*)"efuse_mtp_task"), 512, NULL, tskIDLE_PRIORITY + 1, NULL) != pdPASS)
printf("\n\r%s xTaskCreate(efuse_mtp_task) failed", __FUNCTION__);
/*Enable Schedule, Start Kernel*/
if(rtw_get_scheduler_state() == OS_SCHEDULER_NOT_STARTED)
vTaskStartScheduler();
else
vTaskDelete(NULL);
}

10
project/realtek_amebaz_va0_example/example_sources/efuse_otp/readme.txt Normal file
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Example Description
This example describes how to read/write efuse in OTP.
OTP block has 32 bytes.
Requirement Components:
None

81
project/realtek_amebaz_va0_example/example_sources/efuse_otp/src/main.c Normal file
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#include "FreeRTOS.h"
#include "task.h"
#include "diag.h"
//#include "hal_efuse.h"
#include "efuse_api.h"
#include "osdep_service.h"
#include "device_lock.h"
//======================================================
// OTP : one time programming
//======================================================
#define OTP_MAX_LEN 32 // The OTP max length is 32 bytes
static void efuse_otp_task(void *param)
{
int ret;
u8 i, buf[OTP_MAX_LEN];
DBG_8195A("\nefuse OTP block: Test Start\n");
// read OTP content
device_mutex_lock(RT_DEV_LOCK_EFUSE);
ret = efuse_otp_read(0, OTP_MAX_LEN, buf);
device_mutex_unlock(RT_DEV_LOCK_EFUSE);
if(ret < 0){
DBG_8195A("efuse OTP block: read address and length error\n");
goto exit;
}
for(i=0; i<OTP_MAX_LEN; i+=8){
DBG_8195A("[%d]\t%02X %02X %02X %02X %02X %02X %02X %02X\n",
i, buf[i], buf[i+1], buf[i+2], buf[i+3], buf[i+4], buf[i+5], buf[i+6], buf[i+7]);
}
// write OTP content
_memset(buf, 0xFF, OTP_MAX_LEN);
if(0){ // fill your data
for(i=0; i<OTP_MAX_LEN; i++)
buf[i] = i;
}
if(0){ // write
device_mutex_lock(RT_DEV_LOCK_EFUSE);
ret = efuse_otp_write(0, OTP_MAX_LEN, buf);
device_mutex_unlock(RT_DEV_LOCK_EFUSE);
if(ret < 0){
DBG_8195A("efuse OTP block: write address and length error\n");
goto exit;
}
DBG_8195A("\nWrite Done.\n");
}
DBG_8195A("\n");
// read OTP content
device_mutex_lock(RT_DEV_LOCK_EFUSE);
ret = efuse_otp_read(0, OTP_MAX_LEN, buf);
device_mutex_unlock(RT_DEV_LOCK_EFUSE);
if(ret < 0){
DBG_8195A("efuse OTP block: read address and length error\n");
goto exit;
}
for(i=0; i<OTP_MAX_LEN; i+=8){
DBG_8195A("[%d]\t%02X %02X %02X %02X %02X %02X %02X %02X\n",
i, buf[i], buf[i+1], buf[i+2], buf[i+3], buf[i+4], buf[i+5], buf[i+6], buf[i+7]);
}
DBG_8195A("efuse OTP block: Test Done\n");
vTaskDelete(NULL);
exit:
DBG_8195A("efuse OTP block: Test Fail!\n");
vTaskDelete(NULL);
}
void main(void)
{
if(xTaskCreate(efuse_otp_task, ((const char*)"efuse_otp_task"), 512, NULL, tskIDLE_PRIORITY + 1, NULL) != pdPASS)
printf("\n\r%s xTaskCreate(efuse_otp_task) failed", __FUNCTION__);
/*Enable Schedule, Start Kernel*/
if(rtw_get_scheduler_state() == OS_SCHEDULER_NOT_STARTED)
vTaskStartScheduler();
else
vTaskDelete(NULL);
}

24
project/realtek_amebaz_va0_example/example_sources/flash/Makefile Normal file
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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

8
project/realtek_amebaz_va0_example/example_sources/flash/readme.txt Normal file
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Example Description
This example read a specific flash offset, modify it and re-read again.
Requirement Components:
None

119
project/realtek_amebaz_va0_example/example_sources/flash/src/main.c Normal file
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#include "FreeRTOS.h"
#include "task.h"
#include "diag.h"
#include "objects.h"
#include "flash_api.h"
#include "osdep_service.h"
#include "device_lock.h"
#include "main.h"
// Decide starting flash address for storing application data
// User should pick address carefully to avoid corrupting image section
#define FLASH_APP_BASE 0xFF000
static void flash_test_task(void *param)
{
flash_t flash;
uint32_t address = FLASH_APP_BASE;
#if 1
uint32_t val32_to_write = 0x13572468;
uint32_t val32_to_read;
int loop = 0;
int result = 0;
for(loop = 0; loop < 10; loop++)
{
device_mutex_lock(RT_DEV_LOCK_FLASH);
flash_read_word(&flash, address, &val32_to_read);
DBG_8195A("Read Data 0x%x\n", val32_to_read);
flash_erase_sector(&flash, address);
flash_write_word(&flash, address, val32_to_write);
flash_read_word(&flash, address, &val32_to_read);
device_mutex_unlock(RT_DEV_LOCK_FLASH);
DBG_8195A("Read Data 0x%x\n", val32_to_read);
// verify result
result = (val32_to_write == val32_to_read) ? 1 : 0;
//printf("\r\nResult is %s\r\n", (result) ? "success" : "fail");
DBG_8195A("\r\nResult is %s\r\n", (result) ? "success" : "fail");
result = 0;
}
#else
int VERIFY_SIZE = 256;
int SECTOR_SIZE = 16;
uint8_t writedata[VERIFY_SIZE];
uint8_t readdata[VERIFY_SIZE];
uint8_t verifydata = 0;
int loop = 0;
int index = 0;
int sectorindex = 0;
int result = 0;
int resultsector = 0;
int testloop = 0;
for(testloop = 0; testloop < 1; testloop++){
address = FLASH_APP_BASE;
for(sectorindex = 0; sectorindex < 0x300; sectorindex++){
result = 0;
//address += SECTOR_SIZE;
device_mutex_lock(RT_DEV_LOCK_FLASH);
flash_erase_sector(&flash, address);
device_mutex_unlock(RT_DEV_LOCK_FLASH);
//DBG_8195A("Address = %x \n", address);
for(loop = 0; loop < SECTOR_SIZE; loop++){
for(index = 0; index < VERIFY_SIZE; index++)
{
writedata[index] = verifydata + index;
}
device_mutex_lock(RT_DEV_LOCK_FLASH);
flash_stream_write(&flash, address, VERIFY_SIZE, &writedata);
flash_stream_read(&flash, address, VERIFY_SIZE, &readdata);
device_mutex_unlock(RT_DEV_LOCK_FLASH);
for(index = 0; index < VERIFY_SIZE; index++)
{
//DBG_8195A("Address = %x, Writedata = %x, Readdata = %x \n",address,writedata[index],readdata[index]);
if(readdata[index] != writedata[index]){
DBG_8195A("Error: Loop = %d, Address = %x, Writedata = %x, Readdata = %x \n",testloop,address,writedata[index],readdata[index]);
}
else{
result++;
//DBG_8195A(ANSI_COLOR_BLUE"Correct: Loop = %d, Address = %x, Writedata = %x, Readdata = %x \n"ANSI_COLOR_RESET,testloop,address,writedata[index],readdata[index]);
}
}
address += VERIFY_SIZE;
}
if(result == VERIFY_SIZE * SECTOR_SIZE){
//DBG_8195A("Sector %d Success \n", sectorindex);
resultsector++;
}
}
if(resultsector == 0x300){
DBG_8195A("Test Loop %d Success \n", testloop);
}
resultsector = 0;
verifydata++;
}
//DBG_8195A("%d Sector Success \n", resultsector);
DBG_8195A("Test Done");
#endif
vTaskDelete(NULL);
}
void main(void)
{
if(xTaskCreate(flash_test_task, ((const char*)"flash_test_task"), 1024, NULL, tskIDLE_PRIORITY + 1, NULL) != pdPASS)
printf("\n\r%s xTaskCreate(flash_test_task) failed", __FUNCTION__);
vTaskStartScheduler();
while(1){
vTaskDelay( 1000 / portTICK_RATE_MS );
}
}

24
project/realtek_amebaz_va0_example/example_sources/flash_micron_block_protect/Makefile Normal file
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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

12
project/realtek_amebaz_va0_example/example_sources/flash_micron_block_protect/readme.txt Normal file
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Example Description
This example demonstrates how to configure the status register to protect certain blocks. Note that the status register should be reset
if users want to reload code.
Be cautious!!
The definition of store array is different for Micron flash.
Size Micron MXIC
4KB Subsector Sector
64KB Sector Block

101
project/realtek_amebaz_va0_example/example_sources/flash_micron_block_protect/src/main.c Normal file
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#include "diag.h"
#include "main.h"
#include "objects.h"
#include "flash_api.h"
// Decide starting flash address for storing application data
// User should pick address carefully to avoid corrupting image section
#define FLASH_APP_BASE 0x40000//the start address of the fourth block
#define length 8
void main(void)
{
flash_t flash;
uint32_t address = FLASH_APP_BASE;
int result = 1;
int i = 0;
//int length = 8;
int loop = 0;
char data[length];
char buff[length];
for(loop = 0; loop<8;loop++){
DBG_8195A(ANSI_COLOR_MAGENTA"Test Address = %x\n"ANSI_COLOR_RESET, address);
flash_erase_sector(&flash, address);
for(i = 0; i<length;i++){
data[i] = i;
}
flash_burst_write(&flash, address, length, &data[0]);
flash_stream_read(&flash, address, length, &buff[0]);
DBG_8195A("Before Lock\n");
for(i = 0; i<length;i++){
if(data[i] != buff[i]){
DBG_8195A(ANSI_COLOR_YELLOW"Error : Write Data is = %x, Read Data is %x\n"ANSI_COLOR_RESET, data[i],buff[i]);
result = 0;
}
}
if(result == 1)
DBG_8195A("Success 1\n");
DBG_8195A("Lock first 8 blocks\n");
result = 1;
DBG_8195A("Status Register Before Setting= %x\n", flash_get_status(&flash));
flash_set_status(&flash, 0x30);//Protect 0~7 blocks
flash_erase_sector(&flash, address); //This erase should be ignored if the block is protected
for(i = 0; i<length;i++){
data[i] = ~i;
}
flash_burst_write(&flash, address, length, &data[0]);
flash_stream_read(&flash, address, length, &buff[0]);
for(i = 0; i<length;i++){
if(data[i] != buff[i]){
DBG_8195A(ANSI_COLOR_YELLOW"Error : Write Data is = %x, Read Data is %x\n"ANSI_COLOR_RESET, data[i],buff[i]);
result = 0;
}
}
if(result == 1)
DBG_8195A("Success 2\n");
DBG_8195A("Unlock\n");
result = 1;
DBG_8195A("Status Register Before Setting= %x\n", flash_get_status(&flash));
flash_set_status(&flash, flash_get_status(&flash) & (~0x30)); //Unlock the protected block
flash_erase_sector(&flash, address);//Now the erase operation should be valid
flash_burst_write(&flash, address, length, &data[0]);
flash_stream_read(&flash, address, length, &buff[0]);
for(i = 0; i<length;i++){
if(data[i] != buff[i]){
DBG_8195A(ANSI_COLOR_YELLOW"Error : Write Data is = %x, Read Data is %x\n"ANSI_COLOR_RESET,data[i],buff[i]);
result = 0;
}
}
if(result == 1)
DBG_8195A("Success 3\n");
flash_reset_status(&flash);//make sure the status register is reset if users would like to reload code
DBG_8195A("Status Register After Reset= %x\n", flash_get_status(&flash));
address += 0x10000;
}
DBG_8195A("Test Done\n");
for(;;);
}

24
project/realtek_amebaz_va0_example/example_sources/flash_setstatus/Makefile Normal file
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@ -0,0 +1,24 @@
.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

6
project/realtek_amebaz_va0_example/example_sources/flash_setstatus/readme.txt Normal file
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@ -0,0 +1,6 @@
Example Description
This example demonstrates how to configure the status register to protect certain blocks. Note that the status register should be reset
if users want to reload code.

94
project/realtek_amebaz_va0_example/example_sources/flash_setstatus/src/main.c Normal file
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#include "diag.h"
#include "main.h"
#include "objects.h"
#include "flash_api.h"
// Decide starting flash address for storing application data
// User should pick address carefully to avoid corrupting image section
#define FLASH_APP_BASE 0x1F0000//the start address of the last block((for MX25L1606E, please refer to datasheets for different flash))
#define length 256
void main(void)
{
flash_t flash;
uint32_t address = FLASH_APP_BASE;
int result = 1;
int i = 0;
//int length = 256;
char data[length];
char buff[length];
flash_erase_sector(&flash, address);
for(i = 0; i<length;i++){
data[i] = i;
}
flash_burst_write(&flash, address, length, &data[0]);
flash_stream_read(&flash, address, length, &buff[0]);
for(i = 0; i<length;i++){
if(data[i] != buff[i]){
DBG_8195A(ANSI_COLOR_YELLOW"Error Addr %x, Write Data is = %x, Read Data is %x\n"ANSI_COLOR_RESET, address, data[i],buff[i]);
result = 0;
}
}
if(result == 1)
DBG_8195A("Success 1\n");
result = 1;
DBG_8195A("Status Register Before Setting= %x\n", flash_get_status(&flash));
flash_set_status(&flash, 0x4);//Protect hte last block (for MX25L1606E, please refer to datasheets for different flash)
flash_erase_sector(&flash, address); //This erase should be ignored due to block protect
for(i = 0; i<length;i++){
data[i] = ~i;
}
flash_burst_write(&flash, address, length, &data[0]);
flash_stream_read(&flash, address, length, &buff[0]);
for(i = 0; i<length;i++){
if(data[i] != buff[i]){
DBG_8195A(ANSI_COLOR_YELLOW"Error Addr %x, Write Data is = %x, Read Data is %x\n"ANSI_COLOR_RESET, address, data[i],buff[i]);
result = 0;
}
}
if(result == 1)
DBG_8195A("Success 2\n");
result = 1;
DBG_8195A("Status Register Before Setting= %x\n", flash_get_status(&flash));
flash_set_status(&flash, flash_get_status(&flash) & (~0x4)); //Unlock the protected block
flash_erase_sector(&flash, address);//Now the erase operation should be valid
flash_burst_write(&flash, address, length, &data[0]);
flash_stream_read(&flash, address, length, &buff[0]);
for(i = 0; i<length;i++){
if(data[i] != buff[i]){
DBG_8195A(ANSI_COLOR_YELLOW"Error Addr %x, Write Data is = %x, Read Data is %x\n"ANSI_COLOR_RESET, address, data[i],buff[i]);
result = 0;
}
}
if(result == 1)
DBG_8195A("Success 3\n");
flash_reset_status(&flash);//make sure the status register is reset if users would like to reload code
DBG_8195A("Status Register After Reset= %x\n", flash_get_status(&flash));
DBG_8195A("Test Done\n");
for(;;);
}

24
project/realtek_amebaz_va0_example/example_sources/gdma/Makefile Normal file
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@ -0,0 +1,24 @@
.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

52
project/realtek_amebaz_va0_example/example_sources/gdma/src/Makefile Normal file
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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

159
project/realtek_amebaz_va0_example/example_sources/gdma/src/main.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2015 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "diag.h"
#include "main.h"
#include "dma_api.h"
/* notice: AmebaZ HW not support Multi-Block like Ameba1 */
#if 0
//Multi-Block Example Demo
#define DMA_CPY_LEN 176
#define DMA_BLOCK_LENGTH 22
#define DMA_SRC_OFFSET 0
#define DMA_DST_OFFSET 0
#define BLOCK_NUM 8
gdma_t gdma;
uint8_t TestBuf1[DMA_CPY_LEN];
uint8_t TestBuf2[DMA_CPY_LEN];
volatile uint8_t dma_done;
struct BlockInfo{
u32 SrcAddr;
u32 DstAddr;
u32 BlockLength;
u32 SrcOffset;
u32 DstOffset;
};
void dma_done_handler(uint32_t id) {
DiagPrintf("DMA Copy Done!!\r\n");
dma_done = 1;
}
int main(void) {
int i = 0,err = 0;
struct BlockInfo block_info[BLOCK_NUM];
//Set how many blocks we want to transfer (16 at most)
gdma.gdma_obj.BlockNum = BLOCK_NUM;
//Initialize DMA multi-block mode setting
dma_memcpy_aggr_init(&gdma, dma_done_handler, (uint32_t) &gdma);
_memset(TestBuf1, 0,DMA_CPY_LEN);
for(i = 0; i < DMA_CPY_LEN; i++){
TestBuf1[i] = DMA_CPY_LEN - 1 - i;
}
_memset(TestBuf2, 0,DMA_CPY_LEN);
dma_done = 0;
for(i = 0; i < BLOCK_NUM; i++){
//User can decide the relation between SrcOffset/DstOffset,SrcAddr/DstAddr and Block length
// For example :
//block_info[i].SrcOffset = 0;
//block_info[i].DstOffset = 4;
//block_info[i].SrcAddr = &TestBuf1[ i * DMA_BLOCK_LENGTH] ;//SRC
//block_info[i].DstAddr = &TestBuf2[0] + (DMA_BLOCK_LENGTH + block_info[i].DstOffset )*i;//Dest
//block_info[i].BlockLength = DMA_BLOCK_LENGTH;
block_info[i].SrcOffset = 0;
block_info[i].DstOffset = 0;
block_info[i].SrcAddr = (uint32_t) &TestBuf1[ i * DMA_BLOCK_LENGTH] ;//SRC
block_info[i].DstAddr = (uint32_t) &TestBuf2[ i * DMA_BLOCK_LENGTH] ;//Dest
block_info[i].BlockLength = DMA_BLOCK_LENGTH;
//DiagPrintf("block_info[%d].SrcAddr = %x\r\n",i, block_info[i].SrcAddr);
//DiagPrintf("block_info[%d].DstAddr = %x\r\n",i, block_info[i].DstAddr);
//DiagPrintf("block_info[%d].BlockLength = %x\r\n",i, block_info[i].BlockLength);
//DiagPrintf("block_info[%d].SrcOffset = %x\r\n",i, block_info[i].SrcOffset);
//DiagPrintf("block_info[%d].DstOffset = %x\r\n",i, block_info[i].DstOffset);
}
dma_memcpy_aggr(&gdma, (PHAL_GDMA_BLOCK) &block_info);
while (dma_done == 0);
err = 0;
for (i=0;i<DMA_CPY_LEN;i++) {
//DiagPrintf("dma_done = %x\r\n", dma_done);
//DiagPrintf("TestBuf2[%d] = %x\r\n",i, TestBuf2[i]);
if (TestBuf2[i+DMA_DST_OFFSET] != TestBuf1[i+DMA_SRC_OFFSET]) {
DiagPrintf("DMA Copy Memory Compare Err, %d %x %x\r\n", i, TestBuf1[i+DMA_SRC_OFFSET], TestBuf2[i+DMA_DST_OFFSET]);
DiagPrintf("DMA done = %x\r\n", dma_done);
err = 1;
break;
}
}
if (!err) {
DiagPrintf("DMA Copy Memory Compare OK!! %x\r\n", TestBuf2[DMA_DST_OFFSET+DMA_CPY_LEN - 1]);
}
HalGdmaMemCpyDeInit(&(gdma.gdma_obj));
while(1);
return 0;
}
#else
//Single-Block Example Demo
#define DMA_CPY_LEN 256
#define DMA_SRC_OFFSET 0
#define DMA_DST_OFFSET 0
gdma_t gdma;
uint8_t TestBuf1[512];
uint8_t TestBuf2[512];
volatile uint8_t dma_done;
void dma_done_handler(uint32_t id) {
DiagPrintf("DMA Copy Done!!\r\n");
dma_done = 1;
}
int main(void) {
int i;
int err;
dma_memcpy_init(&gdma, dma_done_handler, (uint32_t)&gdma);
for (i=0;i< 512;i++) {
TestBuf1[i] = i;
}
_memset(TestBuf2, 0xff, 512);
dma_done = 0;
dma_memcpy(&gdma, TestBuf2+DMA_DST_OFFSET, TestBuf1+DMA_SRC_OFFSET, DMA_CPY_LEN);
while (dma_done == 0);
err = 0;
for (i=0;i<DMA_CPY_LEN;i++) {
if (TestBuf2[i+DMA_DST_OFFSET] != TestBuf1[i+DMA_SRC_OFFSET]) {
DiagPrintf("DMA Copy Memory Compare Err, %d %x %x\r\n", i, TestBuf1[i+DMA_SRC_OFFSET], TestBuf2[i+DMA_DST_OFFSET]);
err = 1;
break;
}
}
if (!err) {
DiagPrintf("DMA Copy Memory Compare OK!! %x\r\n", TestBuf2[DMA_DST_OFFSET+DMA_CPY_LEN]);
}
dma_memcpy_deinit(&(gdma));
while(1);
return 0;
}
#endif

24
project/realtek_amebaz_va0_example/example_sources/gpio/Makefile Normal file
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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

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Example Description
This example describes how to use GPIO read/write by mbed api.
Requirement Components:
a LED
a push button
Pin name PA_12 and PA_5 map to GPIOA_12 and GPIOA_5:
- PA_12 as input with internal pull-high, connect a push button to this pin and ground.
- PA_5 as output, connect a LED to this pin and GND.
In this example, the LED is off when the push button is pressed.

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project/realtek_amebaz_va0_example/example_sources/gpio/src/Makefile Normal file
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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "gpio_api.h" // mbed
#include "main.h"
#define GPIO_LED_PIN PA_5
#define GPIO_PUSHBT_PIN PA_12
/**
* @brief Main program.
* @param None
* @retval None
*/
//int main_app(IN u16 argc, IN u8 *argv[])
void main(void)
{
gpio_t gpio_led;
gpio_t gpio_btn;
// Init LED control pin
gpio_init(&gpio_led, GPIO_LED_PIN);
gpio_dir(&gpio_led, PIN_OUTPUT); // Direction: Output
gpio_mode(&gpio_led, PullNone); // No pull
// Initial Push Button pin
gpio_init(&gpio_btn, GPIO_PUSHBT_PIN);
gpio_dir(&gpio_btn, PIN_INPUT); // Direction: Input
gpio_mode(&gpio_btn, PullUp); // Pull-High
while(1){
if (gpio_read(&gpio_btn)) {
// turn off LED
gpio_write(&gpio_led, 0);
}
else {
// turn on LED
gpio_write(&gpio_led, 1);
}
}
}

24
project/realtek_amebaz_va0_example/example_sources/gpio_HC_SR04_ultrasonic/Makefile Normal file
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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

22
project/realtek_amebaz_va0_example/example_sources/gpio_HC_SR04_ultrasonic/readme.txt Normal file
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Example Description
This example describes how to use HC-SR04 ultrasonic.
Requirement Components:
a HC-SR04 ultrasonic
HC-SR04 has 4 pins:
VCC: connect to 5V
TRIG: connect to PA_3
ECHO: connect to PA_1 (with level converter from 5V to 3.3V)
GND: Connect to GND
HC-SR04 use ultrasonic to raging distance.
We send a pulse HIGH on TRIG pin for more than 10us,
then HC-SR04 return a pulse HIGH on ECHO pin which correspond distance.
The speed of sound wave is 340 m/s, which means it takes 29us for 1cm.
Thus the distance of result is:
distance (in cm)
= time (in us) / (29 * 2)

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project/realtek_amebaz_va0_example/example_sources/gpio_HC_SR04_ultrasonic/src/Makefile Normal file
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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

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project/realtek_amebaz_va0_example/example_sources/gpio_HC_SR04_ultrasonic/src/main.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "gpio_api.h" // mbed
#include "gpio_irq_api.h" // mbed
#include "gpio_irq_ex_api.h"
#include "diag.h"
#include "main.h"
#define HC_SR04_TRIG PA_3
#define HC_SR04_ECHO PA_1
/* Speed of sound is around 340 m/s
* So 1cm taks 1000000 / 340 * 100 = 29 us
*/
#define TIME_COST_OF_ONE_CM 29 // unit is microsecond
gpio_t gpio_trig;
gpio_irq_t gpio_irq_echo;
int current_level = IRQ_HIGH;
uint32_t timestamp_ping = 0;
uint32_t timestamp_pong = 0;
void gpio_demo_irq_handler (uint32_t id, gpio_irq_event event)
{
uint32_t echo_time;
uint32_t dist_cm;
uint32_t dist_mm;
// Disable level irq because the irq will keep triggered when it keeps in same level.
gpio_irq_disable(&gpio_irq_echo);
if (current_level == IRQ_LOW )
{
timestamp_pong = us_ticker_read();
echo_time = (timestamp_pong - timestamp_ping);
dist_cm = echo_time / ( TIME_COST_OF_ONE_CM * 2 );
dist_mm = ( echo_time % ( TIME_COST_OF_ONE_CM * 2 ) * 10 ) / ( TIME_COST_OF_ONE_CM * 2 );
DiagPrintf("%d.%d cm\r\n", dist_cm, dist_mm);
// Change to listen to high level event
current_level = IRQ_HIGH;
gpio_irq_set(&gpio_irq_echo, current_level, 1);
gpio_irq_enable(&gpio_irq_echo);
}
else if (current_level == IRQ_HIGH)
{
timestamp_ping = us_ticker_read();
// Change to listen to low level event
current_level = IRQ_LOW;
gpio_irq_set(&gpio_irq_echo, current_level, 1);
gpio_irq_enable(&gpio_irq_echo);
}
}
void trigger_high(gpio_t *gpio, uint32_t us)
{
gpio_write(gpio, 1);
HalDelayUs(us);
gpio_write(gpio, 0);
}
void main(void)
{
// Initial HC-SR04 Trigger pin
gpio_init(&gpio_trig, HC_SR04_TRIG);
gpio_dir(&gpio_trig, PIN_OUTPUT); // Direction: Output
gpio_mode(&gpio_trig, PullNone); // No pull
gpio_write(&gpio_trig, 0);
// Initial HC-SR04 Echo pin
gpio_irq_init(&gpio_irq_echo, HC_SR04_ECHO, gpio_demo_irq_handler, NULL);
gpio_irq_set(&gpio_irq_echo, current_level, 1);
gpio_irq_enable(&gpio_irq_echo);
while(1) {
// trigger event by sending High level signal for 10us
trigger_high(&gpio_trig, 10);
// delay 2s for next calculation
HalDelayUs(2 * 1000 * 1000);
}
}

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project/realtek_amebaz_va0_example/example_sources/gpio_dht_temp_humidity/Makefile Normal file
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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

42
project/realtek_amebaz_va0_example/example_sources/gpio_dht_temp_humidity/readme.txt Normal file
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Example Description
This example describes how to use DHT11/DHT22/DHT21 temperature and humidity sensor.
Since DHT require micorseconds level gpio operation, we use gpio register to perform gpio read.
Requirement Components:
DHT11/DHT22/DHT21
DHT series may have 3 pin or 4 pin product.
3 pin DHT has pin layout:
┌─┬┬┬┬┬┬─ GND
│ ├┼┼┼┼┤
├─┼┼┼┼┼┼─ 3.3V
│ ├┼┼┼┼┤
└─┴┴┴┴┴┴─ DATA
4 pin DHT has pin layout:
┌─┬┬┬┬┬┐
│ ├┼┼┼┼┼─ GND
├┬┼┼┼┼┼┼─ N/A
├┴┼┼┼┼┼┼─ DATA
│ ├┼┼┼┼┼─ 3.3V
└─┴┴┴┴┴┘
All we need is 3.3V, GND, and DATA (connect to PA_5).
DATA has default level high.
To get data, it has 3 stage:
(1) Turn DHT from power saving to high speed mode:
Ameba toggle low on DATA pin
(2) Wait DHT ready:
DHT toggle low on DATA pin
(3) Repeatly get 40 bits of data:
If level high has shorter length than level low, then it's bit 0.
If level high has longer length than level high, then it's bit 1.
_____ _____________
________/ \________/ \_________
bit 0 bit 1

52
project/realtek_amebaz_va0_example/example_sources/gpio_dht_temp_humidity/src/Makefile Normal file
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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "gpio_api.h" // mbed
#include "main.h"
#define DHT11 11
#define DHT22 22
#define DHT21 21
// define your DHT type
#define DHTTYPE DHT11
#define DHT_DATA_PIN PA_5
extern u8 GPIO_EXT_PORT_TBL[];
#define GPIO_DIRECT_READ(port,pin) ((GPIO->EXT_PORT[port]>> pin) & 0x01)
uint32_t expect_pulse(uint8_t port, uint8_t pin, uint32_t expect_level, uint32_t max_cycle) {
uint32_t cycle = 1;
while(expect_level == GPIO_DIRECT_READ(port, pin)) {
if (cycle++ >= max_cycle) {
return 0;
}
}
return cycle;
}
void main(void)
{
int i;
uint32_t reg_value;
uint32_t cycles[80];
uint32_t low_cycles, high_cycles;
uint8_t data[5];
float humidity = 0;
float temperature = 0;
gpio_t gpio_dht;
uint8_t port_num;
uint8_t pin_num;
gpio_init(&gpio_dht, DHT_DATA_PIN);
gpio_dir(&gpio_dht, PIN_INPUT);
gpio_mode(&gpio_dht, PullUp);
port_num = PORT_NUM(DHT_DATA_PIN);
pin_num = PIN_NUM(DHT_DATA_PIN);
while(1)
{
HalDelayUs(2 * 1000 * 1000);
data[0] = data[1] = data[2] = data[3] = data[4] = 0;
gpio_dir(&gpio_dht, PIN_OUTPUT);
gpio_write(&gpio_dht, 1);
HalDelayUs(250 * 1000);
// toggle down to turn DHT from power saving mode to high speed mode
gpio_write(&gpio_dht, 0);
HalDelayUs(20 * 1000);
gpio_write(&gpio_dht, 1);
HalDelayUs(40);
gpio_dir(&gpio_dht, PIN_INPUT);
gpio_mode(&gpio_dht, PullNone);
// wait DHT toggle down to ready
if (expect_pulse(port_num, pin_num, 0, 1000) == 0) {
rtl_printf("Timeout waiting for start signal low pulse.\r\n");
continue;
}
if (expect_pulse(port_num, pin_num, 1, 1000) == 0) {
rtl_printf("Timeout waiting for start signal high pulse.\r\n");
continue;
}
for (i=0; i<80; i+=2) {
cycles[i] = expect_pulse(port_num, pin_num, 0, 1000);
cycles[i+1] = expect_pulse(port_num, pin_num, 1, 1000);
}
for (i=0; i<40; i++) {
low_cycles = cycles[2*i];
high_cycles = cycles[2*i+1];
if (low_cycles == 0 || high_cycles == 0) {
break;
}
data[i/8] <<= 1;
if (high_cycles > low_cycles) {
data[i/8] |= 1;
}
}
if (i != 40) {
rtl_printf("Timeout waiting for pulse.\r\n");
continue;
}
if ( ((data[0] + data[1] + data[2] + data[3]) & 0xFF) != data[4] ) {
rtl_printf("Checksum failure!\r\n");
continue;
}
switch(DHTTYPE) {
case DHT11:
humidity = data[0];
temperature = data[2];
break;
case DHT22:
case DHT21:
humidity = data[0];
humidity *= 256;
humidity += data[1];
humidity *= 0.1;
temperature = data[2] & 0x7F;
temperature *= 256;
temperature += data[3];
temperature *= 0.1;
if (data[2] & 0x80) {
temperature *= -1;
}
break;
}
rtl_printf("Humidity: %.2f %%\t Temperature: %.2f *C\r\n", humidity, temperature);
}
}

24
project/realtek_amebaz_va0_example/example_sources/gpio_irq/Makefile Normal file
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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

13
project/realtek_amebaz_va0_example/example_sources/gpio_irq/readme.txt Normal file
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Example Description
This example describes how to use GPIO_irq to read/write by mbed api.
Requirement Components:
a LED
a push button
Pin name PA_12 and PA_5 map to GPIOA_12 and GPIOA_5:
- PA_12 as input with internal pull-high, connect a push button to this pin and ground.
- PA_5 as output, connect a LED to this pin and ground.
In this example, push the button to trigger interrupt to turn on/off the LED.

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project/realtek_amebaz_va0_example/example_sources/gpio_irq/src/Makefile Normal file
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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

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project/realtek_amebaz_va0_example/example_sources/gpio_irq/src/main.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "gpio_api.h" // mbed
#include "gpio_irq_api.h" // mbed
#include "diag.h"
#include "main.h"
#define GPIO_LED_PIN PA_5
#define GPIO_IRQ_PIN PA_12
int led_ctrl;
gpio_t gpio_led;
extern u32 ConfigDebugWarn;
void gpio_demo_irq_handler (uint32_t id, gpio_irq_event event)
{
gpio_t *gpio_led;
DBG_8195A("%s==>\n", __FUNCTION__);
gpio_led = (gpio_t *)id;
led_ctrl = !led_ctrl;
gpio_write(gpio_led, led_ctrl);
}
/**
* @brief Main program.
* @param None
* @retval None
*/
void main(void)
{
gpio_irq_t gpio_btn;
// Init LED control pin
gpio_init(&gpio_led, GPIO_LED_PIN);
gpio_dir(&gpio_led, PIN_OUTPUT); // Direction: Output
gpio_mode(&gpio_led, PullNone); // No pull
// Initial Push Button pin as interrupt source
gpio_irq_init(&gpio_btn, GPIO_IRQ_PIN, gpio_demo_irq_handler, (uint32_t)(&gpio_led));
gpio_irq_set(&gpio_btn, IRQ_FALL, 1); // Falling Edge Trigger
gpio_irq_enable(&gpio_btn);
led_ctrl = 1;
gpio_write(&gpio_led, led_ctrl);
while(1);
}

24
project/realtek_amebaz_va0_example/example_sources/gpio_jtag/Makefile Normal file
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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

16
project/realtek_amebaz_va0_example/example_sources/gpio_jtag/readme.txt Normal file
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Example Description
This example describes how to disable JTAG module and use GPIO pin to blink led.
Requirement Components:
a LED
a push button
PA_5 as input with internal pull-high, connect a push button to this pin and ground.
PA_12 as output, connect a LED to this pin and ground.
If button is not pressed while device boot up, then we don't turn off jtag module.
If button is pressed while device boot up, then jtag module is turned off.
If jatg module is turned off, then we blink led.

52
project/realtek_amebaz_va0_example/example_sources/gpio_jtag/src/Makefile Normal file
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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

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project/realtek_amebaz_va0_example/example_sources/gpio_jtag/src/main.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "gpio_api.h" // mbed
#include "sys_api.h" // for sys_jtag_off()
#include "main.h"
#define GPIO_JTAG_ENABLE_PIN PA_5
#define GPIO_LED_PIN PA_12
void main(void)
{
int i;
gpio_t gpio_jtag_enable;
gpio_t gpio_led;
gpio_init(&gpio_jtag_enable, GPIO_JTAG_ENABLE_PIN);
gpio_dir(&gpio_jtag_enable, PIN_INPUT);
gpio_mode(&gpio_jtag_enable, PullUp);
if (gpio_read(&gpio_jtag_enable) == 0)
{
// JTAG enable pin is disabled
sys_jtag_off();
DBG_8195A("jtag off\r\n");
// Now you can use jtag pin for other gpio usage
// ex. use PE_0 to blink led
gpio_init(&gpio_led, GPIO_LED_PIN);
gpio_dir(&gpio_led, PIN_OUTPUT); // Direction: Output
gpio_mode(&gpio_led, PullNone); // No pull
while(1)
{
gpio_write(&gpio_led, 1);
for (i=0; i<10000000; i++) asm(" nop"); // simple delay
gpio_write(&gpio_led, 0);
for (i=0; i<10000000; i++) asm(" nop"); // simple delay
}
}
else
{
// JTAG enable pin is enabled
DBG_8195A("jtag on\r\n");
}
for (;;);
}

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project/realtek_amebaz_va0_example/example_sources/gpio_level_irq/Makefile Normal file
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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

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Example Description
This example describes how to implement high/low level trigger on 1 gpio pin.
Pin name PA_12 and PA_5 map to GPIOA_12 and GPIOA_5:
Connect PA_12 and PA_5
- PA_12 as gpio input high/low level trigger.
- PA_5 as gpio output
In this example, PA_5 is signal source that change level to high and low periodically.
PA_12 setup to listen low level events in initial.
When PA_12 catch low level events, it disable the irq to avoid receiving duplicate events.
(NOTE: the level events will keep invoked if level keeps in same level)
Then PA_12 is configured to listen high level events and enable irq.
As PA_12 catches high level events, it changes back to listen low level events.
Thus PA_12 can handle both high/low level events.
In this example, you will see log that prints high/low level event periodically.

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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

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/*
* Routines to access hardware
*
* Copyright (c) 2015 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "gpio_irq_api.h" // mbed
#include "gpio_irq_ex_api.h"
#include "diag.h"
#include "main.h"
#include "gpio_api.h"
#define GPIO_IRQ_LEVEL_PIN PA_12
#define GPIO_SIGNAL_SOURCE PA_5
gpio_irq_t gpio_level;
int current_level = IRQ_LOW;
void gpio_level_irq_handler (uint32_t id, gpio_irq_event event)
{
uint32_t *level = (uint32_t *) id;
// Disable level irq because the irq will keep triggered when it keeps in same level.
gpio_irq_disable(&gpio_level);
// make some software de-bounce here if the signal source is not stable.
if (*level == IRQ_LOW )
{
DBG_8195A("low level event\r\n");
// Change to listen to high level event
*level = IRQ_HIGH;
gpio_irq_set(&gpio_level, IRQ_HIGH, 1);
gpio_irq_enable(&gpio_level);
}
else if (*level == IRQ_HIGH)
{
DBG_8195A("high level event\r\n");
// Change to listen to low level event
*level = IRQ_LOW;
gpio_irq_set(&gpio_level, IRQ_LOW, 1);
gpio_irq_enable(&gpio_level);
}
}
void main(void)
{
int i;
// configure level trigger handler
gpio_irq_init(&gpio_level, GPIO_IRQ_LEVEL_PIN, gpio_level_irq_handler, (uint32_t)(&current_level));
gpio_irq_set(&gpio_level, IRQ_LOW, 1);
gpio_irq_enable(&gpio_level);
// configure gpio as signal source for high/low level trigger
gpio_t gpio_src;
gpio_init(&gpio_src, GPIO_SIGNAL_SOURCE);
gpio_dir(&gpio_src, PIN_OUTPUT); // Direction: Output
gpio_mode(&gpio_src, PullNone);
while(1) {
gpio_write(&gpio_src, 1);
for (i=0; i<20000000; i++) asm("nop");
gpio_write(&gpio_src, 0);
for (i=0; i<20000000; i++) asm("nop");
}
}

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Example Description
This example describes how to use GPIO read/write in a light weight way.
Requirement Components:
a LED
a push button
Pin name PA_12 and PA_5 map to GPIOA_12 and GPIOA_5:
- PA_12 as input with internal pull-high, connect a push button to this pin and ground.
- PA_5 as output, connect a LED to this pin and ground.
In this example, the LED is on when the push button is pressed.

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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "gpio_api.h" // mbed
#include "main.h"
#define GPIO_LED_PIN PA_5
#define GPIO_PUSHBT_PIN PA_12
/* You can improve time cost of gpio write by import source code of
* function "gpio_direct_write" based on your needs.
* In this example, enable CACHE_WRITE_ACTION as demonstration.
*/
#define CACHE_WRITE_ACTION (0)
void main(void)
{
gpio_t gpio_led;
gpio_t gpio_btn;
// Init LED control pin
gpio_init(&gpio_led, GPIO_LED_PIN);
gpio_dir(&gpio_led, PIN_OUTPUT); // Direction: Output
gpio_mode(&gpio_led, PullNone); // No pull
// Initial Push Button pin
gpio_init(&gpio_btn, GPIO_PUSHBT_PIN);
gpio_dir(&gpio_btn, PIN_INPUT); // Direction: Input
gpio_mode(&gpio_btn, PullUp); // Pull-High
#if defined(CACHE_WRITE_ACTION) && (CACHE_WRITE_ACTION == 1)
u8 port_num = PORT_NUM(gpio_led.pin);
u8 pin_num = PIN_NUM(gpio_led.pin);
u32 RegValue;
#endif
while(1){
#if defined(CACHE_WRITE_ACTION) && (CACHE_WRITE_ACTION == 1)
if (gpio_read(&gpio_btn)) {
// turn off LED
RegValue = GPIO->PORT[port_num].DR;
RegValue &= ~(1 << pin_num);
GPIO->PORT[port_num].DR = RegValue;
} else {
// turn on LED
RegValue = GPIO->PORT[port_num].DR;
RegValue |= (1<< pin_num);
GPIO->PORT[port_num].DR = RegValue;
}
#else
if (gpio_read(&gpio_btn)) {
// turn off LED
gpio_direct_write(&gpio_led, 0);
} else {
// turn on LED
gpio_direct_write(&gpio_led, 1);
}
#endif
}
}

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project/realtek_amebaz_va0_example/example_sources/gpio_port/Makefile Normal file
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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

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project/realtek_amebaz_va0_example/example_sources/gpio_port/readme.txt Normal file
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Example Description
This example describes how to use GPIO Port read/write by mbed api.
Requirement Components:
8 LEDs
dupont line
Pin name A0 map to GPIOA_0:
-For 32pin test, the available Gpio port are A0, A5, A12, A18, A19, A22, A23, and A14,A15 are also available when turning off the JTAG function.
-GPIO ports as output pins connect to the LED long leg, and the LED short leg connect to GND.
In this example:
When test Gpio port output, the LEDs is on when corresponding Gpio pins output 1, the LEDs is off when corresponding Gpio pins output 0;
When test Gpio port input, current selected Gpio pins input value is different with original value, trace tool print current Gpio pins value.

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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "port_api.h" // mbed
#include "PortNames.h" // mbed
#include "main.h"
#include "sys_api.h"
#define PORT_OUTPUT_TEST 1 //1: output test, 0: input test
#define LED_PATTERN_NUM 12
port_t port0;
const uint32_t led_pattern[LED_PATTERN_NUM]={0xCCD020, 0xCCD001, 0xCCC021, 0xCC9021, 0xCC5021, 0xC8D021, 0xC4D021, 0x8CD021, 0x4C9021, 0xCCD021, 0x00};
extern void wait_ms(u32);
/**
* @brief Main program.
* @param None
* @retval None
*/
#if PORT_OUTPUT_TEST
void main(void)
{
int i;
unsigned int pin_mask;
pin_mask = 0xCCD021; // each bit map to 1 pin: 0: pin disable, 1: pin enable
sys_jtag_off();
port_init(&port0, PortA, pin_mask, PIN_OUTPUT);
port_mode(&port0, PullNone);
while(1){
for (i=0;i<LED_PATTERN_NUM;i++) {
port_write(&port0, led_pattern[i]);
wait_ms(200);
}
}
}
#else
void main(void)
{
int i;
unsigned int pin_mask;
int value_new, value_tmp, value_old;
int stable;
pin_mask = 0xCCD021; // each bit map to 1 pin: 0: pin disable, 1: pin enable
sys_jtag_off();
port_init(&port0, PortA, pin_mask, PIN_INPUT);
port_mode(&port0, PullNone);
value_old = port_read(&port0);
while(1){
// De-bonse
value_new = port_read(&port0);
stable = 0;
while (stable < 3){
value_tmp = port_read(&port0);
if (value_new != value_tmp) {
value_new = value_tmp;
stable = 0;
}
else {
stable++;
}
}
if (value_old != value_new) {
DBG_8195A("0x%x\r\n", value_new);
value_old = value_new;
}
wait_ms(50);
}
}
#endif

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.PHONY: all copy clean
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC = src inc
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: copy
copy:
for cpf in $(CSRC); do \
cp -rf $$cpf ../..; \
done

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project/realtek_amebaz_va0_example/example_sources/gpio_pulse_measure/readme.txt Normal file
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Example Description
This example describes how to use GPIO read/write mbed api to generate a pulse and to measure the pulse width.
Requirement Components:
a wire
Pin name PA_12 and PA_5 map to GPIOA_12 and GPIOA_5:
- PA_12 as the interrupt GPIO pin with no pull (High-Z).
- PA_5 as output to generate a pulse.
- Use a wire to connect PA_12 and PA_5
In this example, the UART consol will print out the measured width (in us) of the pulse which generated by PA_5.

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include $(MAKE_INCLUDE_GEN)
#include ./Makefile.inc
.PHONY: all clean
CHIP = rtl8195a
HALINCDIR = realtek/v3_0/include
MODULE_IFLAGS += -I$(shell pwd -L)/../inc
MODULE_IFLAGS += -I$(SWLIBDIR)/api
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
#*****************************************************************************#
# Source FILE LIST #
#*****************************************************************************#
CSRC += main.c
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
OBJS = $(CSRC:.c=.o)
#*****************************************************************************#
# Object FILE LIST #
#*****************************************************************************#
#OBJS = monitor.o rtl_consol.o
#*****************************************************************************#
# RULES TO GENERATE TARGETS #
#*****************************************************************************#
# Define the Rules to build the core targets
all: CORE_TARGETS COPY_RAM_OBJS
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
CORE_TARGETS: $(OBJS)
#*****************************************************************************#
# GENERATE OBJECT FILE
#*****************************************************************************#
clean:
rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "device.h"
#include "gpio_api.h" // mbed
#include "gpio_irq_api.h" // mbed
#include "diag.h"
#include "us_ticker_api.h"
#include "main.h"
#define GPIO_OUT_PIN PA_5
#define GPIO_IRQ_PIN PA_12
gpio_t gpio_out;
gpio_irq_t gpio_irq;
volatile char irq_rise;
void gpio_demo_irq_handler (uint32_t id, gpio_irq_event event)
{
static unsigned int rise_time;
static unsigned int fall_time;
if (irq_rise) {
rise_time = us_ticker_read();
// Changed as Falling Edge Trigger
gpio_irq_set_event(&gpio_irq, IRQ_FALL);
irq_rise = 0;
} else {
fall_time = us_ticker_read();
// Changed as Rising Edge Trigger
gpio_irq_set_event(&gpio_irq, IRQ_RISE);
irq_rise = 1;
DBG_8195A("%d\n", (fall_time-rise_time));
}
}
/**
* @brief Main program.
* @param None
* @retval None
*/
void main(void)
{
// Init LED control pin
gpio_init(&gpio_out, GPIO_OUT_PIN);
gpio_dir(&gpio_out, PIN_OUTPUT); // Direction: Output
gpio_mode(&gpio_out, PullNone); // No pull
gpio_write(&gpio_out, 0);
// Initial Push Button pin as interrupt source
gpio_irq_init(&gpio_irq, GPIO_IRQ_PIN, gpio_demo_irq_handler, (uint32_t)(&gpio_irq));
gpio_irq_set(&gpio_irq, IRQ_RISE, 1); // Falling Edge Trigger
irq_rise = 1;
gpio_irq_pull_ctrl(&gpio_irq, PullNone);
gpio_irq_enable(&gpio_irq);
while(1) {
wait_ms(500);
gpio_write(&gpio_out, 1);
wait_us(1000);
gpio_write(&gpio_out, 0);
}
}

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project/realtek_amebaz_va0_example/example_sources/gspi/GSPI block diagram.pdf Normal file
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Example Description
This example describes how to communicate with AmebaZ gspi interface.
How to build:
1. copy src\main.c to project\realtek_amebaz_va0_example\src
This example source code(mian.c) contain both GSPI slave code and SPI master code, you can use "CONFIG_GPSI_SLAVE" to choose which dirver to run.
"#define CONFIG_GPSI_SLAVE 1" for GSPI Slave
"#define CONFIG_GPSI_SLAVE 0" for SPI master
Requirement Components:
2 AmebaZ Board
AmebaZ (A): Assign as SPI master
SPI0_MOSI : PA_23
SPI0_MISO : PA_22
SPI0_SCLK : PA_18
GPIO_CS : PA_28
GPIO_INT : PA_27
AmebaZ (B): Assign as GSPI slave
GSPI_MOSI : PA_20
GSPI_MISO : PA_22
GSPI_CLK : PA_21
GSPI_CS : PA_19
GSPI_INT : PA_23
Setup:connect A and B as given
A: B:
SPI0_SCLK --- GSPI_CLK
GPIO_CS --- GSPI_CS
SPI0_MOSI --- GSPI_MOSI
SPI0_MISO --- GSPI_MISO
GPIO_INT --- GSPI_INT
V3.3 --- V3.3
GND --- GND
Behavior:
A send 2048 bytes to B about every 500ms and B will send whatever received back to A.
Every time if A Checks Rx Datas are the same as Tx Datas,then it logs "Succeed" ,else it logs "Failed" and finished.

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/*
* Routines to access hardware
*
* Copyright (c) 2015 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
#include "device.h"
#include "rtl8710b_gspi_host.h"
#include "rtl8710b_inic.h"
#include "spi_api.h"
#include "spi_ex_api.h"
#include "gpio_api.h"
#include "gpio_irq_api.h"
#include "osdep_service.h"
#define CONFIG_GSPI_SLAVE 0
#define CONFIG_USE_INTERRUPT 1
#define PACK_SIZE 2048
#if !CONFIG_GSPI_SLAVE
/*host endian configuration
little-endian (1)
big-endan (0)
*/
#define CONFIG_HOST_ENDIAN 1
// SPI0
#define SPI0_MOSI PA_23
#define SPI0_MISO PA_22
#define SPI0_SCLK PA_18
#define SPI0_CS PA_19 // This pin is redundant
#if CONFIG_USE_INTERRUPT
#define GPIO_INT PA_27 // gspi external interrupt
#endif
#define GPIO_CS PA_28
#define SPI0_FREQUENCY (62500000/6)
static spi_t spi0_master;
static gpio_irq_t gpio_int;
static gpio_t gpio_cs;
typedef enum {
READ_REG = 0,
WRITE_REG
}_reg_ops;
// GSPI configuration (big endian recommended)
#define GSPI_CONFIG SPI_LITTLE_ENDIAN_32
// SPI master configuration
#define SPI_BITS 8 // Ameba SPI support 8bits and 16bits mode
struct spi_more_data {
unsigned long more_data;
unsigned long len;
};
#define SLAVE_SELECT() gpio_write(&gpio_cs, 0)
#define SLAVE_DESELECT() gpio_write(&gpio_cs, 1)
#define SPI_DUMMY 0xFF
// spi interrupt semaphore
_sema pspiIrqSemaphore;
// spi bus busy
_mutex SPIbusbusy;
volatile bool txDone = FALSE;
volatile bool rxDone = FALSE;
volatile bool txbusIdle = FALSE;
#define AGG_SIZE 5000
#define MAX_DUMMY_LEN 3
#define BUFFER_LEN GSPI_CMD_LEN+SIZE_RX_DESC+PACK_SIZE+8+MAX_DUMMY_LEN // GSPI_CMD + TX_DEC + DATA + GSPI_STATUS
unsigned char TX_DATA[PACK_SIZE];
unsigned char RX_DATA[PACK_SIZE+SIZE_RX_DESC]; // extra 100 byte for SDIO header
u32 rx_done=0;
unsigned char TX_BUFFER[BUFFER_LEN];
unsigned char RX_BUFFER[BUFFER_LEN];
#endif
#define TASK_STACK_SIZE 2048
#define TASK_PRIORITY (tskIDLE_PRIORITY + 1)
#if CONFIG_GSPI_SLAVE
#include "spdio_api.h"
struct spdio_t spdio_dev;
#define SPDIO_TX_BD_NUM 6 // n*2, must be rounded to 2
#define SPDIO_RX_BD_NUM 6 //
#define SPDIO_RX_BUFSZ PACK_SIZE+64 //n*64, must be rounded to 64, extra 64 for TX descriptor
#define CONFIG_RX_BUFFER_REUSE 1
/*
* param: pdata, package
*/
char ex_gspi_tx(u8 *pdata, u16 size, u8 type){
static int rx_cnt = 0;
// LOOPBACK
printf("receive package, size = %d (cnt = %d) heap=%d\n", size, ++rx_cnt, xPortGetFreeHeapSize());
struct spdio_buf_t *tx_buf = (struct spdio_buf_t *)rtw_malloc(sizeof(struct spdio_buf_t));
if(!tx_buf)
return FAIL;
tx_buf->buf_allocated = (u32)rtw_malloc(size + SPDIO_DMA_ALIGN_4);
if(!tx_buf->buf_allocated)
{
rtw_mfree((u8 *)tx_buf, sizeof(struct spdio_buf_t));
return FAIL;
}
tx_buf->size_allocated = size + SPDIO_DMA_ALIGN_4;
tx_buf->buf_addr = (u32)N_BYTE_ALIGMENT((u32)(tx_buf->buf_allocated), SPDIO_DMA_ALIGN_4);
//printf("buf_addr = %x\n", tx_buf->buf_addr);
// copy data
memcpy((void*)tx_buf->buf_addr, pdata, size);
tx_buf->buf_size = size;
tx_buf->type = SPDIO_RX_DATA_USER; // you can define your own data type in spdio_rx_data_t and spdio_tx_data_t
// loopback
spdio_tx(&spdio_dev, tx_buf);
return SUCCESS;
}
/*spdio rx done callback (HOST->Device), manage your package and buffer*/
char ex_gspi_rx_done_cb(void *priv, void *pbuf, u8 *pdata, u16 size, u8 type){
struct spdio_t *obj = (struct spdio_t *)priv;
struct spdio_buf_t* rx_buf = (struct spdio_buf_t*)pbuf;
//2 handle package received
ex_gspi_tx(pdata, size, type);
#if !CONFIG_RX_BUFFER_REUSE
// manage rx_buf here
rtw_mfree((char *)rx_buf->buf_allocated, rx_buf->size_allocated);
//2 assign new buffer to RX
rx_buf->buf_allocated = (u32)rtw_malloc(obj->rx_bd_bufsz + SPDIO_DMA_ALIGN_4);
rx_buf->size_allocated = obj->rx_bd_bufsz + SPDIO_DMA_ALIGN_4;
// this buffer must be 4 byte alignment
rx_buf->buf_addr = (u32)N_BYTE_ALIGMENT((u32)(rx_buf->buf_allocated), SPDIO_DMA_ALIGN_4);
#endif
return SUCCESS;
}
/*spdio tx done callback(Device->HOST), manage buffer*/
// this API will be called after package have been read by HOST
char ex_gspi_tx_done_cb(void *priv, void *pbuf){
struct spdio_buf_t* tx_buf = (struct spdio_buf_t*)pbuf;
rtw_mfree((u8 *)tx_buf->buf_allocated, tx_buf->size_allocated);
rtw_mfree((u8 *)tx_buf, sizeof(struct spdio_buf_t));
return SUCCESS;
}
#else
int spi_transfer(uint8_t* buf, uint32_t buf_len)
{
int i = 0;
int ret = 0;
rtw_mutex_get(&SPIbusbusy);
SLAVE_SELECT();
txbusIdle = FALSE; // ensure TX done
rxDone = FALSE; // ensure RX done
if(spi_master_write_read_stream(&spi0_master, buf, buf, buf_len)!=0x00){
ret = -1;
}else{
ret = 0;
while((!txbusIdle) || (!rxDone)){
wait_us(20);
if (++i > 2000) {
DBG_8195A("SPI write and read Timeout...\r\n");
ret = -1;
break;
}
}
}
/* Chip Select Pull High */
SLAVE_DESELECT();
rtw_mutex_put(&SPIbusbusy);
return ret;
}
static int addr_convert(u32 addr)
{
u32 domain_id = 0 ;
u32 temp_addr = addr&0xffff0000;
switch (temp_addr) {
case SPI_LOCAL_OFFSET:
domain_id = SPI_LOCAL_DOMAIN;
break;
case SPI_TX_FIFO_OFFSET:
domain_id = SPI_TXFIFO_DOMAIN;
break;
case SPI_RX_FIFO_OFFSET:
domain_id = SPI_RXFIFO_DOMAIN;
break;
default:
break;
}
return domain_id;
}
static inline u32 DWORD_endian_reverse(u32 src, _gspi_conf_t gspi_conf)
{
u32 temp = 0;
switch(gspi_conf){
#if CONFIG_HOST_ENDIAN /*host little-endian*/
case SPI_LITTLE_ENDIAN_16:
temp = (((src&0x000000ff)<<8)|((src&0x0000ff00)>>8)|
((src&0x00ff0000)<<8)|((src&0xff000000)>>8));
break;
case SPI_LITTLE_ENDIAN_32:
temp = (((src&0x000000ff)<<24)|((src&0x0000ff00)<<8)|
((src&0x00ff0000)>>8)|((src&0xff000000)>>24));
break;
case SPI_BIG_ENDIAN_16:
case SPI_BIG_ENDIAN_32:
temp = src;
break;
#else /*host big-endian*/
case SPI_LITTLE_ENDIAN_16:
temp = (((src&0x0000ffff)<<16)|((src&0xffff0000)>>16);
break;
case SPI_LITTLE_ENDIAN_32:
temp = src;
break;
case SPI_BIG_ENDIAN_16:
case SPI_BIG_ENDIAN_32:
temp = (((src&0x000000ff)<<24)|((src&0x0000ff00)<<8)|
((src&0x00ff0000)>>8)|((src&0xff000000)>>24));
break;
#endif
}
return temp;
}
/*
* src buffer bit reorder
*/
static void buf_endian_reverse(u8* src, u32 len, u8* dummy_bytes, _gspi_conf_t gspi_conf)
{
u32 *buf = (u32*)src;
u16 count = len/4;
u16 remain = len%4;
int i = 0;
if(remain)
count ++;
for(i = 0;i < count; i++){
buf[i] = DWORD_endian_reverse(buf[i], gspi_conf);
}
if(remain)
*dummy_bytes = 4 - remain;
}
int gspi_read_write_reg(_reg_ops ops_type, u32 addr, char * buf, int len,_gspi_conf_t gspi_conf)
{
int fun = 1, domain_id = 0x0; //LOCAL
unsigned int cmd = 0 ;
int byte_en = 0 ;//,i = 0 ;
int ret = 0;
unsigned char status[GSPI_STATUS_LEN] = {0};
unsigned int data_tmp = 0;
u32 spi_buf[4] = {0};
if (len!=1 && len!=2 && len != 4) {
return -1;
}
domain_id = addr_convert(addr);
addr &= 0x7fff;
len &= 0xff;
if (ops_type == WRITE_REG) //write register
{
int remainder = addr % 4;
u32 val32 = *(u32 *)buf;
switch(len) {
case 1:
byte_en = (0x1 << remainder);
data_tmp = (val32& 0xff)<< (remainder*8);
break;
case 2:
byte_en = (0x3 << remainder);
data_tmp = (val32 & 0xffff)<< (remainder*8);
break;
case 4:
byte_en = 0xf;
data_tmp = val32 & 0xffffffff;
break;
default:
byte_en = 0xf;
data_tmp = val32 & 0xffffffff;
break;
}
}
else //read register
{
switch(len) {
case 1:
byte_en = 0x1;
break;
case 2:
byte_en = 0x3;
break;
case 4:
byte_en = 0xf;
break;
default:
byte_en = 0xf;
break;
}
if(domain_id == SPI_LOCAL_DOMAIN)
byte_en = 0;
}
cmd = FILL_SPI_CMD(byte_en, addr, domain_id, fun, ops_type);
//4 command segment bytes reorder
cmd = DWORD_endian_reverse(cmd, gspi_conf);
if ((ops_type == READ_REG)&& (domain_id!= SPI_RXFIFO_DOMAIN)) {
u32 read_data = 0;
_memset(spi_buf, 0x00, sizeof(spi_buf));
//SPI_OUT:32bit cmd
//SPI_IN:64bits status+ XXbits data
spi_buf[0] = cmd;
spi_buf[1] = 0;
spi_buf[2] = 0;
spi_buf[3] = 0;
spi_transfer((u8*)spi_buf, sizeof(spi_buf));
memcpy(status, (u8 *) &spi_buf[1], GSPI_STATUS_LEN);
read_data = spi_buf[3];
*(u32*)buf = DWORD_endian_reverse(read_data, gspi_conf);
}
else if (ops_type == WRITE_REG ) {
//4 data segment bytes reorder
data_tmp = DWORD_endian_reverse(data_tmp, gspi_conf);
//SPI_OUT:32bits cmd+ XXbits data
//SPI_IN:64bits status
spi_buf[0] = cmd;
spi_buf[1] = data_tmp;
spi_buf[2] = 0;
spi_buf[3] = 0;
spi_transfer((u8*)spi_buf, sizeof(spi_buf));
memcpy(status, (u8 *) &spi_buf[2], GSPI_STATUS_LEN);
}
// translate status
return ret;
}
u8 gspi_read8(u32 addr, s32 *err)
{
u32 ret = 0;
int val32 = 0 , remainder = 0 ;
s32 _err = 0;
_err = gspi_read_write_reg(READ_REG, addr&0xFFFFFFFC, (char *)&ret, 4, GSPI_CONFIG);
remainder = addr % 4;
val32 = ret;
val32 = (val32& (0xff<< (remainder<<3)))>>(remainder<<3);
if (err)
*err = _err;
return (u8)val32;
}
u16 gspi_read16(u32 addr, s32 *err)
{
u32 ret = 0;
int val32 = 0 , remainder = 0 ;
s32 _err = 0;
_err = gspi_read_write_reg(READ_REG, addr&0xFFFFFFFC,(char *)&ret, 4, GSPI_CONFIG);
remainder = addr % 4;
val32 = ret;
val32 = (val32& (0xffff<< (remainder<<3)))>>(remainder<<3);
if (err)
*err = _err;
return (u16)val32;
}
u32 gspi_read32(u32 addr, s32 *err)
{
unsigned int ret = 0;
s32 _err = 0;
_err = gspi_read_write_reg(READ_REG, addr&0xFFFFFFFC,(char *)&ret,4 ,GSPI_CONFIG);
if (err)
*err = _err;
return ret;
}
s32 gspi_write8(u32 addr, u8 buf, s32 *err)
{
int ret = 0;
ret = gspi_read_write_reg(WRITE_REG, addr, (char *)&buf,1, GSPI_CONFIG);
if (err)
*err = ret;
return ret;
}
s32 gspi_write16(u32 addr, u16 buf, s32 *err)
{
int ret = 0;
ret = gspi_read_write_reg(WRITE_REG,addr,(char *)&buf,2, GSPI_CONFIG);
if (err)
*err = ret;
return ret;
}
s32 gspi_write32(u32 addr, u32 buf, s32 *err)
{
int ret = 0;
ret = gspi_read_write_reg(WRITE_REG, addr,(char *)&buf,4, GSPI_CONFIG);
if (err)
*err = ret;
return ret;
}
int gspi_read_rx_fifo(u8 *buf, u32 len, struct spi_more_data * pmore_data,_gspi_conf_t gspi_conf)
{
int fun = 1;
u32 cmd = 0;
u8* spi_buf = (u8 *) (buf);
u8* spi_data = spi_buf + GSPI_CMD_LEN;
u8* spi_status = spi_data + len;
int spi_buf_len = GSPI_CMD_LEN + N_BYTE_ALIGMENT(len, 4) + GSPI_STATUS_LEN;
u8 dummy_bytes = 0;
cmd = FILL_SPI_CMD(len, ((len&0xff00) >>8), SPI_RXFIFO_DOMAIN, fun, (unsigned int)0);
//4 command segment bytes reorder
cmd = DWORD_endian_reverse(cmd, gspi_conf);
memcpy(spi_buf, (u8 *)&cmd, GSPI_CMD_LEN);
//4 clean data segment
memset(spi_data,0x00, len);
//4 clean status segment
memset(spi_status, 0x00, GSPI_STATUS_LEN);
spi_transfer((u8 *) spi_buf, spi_buf_len);
// data segement reorder
buf_endian_reverse(spi_data, len, &dummy_bytes, gspi_conf);
// status segment reorder
spi_status += dummy_bytes;
buf_endian_reverse(spi_status, GSPI_STATUS_LEN, &dummy_bytes, gspi_conf);
pmore_data->more_data = GET_STATUS_HISR(spi_status) & SPI_HIMR_RX_REQUEST_MSK;
pmore_data->len = GET_STATUS_RXQ_REQ_LEN(spi_status);
return 0;
}
static int gspi_write_tx_fifo(u8 *buf, u32 len, _gspi_conf_t gspi_conf)
{
int fun = 1; //TX_HIQ_FIFO
unsigned int cmd = 0;
u8 *spi_buf = (u8 *) (buf);
u8* spi_data = spi_buf + GSPI_CMD_LEN;
u8* spi_status;// = buf + len
u32 spi_buf_len = 0;
u32 NumOfFreeSpace;
u8 wait_num = 0;
u8 dummy_bytes = 0;
NumOfFreeSpace = gspi_read32(LOCAL_REG_FREE_TX_SPACE, NULL);
while (NumOfFreeSpace * (PACK_SIZE+SIZE_TX_DESC) < len) {
if((++wait_num) >= 4){
DBG_8195A("%s(): wait_num is >= 4\n", __FUNCTION__);
return -1;
}
rtw_udelay_os(100); //delay 100us
NumOfFreeSpace = gspi_read32(LOCAL_REG_FREE_TX_SPACE, NULL);
}
cmd = FILL_SPI_CMD(len, ((len&0xff00) >>8), SPI_TXFIFO_DOMAIN, fun, (unsigned int)1);
//4 command segment bytes reorder
cmd = DWORD_endian_reverse(cmd, gspi_conf);
memcpy(spi_buf, (u8 *)&cmd, GSPI_CMD_LEN);
//4 data segment bytes reorder
buf_endian_reverse(spi_data, len, &dummy_bytes, gspi_conf);
//4 status segment
spi_status = spi_data + len + dummy_bytes;
memset(spi_status, 0x00, GSPI_STATUS_LEN);
spi_buf_len = GSPI_CMD_LEN + len + dummy_bytes + GSPI_STATUS_LEN;
spi_transfer((u8 *) spi_buf, spi_buf_len);
// parse status infomation
// GET_STATUS_HISR(status)
// GET_STATUS_FREE_TX(status)
// GET_STATUS_RXQ_REQ_LEN(status)
// GET_STATUS_TX_SEQ(status)
return 0;
}
static int gspi_write_page(u8 *buf, u32 len, u8 agg_cnt){
int res;
u32 tot_len = SIZE_TX_DESC + len;
PGSPI_TX_DESC ptxdesc;
// clean GSPI command and tx descriptor area
memset(TX_BUFFER, 0, GSPI_CMD_LEN+SIZE_TX_DESC);
ptxdesc = (PGSPI_TX_DESC)(TX_BUFFER + GSPI_CMD_LEN); // reserve 4 byte for GSPI cmd
ptxdesc->txpktsize = len;
ptxdesc->offset = SIZE_TX_DESC;
ptxdesc->bus_agg_num = agg_cnt;
ptxdesc->type = GSPI_CMD_TX;
memcpy(TX_BUFFER+GSPI_CMD_LEN+SIZE_TX_DESC, buf, len);
res = gspi_write_tx_fifo(TX_BUFFER, tot_len, GSPI_CONFIG);
return res;
}
int gspi_configuration(_gspi_conf_t gspi_conf){
u8 conf = gspi_conf;
u8 retry_t = 0;
retry:
/*GSPI default mode: SPI_LITTLE_ENDIAN_32*/
gspi_read_write_reg(WRITE_REG, SPI_LOCAL_OFFSET|SPI_REG_SPI_CFG,(char *)&conf,1 ,SPI_LITTLE_ENDIAN_32);
// read gspi config
conf = 0xff;
conf = gspi_read8(SPI_LOCAL_OFFSET|SPI_REG_SPI_CFG, NULL);
if(conf != gspi_conf){
if(++ retry_t <= 3)
goto retry;
DBG_8195A("%s: config fail@ 0x%x\n", __FUNCTION__, conf);
return 1;
}
char *s;
switch (conf) {
case SPI_LITTLE_ENDIAN_16:
s = "LITTLE_ENDIAN|WORD_LEN_16"; break;
case SPI_LITTLE_ENDIAN_32:
s = "LITTLE_ENDIAN|WORD_LEN_32"; break;
case SPI_BIG_ENDIAN_16:
s = "BIG_ENDIAN|WORD_LEN_16"; break;
case SPI_BIG_ENDIAN_32:
s = "BIG_ENDIAN|WORD_LEN_32"; break;
default:
s = "UNKNOW CONFIGURATION"; break;
};
DBG_8195A("%s: Current configuration:%s\n", __FUNCTION__, s);
return 0;
}
u8 check_trx_data(u8 *src,u8*dst,u16 len){
u16 i;
u8 result=1;
for(i=0;i<len;i++)
if(*(src+i) !=*(dst+i)){
result=0;
break;
}
return result;
}
#if CONFIG_USE_INTERRUPT
void spi_interrupt_thread(){
u32 spi_hisr;
u32 spi_himr;
u32 rx_cnt = 0;
while(1){
if (rtw_down_sema(&pspiIrqSemaphore) == _FAIL){
DBG_8195A("%s, Take Semaphore Fail\n", __FUNCTION__);
goto exit;
}
spi_himr = gspi_read32(SPI_LOCAL_OFFSET | SPI_REG_HIMR, NULL);
spi_hisr = gspi_read32(SPI_LOCAL_OFFSET | SPI_REG_HISR, NULL);
if (spi_hisr & spi_himr){
if(spi_hisr & SPI_HISR_RX_REQUEST) {
u8* rx_buf = NULL;
u8* payload = NULL;
u32 rx_len = 0;
u8 rx_len_rdy = 0;
PINIC_RX_DESC prxdesc;
struct spi_more_data more_data = {0};
// clean RX buffer
memset(RX_DATA, 0, AGG_SIZE + 100);
rx_buf = RX_DATA;
do {
//validate RX_LEN_RDY before reading RX0_REQ_LEN
if(rx_len==0){
rx_len_rdy = gspi_read8(SPI_LOCAL_OFFSET|(SPI_REG_RX0_REQ_LEN + 3), NULL);
if(rx_len_rdy & BIT7){
rx_len = (gspi_read32(SPI_LOCAL_OFFSET | SPI_REG_RX0_REQ_LEN, NULL)) &0xffffff;
}
}
if (rx_len >(PACK_SIZE+SIZE_RX_DESC))
rx_len = PACK_SIZE+SIZE_RX_DESC;
if(rx_len){
memset(RX_BUFFER, 0, BUFFER_LEN);
gspi_read_rx_fifo(RX_BUFFER, rx_len, &more_data,GSPI_CONFIG);
memcpy(rx_buf, RX_BUFFER+GSPI_CMD_LEN, rx_len);
prxdesc = (PINIC_RX_DESC)rx_buf;
DBG_8195A("Receive Data lenth = %d (cnt = %d)\n",prxdesc->pkt_len, ++rx_cnt);
payload = rx_buf + prxdesc->offset;
rx_buf += rx_len;
rx_len = 0;
rx_done=1;
}else{
break;
}
}while(1);
}
}
// query other interrupt here
}
exit:
vTaskDelete(NULL);
}
#endif
// external GSPI interrupt handler
void gspi_irq_handler (uint32_t id, gpio_irq_event event)
{
//DBG_8195A("gspi_irq_handler....\n");
if(!pspiIrqSemaphore)
return;
rtw_up_sema_from_isr(&pspiIrqSemaphore);
}
// SPI master interrupt callback if use interrupt mode
void spi_tx_rx_intr_callback(void *pdata, SpiIrq event){
switch(event){
case SpiRxIrq:
rxDone = TRUE;
break;
case SpiTxIrq:
txDone = TRUE;
break;
default:
DBG_8195A("unknown interrput evnent!\n");
}
}
void spi_tx_bus_idle_callback(void *pdata, SpiIrq event){
txbusIdle = TRUE;
}
void spi_init_intr(){
#if CONFIG_USE_INTERRUPT
// init gspi external interrupt
gpio_irq_init(&gpio_int, GPIO_INT, gspi_irq_handler, NULL);
gpio_irq_set(&gpio_int, IRQ_FALL, 1); // Falling Edge Trigger
gpio_irq_enable(&gpio_int);
#endif
// init spi master tx/rx done interrupt
spi_irq_hook(&spi0_master, (spi_irq_handler)spi_tx_rx_intr_callback, NULL);
// init spi master tx bus idle interrupt
spi_bus_tx_done_irq_hook(&spi0_master, (spi_irq_handler)spi_tx_bus_idle_callback, NULL);
}
void spi_init_master(){
// init spi master
spi0_master.spi_idx=MBED_SPI1;
spi_init(&spi0_master, SPI0_MOSI, SPI0_MISO, SPI0_SCLK, SPI0_CS);
spi_format(&spi0_master, SPI_BITS, 0, 0);
spi_frequency(&spi0_master, SPI0_FREQUENCY);
printf("spi master frequency %d Hz\n",SPI0_FREQUENCY);
gpio_init(&gpio_cs, GPIO_CS);
gpio_mode(&gpio_cs, PullDown);
gpio_dir(&gpio_cs, PIN_OUTPUT);
SLAVE_DESELECT(); // deselect slave
}
#endif
void gspi_demo(void)
{
#if CONFIG_GSPI_SLAVE
int i;
DBG_8195A("Init GSPI slave....\n");
spdio_dev.priv = NULL;
spdio_dev.rx_bd_num = SPDIO_RX_BD_NUM;
spdio_dev.tx_bd_num = SPDIO_TX_BD_NUM;
spdio_dev.rx_bd_bufsz = SPDIO_RX_BUFSZ;
spdio_dev.rx_buf = (struct spdio_buf_t *)rtw_malloc(SPDIO_RX_BD_NUM*sizeof(struct spdio_buf_t));
for(i=0;i<SPDIO_RX_BD_NUM;i++){
spdio_dev.rx_buf[i].buf_allocated = (u32)rtw_malloc(SPDIO_RX_BUFSZ + SPDIO_DMA_ALIGN_4);
if(!spdio_dev.rx_buf[i].buf_allocated){
printf("malloc failed for spdio buffer!\n");
return;
}
spdio_dev.rx_buf[i].size_allocated = SPDIO_RX_BUFSZ + SPDIO_DMA_ALIGN_4;
// this buffer must be 4 byte alignment
spdio_dev.rx_buf[i].buf_addr = (u32)N_BYTE_ALIGMENT((u32)(spdio_dev.rx_buf[i].buf_allocated), SPDIO_DMA_ALIGN_4);
}
spdio_dev.rx_done_cb = ex_gspi_rx_done_cb;
spdio_dev.tx_done_cb = ex_gspi_tx_done_cb;
DBG_INFO_MSG_OFF(_DBG_SDIO_);
DBG_WARN_MSG_OFF(_DBG_SDIO_);
DBG_ERR_MSG_ON(_DBG_SDIO_);
spdio_init(&spdio_dev);
DBG_8195A("Init GSPI slave Done,Ready for TRx....\n");
#else
DBG_8195A("Init SPI master....\n");
u32 spi_himr = 0;
u32 spi_hisr = 0;
u32 spi_ictlr = 0;
u32 rx_agg_ctrl = 0;
s8 res = 0;
int test_loop = 1000;
u16 counter=0;
//1 SPI host init
spi_init_master();
spi_init_intr();
rtw_init_sema(&pspiIrqSemaphore, 0);
// used for sync SPI bus, SPI bus shold not be interrupt
rtw_mutex_init(&SPIbusbusy);
if( xTaskCreate( (TaskFunction_t)spi_interrupt_thread, "SPI INTERRUPT", (TASK_STACK_SIZE/4), NULL, TASK_PRIORITY+2, NULL) != pdPASS) {
DBG_8195A("Cannot create SPI INTERRUPT task\n\r");
goto err;
}
//1 GSPI slave configuration
res = gspi_configuration(GSPI_CONFIG);
if(res){
DBG_8195A("gspi configure error....\n");
while(1);
}
// INT_CTRL-clean INT control register
spi_ictlr = 0;
gspi_write32(SPI_LOCAL_OFFSET |SPI_REG_INT_CTRL, spi_ictlr, NULL);
// HISR - clean interrupt status register
gspi_write32(SPI_LOCAL_OFFSET |SPI_REG_HISR, 0xFFFFFFFF, NULL);
// HIMR - turn all off
gspi_write32(SPI_LOCAL_OFFSET |SPI_REG_HIMR, SPI_HIMR_DISABLED, NULL);
// Set intterrupt mask
spi_himr = (u32)(SPI_HISR_RX_REQUEST|SPI_HISR_CPWM1_INT);
// Write and enable interrupt
gspi_write32(SPI_LOCAL_OFFSET | SPI_REG_HIMR, spi_himr, NULL);
#if 1
// set RX AGG control register
rx_agg_ctrl = 0;
gspi_write32(SPI_LOCAL_OFFSET | SPI_REG_RX_AGG_CTL, rx_agg_ctrl, NULL);
#endif
DBG_8195A("Loopback Test Start...\n");
// prepare test data (0x00-0xFF, 0x00-0xFF......)
for(int i=0;i<PACK_SIZE;i++)
memset(TX_DATA+i, i%256, 1);
do{
res = gspi_write_page(TX_DATA, PACK_SIZE, 1);
if(res) {
DBG_8195A("spi_write_page: Error!\n");
// handle error msg here
}
counter=0;
while (!rx_done){
counter++;
rtw_mdelay_os(10);
if(counter==100){
DBG_8195A("Master Rx data Timeout... test aborted!\n");
goto err;
}
}
rx_done=0;
if(check_trx_data(TX_DATA,RX_DATA+SIZE_RX_DESC,PACK_SIZE))
DBG_8195A("loop %d Test Succeed!\n",1000-test_loop);
else {
DBG_8195A("loop %d Test Failed!\n",1000-test_loop);
goto err;
}
rtw_mdelay_os(500);
}while(--test_loop);
#if !CONFIG_USE_INTERRUPT
#endif
#endif
err:
// spi_free(&spi0_master);
/* Kill init thread after all init tasks done */
vTaskDelete(NULL);
}
void main(void)
{
// create demo Task
if( xTaskCreate( (TaskFunction_t)gspi_demo, "GSPI DEMO", (TASK_STACK_SIZE/4), NULL, TASK_PRIORITY, NULL) != pdPASS) {
DBG_8195A("Cannot create demo task\n\r");
}
#if defined(CONFIG_KERNEL) && !TASK_SCHEDULER_DISABLED
#ifdef PLATFORM_FREERTOS
vTaskStartScheduler();
#endif
#else
#error !!!Need FREERTOS!!!
#endif
}

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/**
******************************************************************************
* @file rtl8710b_gspi_host.h
* @author
* @version V1.0.0
* @date 2016-12-9
* @brief This file contains all the functions prototypes for the GSPI firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef __RTL8710B_GSPI_H__
#define __RTL8710B_GSPI_H__
#define SPI_LOCAL_DOMAIN 0x0
#define SPI_TXFIFO_DOMAIN 0xc
#define SPI_RXFIFO_DOMAIN 0x1f
//IO Bus domain address mapping
#define DEFUALT_OFFSET 0x0
#define SPI_LOCAL_OFFSET 0x10250000
#define SPI_TX_FIFO_OFFSET 0x10310000
#define SPI_RX_FIFO_OFFSET 0x10340000
#define SPI_LOCAL_DEVICE_ID 0
#define SPI_TXQ_FIFO_DEVICE_ID 3
#define SPI_RXQ_FIFO_DEVICE_ID 7
#define SPI_UNDEFINED_DEVICE_ID (-1)
//SPI Local registers
#define SPI_REG_INT_CTRL 0x0004 // 4 bytes, SPI INT Control
#define SPI_REG_INT_TIMEOUT 0x0006 // 2 bytes, SPI 32us INT timout
#define SPI_REG_HIMR 0x0014 // 4 bytes, SPI Host Interrupt Mask
#define SPI_REG_HISR 0x0018 // 4 bytes, SPI Host Interrupt Service Routine
#define SPI_REG_RX0_REQ_LEN 0x001C // 4 bytes, RXDMA Request Length
#define SPI_REG_FREE_TX_SPACE 0x0020 // 4 bytes, Free Tx Buffer Page
#define SPI_REG_TX_SEQNUM 0x0024 // 1 byte, TX Sequence Number Definition
#define SPI_REG_HCPWM 0x0038 // 1 byte, HCI Current Power Mode
#define SPI_REG_HCPWM2 0x003A // 2 bytes, HCI Current Power Mode 2
#define SPI_REG_AVAI_PATH_L 0x0040 // 4 bytes, SPI TX Available Low Size reg
#define SPI_REG_AVAI_PATH_H 0x0044 // 4 bytes, SPI TX Available High Size reg
#define SPI_REG_RX_AGG_CTL 0x0048 // 4 bytes, SPI RX AGG control
#define SPI_REG_H2C_MSG 0x004C // 4 bytes, SPI_REG_H2C_MSG
#define SPI_REG_C2H_MSG 0x0050 // 4 bytes, SPI_REG_C2H_MSG
#define SPI_REG_HRPWM 0x0080 // 1 byte, SPI_REG_HRPWM
#define SPI_REG_HRPWM2 0x82 // 2bytes, driver to FW, host domain, sync to CRPWM2
#define SPI_REG_HPS_CLKR 0x0084 // 1 byte, not uesd
#define SPI_REG_CPU_IND 0x0087 // 1 byte, firmware indication to host
#define SPI_REG_32K_TRANS_CTL 0x0088 // 1 byte, 32K transparent control, BIT0 EN32K_TRANS
#define SPI_REG_32K_IDLE_TIME 0x008B // 1 byte, 32K idle time,
#define SPI_REG_DELY_LINE_SEL 0x008C // 1 byte, Delay line selection,
#define SPI_REG_SPI_CFG 0x00F0 // 1 byte, SPI configuration,
#define LOCAL_REG_FREE_TX_SPACE (SPI_LOCAL_OFFSET | SPI_REG_FREE_TX_SPACE)
// Register SPI_REG_CPU_IND
#define SPI_CPU_RDY_IND (BIT0)
#define SPI_MEM_WR_DONE (BIT1)
/************************************************/
// SPI_REG_HISR: SDIO Host Interrupt Service Routine
#define SPI_HISR_RX_REQUEST (BIT0)
#define SPI_HISR_AVAL_INT (BIT1)
#define SPI_HISR_TXPKT_OVER_BUFF (BIT2)
#define SPI_HISR_TX_AGG_SIZE_MISMATCH (BIT3)
#define SPI_HISR_TXBD_OVF (BIT4)
//BIT5~16 not used
#define SPI_HISR_C2H_MSG_INT (BIT17)
#define SPI_HISR_CPWM1_INT (BIT18)
#define SPI_HISR_CPWM2_INT (BIT19)
//BIT20~31 not used
#define SPI_HISR_CPU_NOT_RDY (BIT22)
/*
#define MASK_SPI_HISR_CLEAR (SPI_HISR_RX_REQUEST |\
SPI_HISR_AVAL_INT |\
SPI_HISR_TXPKT_OVER_BUFF |\
SPI_HISR_TX_AGG_SIZE_MISMATCH |\
SPI_HISR_TXBD_OVF |\
SPI_HISR_C2H_MSG_INT |\
SPI_HISR_CPWM1_INT |\
SPI_HISR_CPWM2_INT)
*/
#define MASK_SPI_HISR_CLEAR (SPI_HISR_TXPKT_OVER_BUFF |\
SPI_HISR_TX_AGG_SIZE_MISMATCH |\
SPI_HISR_TXBD_OVF |\
SPI_HISR_C2H_MSG_INT |\
SPI_HISR_CPWM1_INT |\
SPI_HISR_CPWM2_INT)
// RTL8195A SPI Host Interrupt Mask Register
#define SPI_HIMR_RX_REQUEST_MSK (BIT0)
#define SPI_HIMR_AVAL_MSK (BIT1)
#define SPI_HIMR_TXPKT_SIZE_OVER_BUFF_MSK (BIT2)
#define SPI_HIMR_AGG_SIZE_MISMATCH_MSK (BIT3)
#define SPI_HIMR_TXBD_OVF_MSK (BIT4)
//BIT5~16 not used
#define SPI_HIMR_C2H_MSG_INT_MSK (BIT17)
#define SPI_HIMR_CPWM1_INT_MSK (BIT18)
#define SPI_HIMR_CPWM2_INT_MSK (BIT19)
//BIT20~31 not used
#define SPI_HIMR_DISABLED 0
// Register SPI_REG_HCPWM
#define SPI_HCPWM_WLAN_TRX (BIT1)
enum{
SPI_LITTLE_ENDIAN = 2,
SPI_BIG_ENDIAN = 0
};
enum{
SPI_WORD_LEN_16 = 0,
SPI_WORD_LEN_32 = 1
};
typedef enum{
SPI_LITTLE_ENDIAN_16 = SPI_LITTLE_ENDIAN|SPI_WORD_LEN_16,
SPI_LITTLE_ENDIAN_32 = SPI_LITTLE_ENDIAN|SPI_WORD_LEN_32, // default configure
SPI_BIG_ENDIAN_16 = SPI_BIG_ENDIAN|SPI_WORD_LEN_16,
SPI_BIG_ENDIAN_32 = SPI_BIG_ENDIAN|SPI_WORD_LEN_32
}_gspi_conf_t;
#define GSPI_CMD_LEN 4
#define GSPI_STATUS_LEN 8
#define FILL_SPI_CMD(byte_en, addr, domain_id, fun, write_flag) ((byte_en & 0xff) | ((addr & 0xffff) << 8) \
| ((domain_id & 0x1f) << 24) | ((fun & 0x3) << 29) | ((write_flag & 0x1) << 31))
#define GET_STATUS_HISR(status) ((((*(u32*)status)) & 0x3) |((((*(u32*)status) >> 2) & 0x7) << 17))
#define GET_STATUS_FREE_TX(status) ((((*(u32*)status) >> 5) & 0x7ffffff) << 2)
#define GET_STATUS_RXQ_REQ_LEN(status) (((*(u32*)((u8 *)status + 4))) & 0xffffff)
#define GET_STATUS_TX_SEQ(status) (((*(u32*)((u8 *)status + 4)) >> 24) & 0xff)
#define GSPI_CMD_TX 0x83 //
#define GSPI_CMD_RX 0X82
// define transmit packat type
#define GPSI_TX_PACKET_802_3 (0x83)
#define GSPI_TX_PACKET_802_11 (0x81)
#define GSPI_TX_H2C_CMD (0x11)
#define GSPI_TX_MEM_READ (0x51)
#define GSPI_TX_MEM_WRITE (0x53)
#define GSPI_TX_MEM_SET (0x55)
#define GSPI_TX_FM_FREETOGO (0x61)
#define GSPI_TX_PACKET_USER (0x41)
//define receive packet type
#define GSPI_RX_PACKET_802_3 (0x82)
#define GSPI_RX_PACKET_802_11 (0x80)
#define GSPI_RX_C2H_CMD (0x10)
#define GSPI_RX_MEM_READ (0x50)
#define GSPI_RX_MEM_WRITE (0x52)
#define GSPI_RX_MEM_SET (0x54)
#define GSPI_RX_FM_FREETOGO (0x60)
#define GSPI_RX_PACKET_USER (0x40)
typedef struct {
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 data:8; // bit[8:15], the value to be written to the memory
u32 reply:1; // bit[16], request to send a reply message
u32 rsvd0:15;
#else
u32 rsvd0:15;
u32 reply:1; // bit[16], request to send a reply message
u32 data:8; // bit[8:15], the value to be written to the memory
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 start_addr; // memory write/read start address, function start address
// u4Byte 3
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 data_len:16; // bit[15:0], the length to write/read
u32 rsvd2:16; // bit[31:16]
#else
u32 rsvd2:16; // bit[31:16]
u32 data_len:16; // bit[15:0], the length to write/read
#endif
} GSPI_TX_DESC, *PGSPI_TX_DESC;
typedef struct {
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 pkt_len:16; // bit[15:0], the packet size
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 rsvd0:6; // bit[29:24]
u32 icv:1; //icv error
u32 crc:1; // crc error
#else
u32 rsvd0:6; // bit[29:24]
u32 icv:1; //icv error
u32 crc:1; // crc error
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 pkt_len:16; // bit[15:0], the packet size
#endif
// u4Byte 1
/************************************************/
/*****************receive packet type*********************/
/* 0x82: 802.3 packet */
/* 0x80: 802.11 packet */
/* 0x10: C2H command */
/* 0x50: Memory Read */
/* 0x52: Memory Write */
/* 0x54: Memory Set */
/* 0x60: Indicate the firmware is started */
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the type of this packet
u32 rsvd1:24; // bit[31:8]
#else
u32 rsvd1:24; // bit[31:8]
u32 type:8; // bit[7:0], the type of this packet
#endif
// u4Byte 2
u32 start_addr;
// u4Byte 3
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 data_len:16; // bit[15:0], the type of this packet
u32 result:8; // bit[23:16], the result of memory write command
u32 rsvd2:8; // bit[31:24]
#else
u32 rsvd2:8; // bit[31:24]
u32 result:8; // bit[23:16], the result of memory write command
u32 data_len:16; // bit[15:0], the type of this packet
#endif
} GSPI_RX_DESC, *PGSPI_RX_DESC;
#define SIZE_TX_DESC (sizeof(GSPI_TX_DESC))
#define SIZE_RX_DESC (sizeof(GSPI_RX_DESC))
// CCPWM2 bit map definition for Firmware download
#define GSPI_INIT_DONE (BIT0)
#define GSPI_MEM_WR_DONE (BIT1)
#define GSPI_MEM_RD_DONE (BIT2)
#define GSPI_MEM_ST_DONE (BIT3)
#define GSPI_CPWM2_TOGGLE (BIT15)
// Register REG_SPDIO_CPU_IND
#define GPSI_SYSTEM_TRX_RDY_IND (BIT0)
#endif //__GSPI_REG_H__

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Example Description
This example describes SPI Master how to download firmware to GSPI slave.
copy "src/main.c" to cover the original ones under the default project path.
Users can use their own image to replace default image,do as follows:
(1)Prepare ram_1.bin & ram_2.bin: Slave firmware
(2)Use bin array tools to change ram_1.bin and ram_2.bin to array ram1 and ram2,
and copy array ram1 and ram2 to the Master main.c.
Requirement Components:
2 AmebaZ_DEV01 are needed in this demo:One(AmebaZ-1) is Assigned as SPI master,the other (AmebaZ-2) is Assigned as GSPI slave
AmebaZ-1:SPI master
SPI0_SCLK : PA_18
GPIO_CS : PA_28
SPI0_MOSI : PA_23
SPI0_MISO : PA_22
AmebaZ-2:GSPI slave (must be configured as boot from SDIO)
SPI_IN : PA_22
SPI_OUT : PA_20
SPI_CLK : PA_21
SPI_CS : PA_19
Build bin files:
1. example_sources\gspi_mp_downloader\src\main.c
(A) boot_all.bin & image2_all_ota1.bin: Host firmware downloader
Demo setup:
Use ImageTool.exe to load firmware (A) to host. (Highly Recommended: Erase the whole flash first)
connect AmebaZ-1 and AmebaZ-2 as given
AmebaZ-1 : AmebaZ-2
SPI0_SCLK ---- SPI_CLK
GPIO_CS ---- SPI_CS
SPI0_MOSI ---- SPI_OUT
SPI0_MISO ---- SPI_IN
V3.3 --- V3.3
GND --- GND
Behavior:
1. Slave end boot from SDIO, waiting master end download firmware
2. Master end download firmware to slave end, and wait slave firmware ready
3. Slave boot from SDIO Succeeds.

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