mirror of
https://github.com/drasko/open-ameba.git
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94 lines
1.8 KiB
C
94 lines
1.8 KiB
C
/*
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* Routines to access hardware
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*
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* Copyright (c) 2015 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#include "device.h"
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#include "serial_api.h"
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#include "serial_ex_api.h"
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#include "main.h"
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#define UART_TX PA_7
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#define UART_RX PA_6
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/* 100 bytes data, 500 clocks, provide buadrate/2 frequency */
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#define SREAM_LEN 128
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char sim_clock[SREAM_LEN+1];
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volatile uint32_t is_stop = 0;
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static serial_t sobj_clk;
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void uart_clock_send_string(serial_t *sobj, char *pstr)
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{
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int32_t ret=0;
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ret = serial_send_stream_dma(sobj, pstr, _strlen(pstr));
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if (ret != 0) {
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DBG_8195A("%s Error(%d)\n", __FUNCTION__, ret);
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}
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}
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void uart_clock_send_string_done(uint32_t id)
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{
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serial_t *sobj = (void*)id;
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if(!is_stop)
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uart_clock_send_string(sobj, sim_clock);
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}
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void uart_clock_deinit(void)
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{
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is_stop = 1;
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serial_free(&sobj_clk);
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}
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void uart_clock_init(int rate)
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{
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//serial_t sobj;
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int ret;
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int i;
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for (i=0;i<SREAM_LEN;i++) {
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sim_clock[i] = 0x55;
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}
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sim_clock[i] = 0;
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serial_init(&sobj_clk,UART_TX,UART_RX);
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serial_baud(&sobj_clk, rate*2);
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serial_format(&sobj_clk, 8, ParityNone, 0);
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serial_send_comp_handler(&sobj_clk, (void*)uart_clock_send_string_done, (uint32_t) &sobj_clk);
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}
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void uart_clock_on(void)
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{
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is_stop = 0;
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uart_clock_send_string(&sobj_clk, sim_clock);
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}
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void uart_clock_off(void)
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{
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is_stop = 1;
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serial_send_stream_abort(&sobj_clk);
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}
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void main(void)
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{
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// only support 33kHz, 36kHz, 36.7kHz 38kHz, 40kHz, 56kHz
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uart_clock_init(38000);
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while(1) {
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uart_clock_on();
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wait_ms(5000);
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uart_clock_off();
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wait_ms(5000);
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}
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}
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