mirror of
https://github.com/drasko/open-ameba.git
synced 2024-11-24 23:14:17 +00:00
336 lines
9.8 KiB
C
336 lines
9.8 KiB
C
/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef _HAL_SSI_H_
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#define _HAL_SSI_H_
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#include "rtl8195a_ssi.h"
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/**
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* LOG Configurations
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*/
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extern u32 SSI_DBG_CONFIG;
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extern uint8_t SPI0_IS_AS_SLAVE;
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#define SSI_DBG_ENTRANCE(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENTRANCE)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE ANSI_COLOR_GREEN __VA_ARGS__ ANSI_COLOR_RESET); \
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}while(0)
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#define SSI_DBG_INIT(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
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}while(0)
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#define SSI_DBG_INIT_V(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_V)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
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}while(0)
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#define SSI_DBG_INIT_VV(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_VV)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
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}while(0)
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#define SSI_DBG_PINMUX(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_PINMUX)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
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}while(0)
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#define SSI_DBG_ENDIS(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENDIS)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
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}while(0)
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#define SSI_DBG_INT(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
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}while(0)
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#define SSI_DBG_INT_V(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_V)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
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}while(0)
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#define SSI_DBG_INT_HNDLR(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_HNDLR)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
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}while(0)
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#define SSI_DBG_INT_READ(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_READ)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
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}while(0)
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#define SSI_DBG_INT_WRITE(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_WRITE)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
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}while(0)
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#define SSI_DBG_STATUS(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_STATUS)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
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}while(0)
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#define SSI_DBG_FIFO(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_FIFO)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
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}while(0)
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#define SSI_DBG_READ(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_READ)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
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}while(0)
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#define SSI_DBG_WRITE(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_WRITE)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
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}while(0)
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#define SSI_DBG_SLV_CTRL(...) do {\
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if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_SLV_CTRL)) \
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DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
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}while(0)
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typedef enum _SSI_DBG_TYPE_LIST_ {
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DBG_TYPE_ENTRANCE = 1 << 0,
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DBG_TYPE_INIT = 1 << 1,
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DBG_TYPE_INIT_V = 1 << 2,
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DBG_TYPE_INIT_VV = 1 << 3,
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DBG_TYPE_PINMUX = 1 << 4,
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DBG_TYPE_ENDIS = 1 << 5,
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DBG_TYPE_INT = 1 << 6,
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DBG_TYPE_INT_V = 1 << 7,
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DBG_TYPE_INT_HNDLR = 1 << 8,
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DBG_TYPE_INT_READ = 1 << 9,
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DBG_TYPE_INT_WRITE = 1 << 10,
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DBG_TYPE_STATUS = 1 << 11,
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DBG_TYPE_FIFO = 1 << 12,
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DBG_TYPE_READ = 1 << 13,
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DBG_TYPE_WRITE = 1 << 14,
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DBG_TYPE_SLV_CTRL = 1 << 15
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} SSI_DBG_TYPE_LIST, *PSSI_DBG_TYPE_LIST;
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typedef struct _SSI_DMA_CONFIG_ {
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VOID *pHalGdmaOp;
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VOID *pTxHalGdmaAdapter;
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VOID *pRxHalGdmaAdapter;
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u8 RxDmaBurstSize;
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u8 TxDmaBurstSize;
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u8 RxDmaEnable;
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u8 TxDmaEnable;
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IRQ_HANDLE RxGdmaIrqHandle;
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IRQ_HANDLE TxGdmaIrqHandle;
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}SSI_DMA_CONFIG, *PSSI_DMA_CONFIG;
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#ifdef CONFIG_GDMA_EN
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typedef struct _HAL_SSI_DMA_MULTIBLK_ {
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volatile GDMA_CH_LLI_ELE GdmaChLli[16];
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struct GDMA_CH_LLI Lli[16];
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struct BLOCK_SIZE_LIST BlockSizeList[16];
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}SSI_DMA_MULTIBLK, *PSSI_DMA_MULTIBLK;
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#endif
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/**
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* DesignWare SSI Configurations
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*/
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typedef struct _HAL_SSI_ADAPTOR_ {
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SSI_DMA_CONFIG DmaConfig;
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IRQ_HANDLE IrqHandle;
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//
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VOID (*RxCompCallback)(VOID *Para);
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VOID *RxCompCbPara;
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VOID *RxData;
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VOID (*TxCompCallback)(VOID *Para);
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VOID *TxCompCbPara;
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VOID *TxData;
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u32 DmaRxDataLevel;
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u32 DmaTxDataLevel;
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u32 InterruptPriority;
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u32 RxLength;
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u32 RxLengthRemainder;
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u32 RxThresholdLevel;
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u32 TxLength;
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u32 TxThresholdLevel;
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u32 SlaveSelectEnable;
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//
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u16 ClockDivider;
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u16 DataFrameNumber;
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//
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u8 ControlFrameSize;
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u8 DataFrameFormat;
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u8 DataFrameSize;
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u8 DmaControl;
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u8 Index;
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u8 InterruptMask;
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u8 MicrowireDirection;
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u8 MicrowireHandshaking;
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u8 MicrowireTransferMode;
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u8 PinmuxSelect;
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u8 Role;
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u8 SclkPhase;
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u8 SclkPolarity;
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u8 SlaveOutputEnable;
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u8 TransferMode;
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u8 TransferMechanism;
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// Extend
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u8 Reserve;
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u8 HaveTxChannel;
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u8 HaveRxChannel;
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u8 DefaultRxThresholdLevel;
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#ifdef CONFIG_GDMA_EN
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SSI_DMA_MULTIBLK DmaTxMultiBlk, DmaRxMultiBlk;
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#endif
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u32 ReservedDummy;
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VOID (*TxIdleCallback)(VOID *Para);
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VOID *TxIdleCbPara;
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}HAL_SSI_ADAPTOR, *PHAL_SSI_ADAPTOR;
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typedef struct _HAL_SSI_OP_{
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HAL_Status (*HalSsiPinmuxEnable)(VOID *Adaptor);
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HAL_Status (*HalSsiPinmuxDisable)(VOID *Adaptor);
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HAL_Status (*HalSsiEnable)(VOID *Adaptor);
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HAL_Status (*HalSsiDisable)(VOID *Adaptor);
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HAL_Status (*HalSsiInit)(VOID *Adaptor);
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HAL_Status (*HalSsiSetSclkPolarity)(VOID *Adaptor);
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HAL_Status (*HalSsiSetSclkPhase)(VOID *Adaptor);
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HAL_Status (*HalSsiWrite)(VOID *Adaptor, u32 value);
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HAL_Status (*HalSsiLoadSetting)(VOID *Adaptor, VOID *Setting);
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HAL_Status (*HalSsiSetInterruptMask)(VOID *Adaptor);
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HAL_Status (*HalSsiSetDeviceRole)(VOID *Adaptor, u32 Role);
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HAL_Status (*HalSsiInterruptEnable)(VOID *Adaptor);
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HAL_Status (*HalSsiInterruptDisable)(VOID *Adaptor);
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HAL_Status (*HalSsiReadInterrupt)(VOID *Adaptor, VOID *RxData, u32 Length);
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HAL_Status (*HalSsiSetRxFifoThresholdLevel)(VOID *Adaptor);
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HAL_Status (*HalSsiSetTxFifoThresholdLevel)(VOID *Adaptor);
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HAL_Status (*HalSsiWriteInterrupt)(VOID *Adaptor, u8 *TxData, u32 Length);
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HAL_Status (*HalSsiSetSlaveEnableRegister)(VOID *Adaptor, u32 SlaveIndex);
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u32 (*HalSsiBusy)(VOID *Adaptor);
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u32 (*HalSsiReadable)(VOID *Adaptor);
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u32 (*HalSsiWriteable)(VOID *Adaptor);
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u32 (*HalSsiGetInterruptMask)(VOID *Adaptor);
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u32 (*HalSsiGetRxFifoLevel)(VOID *Adaptor);
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u32 (*HalSsiGetTxFifoLevel)(VOID *Adaptor);
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u32 (*HalSsiGetStatus)(VOID *Adaptor);
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u32 (*HalSsiGetInterruptStatus)(VOID *Adaptor);
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u32 (*HalSsiRead)(VOID *Adaptor);
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u32 (*HalSsiGetRawInterruptStatus)(VOID *Adaptor);
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u32 (*HalSsiGetSlaveEnableRegister)(VOID *Adaptor);
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}HAL_SSI_OP, *PHAL_SSI_OP;
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typedef struct _DW_SSI_DEFAULT_SETTING_ {
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VOID (*RxCompCallback)(VOID *Para);
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VOID *RxCompCbPara;
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VOID *RxData;
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VOID (*TxCompCallback)(VOID *Para);
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VOID *TxCompCbPara;
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VOID *TxData;
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u32 DmaRxDataLevel;
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u32 DmaTxDataLevel;
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u32 InterruptPriority;
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u32 RxLength;
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u32 RxLengthRemainder;
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u32 RxThresholdLevel;
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u32 TxLength;
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u32 TxThresholdLevel;
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u32 SlaveSelectEnable;
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//
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u16 ClockDivider;
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u16 DataFrameNumber;
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//
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u8 ControlFrameSize;
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u8 DataFrameFormat;
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u8 DataFrameSize;
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u8 DmaControl;
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//u8 Index;
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u8 InterruptMask;
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u8 MicrowireDirection;
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u8 MicrowireHandshaking;
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u8 MicrowireTransferMode;
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//u8 PinmuxSelect;
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//u8 Role;
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u8 SclkPhase;
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u8 SclkPolarity;
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u8 SlaveOutputEnable;
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u8 TransferMode;
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u8 TransferMechanism;
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} DW_SSI_DEFAULT_SETTING, *PDW_SSI_DEFAULT_SETTING;
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struct spi_s {
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HAL_SSI_ADAPTOR spi_adp;
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HAL_SSI_OP spi_op;
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u32 irq_handler;
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u32 irq_id;
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u32 dma_en;
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u32 state;
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u8 sclk;
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#ifdef CONFIG_GDMA_EN
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HAL_GDMA_ADAPTER spi_gdma_adp_tx;
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HAL_GDMA_ADAPTER spi_gdma_adp_rx;
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#endif
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u32 bus_tx_done_handler;
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u32 bus_tx_done_irq_id;
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};
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VOID HalSsiOpInit(VOID *Adaptor);
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static __inline__ VOID HalSsiSetSclk(
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IN PHAL_SSI_ADAPTOR pHalSsiAdapter,
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IN u32 ClkRate)
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{
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HalSsiSetSclkRtl8195a((VOID*)pHalSsiAdapter, ClkRate);
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}
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HAL_Status HalSsiInit(VOID * Data);
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HAL_Status HalSsiDeInit(VOID * Data);
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HAL_Status HalSsiEnable(VOID * Data);
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HAL_Status HalSsiDisable(VOID * Data);
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HAL_Status HalSsiEnterCritical(VOID * Data);
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HAL_Status HalSsiExitCritical(VOID * Data);
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HAL_Status HalSsiTimeout(u32 StartCount, u32 TimeoutCnt);
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HAL_Status HalSsiStopRecv(VOID * Data);
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HAL_Status HalSsiSetFormat(VOID * Data);
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#ifdef CONFIG_GDMA_EN
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HAL_Status HalSsiTxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
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VOID HalSsiTxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
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HAL_Status HalSsiRxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
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VOID HalSsiRxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
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HAL_Status HalSsiRxMultiBlkChnl(PHAL_SSI_ADAPTOR pHalSsiAdapter);
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HAL_Status HalSsiDmaRecv(VOID * Adapter, u8 * pRxData, u32 Length);
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HAL_Status HalSsiDmaSend(VOID *Adapter, u8 *pTxData, u32 Length);
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static __inline__ VOID
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HalSsiDmaInit(
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IN PHAL_SSI_ADAPTOR pHalSsiAdapter
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)
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{
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#if CONFIG_CHIP_E_CUT
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HalSsiDmaInitRtl8195a_V04((void *)pHalSsiAdapter);
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#else
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HalSsiDmaInitRtl8195a((void *)pHalSsiAdapter);
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#endif
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}
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/*
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static __inline__ HAL_Status HalSsiDmaSend(VOID *Adapter, u8 *pTxData, u32 Length)
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{
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return (HalSsiDmaSendRtl8195a(Adapter, pTxData, Length));
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}
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static __inline__ HAL_Status HalSsiDmaRecv(VOID *Adapter, u8 *pRxData, u32 Length)
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{
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return (HalSsiDmaRecvRtl8195a(Adapter, pRxData, Length));
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}
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*/
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#endif // end of "#ifdef CONFIG_GDMA_EN"
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#endif
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