mirror of
https://github.com/drasko/open-ameba.git
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233 lines
7.5 KiB
C
233 lines
7.5 KiB
C
/*
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* rtl_bios_data.h
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*
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* Created on: 12/02/2017
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* Author: pvvx
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*
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* This variables declared in ROM code!
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* Variables use fixed addresses!
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* (see *.ld script)
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*/
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#ifndef _RTL_BIOS_DATA_H_
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#define _RTL_BIOS_DATA_H_
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#include <stdarg.h>
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#include <stddef.h>
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#include <stdio.h>
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#include <sys/reent.h>
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// component/soc/realtek/common/bsp/
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#include "basic_types.h"
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// component/soc/realtek/8195a/fwlib/
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#include "rtl8195a/rtl8195a.h"
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#include "hal_gpio.h"
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#include "hal_irqn.h"
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#include "hal_timer.h"
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#include "hal_sdr_controller.h"
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// component/soc/realtek/8195a/fwlib/
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#include "ram_lib/wlan/realtek/wlan_ram_map/rom/rom_wlan_ram_map.h"
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// component/soc/realtek/8195a/misc/driver/
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#include "rtl_consol.h"
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// component/soc/realtek/8195a/misc/rtl_std_lib/
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#include "include/rtl_lib.h"
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#include "include/rt_lib_rom.h"
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#include "libc/rom/string/rom_libc_string.h"
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#include "libgloss/rtl8195a/rom/rom_libgloss_retarget.h"
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//#include "rom/rom_libgloss_retarget.h"
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typedef void (*START_FUNC)(void);
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/* ROM + startup.c */
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extern IRQ_FUN NewVectorTable[64]; // 10000000
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extern IRQ_FUN UserIrqFunTable[64]; // 10000100
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extern u32 UserIrqDataTable[64]; // 10000200
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/* ROM + diag.h */
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extern u32 CfgSysDebugWarn; // 10000300
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extern u32 CfgSysDebugInfo; // 10000304
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extern u32 CfgSysDebugErr; // 10000308
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extern u32 ConfigDebugWarn; // 1000030c
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extern u32 ConfigDebugInfo; // 10000310
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extern u32 ConfigDebugErr; // 10000314
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/* ROM + hal_timer.h & .. */
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extern HAL_TIMER_OP HalTimerOp; // 10000318
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extern u16 GPIOState[11]; // 10000334 // побитно 16 бит для каждого порта (A..K), бит=номер задействованного пина в порту на периферию.
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extern u32 gTimerRecord; // 1000034C
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/* ROM + hal_ssi.h */
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extern u32 SSI_DBG_CONFIG; // 10000350
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extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter; // 10000354
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/* ROM + rtl8195a_timer.c */
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extern IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM]; // 10000358
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/* ROM + Rand() */
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extern u32 _rand_z4, _rand_z3, _rand_z2, _rand_z1, _rand_first; // 10000370..
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/* ROM + rtl_consol.c */
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extern volatile UART_LOG_CTL *pUartLogCtl; // 10000384
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extern UART_LOG_BUF UartLogBuf; // 10000388
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extern volatile UART_LOG_CTL UartLogCtl; // 10000408
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extern u8 UartLogHistoryBuf[UART_LOG_HISTORY_LEN][UART_LOG_CMD_BUFLEN]; // 10000430 UartLogHistoryBuf[5][127] !
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extern u8 *ArgvArray[MAX_ARGV]; // 100006AC *ArgvArray[10] !
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/* ROM + ?? */
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extern struct _rom_wlan_ram_map rom_wlan_ram_map; // 100006D4
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typedef struct _FALSE_ALARM_STATISTICS {
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u32 Cnt_Parity_Fail;
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u32 Cnt_Rate_Illegal;
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u32 Cnt_Crc8_fail;
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u32 Cnt_Mcs_fail;
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u32 Cnt_Ofdm_fail;
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u32 Cnt_Ofdm_fail_pre;
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u32 Cnt_Cck_fail;
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u32 Cnt_all;
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u32 Cnt_Fast_Fsync;
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u32 Cnt_SB_Search_fail;
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u32 Cnt_OFDM_CCA;
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u32 Cnt_CCK_CCA;
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u32 Cnt_CCA_all;
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u32 Cnt_BW_USC;
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u32 Cnt_BW_LSC;
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} FALSE_ALARM_STATISTICS;
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extern FALSE_ALARM_STATISTICS FalseAlmCnt; // 100006E0
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typedef struct _rom_info {
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u8 EEPROMVersion;
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u8 CrystalCap;
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u64 DebugComponents;
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u32 DebugLevel;
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} ROM_INFO;
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extern ROM_INFO ROMInfo; // 10000720
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typedef struct _CFO_TRACKING_ {
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BOOL bATCStatus;
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BOOL largeCFOHit;
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BOOL bAdjust;
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u8 CrystalCap;
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u8 DefXCap;
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u32 CFO_tail[2];
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u32 CFO_ave_pre;
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u32 packetCount;
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u32 packetCount_pre;
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BOOL bForceXtalCap;
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BOOL bReset;
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u8 CFO_TH_XTAL_HIGH;
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u8 CFO_TH_XTAL_LOW;
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u8 CFO_TH_ATC;
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}CFO_TRACKING;
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extern CFO_TRACKING DM_CfoTrack; // 10000738
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/* in rom_libgloss_retarget.h
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struct _rom_libgloss_ram_map {
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int (*libgloss_close)(int fildes);
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int (*libgloss_fstat)(int fildes , struct stat *st);
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int (*libgloss_isatty)(int file);
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int (*libgloss_lseek)(int file , int ptr , int dir);
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int (*libgloss_open)(char *file , int flags , int mode);
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int (*libgloss_read)(int file , char *ptr , int len);
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int (*libgloss_write)(int file , const char *ptr , int len);
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void* (*libgloss_sbrk)(int incr);
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};
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*/
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extern struct _rom_libgloss_ram_map rom_libgloss_ram_map; // 10000760
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struct malloc_chunk
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{
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size_t prev_size;
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size_t size;
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struct malloc_chunk *fd;
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struct malloc_chunk *bk;
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};
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extern struct malloc_chunk * __rtl_malloc_av_[258]; // 10000780 __rom_mallocr_init_v1_00(), _rtl_free_r_v1_00()..
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extern u32 __rtl_malloc_trim_threshold; // 10000b88 __rom_mallocr_init_v1_00()
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extern u32 __rtl_malloc_top_pad; // 10000b8c __rom_mallocr_init_v1_00()
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extern u8 * __rtl_malloc_sbrk_base; // 10000b90 __rom_mallocr_init_v1_00()
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extern u32 __rtl_malloc_max_sbrked_mem; // 10000b94 __rom_mallocr_init_v1_00()
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extern u32 __rtl_malloc_max_total_mem; // 10000b98 __rom_mallocr_init_v1_00()
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struct mallinfo
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{
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int arena;
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int ordblks;
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int smblks;
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int hblks;
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int hblkhd;
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int usmblks;
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int fsmblks;
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int uordblks;
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int fordblks;
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int keepcost;
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};
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extern struct mallinfo __rtl_malloc_current_mallinfo; // 10000b9c __rom_mallocr_init_v1_00()
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/* IMAGE1 HEAD: ROM + startup.c (bootloader) */
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extern RAM_START_FUNCTION gRamStartFun; // 10000bc8 = { PreProcessForVendor + 1 };
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extern RAM_START_FUNCTION gRamPatchWAKE; // 10000bcc = { RtlBootToSram + 1 };
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extern RAM_START_FUNCTION gRamPatchFun0; // 10000bd0 = { RtlBootToSram + 1 };
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extern RAM_START_FUNCTION gRamPatchFun1; // 10000bd4 = { RtlBootToSram + 1 };
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extern RAM_START_FUNCTION gRamPatchFun2; // 10000bd8 = { RtlBootToSram + 1 };
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extern uint8 RAM_IMG1_VALID_PATTEN[8]; // 10000bdc = { 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff };
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/* ROM + hal_sdr_controller.c */
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extern u32 rand_x; // 10000be4: ChangeRandSeed_rom(), Sdr_Rand2_rom()
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#define REC_NUM 512
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extern u32 AvaWds[2][REC_NUM]; // 10000be8
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extern DRAM_DEVICE_INFO SdrDramInfo; // 10001be8
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#define DRAM_DEVICE_INFO_INIT() { \
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&SdrDramDev, \
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&SdrDramModeReg, \
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&SdrDramTiming, \
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DRAM_TIMING_TCK, \
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DFI_RATIO_1 }
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extern DRAM_TIMING_INFO SdrDramTiming; // 10001bfc
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#define DRAM_TIMING_INFO_INIT() { \
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DRAM_TIMING_TRFC, /* TrfcPs; */ \
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DRAM_TIMING_TREFI, /* TrefiPs; */ \
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DRAM_TIMING_TWRMAXTCK, /* WrMaxTck; */\
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DRAM_TIMING_TRCD, /* TrcdPs; */ \
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DRAM_TIMING_TRP, /* TrpPs; */ \
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DRAM_TIMING_TRAS, /* TrasPs; */ \
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DRAM_TIMING_TRRD, /* TrrdTck; */ \
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DRAM_TIMING_TWR, /* TwrPs; */ \
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DRAM_TIMING_TWTR, /* TwtrTck; */ \
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/* 13090, */ /* TrtpPs; */ \
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DRAM_TIMING_TMRD, /* TmrdTck; */ \
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DRAM_TIMING_TRTP, /* TrtpTck; */ \
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DRAM_TIMING_TCCD, /* TccdTck; */ \
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DRAM_TIMING_TRC } /* TrcPs; */
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extern DRAM_MODE_REG_INFO SdrDramModeReg; // 10001c30
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#define DRAM_MODE_REG_INFO_INIT() { \
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BST_LEN_4, \
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SENQUENTIAL, \
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0x3, /* Mode0Cas: 3 */ \
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0x0, /* Mode0Wr */ \
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0, /* Mode1DllEnN */ \
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0, /* Mode1AllLat */ \
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0 } /* Mode2Cwl */
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extern DRAM_INFO SdrDramDev; // 10001c4c
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#define DRAM_INFO_INIT() { DRAM_INFO_TYPE, DRAM_INFO_COL_ADDR_WTH,DRAM_INFO_BANK_SZ, DRAM_INFO_DQ_WTH }
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//extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // SpicInitParaAllClk[3][6] !
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/* ROM + "C" standard library */
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extern struct _reent * _rtl_impure_ptr; // 10001c60 = { &impure_reent };
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extern struct _reent impure_reent; // 10001c68 = _REENT_INIT(impure_reent);
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/* ROM ? UserData? */
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extern u32 _rom_unc_data[9]; // 100020e8
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/* ROM + hal_sdr_controller.c: Sdr_Rand2() */
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extern u32 _sdr_rnd2_c, _sdr_rnd2_z, _sdr_rnd2_y; // 100020BC, 100020B8, 100020B4
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/* *.ld */
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extern u8 __rom_bss_start__, __rom_bss_end__;
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extern u8 __image1_bss_start__, __image1_bss_end__;
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extern START_FUNC __image2_entry_func__;
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//extern RAM_START_FUNCTION __image2_entry_func__;
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extern u8 __image2_validate_code__;
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#ifndef STACK_TOP
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#define STACK_TOP 0x1ffffffc
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#endif
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#endif /* _RTL_BIOS_DATA_H_ */
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