mirror of
https://github.com/drasko/open-ameba.git
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124 lines
2.5 KiB
INI
124 lines
2.5 KiB
INI
# Main file for Ameba1 series Cortex-M3 parts
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#
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# !!!!!!
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#
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set CHIPNAME rtl8195a
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set CHIPSERIES ameba1
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# Adapt based on what transport is active.
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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error "CHIPNAME not set. Please do not include ameba1.cfg directly."
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}
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if { [info exists CHIPSERIES] } {
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# Validate chip series is supported
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if { $CHIPSERIES != "ameba1" } {
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error "Unsupported chip series specified."
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}
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set _CHIPSERIES $CHIPSERIES
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} else {
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error "CHIPSERIES not set. Please do not include ameba1.cfg directly."
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}
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if { [info exists CPUTAPID] } {
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# Allow user override
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set _CPUTAPID $CPUTAPID
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} else {
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# Ameba1 use a Cortex M3 core.
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if { $_CHIPSERIES == "ameba1" } {
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if { [using_jtag] } {
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set _CPUTAPID 0x4ba00477
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} {
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set _CPUTAPID 0x2ba01477
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}
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
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# Run with *real slow* clock by default since the
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# boot rom could have been playing with the PLL, so
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# we have no idea what clock the target is running at.
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adapter_khz 1000
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# delays on reset lines
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adapter_nsrst_delay 200
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if {[using_jtag]} {
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jtag_ntrst_delay 200
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}
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# Ameba1 (Cortex M3 core) support SYSRESETREQ
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event reset-init {ameba1_init}
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# Ameba1 SDRAM enable
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proc ameba1_init { } {
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# init System
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mww 0x40000014 0x00000021
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sleep 10
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mww 0x40000304 0x1fc00002
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sleep 10
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mww 0x40000250 0x00000400
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sleep 10
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mww 0x40000340 0x00000000
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sleep 10
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mww 0x40000230 0x0000dcc4
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sleep 10
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mww 0x40000210 0x00011117
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sleep 10
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mww 0x40000210 0x00011157
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sleep 10
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mww 0x400002c0 0x00110011
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sleep 10
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mww 0x40000320 0xffffffff
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sleep 10
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# init SDRAM
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mww 0x40000040 0x00fcc702
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sleep 10
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mdw 0x40000040
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mww 0x40005224 0x00000001
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sleep 10
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mww 0x40005004 0x00000208
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sleep 10
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mww 0x40005008 0xffffd000
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sleep 13
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mww 0x40005020 0x00000022
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sleep 13
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mww 0x40005010 0x09006201
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sleep 13
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mww 0x40005014 0x00002611
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sleep 13
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mww 0x40005018 0x00068413
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sleep 13
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mww 0x4000501c 0x00000042
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sleep 13
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mww 0x4000500c 0x700 ;# set Idle
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sleep 20
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mww 0x40005000 0x1 ;# start init
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sleep 100
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mdw 0x40005000
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mww 0x4000500c 0x600 ;# enter memory mode
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sleep 30
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mww 0x40005008 0x00000000 ;# 0xf00
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;# mww 0x40005008 0x00000f00
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sleep 3
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mww 0x40000300 0x0006005e ;# 0x5e
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;# mww 0x40000300 0x0000005e
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sleep 3
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}
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