mirror of
https://github.com/drasko/open-ameba.git
synced 2024-11-29 09:40:28 +00:00
102 lines
3.4 KiB
C
102 lines
3.4 KiB
C
/*
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* Test: Speed rd Flash
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*/
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#include "rtl8195a.h"
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//#include "cortex.h"
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//#include "rtl8710.h"
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//#include "rom_lib.h"
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//#include "mask.h"
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#include "core_cm3.h"
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#include "flash_api.h"
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//extern uint8_t __StackTop;
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int main(void)
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{
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u32 t[10];
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int i = 333333, x = SpicDualBitMode + 1;
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HalPinCtrlRtl8195A(JTAG, 0, 1);
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HalCpuClkConfig(1); // 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
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ConfigDebugErr = -1;
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ConfigDebugInfo = -1;
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ConfigDebugWarn = -1;
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VectorTableInitRtl8195A(0x1FFFFFFC);
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HalInitPlatformLogUartV02();
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HalInitPlatformTimerV02();
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HalShowBuildInfoV02();
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flash_turnon();
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flash_init(&flashobj);
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// HalPinCtrlRtl8195A(SPI_FLASH, 0, 1); // SPI_FLASH_PIN_FCTRL(ON); // enable spi flash pins
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// SpicLoadInitParaFromClockRtl8195AV02();
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// SpicInitRtl8195AV02(2, SpicDualBitMode); //
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// SpicWaitBusyDoneRtl8195A();
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DiagPrintf("Flash[0]: 0x%08X\r\n", *(volatile u32 *)SPI_FLASH_BASE );
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// HalDelayUs(1000000);
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DiagPrintf("CPU CLK : %d Hz\r\n", HalGetCpuClk());
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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if(!(DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk)) {
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DWT->CYCCNT = 0;
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DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
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}
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while(x) {
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x--;
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DiagPrintf("<---- Init %d ---->\n", x);
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if (!SpicFlashInitRtl8195A(x)) {// SpicOneBitMode)){
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DiagPrintf("SPI Init Fail!\n"); // DBG_SPIF_ERR?
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HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO3, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO3)|0xf);
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while(1);
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}
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t[0] = DWT->CYCCNT;
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DiagPrintf("Test: t0 = %d\r\n", DWT->CYCCNT - t[0]);
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t[0] = DWT->CYCCNT;
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volatile u32 * ptr = (volatile u32 *)SPI_FLASH_BASE+0x4000;
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for(i=0; i < 16384; i++) *ptr++;
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t[1] = DWT->CYCCNT - t[0];
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DiagPrintf("read(): tFlash = %d, clk/byte = %d\r\n", t[1], t[1] >> 16);
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ptr = (volatile u32 *)SPI_FLASH_BASE+0x10000;
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t[0] = DWT->CYCCNT;
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memcpy((u8 *)0x10060000,(u8 *) SPI_FLASH_BASE+0x10000, 65536);
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for(i=0; i < 16384; i++) *ptr++;
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t[2] = DWT->CYCCNT - t[0];
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DiagPrintf("memcpy(): tFlash = %d, clk/byte = %d\r\n", t[2], t[2] >> 16);
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ptr = (volatile u32 *)0x10060000;
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t[0] = DWT->CYCCNT;
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for(i=0; i < 16384; i++) *ptr++;
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t[3] = DWT->CYCCNT - t[0];
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DiagPrintf("Speed rd RAM = %d, clk/byte = %d\r\n", t[3], t[3]>>16);
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ptr = (volatile u32 *)0x1FFF0000;
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t[0] = DWT->CYCCNT;
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for(i=0; i < 16384; i++) *ptr++;
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t[4] = DWT->CYCCNT - t[0];
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DiagPrintf("Speed rd TCM = %d, clk/byte = %d\r\n", t[4], t[4]>>16);
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DiagPrintf("read(): tFlash/tTCM = %d, tFlash/tRAM = %d\r\n", t[1]/t[4], t[1]/t[3]);
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DiagPrintf("memcpy(): tFlash/tTCM = %d, tFlash/tRAM = %d\r\n", t[2]/t[4], t[2]/t[3]);
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t[0] = DWT->CYCCNT;
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SpicUserReadRtl8195A(16384*2, 0, (u8 *)0x10060000, x);
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t[1] = DWT->CYCCNT - t[0];
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DiagPrintf("Spic 1Read to RAM = %d, clk/byte = %d\r\n", t[1], t[1]>>16);
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t[0] = DWT->CYCCNT;
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SpicUserReadFourByteRtl8195A(16384*2, 0, (u32 *)0x10060000, x);
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t[1] = DWT->CYCCNT - t[0];
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DiagPrintf("Spic 4Read to RAM = %d, clk/byte = %d\r\n", t[1], t[1]>>16);
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t[0] = DWT->CYCCNT;
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SpicUserReadRtl8195A(16384*2, 0, (u8 *)0x1FFF0000, x);
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t[1] = DWT->CYCCNT - t[0];
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DiagPrintf("Spic 1Read to TCM = %d, clk/byte = %d\r\n", t[1], t[1]>>16);
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t[0] = DWT->CYCCNT;
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SpicUserReadFourByteRtl8195A(16384*2, 0, (u32 *)0x1FFF0000, x);
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t[1] = DWT->CYCCNT - t[0];
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DiagPrintf("Spic 4Read to TCM = %d, clk/byte = %d\r\n", t[1], t[1]>>16);
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}
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DiagPrintf("Flash[0]: 0x%08X\r\n", *(volatile u32 *)SPI_FLASH_BASE );
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DiagPrintf("End");
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while(1);
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}
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