mirror of
https://github.com/drasko/open-ameba.git
synced 2024-11-28 17:20:32 +00:00
207 lines
6.8 KiB
C
207 lines
6.8 KiB
C
/*
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* StartUp SDK
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* Created on: 02/03/2017
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* Author: pvvx
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*/
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#include "rtl8195a.h"
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#include "diag.h"
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#include "hal_spi_flash.h"
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#include "hal_api.h"
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#include "hal_platform.h"
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#include "diag.h"
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#include "hal_diag.h"
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#include "rtl8195a_uart.h"
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#include "rtl8195a/rtl8195a_peri_on.h"
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#include "hal_peri_on.h"
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#include "rtl_bios_data.h"
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#include "wifi_conf.h"
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#include "rtl_consol.h"
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//-------------------------------------------------------------------------
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// Function declarations
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void InfraStart(void);
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//extern void HalWdgIntrHandle(void);
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extern void xPortPendSVHandler(void);
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extern void xPortSysTickHandler(void);
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extern void vPortSVCHandler(void);
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extern void rtl_libc_init(void);
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//extern void ShowRamBuildInfo(void); // app_start.c: VOID ShowRamBuildInfo(VOID)
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//void HalNMIHandler_Patch(void);
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void SDIO_Device_Off(void);
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//void VectorTableOverrideRtl8195A(u32 StackP);
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void SYSPlatformInit(void);
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//-------------------------------------------------------------------------
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// Data declarations
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extern u8 __bss_start__, __bss_end__;
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extern const unsigned char cus_sig[32]; // images name
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//extern HAL_TIMER_OP HalTimerOp;
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IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 =
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{ InfraStart + 1 };
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/*
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//----- HalNMIHandler_Patch
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void HalNMIHandler_Patch(void) {
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DBG_8195A_HAL("%s:NMI Error!\n", __func__);
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if ( HAL_READ32(VENDOR_REG_BASE, 0) < 0)
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HalWdgIntrHandle(); // ROM: HalWdgIntrHandle = 0x3485;
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}
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*/
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/*
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* 16 bytes FIFO ... 16*11/38400 = 0.004583 sec
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* (0.005/5)*166666666 = 166666.666
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*/
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LOCAL void INFRA_START_SECTION loguart_wait_tx_fifo_empty(void) {
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int x = 16384;
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while((!(HAL_READ8(LOG_UART_REG_BASE, 0x14) & BIT6)) && x--);
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}
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//----- SDIO_Device_Off
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void INFRA_START_SECTION SDIO_Device_Off(void) {
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HAL_PERI_ON_WRITE32(REG_PESOC_HCI_CLK_CTRL0,
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HAL_PERI_ON_READ32(REG_PESOC_HCI_CLK_CTRL0)
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& (~BIT_SOC_ACTCK_SDIO_DEV_EN));
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HAL_PERI_ON_WRITE32(REG_SOC_HCI_COM_FUNC_EN,
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HAL_PERI_ON_READ32(REG_SOC_HCI_COM_FUNC_EN)
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& (~(BIT_SOC_HCI_SDIOD_ON_EN | BIT_SOC_HCI_SDIOD_OFF_EN)));
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HAL_PERI_ON_WRITE32(REG_HCI_PINMUX_CTRL,
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HAL_PERI_ON_READ32(REG_HCI_PINMUX_CTRL)
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& (~(BIT_HCI_SDIOD_PIN_EN)));
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}
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//----- SYSPlatformInit
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void INFRA_START_SECTION SYSPlatformInit(void) {
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HAL_SYS_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0,
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(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0)
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& (~(BIT_MASK_SYS_EEROM_LDO_PAR_07_04 << BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04)))
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| BIT_SYS_EEROM_LDO_PAR_07_04(6)); // & 0xF0FFFFFF | 0x6000000
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HAL_SYS_CTRL_WRITE32(REG_SYS_XTAL_CTRL1,
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(HAL_SYS_CTRL_READ32(REG_SYS_XTAL_CTRL1)
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& (~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1)))
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| BIT_SYS_XTAL_DRV_RF1(1)); // & 0xFFFFFFE7 | 8;
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}
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// weak __low_level_init function!
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__weak void __low_level_init(void) {
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}
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// weak main function!
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__weak int main(void) {
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DiagPrintf("\r\nRTL Console ROM: Start - press key 'Up', Help '?'\r\n");
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while (pUartLogCtl->ExecuteEsc != 1);
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pUartLogCtl->RevdNo = 0;
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pUartLogCtl->BootRdy = 1;
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DiagPrintf("\r<RTL>");
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while (1) {
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while (pUartLogCtl->ExecuteCmd != 1);
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UartLogCmdExecute(pUartLogCtl);
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DiagPrintf("\r<RTL>");
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pUartLogCtl->ExecuteCmd = 0;
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}
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return 0;
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}
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//----- InfraStart
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void INFRA_START_SECTION InfraStart(void) {
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// NewVectorTable[2] = HalNMIHandler_Patch;
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DBG_8195A("===== Enter Image: %s ====\n", cus_sig);
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// ShowRamBuildInfo(); // app_start.c: VOID ShowRamBuildInfo(VOID)
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memset(&__bss_start__, 0, &__bss_end__ - &__bss_start__);
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rtl_libc_init(); // ROM Lib C init (rtl_printf!)
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// SYSPlatformInit();
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// SDIO_Device_Off();
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//- Должно быть в boot
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extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
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memset(&gBoot_Gpio_Adapter, 0, sizeof(gBoot_Gpio_Adapter));
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_pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
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VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC
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loguart_wait_tx_fifo_empty(); // иначе глючит LogUART, если переключение CLK приходится на вывод символов !
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#if 1 // if set CLK CPU
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if(HalGetCpuClk() != PLATFORM_CLOCK) {
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//----- CLK CPU
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#if CPU_CLOCK_SEL_DIV5_3
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// 6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000 Hz
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HalCpuClkConfig(CPU_CLOCK_SEL_VALUE);
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*((int *)(SYSTEM_CTRL_BASE+REG_SYS_SYSPLL_CTRL1)) |= (1<<17);// REG_SYS_SYSPLL_CTRL1 |= BIT_SYS_SYSPLL_DIV5_3
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#else
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// 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
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*((int *) (SYSTEM_CTRL_BASE + REG_SYS_SYSPLL_CTRL1)) &= ~(1 << 17); // REG_SYS_SYSPLL_CTRL1 &= ~BIT_SYS_SYSPLL_DIV5_3
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HalCpuClkConfig(CPU_CLOCK_SEL_VALUE);
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#endif // CPU_CLOCK_SEL_DIV5_3
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};
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#endif
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PSHalInitPlatformLogUart(); // HalInitPlatformLogUartV02(); // Show "<RTL8195A>"... :(
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HalReInitPlatformTimer(); // HalInitPlatformTimerV02(); HalTimerOpInit_Patch((VOID*) (&HalTimerOp));
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SystemCoreClockUpdate();
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En32KCalibration();
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//---- Spic
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// _memset(SpicInitParaAllClk, 0, sizeof(SpicInitParaAllClk));
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*(uint32 *)(&SpicInitParaAllClk[0][0].BaudRate) = 0x01310202; // patch
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*(uint32 *)(&SpicInitParaAllClk[1][0].BaudRate) = 0x11311301; // patch
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// *(uint32 *)(&SpicInitParaAllClk[2][0].BaudRate) = 0x21311301; // patch
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SPI_FLASH_PIN_FCTRL(ON);
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/*
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// uint8 SpicBaudRate = CPU_CLK_TYPE_NO - 1 - ((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7);
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uint8 SpicBaudRate = 3; // HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7;
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DBG_8195A("SpicBaudRate = %d\n", SpicBaudRate);
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SpicInitRtl8195AV02(SpicBaudRate, SpicDualBitMode);
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if(!SpicCmpDataForCalibrationRtl8195A()) {
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DBG_8195A("ReInit Spic to SIO...\n");
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SpicInitRtl8195AV02(SpicBaudRate, SpicOneBitMode);
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if(!SpicCmpDataForCalibrationRtl8195A()) {
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DBG_8195A("Error Init Spic!\n");
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};
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};
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*/
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// SpicFlashInitRtl8195A(SpicDualBitMode); // SpicReadIDRtl8195A(); SpicDualBitMode
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//---- SDRAM
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uint8 ChipId = HalGetChipId();
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if (ChipId >= CHIP_ID_8195AM) {
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#ifdef CONFIG_SDR_EN
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if((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // уже загружена?
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SdrCtrlInit();
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if(SdrControllerInit()) {
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DBG_8195A("SDR Controller Init fail!\n");
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};
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};
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#endif
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// clear SDRAM bss
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extern uint8 __sdram_bss_start__[];
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extern uint8 __sdram_bss_end__[];
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if((uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__ > 0)
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memset(__sdram_bss_start__, 0, (uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__);
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}
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else
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{
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//----- SDRAM Off
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SDR_PIN_FCTRL(OFF);
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LDO25M_CTRL(OFF);
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Off
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};
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//----- Close Flash
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SPI_FLASH_PIN_FCTRL(OFF);
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InitSoCPM();
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VectorTableInitForOSRtl8195A(&vPortSVCHandler, &xPortPendSVHandler,
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&xPortSysTickHandler);
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#if CONFIG_DEBUG_LOG > 4
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DBG_8195A("\rSet CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
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#endif
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// force SP align to 8 byte not 4 byte (initial SP is 4 byte align)
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__asm(
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"mov r0, sp\n"
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"bic r0, r0, #7\n"
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"mov sp, r0\n"
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);
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__low_level_init();
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main();
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}
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