mirror of
https://github.com/drasko/open-ameba.git
synced 2026-07-11 22:05:41 +00:00
Change SDK dir name. Use OpenOCD only.
Signed-off-by: Drasko DRASKOVIC <drasko.draskovic@gmail.com>
This commit is contained in:
Drasko DRASKOVIC
parent
05b731b5f3
commit
eeb7f808ae
1446 changed files with 1 additions and 65 deletions
|
|
@ -0,0 +1,239 @@
|
|||
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
INCLUDE "export-rom_v03.txt"
|
||||
|
||||
|
||||
MEMORY
|
||||
{
|
||||
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 65536
|
||||
ROM_USED_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 21560 /* end 0x10006000 */
|
||||
RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 16128 /* end 0x10006000 */
|
||||
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 434176
|
||||
//RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 7936 /* end 0x10004000 */
|
||||
//BD_RAM (rwx) : ORIGIN = 0x10004000, LENGTH = 442368
|
||||
SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
|
||||
}
|
||||
|
||||
EXTERN(PreProcessForVendor)
|
||||
EXTERN(RtlBootToSram)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__rom_bss_start__ = 0x10000300;
|
||||
__rom_bss_end__ = 0x10000bc8;
|
||||
|
||||
.ram.start.table :
|
||||
{
|
||||
__ram_image1_text_start__ = .;
|
||||
__ram_start_table_start__ = .;
|
||||
KEEP(*(SORT(.start.ram.data*)))
|
||||
KEEP(*(.image1.validate.rodata*))
|
||||
__ram_start_table_end__ = .;
|
||||
|
||||
} > ROM_USED_RAM
|
||||
|
||||
/* Add . to assign the start address of the section,
|
||||
* to prevent the change of the start address by ld doing section alignment */
|
||||
|
||||
|
||||
/* these 4 sections is used by ROM global variable */
|
||||
/* Don't move them and never add RAM code variable to these sections */
|
||||
.ram_image1.text :
|
||||
{
|
||||
__image1_validate_code__ = .;
|
||||
*(.infra.ram.data*)
|
||||
*(.infra.ram.text*)
|
||||
*(.hal.ram.text*)
|
||||
*(.hal.flash.text)
|
||||
*(.hal.sdrc.text)
|
||||
*(.text*)
|
||||
*(.sdram.text*)
|
||||
*(.rodata*)
|
||||
*(.infra.ram.start*)
|
||||
*(.data*)
|
||||
*(.hal.ram.data*)
|
||||
*(.hal.gpio.data*)
|
||||
*(.hal.flash.data*)
|
||||
*(.hal.sdrc.data*)
|
||||
__ram_image1_data_end__ = .;
|
||||
__image1_bss_start__ = .;
|
||||
.ram.bss$$Base = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__image1_bss_end__ = .;
|
||||
__ram_image1_text_end__ = .;
|
||||
} > ROM_USED_RAM
|
||||
|
||||
.tcm :
|
||||
{
|
||||
__tcm_start__ = .;
|
||||
*(.tcm.heap)
|
||||
__tcm_end__ = .;
|
||||
} > TCM
|
||||
/*
|
||||
OVERLAY 0x1FFF0000:
|
||||
{
|
||||
.valid
|
||||
{
|
||||
*mem.o (.bss*)
|
||||
*memp.o (.bss*)
|
||||
*(.tcm.heap)
|
||||
}
|
||||
.dummy
|
||||
{
|
||||
__ram_image1_text_start__ = .;
|
||||
__ram_start_table_start__ = .;
|
||||
KEEP(*(SORT(.start.ram.data*)))
|
||||
__ram_start_table_end__ = .;
|
||||
__image1_validate_code__ = .;
|
||||
KEEP(*(.image1.validate.rodata*))
|
||||
KEEP(*(.infra.ram.data*))
|
||||
KEEP(*(.timer.ram.data*))
|
||||
KEEP(*(.cutb.ram.data*))
|
||||
KEEP(*(.cutc.ram.data*))
|
||||
KEEP(*(.hal.ram.data*))
|
||||
__image1_bss_start__ = .;
|
||||
.ram_image1.bss$$Base = .;
|
||||
__image1_bss_end__ = .;
|
||||
.ram_image1.bss$$Limit = .;
|
||||
__ram_image1_data_end__ = .;
|
||||
|
||||
*(.hal.ram.text*)
|
||||
*(.infra.ram.text*)
|
||||
}
|
||||
} > TCM
|
||||
*/
|
||||
.image2.start.table :
|
||||
{
|
||||
__ram_image2_text_start__ = .;
|
||||
__image2_entry_func__ = .;
|
||||
.image2.start.table1$$Base = .;
|
||||
*(SORT(.image2.ram.data*))
|
||||
__image2_validate_code__ = .;
|
||||
*(.image2.validate.rodata*)
|
||||
*(.custom.validate.rodata*)
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.text :
|
||||
{
|
||||
*(.infra.ram.start*)
|
||||
*(.mon.ram.text*)
|
||||
*(.hal.flash.text*)
|
||||
*(.hal.sdrc.text*)
|
||||
*(.hal.gpio.text*)
|
||||
*(.fwu.text*)
|
||||
*(.text*)
|
||||
*(.sdram.text*)
|
||||
*(.p2p.text*)
|
||||
*(.wps.text*)
|
||||
*(.websocket.text*)
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.rodata :
|
||||
{
|
||||
*(.rodata*)
|
||||
*(.fwu.rodata*)
|
||||
*(.sdram.rodata*)
|
||||
*(.p2p.rodata*)
|
||||
*(.wps.rodata*)
|
||||
*(.websocket.rodata*)
|
||||
} > BD_RAM
|
||||
|
||||
.ram.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(.data*)
|
||||
*(.sdram.data*)
|
||||
*(.p2p.data*)
|
||||
*(.wps.data*)
|
||||
*(.websocket.data*)
|
||||
__data_end__ = .;
|
||||
__ram_image2_text_end__ = .;
|
||||
} > BD_RAM
|
||||
|
||||
.ram.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
.ram.bss$$Base = .;
|
||||
*(.hal.flash.data*)
|
||||
*(.hal.sdrc.data*)
|
||||
*(.hal.gpio.data*)
|
||||
*(.fwu.data*)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
*(.bdsram.data*)
|
||||
*(.sdram.bss*)
|
||||
*(.p2p.bss*)
|
||||
*(.wps.bss*)
|
||||
*(.websocket.bss*)
|
||||
__bss_end__ = .;
|
||||
.ram.bss$$Limit = .;
|
||||
} > BD_RAM
|
||||
|
||||
.bf_data :
|
||||
{
|
||||
__buffer_data_start__ = .;
|
||||
*(.bfsram.data*)
|
||||
__buffer_data_end__ = .;
|
||||
|
||||
} > BD_RAM
|
||||
/*
|
||||
.bf_data2 :
|
||||
{
|
||||
__buffer_data_start2__ = .;
|
||||
__buffer_data_end2__ = .;
|
||||
|
||||
} > RECY_RAM
|
||||
*/
|
||||
.sdr_text :
|
||||
{
|
||||
__sdram_data_start__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_rodata :
|
||||
{
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_data :
|
||||
{
|
||||
__sdram_data_end__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_bss :
|
||||
{
|
||||
__sdram_bss_start__ = .;
|
||||
__sdram_bss_end__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.heap :
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > BD_RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy :
|
||||
{
|
||||
*(.stack)
|
||||
} > BD_RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(BD_RAM) + LENGTH(BD_RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
|
||||
.boot.head :
|
||||
{
|
||||
KEEP(*(.loader.head*))
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,738 @@
|
|||
SECTIONS
|
||||
{
|
||||
__vectors_table = 0x0;
|
||||
Reset_Handler = 0x101;
|
||||
NMI_Handler = 0x109;
|
||||
HardFault_Handler = 0x10d;
|
||||
MemManage_Handler = 0x121;
|
||||
BusFault_Handler = 0x125;
|
||||
UsageFault_Handler = 0x129;
|
||||
HalLogUartInit = 0x201;
|
||||
HalSerialPutcRtl8195a = 0x2d9;
|
||||
HalSerialGetcRtl8195a = 0x309;
|
||||
HalSerialGetIsrEnRegRtl8195a = 0x329;
|
||||
HalSerialSetIrqEnRegRtl8195a = 0x335;
|
||||
HalCpuClkConfig = 0x341;
|
||||
HalGetCpuClk = 0x355;
|
||||
HalRomInfo = 0x39d;
|
||||
HalGetRomInfo = 0x3b5;
|
||||
HalResetVsr = 0x3c5;
|
||||
HalDelayUs = 0x899;
|
||||
HalNMIHandler = 0x8e1;
|
||||
HalHardFaultHandler = 0x911;
|
||||
HalMemManageHandler = 0xc09;
|
||||
HalBusFaultHandler = 0xc39;
|
||||
HalUsageFaultHandler = 0xc69;
|
||||
HalUart0PinCtrlRtl8195A = 0xcfd;
|
||||
HalUart1PinCtrlRtl8195A = 0xdc9;
|
||||
HalUart2PinCtrlRtl8195A = 0xe9d;
|
||||
HalSPI0PinCtrlRtl8195A = 0xf75;
|
||||
HalSPI1PinCtrlRtl8195A = 0x1015;
|
||||
HalSPI2PinCtrlRtl8195A = 0x10e5;
|
||||
HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
|
||||
HalI2C0PinCtrlRtl8195A = 0x1275;
|
||||
HalI2C1PinCtrlRtl8195A = 0x1381;
|
||||
HalI2C2PinCtrlRtl8195A = 0x1459;
|
||||
HalI2C3PinCtrlRtl8195A = 0x1529;
|
||||
HalI2S0PinCtrlRtl8195A = 0x1639;
|
||||
HalI2S1PinCtrlRtl8195A = 0x176d;
|
||||
HalPCM0PinCtrlRtl8195A = 0x1845;
|
||||
HalPCM1PinCtrlRtl8195A = 0x1949;
|
||||
HalSDIODPinCtrlRtl8195A = 0x1a1d;
|
||||
HalSDIOHPinCtrlRtl8195A = 0x1a6d;
|
||||
HalMIIPinCtrlRtl8195A = 0x1ab9;
|
||||
HalWLLEDPinCtrlRtl8195A = 0x1b51;
|
||||
HalWLANT0PinCtrlRtl8195A = 0x1c0d;
|
||||
HalWLANT1PinCtrlRtl8195A = 0x1c61;
|
||||
HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
|
||||
HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
|
||||
HalNFCPinCtrlRtl8195A = 0x1d59;
|
||||
HalPWM0PinCtrlRtl8195A = 0x1da9;
|
||||
HalPWM1PinCtrlRtl8195A = 0x1ead;
|
||||
HalPWM2PinCtrlRtl8195A = 0x1fb5;
|
||||
HalPWM3PinCtrlRtl8195A = 0x20b1;
|
||||
HalETE0PinCtrlRtl8195A = 0x21b9;
|
||||
HalETE1PinCtrlRtl8195A = 0x22c1;
|
||||
HalETE2PinCtrlRtl8195A = 0x23c9;
|
||||
HalETE3PinCtrlRtl8195A = 0x24d1;
|
||||
HalEGTIMPinCtrlRtl8195A = 0x25d9;
|
||||
HalSPIFlashPinCtrlRtl8195A = 0x2679;
|
||||
HalSDRPinCtrlRtl8195A = 0x2725;
|
||||
HalJTAGPinCtrlRtl8195A = 0x280d;
|
||||
HalTRACEPinCtrlRtl8195A = 0x2861;
|
||||
HalLOGUartPinCtrlRtl8195A = 0x28b9;
|
||||
HalLOGUartIRPinCtrlRtl8195A = 0x291d;
|
||||
HalSICPinCtrlRtl8195A = 0x2981;
|
||||
HalEEPROMPinCtrlRtl8195A = 0x29d9;
|
||||
HalDEBUGPinCtrlRtl8195A = 0x2a31;
|
||||
HalPinCtrlRtl8195A = 0x2b39;
|
||||
SpicRxCmdRtl8195A = 0x2e5d;
|
||||
SpicWaitBusyDoneRtl8195A = 0x2ea5;
|
||||
SpicGetFlashStatusRtl8195A = 0x2eb5;
|
||||
SpicWaitWipDoneRtl8195A = 0x2f55;
|
||||
SpicTxCmdRtl8195A = 0x2f6d;
|
||||
SpicSetFlashStatusRtl8195A = 0x2fc1;
|
||||
SpicCmpDataForCalibrationRtl8195A = 0x3049;
|
||||
SpicLoadInitParaFromClockRtl8195A = 0x3081;
|
||||
SpicInitRtl8195A = 0x30e5;
|
||||
SpicEraseFlashRtl8195A = 0x31bd;
|
||||
SpiFlashApp = 0x3279;
|
||||
HalPeripheralIntrHandle = 0x33b5;
|
||||
HalSysOnIntrHandle = 0x3439;
|
||||
HalWdgIntrHandle = 0x3485;
|
||||
HalTimer0IntrHandle = 0x34d5;
|
||||
HalTimer1IntrHandle = 0x3525;
|
||||
HalI2C3IntrHandle = 0x3575;
|
||||
HalTimer2To7IntrHandle = 0x35c5;
|
||||
HalSpi0IntrHandle = 0x3615;
|
||||
HalGpioIntrHandle = 0x3665;
|
||||
HalUart0IntrHandle = 0x36b5;
|
||||
HalSpiFlashIntrHandle = 0x3705;
|
||||
HalUsbOtgIntrHandle = 0x3755;
|
||||
HalSdioHostIntrHandle = 0x37a5;
|
||||
HalI2s0OrPcm0IntrHandle = 0x37f5;
|
||||
HalI2s1OrPcm1IntrHandle = 0x3845;
|
||||
HalWlDmaIntrHandle = 0x3895;
|
||||
HalWlProtocolIntrHandle = 0x38e5;
|
||||
HalCryptoIntrHandle = 0x3935;
|
||||
HalGmacIntrHandle = 0x3985;
|
||||
HalGdma0Ch0IntrHandle = 0x39d5;
|
||||
HalGdma0Ch1IntrHandle = 0x3a25;
|
||||
HalGdma0Ch2IntrHandle = 0x3a75;
|
||||
HalGdma0Ch3IntrHandle = 0x3ac5;
|
||||
HalGdma0Ch4IntrHandle = 0x3b15;
|
||||
HalGdma0Ch5IntrHandle = 0x3b65;
|
||||
HalGdma1Ch0IntrHandle = 0x3bb5;
|
||||
HalGdma1Ch1IntrHandle = 0x3c05;
|
||||
HalGdma1Ch2IntrHandle = 0x3c55;
|
||||
HalGdma1Ch3IntrHandle = 0x3ca5;
|
||||
HalGdma1Ch4IntrHandle = 0x3cf5;
|
||||
HalGdma1Ch5IntrHandle = 0x3d45;
|
||||
HalSdioDeviceIntrHandle = 0x3d95;
|
||||
VectorTableInitRtl8195A = 0x3de5;
|
||||
VectorTableInitForOSRtl8195A = 0x4019;
|
||||
VectorIrqRegisterRtl8195A = 0x4029;
|
||||
VectorIrqUnRegisterRtl8195A = 0x4091;
|
||||
VectorIrqEnRtl8195A = 0x40f1;
|
||||
VectorIrqDisRtl8195A = 0x418d;
|
||||
_UartRxDmaIrqHandle = 0x422d;
|
||||
HalRuartPutCRtl8195a = 0x4281;
|
||||
HalRuartGetCRtl8195a = 0x429d;
|
||||
HalRuartRTSCtrlRtl8195a = 0x42bd;
|
||||
HalRuartGetDebugValueRtl8195a = 0x42e1;
|
||||
HalRuartGetIMRRtl8195a = 0x43e1;
|
||||
HalRuartSetIMRRtl8195a = 0x442d;
|
||||
_UartIrqHandle = 0x4465;
|
||||
HalRuartDmaInitRtl8195a = 0x4681;
|
||||
HalRuartIntDisableRtl8195a = 0x4845;
|
||||
HalRuartDeInitRtl8195a = 0x4855;
|
||||
HalRuartIntEnableRtl8195a = 0x4985;
|
||||
_UartTxDmaIrqHandle = 0x4995;
|
||||
HalRuartRegIrqRtl8195a = 0x49d1;
|
||||
HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
|
||||
HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
|
||||
HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
|
||||
RuartLock = 0x4cc9;
|
||||
RuartUnLock = 0x4ced;
|
||||
HalRuartIntSendRtl8195a = 0x4d09;
|
||||
HalRuartDmaSendRtl8195a = 0x4e35;
|
||||
HalRuartStopSendRtl8195a = 0x4f89;
|
||||
HalRuartIntRecvRtl8195a = 0x504d;
|
||||
HalRuartDmaRecvRtl8195a = 0x51ad;
|
||||
HalRuartStopRecvRtl8195a = 0x52cd;
|
||||
RuartIsTimeout = 0x5385;
|
||||
HalRuartSendRtl8195a = 0x53b1;
|
||||
HalRuartRecvRtl8195a = 0x5599;
|
||||
RuartResetRxFifoRtl8195a = 0x5751;
|
||||
HalRuartResetRxFifoRtl8195a = 0x5775;
|
||||
HalRuartInitRtl8195a = 0x5829;
|
||||
HalGdmaOnOffRtl8195a = 0x5df1;
|
||||
HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
|
||||
HalGdmaChEnRtl8195a = 0x5e51;
|
||||
HalGdmaChDisRtl8195a = 0x5e6d;
|
||||
HalGdamChInitRtl8195a = 0x5e91;
|
||||
HalGdmaChSetingRtl8195a = 0x5ebd;
|
||||
HalGdmaChBlockSetingRtl8195a = 0x000060dd;
|
||||
HalGdmaChIsrCleanRtl8195a = 0x6419;
|
||||
HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
|
||||
HalGdmaChCleanAutoDstRtl8195a = 0x6501;
|
||||
HalEFUSEPowerSwitch8195AROM = 0x6561;
|
||||
HALEFUSEOneByteReadROM = 0x65f9;
|
||||
HALEFUSEOneByteWriteROM = 0x6699;
|
||||
__rtl_memcmpb_v1_00 = 0x681d;
|
||||
__rtl_random_v1_00 = 0x6861;
|
||||
__rtl_align_to_be32_v1_00 = 0x6881;
|
||||
__rtl_memsetw_v1_00 = 0x6899;
|
||||
__rtl_memsetb_v1_00 = 0x68ad;
|
||||
__rtl_memcpyw_v1_00 = 0x68bd;
|
||||
__rtl_memcpyb_v1_00 = 0x68dd;
|
||||
__rtl_memDump_v1_00 = 0x68f5;
|
||||
__rtl_AES_set_encrypt_key = 0x6901;
|
||||
__rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
|
||||
__rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
|
||||
__rtl_cryptoEngine_init_v1_00 = 0x6ea9;
|
||||
__rtl_cryptoEngine_exit_v1_00 = 0x7055;
|
||||
__rtl_cryptoEngine_reset_v1_00 = 0x70b1;
|
||||
__rtl_cryptoEngine_v1_00 = 0x70ed;
|
||||
__rtl_crypto_cipher_init_v1_00 = 0x7c69;
|
||||
__rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
|
||||
__rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
|
||||
HalSsiPinmuxEnableRtl8195a = 0x7cd5;
|
||||
HalSsiEnableRtl8195a = 0x7e45;
|
||||
HalSsiDisableRtl8195a = 0x7ef9;
|
||||
HalSsiLoadSettingRtl8195a = 0x7fad;
|
||||
HalSsiSetInterruptMaskRtl8195a = 0x8521;
|
||||
HalSsiGetInterruptMaskRtl8195a = 0x85c9;
|
||||
HalSsiSetSclkPolarityRtl8195a = 0x863d;
|
||||
HalSsiSetSclkPhaseRtl8195a = 0x8715;
|
||||
HalSsiWriteRtl8195a = 0x87e9;
|
||||
HalSsiSetDeviceRoleRtl8195a = 0x8861;
|
||||
HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
|
||||
HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
|
||||
HalSsiReadRtl8195a = 0x89b9;
|
||||
HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
|
||||
HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
|
||||
HalSsiGetStatusRtl8195a = 0x8b1d;
|
||||
HalSsiWriteableRtl8195a = 0x8b91;
|
||||
HalSsiReadableRtl8195a = 0x8c09;
|
||||
HalSsiBusyRtl8195a = 0x8c81;
|
||||
HalSsiReadInterruptRtl8195a = 0x8cf9;
|
||||
HalSsiWriteInterruptRtl8195a = 0x8efd;
|
||||
HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
|
||||
HalSsiGetInterruptStatusRtl8195a = 0x90d9;
|
||||
HalSsiInterruptEnableRtl8195a = 0x914d;
|
||||
HalSsiInterruptDisableRtl8195a = 0x9299;
|
||||
HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
|
||||
HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
|
||||
HalSsiInitRtl8195a = 0x94d1;
|
||||
_SsiReadInterrupt = 0x9ba5;
|
||||
_SsiWriteInterrupt = 0x9db1;
|
||||
_SsiIrqHandle = 0x9eb1;
|
||||
HalI2CWrite32 = 0xa061;
|
||||
HalI2CRead32 = 0xa09d;
|
||||
HalI2CDeInit8195a = 0xa0dd;
|
||||
HalI2CSendRtl8195a = 0xa1f1;
|
||||
HalI2CReceiveRtl8195a = 0xa25d;
|
||||
HalI2CEnableRtl8195a = 0xa271;
|
||||
HalI2CIntrCtrl8195a = 0xa389;
|
||||
HalI2CReadRegRtl8195a = 0xa3a1;
|
||||
HalI2CWriteRegRtl8195a = 0xa3b1;
|
||||
HalI2CSetCLKRtl8195a = 0xa3c5;
|
||||
HalI2CMassSendRtl8195a = 0xa6e9;
|
||||
HalI2CClrIntrRtl8195a = 0xa749;
|
||||
HalI2CClrAllIntrRtl8195a = 0xa761;
|
||||
HalI2CInit8195a = 0xa775;
|
||||
HalI2CDMACtrl8195a = 0xaa31;
|
||||
RtkI2CIoCtrl = 0xaa61;
|
||||
RtkI2CPowerCtrl = 0xaa65;
|
||||
HalI2COpInit = 0xaa69;
|
||||
I2CIsTimeout = 0xac65;
|
||||
I2CTXGDMAISRHandle = 0xb435;
|
||||
I2CRXGDMAISRHandle = 0xb4c1;
|
||||
RtkI2CIrqInit = 0xb54d;
|
||||
RtkI2CIrqDeInit = 0xb611;
|
||||
RtkI2CPinMuxInit = 0xb675;
|
||||
RtkI2CPinMuxDeInit = 0xb7c9;
|
||||
RtkI2CDMAInit = 0xb955;
|
||||
RtkI2CInit = 0xbc95;
|
||||
RtkI2CDMADeInit = 0xbdad;
|
||||
RtkI2CDeInit = 0xbe4d;
|
||||
RtkI2CSendUserAddr = 0xbee5;
|
||||
RtkI2CSend = 0xc07d;
|
||||
RtkI2CLoadDefault = 0xce51;
|
||||
RtkSalI2COpInit = 0xcf21;
|
||||
HalI2SWrite32 = 0xcf65;
|
||||
HalI2SRead32 = 0xcf85;
|
||||
HalI2SDeInitRtl8195a = 0xcfa9;
|
||||
HalI2STxRtl8195a = 0xcfc9;
|
||||
HalI2SRxRtl8195a = 0xd011;
|
||||
HalI2SEnableRtl8195a = 0xd05d;
|
||||
HalI2SIntrCtrlRtl8195a = 0xd0b1;
|
||||
HalI2SReadRegRtl8195a = 0xd0d1;
|
||||
HalI2SClrIntrRtl8195a = 0xd0dd;
|
||||
HalI2SClrAllIntrRtl8195a = 0xd0fd;
|
||||
HalI2SInitRtl8195a = 0xd11d;
|
||||
GPIO_GetIPPinName_8195a = 0xd2e5;
|
||||
GPIO_GetChipPinName_8195a = 0xd331;
|
||||
GPIO_PullCtrl_8195a = 0xd39d;
|
||||
GPIO_FuncOn_8195a = 0xd421;
|
||||
GPIO_FuncOff_8195a = 0xd481;
|
||||
GPIO_Int_Mask_8195a = 0xd4e9;
|
||||
GPIO_Int_SetType_8195a = 0xd511;
|
||||
HAL_GPIO_IrqHandler_8195a = 0xd5fd;
|
||||
HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
|
||||
HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
|
||||
HAL_GPIO_IntCtrl_8195a = 0xd6cd;
|
||||
HAL_GPIO_Init_8195a = 0xd805;
|
||||
HAL_GPIO_DeInit_8195a = 0xdac1;
|
||||
HAL_GPIO_ReadPin_8195a = 0xdbd1;
|
||||
HAL_GPIO_WritePin_8195a = 0xdc91;
|
||||
HAL_GPIO_RegIrq_8195a = 0xddad;
|
||||
HAL_GPIO_UnRegIrq_8195a = 0xddf5;
|
||||
HAL_GPIO_UserRegIrq_8195a = 0xde15;
|
||||
HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
|
||||
HAL_GPIO_MaskIrq_8195a = 0xdfc1;
|
||||
HAL_GPIO_UnMaskIrq_8195a = 0xe061;
|
||||
HAL_GPIO_IntDebounce_8195a = 0xe101;
|
||||
HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
|
||||
HAL_GPIO_PullCtrl_8195a = 0xe1c9;
|
||||
DumpForOneBytes = 0xe259;
|
||||
CmdRomHelp = 0xe419;
|
||||
CmdWriteWord = 0xe491;
|
||||
CmdDumpHelfWord = 0xe505;
|
||||
CmdDumpWord = 0xe5f1;
|
||||
CmdDumpByte = 0xe6f5;
|
||||
CmdSpiFlashTool = 0xe751;
|
||||
GetRomCmdNum = 0xe7a9;
|
||||
CmdWriteByte = 0xe7ad;
|
||||
Isspace = 0xe7ed;
|
||||
Strtoul = 0xe801;
|
||||
ArrayInitialize = 0xe8b1;
|
||||
GetArgc = 0xe8c9;
|
||||
GetArgv = 0xe8f9;
|
||||
UartLogCmdExecute = 0xe95d;
|
||||
UartLogShowBackSpace = 0xe9fd;
|
||||
UartLogRecallOldCmd = 0xea39;
|
||||
UartLogHistoryCmd = 0xea71;
|
||||
UartLogCmdChk = 0xeadd;
|
||||
UartLogIrqHandle = 0xebf5;
|
||||
RtlConsolInit = 0xecc5;
|
||||
RtlConsolTaskRom = 0xed49;
|
||||
RtlExitConsol = 0xed79;
|
||||
RtlConsolRom = 0xedcd;
|
||||
HalTimerOpInit = 0xee0d;
|
||||
HalTimerIrq2To7Handle = 0xee59;
|
||||
HalGetTimerIdRtl8195a = 0xef09;
|
||||
HalTimerInitRtl8195a = 0xef3d;
|
||||
HalTimerDisRtl8195a = 0xf069;
|
||||
HalTimerEnRtl8195a = 0xf089;
|
||||
HalTimerReadCountRtl8195a = 0xf0a9;
|
||||
HalTimerIrqClearRtl8195a = 0xf0bd;
|
||||
HalTimerDumpRegRtl8195a = 0xf0d1;
|
||||
VSprintf = 0xf129;
|
||||
DiagPrintf = 0xf39d;
|
||||
DiagSPrintf = 0xf3b9;
|
||||
DiagSnPrintf = 0xf3d1;
|
||||
prvDiagPrintf = 0xf3ed;
|
||||
prvDiagSPrintf = 0xf40d;
|
||||
_memcmp = 0xf429;
|
||||
_memcpy = 0xf465;
|
||||
_memset = 0xf511;
|
||||
Rand = 0xf585;
|
||||
_strncpy = 0xf60d;
|
||||
_strcpy = 0xf629;
|
||||
prvStrCpy = 0xf639;
|
||||
_strlen = 0xf651;
|
||||
_strnlen = 0xf669;
|
||||
prvStrLen = 0xf699;
|
||||
_strcmp = 0xf6b1;
|
||||
_strncmp = 0xf6d1;
|
||||
prvStrCmp = 0xf719;
|
||||
StrUpr = 0xf749;
|
||||
prvAtoi = 0xf769;
|
||||
prvStrStr = 0xf7bd;
|
||||
_strsep = 0xf7d5;
|
||||
skip_spaces = 0xf815;
|
||||
skip_atoi = 0xf831;
|
||||
_parse_integer_fixup_radix = 0xf869;
|
||||
_parse_integer = 0xf8bd;
|
||||
simple_strtoull = 0xf915;
|
||||
simple_strtoll = 0xf945;
|
||||
simple_strtoul = 0xf965;
|
||||
simple_strtol = 0xf96d;
|
||||
_vsscanf = 0xf985;
|
||||
_sscanf = 0xff71;
|
||||
div_u64 = 0xff91;
|
||||
div_s64 = 0xff99;
|
||||
div_u64_rem = 0xffa1;
|
||||
div_s64_rem = 0xffb1;
|
||||
_strpbrk = 0xffc1;
|
||||
_strchr = 0xffed;
|
||||
aes_set_key = 0x10005;
|
||||
aes_encrypt = 0x103d1;
|
||||
aes_decrypt = 0x114a5;
|
||||
AES_WRAP = 0x125c9;
|
||||
AES_UnWRAP = 0x12701;
|
||||
crc32_get = 0x12861;
|
||||
arc4_byte = 0x12895;
|
||||
rt_arc4_init = 0x128bd;
|
||||
rt_arc4_crypt = 0x12901;
|
||||
rt_md5_init = 0x131c1;
|
||||
rt_md5_append = 0x131f5;
|
||||
rt_md5_final = 0x1327d;
|
||||
rt_md5_hmac = 0x132d5;
|
||||
rtw_get_bit_value_from_ieee_value = 0x13449;
|
||||
rtw_is_cckrates_included = 0x13475;
|
||||
rtw_is_cckratesonly_included = 0x134b5;
|
||||
rtw_check_network_type = 0x134dd;
|
||||
rtw_set_fixed_ie = 0x1350d;
|
||||
rtw_set_ie = 0x1352d;
|
||||
rtw_get_ie = 0x1355d;
|
||||
rtw_set_supported_rate = 0x13591;
|
||||
rtw_get_rateset_len = 0x13611;
|
||||
rtw_get_wpa_ie = 0x1362d;
|
||||
rtw_get_wpa2_ie = 0x136c9;
|
||||
rtw_get_wpa_cipher_suite = 0x13701;
|
||||
rtw_get_wpa2_cipher_suite = 0x13769;
|
||||
rtw_parse_wpa_ie = 0x137d1;
|
||||
rtw_parse_wpa2_ie = 0x138ad;
|
||||
rtw_get_sec_ie = 0x13965;
|
||||
rtw_get_wps_ie = 0x13a15;
|
||||
rtw_get_wps_attr = 0x13a99;
|
||||
rtw_get_wps_attr_content = 0x13b49;
|
||||
rtw_ieee802_11_parse_elems = 0x13b91;
|
||||
str_2char2num = 0x13d9d;
|
||||
key_2char2num = 0x13db9;
|
||||
convert_ip_addr = 0x13dd1;
|
||||
rom_psk_PasswordHash = 0x13e9d;
|
||||
rom_psk_CalcGTK = 0x13ed5;
|
||||
rom_psk_CalcPTK = 0x13f69;
|
||||
wep_80211_encrypt = 0x14295;
|
||||
wep_80211_decrypt = 0x142f5;
|
||||
tkip_micappendbyte = 0x14389;
|
||||
rtw_secmicsetkey = 0x143d9;
|
||||
rtw_secmicappend = 0x14419;
|
||||
rtw_secgetmic = 0x14435;
|
||||
rtw_seccalctkipmic = 0x1449d;
|
||||
tkip_phase1 = 0x145a5;
|
||||
tkip_phase2 = 0x14725;
|
||||
tkip_80211_encrypt = 0x14941;
|
||||
tkip_80211_decrypt = 0x149d5;
|
||||
aes1_encrypt = 0x14a8d;
|
||||
aesccmp_construct_mic_iv = 0x14c65;
|
||||
aesccmp_construct_mic_header1 = 0x14ccd;
|
||||
aesccmp_construct_mic_header2 = 0x14d21;
|
||||
aesccmp_construct_ctr_preload = 0x14db5;
|
||||
aes_80211_encrypt = 0x14e29;
|
||||
aes_80211_decrypt = 0x151ad;
|
||||
_sha1_process_message_block = 0x155b9;
|
||||
_sha1_pad_message = 0x15749;
|
||||
rt_sha1_init = 0x157e5;
|
||||
rt_sha1_update = 0x15831;
|
||||
rt_sha1_finish = 0x158a9;
|
||||
rt_hmac_sha1 = 0x15909;
|
||||
rom_aes_128_cbc_encrypt = 0x15a65;
|
||||
rom_aes_128_cbc_decrypt = 0x15ae1;
|
||||
rom_rijndaelKeySetupEnc = 0x15b5d;
|
||||
rom_aes_decrypt_init = 0x15c39;
|
||||
rom_aes_internal_decrypt = 0x15d15;
|
||||
rom_aes_decrypt_deinit = 0x16071;
|
||||
rom_aes_encrypt_init = 0x16085;
|
||||
rom_aes_internal_encrypt = 0x1609d;
|
||||
rom_aes_encrypt_deinit = 0x16451;
|
||||
bignum_init = 0x17b35;
|
||||
bignum_deinit = 0x17b61;
|
||||
bignum_get_unsigned_bin_len = 0x17b81;
|
||||
bignum_get_unsigned_bin = 0x17b85;
|
||||
bignum_set_unsigned_bin = 0x17c21;
|
||||
bignum_cmp = 0x17cd1;
|
||||
bignum_cmp_d = 0x17cd5;
|
||||
bignum_add = 0x17cfd;
|
||||
bignum_sub = 0x17d0d;
|
||||
bignum_mul = 0x17d1d;
|
||||
bignum_exptmod = 0x17d2d;
|
||||
WPS_realloc = 0x17d51;
|
||||
os_zalloc = 0x17d99;
|
||||
rom_hmac_sha256_vector = 0x17dc1;
|
||||
rom_hmac_sha256 = 0x17ebd;
|
||||
rom_sha256_vector = 0x18009;
|
||||
phy_CalculateBitShift = 0x18221;
|
||||
PHY_SetBBReg_8195A = 0x18239;
|
||||
PHY_QueryBBReg_8195A = 0x18279;
|
||||
ROM_odm_QueryRxPwrPercentage = 0x1829d;
|
||||
ROM_odm_EVMdbToPercentage = 0x182bd;
|
||||
ROM_odm_SignalScaleMapping_8195A = 0x182e5;
|
||||
ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
|
||||
ROM_odm_SetEDCCAThreshold = 0x18721;
|
||||
ROM_odm_SetTRxMux = 0x18749;
|
||||
ROM_odm_SetCrystalCap = 0x18771;
|
||||
ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
|
||||
ROM_ODM_CfoTrackingReset = 0x187e9;
|
||||
ROM_odm_CfoTrackingFlow = 0x18811;
|
||||
curve25519_donna = 0x1965d;
|
||||
aes_test_alignment_detection = 0x1a391;
|
||||
aes_mode_reset = 0x1a3ed;
|
||||
aes_ecb_encrypt = 0x1a3f9;
|
||||
aes_ecb_decrypt = 0x1a431;
|
||||
aes_cbc_encrypt = 0x1a469;
|
||||
aes_cbc_decrypt = 0x1a579;
|
||||
aes_cfb_encrypt = 0x1a701;
|
||||
aes_cfb_decrypt = 0x1a9e5;
|
||||
aes_ofb_crypt = 0x1acc9;
|
||||
aes_ctr_crypt = 0x1af7d;
|
||||
aes_encrypt_key128 = 0x1b289;
|
||||
aes_encrypt_key192 = 0x1b2a5;
|
||||
aes_encrypt_key256 = 0x1b2c1;
|
||||
aes_encrypt_key = 0x1b2e1;
|
||||
aes_decrypt_key128 = 0x1b351;
|
||||
aes_decrypt_key192 = 0x1b36d;
|
||||
aes_decrypt_key256 = 0x1b389;
|
||||
aes_decrypt_key = 0x1b3a9;
|
||||
aes_init = 0x1b419;
|
||||
CRYPTO_chacha_20 = 0x1b41d;
|
||||
CRYPTO_poly1305_init = 0x1bc25;
|
||||
CRYPTO_poly1305_update = 0x1bd09;
|
||||
CRYPTO_poly1305_finish = 0x1bd8d;
|
||||
rom_sha512_starts = 0x1ceb5;
|
||||
rom_sha512_update = 0x1d009;
|
||||
rom_sha512_finish = 0x1d011;
|
||||
rom_sha512 = 0x1d261;
|
||||
rom_sha512_hmac_starts = 0x1d299;
|
||||
rom_sha512_hmac_update = 0x1d35d;
|
||||
rom_sha512_hmac_finish = 0x1d365;
|
||||
rom_sha512_hmac_reset = 0x1d3b5;
|
||||
rom_sha512_hmac = 0x1d3d1;
|
||||
rom_sha512_hkdf = 0x1d40d;
|
||||
rom_ed25519_gen_keypair = 0x1d501;
|
||||
rom_ed25519_gen_signature = 0x1d505;
|
||||
rom_ed25519_verify_signature = 0x1d51d;
|
||||
rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
|
||||
rom_ed25519_crypto_sign_detached = 0x1d579;
|
||||
rom_ed25519_crypto_sign_verify_detached = 0x1d655;
|
||||
rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
|
||||
rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
|
||||
rom_ed25519_ge_p3_tobytes = 0x207d5;
|
||||
rom_ed25519_ge_scalarmult_base = 0x20821;
|
||||
rom_ed25519_ge_tobytes = 0x209e1;
|
||||
rom_ed25519_sc_muladd = 0x20a2d;
|
||||
rom_ed25519_sc_reduce = 0x2603d;
|
||||
__rtl_memchr_v1_00 = 0x28a4d;
|
||||
__rtl_memcmp_v1_00 = 0x28ae1;
|
||||
__rtl_memcpy_v1_00 = 0x28b49;
|
||||
__aeabi_memcpy = 0x28b49;
|
||||
__aeabi_memcpy4 = 0x28b49;
|
||||
__rtl_memmove_v1_00 = 0x28bed;
|
||||
__rtl_memset_v1_00 = 0x28cb5;
|
||||
__aeabi_memset = 0x28cb5;
|
||||
__rtl_strcat_v1_00 = 0x28d49;
|
||||
__rtl_strchr_v1_00 = 0x28d91;
|
||||
__rtl_strcmp_v1_00 = 0x28e55;
|
||||
__rtl_strcpy_v1_00 = 0x28ec9;
|
||||
__rtl_strlen_v1_00 = 0x28f15;
|
||||
__rtl_strncat_v1_00 = 0x28f69;
|
||||
__rtl_strncmp_v1_00 = 0x28fc5;
|
||||
__rtl_strncpy_v1_00 = 0x2907d;
|
||||
__rtl_strstr_v1_00 = 0x293cd;
|
||||
__rtl_strsep_v1_00 = 0x2960d;
|
||||
__rtl_strtok_v1_00 = 0x29619;
|
||||
__rtl__strtok_r_v1_00 = 0x2962d;
|
||||
__rtl_strtok_r_v1_00 = 0x29691;
|
||||
__rtl_close_v1_00 = 0x29699;
|
||||
__rtl_fstat_v1_00 = 0x296ad;
|
||||
__rtl_isatty_v1_00 = 0x296c1;
|
||||
__rtl_lseek_v1_00 = 0x296d5;
|
||||
__rtl_open_v1_00 = 0x296e9;
|
||||
__rtl_read_v1_00 = 0x296fd;
|
||||
__rtl_write_v1_00 = 0x29711;
|
||||
__rtl_sbrk_v1_00 = 0x29725;
|
||||
__rtl_ltoa_v1_00 = 0x297bd;
|
||||
__rtl_ultoa_v1_00 = 0x29855;
|
||||
__rtl_dtoi_v1_00 = 0x298c5;
|
||||
__rtl_dtoi64_v1_00 = 0x29945;
|
||||
__rtl_dtoui_v1_00 = 0x299dd;
|
||||
__rtl_ftol_v1_00 = 0x299e5;
|
||||
__rtl_itof_v1_00 = 0x29a51;
|
||||
__rtl_itod_v1_00 = 0x29ae9;
|
||||
__rtl_i64tod_v1_00 = 0x29b79;
|
||||
__rtl_uitod_v1_00 = 0x29c55;
|
||||
__rtl_ftod_v1_00 = 0x29d2d;
|
||||
__rtl_dtof_v1_00 = 0x29de9;
|
||||
__rtl_uitof_v1_00 = 0x29e89;
|
||||
__rtl_fadd_v1_00 = 0x29f65;
|
||||
__rtl_fsub_v1_00 = 0x2a261;
|
||||
__rtl_fmul_v1_00 = 0x2a559;
|
||||
__rtl_fdiv_v1_00 = 0x2a695;
|
||||
__rtl_dadd_v1_00 = 0x2a825;
|
||||
__rtl_dsub_v1_00 = 0x2aed9;
|
||||
__rtl_dmul_v1_00 = 0x2b555;
|
||||
__rtl_ddiv_v1_00 = 0x2b8ad;
|
||||
__rtl_dcmpeq_v1_00 = 0x2be4d;
|
||||
__rtl_dcmplt_v1_00 = 0x2bebd;
|
||||
__rtl_dcmpgt_v1_00 = 0x2bf51;
|
||||
__rtl_dcmple_v1_00 = 0x2c049;
|
||||
__rtl_fcmplt_v1_00 = 0x2c139;
|
||||
__rtl_fcmpgt_v1_00 = 0x2c195;
|
||||
__rtl_cos_f32_v1_00 = 0x2c229;
|
||||
__rtl_sin_f32_v1_00 = 0x2c435;
|
||||
__rtl_fabs_v1_00 = 0x2c639;
|
||||
__rtl_fabsf_v1_00 = 0x2c641;
|
||||
__rtl_dtoa_r_v1_00 = 0x2c77d;
|
||||
__rom_mallocr_init_v1_00 = 0x2d7d1;
|
||||
__rtl_free_r_v1_00 = 0x2d841;
|
||||
__rtl_malloc_r_v1_00 = 0x2da31;
|
||||
__rtl_realloc_r_v1_00 = 0x2df55;
|
||||
__rtl_memalign_r_v1_00 = 0x2e331;
|
||||
__rtl_valloc_r_v1_00 = 0x2e421;
|
||||
__rtl_pvalloc_r_v1_00 = 0x2e42d;
|
||||
__rtl_calloc_r_v1_00 = 0x2e441;
|
||||
__rtl_cfree_r_v1_00 = 0x2e4a9;
|
||||
__rtl_Balloc_v1_00 = 0x2e515;
|
||||
__rtl_Bfree_v1_00 = 0x2e571;
|
||||
__rtl_i2b_v1_00 = 0x2e585;
|
||||
__rtl_multadd_v1_00 = 0x2e599;
|
||||
__rtl_mult_v1_00 = 0x2e629;
|
||||
__rtl_pow5mult_v1_00 = 0x2e769;
|
||||
__rtl_hi0bits_v1_00 = 0x2e809;
|
||||
__rtl_d2b_v1_00 = 0x2e845;
|
||||
__rtl_lshift_v1_00 = 0x2e901;
|
||||
__rtl_cmp_v1_00 = 0x2e9bd;
|
||||
__rtl_diff_v1_00 = 0x2ea01;
|
||||
__rtl_sread_v1_00 = 0x2eae9;
|
||||
__rtl_seofread_v1_00 = 0x2eb39;
|
||||
__rtl_swrite_v1_00 = 0x2eb3d;
|
||||
__rtl_sseek_v1_00 = 0x2ebc1;
|
||||
__rtl_sclose_v1_00 = 0x2ec11;
|
||||
__rtl_sbrk_r_v1_00 = 0x2ec41;
|
||||
__rtl_fflush_r_v1_00 = 0x2ef8d;
|
||||
__rtl_vfprintf_r_v1_00 = 0x2f661;
|
||||
__rtl_fpclassifyd = 0x30c15;
|
||||
CpkClkTbl = 0x30c68;
|
||||
ROM_IMG1_VALID_PATTEN = 0x30c80;
|
||||
SpicCalibrationPattern = 0x30c88;
|
||||
SpicInitCPUCLK = 0x30c98;
|
||||
BAUDRATE = 0x30ca8;
|
||||
OVSR = 0x30d1c;
|
||||
DIV = 0x30d90;
|
||||
OVSR_ADJ = 0x30e04;
|
||||
__AES_rcon = 0x30e78;
|
||||
__AES_Te4 = 0x30ea0;
|
||||
I2CDmaChNo = 0x312a0;
|
||||
_GPIO_PinMap_Chip2IP_8195a = 0x312b4;
|
||||
_GPIO_PinMap_PullCtrl_8195a = 0x3136c;
|
||||
_GPIO_SWPORT_DDR_TBL = 0x31594;
|
||||
_GPIO_EXT_PORT_TBL = 0x31598;
|
||||
_GPIO_SWPORT_DR_TBL = 0x3159c;
|
||||
UartLogRomCmdTable = 0x316a0;
|
||||
_HalRuartOp = 0x31700;
|
||||
_HalGdmaOp = 0x31760;
|
||||
RTW_WPA_OUI_TYPE = 0x3540c;
|
||||
WPA_CIPHER_SUITE_NONE = 0x35410;
|
||||
WPA_CIPHER_SUITE_WEP40 = 0x35414;
|
||||
WPA_CIPHER_SUITE_TKIP = 0x35418;
|
||||
WPA_CIPHER_SUITE_CCMP = 0x3541c;
|
||||
WPA_CIPHER_SUITE_WEP104 = 0x35420;
|
||||
RSN_CIPHER_SUITE_NONE = 0x35424;
|
||||
RSN_CIPHER_SUITE_WEP40 = 0x35428;
|
||||
RSN_CIPHER_SUITE_TKIP = 0x3542c;
|
||||
RSN_CIPHER_SUITE_CCMP = 0x35430;
|
||||
RSN_CIPHER_SUITE_WEP104 = 0x35434;
|
||||
RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
|
||||
RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
|
||||
RSN_VERSION_BSD = 0x3544c;
|
||||
rom_wps_Te0 = 0x35988;
|
||||
rom_wps_rcons = 0x35d88;
|
||||
rom_wps_Td4s = 0x35d94;
|
||||
rom_wps_Td0 = 0x35e94;
|
||||
__rom_b_cut_end__ = 0x4467c;
|
||||
__rom_c_cut_text_start__ = 0x4467c;
|
||||
HalInitPlatformLogUartV02 = 0x4467d;
|
||||
HalReInitPlatformLogUartV02 = 0x4471d;
|
||||
HalInitPlatformTimerV02 = 0x44755;
|
||||
HalShowBuildInfoV02 = 0x447cd;
|
||||
SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
|
||||
HalSpiInitV02 = 0x4488d;
|
||||
HalBootFlowV02 = 0x44a29;
|
||||
HalInitialROMCodeGlobalVarV02 = 0x44ae5;
|
||||
HalResetVsrV02 = 0x44b41;
|
||||
HalI2CSendRtl8195aV02 = 0x44ce1;
|
||||
HalI2CSetCLKRtl8195aV02 = 0x44d59;
|
||||
RtkI2CSendV02 = 0x4508d;
|
||||
RtkI2CReceiveV02 = 0x459a1;
|
||||
HalI2COpInitV02 = 0x461ed;
|
||||
I2CISRHandleV02 = 0x463e9;
|
||||
RtkSalI2COpInitV02 = 0x46be1;
|
||||
SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
|
||||
SpiFlashAppV02 = 0x46c85;
|
||||
SpicInitRtl8195AV02 = 0x46dc5;
|
||||
SpicEraseFlashRtl8195AV02 = 0x46ea1;
|
||||
HalTimerIrq2To7HandleV02 = 0x46f5d;
|
||||
HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
|
||||
HalTimerInitRtl8195aV02 = 0x4706d;
|
||||
HalTimerReadCountRtl8195aV02 = 0x471b5;
|
||||
HalTimerReLoadRtl8195aV02 = 0x471d1;
|
||||
HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
|
||||
HalTimerDeInitRtl8195aV02 = 0x472c1;
|
||||
HalTimerOpInitV02 = 0x472f9;
|
||||
GPIO_LockV02 = 0x47345;
|
||||
GPIO_UnLockV02 = 0x47379;
|
||||
GPIO_Int_Clear_8195aV02 = 0x473a5;
|
||||
HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
|
||||
FindElementIndexV02 = 0x47541;
|
||||
HalRuartInitRtl8195aV02 = 0x4756d;
|
||||
DramInit_rom = 0x47619;
|
||||
ChangeRandSeed_rom = 0x47979;
|
||||
Sdr_Rand2_rom = 0x47985;
|
||||
MemTest_rom = 0x479dd;
|
||||
SdrCalibration_rom = 0x47a45;
|
||||
SdrControllerInit_rom = 0x47d99;
|
||||
SDIO_EnterCritical = 0x47e39;
|
||||
SDIO_ExitCritical = 0x47e85;
|
||||
SDIO_IRQ_Handler_Rom = 0x47ec5;
|
||||
SDIO_Interrupt_Init_Rom = 0x47f31;
|
||||
SDIO_Device_Init_Rom = 0x47f81;
|
||||
SDIO_Interrupt_DeInit_Rom = 0x48215;
|
||||
SDIO_Device_DeInit_Rom = 0x48255;
|
||||
SDIO_Enable_Interrupt_Rom = 0x48281;
|
||||
SDIO_Disable_Interrupt_Rom = 0x482a1;
|
||||
SDIO_Clear_ISR_Rom = 0x482c1;
|
||||
SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
|
||||
SDIO_Free_Rx_Pkt_Rom = 0x48331;
|
||||
SDIO_Recycle_Rx_BD_Rom = 0x48355;
|
||||
SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
|
||||
SDIO_RxTask_Rom = 0x4851d;
|
||||
SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
|
||||
SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
|
||||
SDIO_Process_RPWM_Rom = 0x485b5;
|
||||
SDIO_Reset_Cmd_Rom = 0x485e9;
|
||||
SDIO_Rx_Data_Transaction_Rom = 0x48611;
|
||||
SDIO_Send_C2H_PktMsg_Rom = 0x48829;
|
||||
SDIO_Register_Tx_Callback_Rom = 0x488f5;
|
||||
SDIO_ReadMem_Rom = 0x488fd;
|
||||
SDIO_WriteMem_Rom = 0x489a9;
|
||||
SDIO_SetMem_Rom = 0x48a69;
|
||||
SDIO_TX_Pkt_Handle_Rom = 0x48b29;
|
||||
SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
|
||||
SDIO_IRQ_Handler_BH_Rom = 0x48d95;
|
||||
SDIO_TxTask_Rom = 0x48e9d;
|
||||
SDIO_TaskUp_Rom = 0x48eed;
|
||||
SDIO_Boot_Up = 0x48f55;
|
||||
__rom_c_cut_text_end__ = 0x49070;
|
||||
__rom_c_cut_rodata_start__ = 0x49070;
|
||||
BAUDRATE_v02 = 0x49070;
|
||||
OVSR_v02 = 0x490fc;
|
||||
DIV_v02 = 0x49188;
|
||||
OVSR_ADJ_v02 = 0x49214;
|
||||
SdrDramInfo_rom = 0x492a0;
|
||||
SdrDramTiming_rom = 0x492b4;
|
||||
SdrDramModeReg_rom = 0x492e8;
|
||||
SdrDramDev_rom = 0x49304;
|
||||
__rom_c_cut_rodata_end__ = 0x49314;
|
||||
NewVectorTable = 0x10000000;
|
||||
UserIrqFunTable = 0x10000100;
|
||||
UserIrqDataTable = 0x10000200;
|
||||
__rom_bss_start__ = 0x10000300;
|
||||
CfgSysDebugWarn = 0x10000300;
|
||||
CfgSysDebugInfo = 0x10000304;
|
||||
CfgSysDebugErr = 0x10000308;
|
||||
ConfigDebugWarn = 0x1000030c;
|
||||
ConfigDebugInfo = 0x10000310;
|
||||
ConfigDebugErr = 0x10000314;
|
||||
HalTimerOp = 0x10000318;
|
||||
GPIOState = 0x10000334;
|
||||
gTimerRecord = 0x1000034c;
|
||||
SSI_DBG_CONFIG = 0x10000350;
|
||||
_pHAL_Gpio_Adapter = 0x10000354;
|
||||
Timer2To7VectorTable = 0x10000358;
|
||||
pUartLogCtl = 0x10000384;
|
||||
UartLogBuf = 0x10000388;
|
||||
UartLogCtl = 0x10000408;
|
||||
UartLogHistoryBuf = 0x10000430;
|
||||
ArgvArray = 0x100006ac;
|
||||
rom_wlan_ram_map = 0x100006d4;
|
||||
FalseAlmCnt = 0x100006e0;
|
||||
ROMInfo = 0x10000720;
|
||||
DM_CfoTrack = 0x10000738;
|
||||
rom_libgloss_ram_map = 0x10000760;
|
||||
__rtl_errno = 0x10000bc4;
|
||||
_rtl_impure_ptr = 0x10001c60;
|
||||
}
|
||||
|
|
@ -0,0 +1,743 @@
|
|||
SECTIONS
|
||||
{
|
||||
__vectors_table = 0x0;
|
||||
Reset_Handler = 0x101;
|
||||
NMI_Handler = 0x109;
|
||||
HardFault_Handler = 0x10d;
|
||||
MemManage_Handler = 0x121;
|
||||
BusFault_Handler = 0x125;
|
||||
UsageFault_Handler = 0x129;
|
||||
HalLogUartInit = 0x201;
|
||||
HalSerialPutcRtl8195a = 0x2d9;
|
||||
HalSerialGetcRtl8195a = 0x309;
|
||||
HalSerialGetIsrEnRegRtl8195a = 0x329;
|
||||
HalSerialSetIrqEnRegRtl8195a = 0x335;
|
||||
HalCpuClkConfig = 0x341;
|
||||
HalGetCpuClk = 0x355;
|
||||
HalRomInfo = 0x39d;
|
||||
HalGetRomInfo = 0x3b5;
|
||||
HalResetVsr = 0x3c5;
|
||||
HalDelayUs = 0x899;
|
||||
HalNMIHandler = 0x8e1;
|
||||
HalHardFaultHandler = 0x911;
|
||||
HalMemManageHandler = 0xc09;
|
||||
HalBusFaultHandler = 0xc39;
|
||||
HalUsageFaultHandler = 0xc69;
|
||||
HalUart0PinCtrlRtl8195A = 0xcfd;
|
||||
HalUart1PinCtrlRtl8195A = 0xdc9;
|
||||
HalUart2PinCtrlRtl8195A = 0xe9d;
|
||||
HalSPI0PinCtrlRtl8195A = 0xf75;
|
||||
HalSPI1PinCtrlRtl8195A = 0x1015;
|
||||
HalSPI2PinCtrlRtl8195A = 0x10e5;
|
||||
HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
|
||||
HalI2C0PinCtrlRtl8195A = 0x1275;
|
||||
HalI2C1PinCtrlRtl8195A = 0x1381;
|
||||
HalI2C2PinCtrlRtl8195A = 0x1459;
|
||||
HalI2C3PinCtrlRtl8195A = 0x1529;
|
||||
HalI2S0PinCtrlRtl8195A = 0x1639;
|
||||
HalI2S1PinCtrlRtl8195A = 0x176d;
|
||||
HalPCM0PinCtrlRtl8195A = 0x1845;
|
||||
HalPCM1PinCtrlRtl8195A = 0x1949;
|
||||
HalSDIODPinCtrlRtl8195A = 0x1a1d;
|
||||
HalSDIOHPinCtrlRtl8195A = 0x1a6d;
|
||||
HalMIIPinCtrlRtl8195A = 0x1ab9;
|
||||
HalWLLEDPinCtrlRtl8195A = 0x1b51;
|
||||
HalWLANT0PinCtrlRtl8195A = 0x1c0d;
|
||||
HalWLANT1PinCtrlRtl8195A = 0x1c61;
|
||||
HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
|
||||
HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
|
||||
HalNFCPinCtrlRtl8195A = 0x1d59;
|
||||
HalPWM0PinCtrlRtl8195A = 0x1da9;
|
||||
HalPWM1PinCtrlRtl8195A = 0x1ead;
|
||||
HalPWM2PinCtrlRtl8195A = 0x1fb5;
|
||||
HalPWM3PinCtrlRtl8195A = 0x20b1;
|
||||
HalETE0PinCtrlRtl8195A = 0x21b9;
|
||||
HalETE1PinCtrlRtl8195A = 0x22c1;
|
||||
HalETE2PinCtrlRtl8195A = 0x23c9;
|
||||
HalETE3PinCtrlRtl8195A = 0x24d1;
|
||||
HalEGTIMPinCtrlRtl8195A = 0x25d9;
|
||||
HalSPIFlashPinCtrlRtl8195A = 0x2679;
|
||||
HalSDRPinCtrlRtl8195A = 0x2725;
|
||||
HalJTAGPinCtrlRtl8195A = 0x280d;
|
||||
HalTRACEPinCtrlRtl8195A = 0x2861;
|
||||
HalLOGUartPinCtrlRtl8195A = 0x28b9;
|
||||
HalLOGUartIRPinCtrlRtl8195A = 0x291d;
|
||||
HalSICPinCtrlRtl8195A = 0x2981;
|
||||
HalEEPROMPinCtrlRtl8195A = 0x29d9;
|
||||
HalDEBUGPinCtrlRtl8195A = 0x2a31;
|
||||
HalPinCtrlRtl8195A = 0x2b39;
|
||||
SpicRxCmdRtl8195A = 0x2e5d;
|
||||
SpicWaitBusyDoneRtl8195A = 0x2ea5;
|
||||
SpicGetFlashStatusRtl8195A = 0x2eb5;
|
||||
SpicWaitWipDoneRtl8195A = 0x2f55;
|
||||
SpicTxCmdRtl8195A = 0x2f6d;
|
||||
SpicSetFlashStatusRtl8195A = 0x2fc1;
|
||||
SpicCmpDataForCalibrationRtl8195A = 0x3049;
|
||||
SpicLoadInitParaFromClockRtl8195A = 0x3081;
|
||||
SpicInitRtl8195A = 0x30e5;
|
||||
SpicEraseFlashRtl8195A = 0x31bd;
|
||||
SpiFlashApp = 0x3279;
|
||||
HalPeripheralIntrHandle = 0x33b5;
|
||||
HalSysOnIntrHandle = 0x3439;
|
||||
HalWdgIntrHandle = 0x3485;
|
||||
HalTimer0IntrHandle = 0x34d5;
|
||||
HalTimer1IntrHandle = 0x3525;
|
||||
HalI2C3IntrHandle = 0x3575;
|
||||
HalTimer2To7IntrHandle = 0x35c5;
|
||||
HalSpi0IntrHandle = 0x3615;
|
||||
HalGpioIntrHandle = 0x3665;
|
||||
HalUart0IntrHandle = 0x36b5;
|
||||
HalSpiFlashIntrHandle = 0x3705;
|
||||
HalUsbOtgIntrHandle = 0x3755;
|
||||
HalSdioHostIntrHandle = 0x37a5;
|
||||
HalI2s0OrPcm0IntrHandle = 0x37f5;
|
||||
HalI2s1OrPcm1IntrHandle = 0x3845;
|
||||
HalWlDmaIntrHandle = 0x3895;
|
||||
HalWlProtocolIntrHandle = 0x38e5;
|
||||
HalCryptoIntrHandle = 0x3935;
|
||||
HalGmacIntrHandle = 0x3985;
|
||||
HalGdma0Ch0IntrHandle = 0x39d5;
|
||||
HalGdma0Ch1IntrHandle = 0x3a25;
|
||||
HalGdma0Ch2IntrHandle = 0x3a75;
|
||||
HalGdma0Ch3IntrHandle = 0x3ac5;
|
||||
HalGdma0Ch4IntrHandle = 0x3b15;
|
||||
HalGdma0Ch5IntrHandle = 0x3b65;
|
||||
HalGdma1Ch0IntrHandle = 0x3bb5;
|
||||
HalGdma1Ch1IntrHandle = 0x3c05;
|
||||
HalGdma1Ch2IntrHandle = 0x3c55;
|
||||
HalGdma1Ch3IntrHandle = 0x3ca5;
|
||||
HalGdma1Ch4IntrHandle = 0x3cf5;
|
||||
HalGdma1Ch5IntrHandle = 0x3d45;
|
||||
HalSdioDeviceIntrHandle = 0x3d95;
|
||||
VectorTableInitRtl8195A = 0x3de5;
|
||||
VectorTableInitForOSRtl8195A = 0x4019;
|
||||
VectorIrqRegisterRtl8195A = 0x4029;
|
||||
VectorIrqUnRegisterRtl8195A = 0x4091;
|
||||
VectorIrqEnRtl8195A = 0x40f1;
|
||||
VectorIrqDisRtl8195A = 0x418d;
|
||||
_UartRxDmaIrqHandle = 0x422d;
|
||||
HalRuartPutCRtl8195a = 0x4281;
|
||||
HalRuartGetCRtl8195a = 0x429d;
|
||||
HalRuartRTSCtrlRtl8195a = 0x42bd;
|
||||
HalRuartGetDebugValueRtl8195a = 0x42e1;
|
||||
HalRuartGetIMRRtl8195a = 0x43e1;
|
||||
HalRuartSetIMRRtl8195a = 0x442d;
|
||||
_UartIrqHandle = 0x4465;
|
||||
HalRuartDmaInitRtl8195a = 0x4681;
|
||||
HalRuartIntDisableRtl8195a = 0x4845;
|
||||
HalRuartDeInitRtl8195a = 0x4855;
|
||||
HalRuartIntEnableRtl8195a = 0x4985;
|
||||
_UartTxDmaIrqHandle = 0x4995;
|
||||
HalRuartRegIrqRtl8195a = 0x49d1;
|
||||
HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
|
||||
HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
|
||||
HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
|
||||
RuartLock = 0x4cc9;
|
||||
RuartUnLock = 0x4ced;
|
||||
HalRuartIntSendRtl8195a = 0x4d09;
|
||||
HalRuartDmaSendRtl8195a = 0x4e35;
|
||||
HalRuartStopSendRtl8195a = 0x4f89;
|
||||
HalRuartIntRecvRtl8195a = 0x504d;
|
||||
HalRuartDmaRecvRtl8195a = 0x51ad;
|
||||
HalRuartStopRecvRtl8195a = 0x52cd;
|
||||
RuartIsTimeout = 0x5385;
|
||||
HalRuartSendRtl8195a = 0x53b1;
|
||||
HalRuartRecvRtl8195a = 0x5599;
|
||||
RuartResetRxFifoRtl8195a = 0x5751;
|
||||
HalRuartResetRxFifoRtl8195a = 0x5775;
|
||||
HalRuartInitRtl8195a = 0x5829;
|
||||
HalGdmaOnOffRtl8195a = 0x5df1;
|
||||
HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
|
||||
HalGdmaChEnRtl8195a = 0x5e51;
|
||||
HalGdmaChDisRtl8195a = 0x5e6d;
|
||||
HalGdamChInitRtl8195a = 0x5e91;
|
||||
HalGdmaChSetingRtl8195a = 0x5ebd;
|
||||
HalGdmaChBlockSetingRtl8195a = 0x000060dd;
|
||||
HalGdmaChIsrCleanRtl8195a = 0x6419;
|
||||
HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
|
||||
HalGdmaChCleanAutoDstRtl8195a = 0x6501;
|
||||
HalEFUSEPowerSwitch8195AROM = 0x6561;
|
||||
HALEFUSEOneByteReadROM = 0x65f9;
|
||||
HALEFUSEOneByteWriteROM = 0x6699;
|
||||
__rtl_memcmpb_v1_00 = 0x681d;
|
||||
__rtl_random_v1_00 = 0x6861;
|
||||
__rtl_align_to_be32_v1_00 = 0x6881;
|
||||
__rtl_memsetw_v1_00 = 0x6899;
|
||||
__rtl_memsetb_v1_00 = 0x68ad;
|
||||
__rtl_memcpyw_v1_00 = 0x68bd;
|
||||
__rtl_memcpyb_v1_00 = 0x68dd;
|
||||
__rtl_memDump_v1_00 = 0x68f5;
|
||||
__rtl_AES_set_encrypt_key = 0x6901;
|
||||
__rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
|
||||
__rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
|
||||
__rtl_cryptoEngine_init_v1_00 = 0x6ea9;
|
||||
__rtl_cryptoEngine_exit_v1_00 = 0x7055;
|
||||
__rtl_cryptoEngine_reset_v1_00 = 0x70b1;
|
||||
__rtl_cryptoEngine_v1_00 = 0x70ed;
|
||||
__rtl_crypto_cipher_init_v1_00 = 0x7c69;
|
||||
__rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
|
||||
__rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
|
||||
HalSsiPinmuxEnableRtl8195a = 0x7cd5;
|
||||
HalSsiEnableRtl8195a = 0x7e45;
|
||||
HalSsiDisableRtl8195a = 0x7ef9;
|
||||
HalSsiLoadSettingRtl8195a = 0x7fad;
|
||||
HalSsiSetInterruptMaskRtl8195a = 0x8521;
|
||||
HalSsiGetInterruptMaskRtl8195a = 0x85c9;
|
||||
HalSsiSetSclkPolarityRtl8195a = 0x863d;
|
||||
HalSsiSetSclkPhaseRtl8195a = 0x8715;
|
||||
HalSsiWriteRtl8195a = 0x87e9;
|
||||
HalSsiSetDeviceRoleRtl8195a = 0x8861;
|
||||
HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
|
||||
HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
|
||||
HalSsiReadRtl8195a = 0x89b9;
|
||||
HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
|
||||
HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
|
||||
HalSsiGetStatusRtl8195a = 0x8b1d;
|
||||
HalSsiWriteableRtl8195a = 0x8b91;
|
||||
HalSsiReadableRtl8195a = 0x8c09;
|
||||
HalSsiBusyRtl8195a = 0x8c81;
|
||||
HalSsiReadInterruptRtl8195a = 0x8cf9;
|
||||
HalSsiWriteInterruptRtl8195a = 0x8efd;
|
||||
HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
|
||||
HalSsiGetInterruptStatusRtl8195a = 0x90d9;
|
||||
HalSsiInterruptEnableRtl8195a = 0x914d;
|
||||
HalSsiInterruptDisableRtl8195a = 0x9299;
|
||||
HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
|
||||
HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
|
||||
HalSsiInitRtl8195a = 0x94d1;
|
||||
_SsiReadInterrupt = 0x9ba5;
|
||||
_SsiWriteInterrupt = 0x9db1;
|
||||
_SsiIrqHandle = 0x9eb1;
|
||||
HalI2CWrite32 = 0xa061;
|
||||
HalI2CRead32 = 0xa09d;
|
||||
HalI2CDeInit8195a = 0xa0dd;
|
||||
HalI2CSendRtl8195a = 0xa1f1;
|
||||
HalI2CReceiveRtl8195a = 0xa25d;
|
||||
HalI2CEnableRtl8195a = 0xa271;
|
||||
HalI2CIntrCtrl8195a = 0xa389;
|
||||
HalI2CReadRegRtl8195a = 0xa3a1;
|
||||
HalI2CWriteRegRtl8195a = 0xa3b1;
|
||||
HalI2CSetCLKRtl8195a = 0xa3c5;
|
||||
HalI2CMassSendRtl8195a = 0xa6e9;
|
||||
HalI2CClrIntrRtl8195a = 0xa749;
|
||||
HalI2CClrAllIntrRtl8195a = 0xa761;
|
||||
HalI2CInit8195a = 0xa775;
|
||||
HalI2CDMACtrl8195a = 0xaa31;
|
||||
RtkI2CIoCtrl = 0xaa61;
|
||||
RtkI2CPowerCtrl = 0xaa65;
|
||||
HalI2COpInit = 0xaa69;
|
||||
I2CIsTimeout = 0xac65;
|
||||
I2CTXGDMAISRHandle = 0xb435;
|
||||
I2CRXGDMAISRHandle = 0xb4c1;
|
||||
RtkI2CIrqInit = 0xb54d;
|
||||
RtkI2CIrqDeInit = 0xb611;
|
||||
RtkI2CPinMuxInit = 0xb675;
|
||||
RtkI2CPinMuxDeInit = 0xb7c9;
|
||||
RtkI2CDMAInit = 0xb955;
|
||||
RtkI2CInit = 0xbc95;
|
||||
RtkI2CDMADeInit = 0xbdad;
|
||||
RtkI2CDeInit = 0xbe4d;
|
||||
RtkI2CSendUserAddr = 0xbee5;
|
||||
RtkI2CSend = 0xc07d;
|
||||
RtkI2CLoadDefault = 0xce51;
|
||||
RtkSalI2COpInit = 0xcf21;
|
||||
HalI2SWrite32 = 0xcf65;
|
||||
HalI2SRead32 = 0xcf85;
|
||||
HalI2SDeInitRtl8195a = 0xcfa9;
|
||||
HalI2STxRtl8195a = 0xcfc9;
|
||||
HalI2SRxRtl8195a = 0xd011;
|
||||
HalI2SEnableRtl8195a = 0xd05d;
|
||||
HalI2SIntrCtrlRtl8195a = 0xd0b1;
|
||||
HalI2SReadRegRtl8195a = 0xd0d1;
|
||||
HalI2SClrIntrRtl8195a = 0xd0dd;
|
||||
HalI2SClrAllIntrRtl8195a = 0xd0fd;
|
||||
HalI2SInitRtl8195a = 0xd11d;
|
||||
GPIO_GetIPPinName_8195a = 0xd2e5;
|
||||
GPIO_GetChipPinName_8195a = 0xd331;
|
||||
GPIO_PullCtrl_8195a = 0xd39d;
|
||||
GPIO_FuncOn_8195a = 0xd421;
|
||||
GPIO_FuncOff_8195a = 0xd481;
|
||||
GPIO_Int_Mask_8195a = 0xd4e9;
|
||||
GPIO_Int_SetType_8195a = 0xd511;
|
||||
HAL_GPIO_IrqHandler_8195a = 0xd5fd;
|
||||
HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
|
||||
HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
|
||||
HAL_GPIO_IntCtrl_8195a = 0xd6cd;
|
||||
HAL_GPIO_Init_8195a = 0xd805;
|
||||
HAL_GPIO_DeInit_8195a = 0xdac1;
|
||||
HAL_GPIO_ReadPin_8195a = 0xdbd1;
|
||||
HAL_GPIO_WritePin_8195a = 0xdc91;
|
||||
HAL_GPIO_RegIrq_8195a = 0xddad;
|
||||
HAL_GPIO_UnRegIrq_8195a = 0xddf5;
|
||||
HAL_GPIO_UserRegIrq_8195a = 0xde15;
|
||||
HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
|
||||
HAL_GPIO_MaskIrq_8195a = 0xdfc1;
|
||||
HAL_GPIO_UnMaskIrq_8195a = 0xe061;
|
||||
HAL_GPIO_IntDebounce_8195a = 0xe101;
|
||||
HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
|
||||
HAL_GPIO_PullCtrl_8195a = 0xe1c9;
|
||||
DumpForOneBytes = 0xe259;
|
||||
CmdRomHelp = 0xe419;
|
||||
CmdWriteWord = 0xe491;
|
||||
CmdDumpHelfWord = 0xe505;
|
||||
CmdDumpWord = 0xe5f1;
|
||||
CmdDumpByte = 0xe6f5;
|
||||
CmdSpiFlashTool = 0xe751;
|
||||
GetRomCmdNum = 0xe7a9;
|
||||
CmdWriteByte = 0xe7ad;
|
||||
Isspace = 0xe7ed;
|
||||
Strtoul = 0xe801;
|
||||
ArrayInitialize = 0xe8b1;
|
||||
GetArgc = 0xe8c9;
|
||||
GetArgv = 0xe8f9;
|
||||
UartLogCmdExecute = 0xe95d;
|
||||
UartLogShowBackSpace = 0xe9fd;
|
||||
UartLogRecallOldCmd = 0xea39;
|
||||
UartLogHistoryCmd = 0xea71;
|
||||
UartLogCmdChk = 0xeadd;
|
||||
UartLogIrqHandle = 0xebf5;
|
||||
RtlConsolInit = 0xecc5;
|
||||
RtlConsolTaskRom = 0xed49;
|
||||
RtlExitConsol = 0xed79;
|
||||
RtlConsolRom = 0xedcd;
|
||||
HalTimerOpInit = 0xee0d;
|
||||
HalTimerIrq2To7Handle = 0xee59;
|
||||
HalGetTimerIdRtl8195a = 0xef09;
|
||||
HalTimerInitRtl8195a = 0xef3d;
|
||||
HalTimerDisRtl8195a = 0xf069;
|
||||
HalTimerEnRtl8195a = 0xf089;
|
||||
HalTimerReadCountRtl8195a = 0xf0a9;
|
||||
HalTimerIrqClearRtl8195a = 0xf0bd;
|
||||
HalTimerDumpRegRtl8195a = 0xf0d1;
|
||||
VSprintf = 0xf129;
|
||||
DiagPrintf = 0xf39d;
|
||||
DiagSPrintf = 0xf3b9;
|
||||
DiagSnPrintf = 0xf3d1;
|
||||
prvDiagPrintf = 0xf3ed;
|
||||
prvDiagSPrintf = 0xf40d;
|
||||
_memcmp = 0xf429;
|
||||
_memcpy = 0xf465;
|
||||
_memset = 0xf511;
|
||||
Rand = 0xf585;
|
||||
_strncpy = 0xf60d;
|
||||
_strcpy = 0xf629;
|
||||
prvStrCpy = 0xf639;
|
||||
_strlen = 0xf651;
|
||||
_strnlen = 0xf669;
|
||||
prvStrLen = 0xf699;
|
||||
_strcmp = 0xf6b1;
|
||||
_strncmp = 0xf6d1;
|
||||
prvStrCmp = 0xf719;
|
||||
StrUpr = 0xf749;
|
||||
prvAtoi = 0xf769;
|
||||
prvStrStr = 0xf7bd;
|
||||
_strsep = 0xf7d5;
|
||||
skip_spaces = 0xf815;
|
||||
skip_atoi = 0xf831;
|
||||
_parse_integer_fixup_radix = 0xf869;
|
||||
_parse_integer = 0xf8bd;
|
||||
simple_strtoull = 0xf915;
|
||||
simple_strtoll = 0xf945;
|
||||
simple_strtoul = 0xf965;
|
||||
simple_strtol = 0xf96d;
|
||||
_vsscanf = 0xf985;
|
||||
_sscanf = 0xff71;
|
||||
div_u64 = 0xff91;
|
||||
div_s64 = 0xff99;
|
||||
div_u64_rem = 0xffa1;
|
||||
div_s64_rem = 0xffb1;
|
||||
_strpbrk = 0xffc1;
|
||||
_strchr = 0xffed;
|
||||
aes_set_key = 0x10005;
|
||||
aes_encrypt = 0x103d1;
|
||||
aes_decrypt = 0x114a5;
|
||||
AES_WRAP = 0x125c9;
|
||||
AES_UnWRAP = 0x12701;
|
||||
crc32_get = 0x12861;
|
||||
arc4_byte = 0x12895;
|
||||
rt_arc4_init = 0x128bd;
|
||||
rt_arc4_crypt = 0x12901;
|
||||
rt_md5_init = 0x131c1;
|
||||
rt_md5_append = 0x131f5;
|
||||
rt_md5_final = 0x1327d;
|
||||
rt_md5_hmac = 0x132d5;
|
||||
rtw_get_bit_value_from_ieee_value = 0x13449;
|
||||
rtw_is_cckrates_included = 0x13475;
|
||||
rtw_is_cckratesonly_included = 0x134b5;
|
||||
rtw_check_network_type = 0x134dd;
|
||||
rtw_set_fixed_ie = 0x1350d;
|
||||
rtw_set_ie = 0x1352d;
|
||||
rtw_get_ie = 0x1355d;
|
||||
rtw_set_supported_rate = 0x13591;
|
||||
rtw_get_rateset_len = 0x13611;
|
||||
rtw_get_wpa_ie = 0x1362d;
|
||||
rtw_get_wpa2_ie = 0x136c9;
|
||||
rtw_get_wpa_cipher_suite = 0x13701;
|
||||
rtw_get_wpa2_cipher_suite = 0x13769;
|
||||
rtw_parse_wpa_ie = 0x137d1;
|
||||
rtw_parse_wpa2_ie = 0x138ad;
|
||||
rtw_get_sec_ie = 0x13965;
|
||||
rtw_get_wps_ie = 0x13a15;
|
||||
rtw_get_wps_attr = 0x13a99;
|
||||
rtw_get_wps_attr_content = 0x13b49;
|
||||
rtw_ieee802_11_parse_elems = 0x13b91;
|
||||
str_2char2num = 0x13d9d;
|
||||
key_2char2num = 0x13db9;
|
||||
convert_ip_addr = 0x13dd1;
|
||||
rom_psk_PasswordHash = 0x13e9d;
|
||||
rom_psk_CalcGTK = 0x13ed5;
|
||||
rom_psk_CalcPTK = 0x13f69;
|
||||
wep_80211_encrypt = 0x14295;
|
||||
wep_80211_decrypt = 0x142f5;
|
||||
tkip_micappendbyte = 0x14389;
|
||||
rtw_secmicsetkey = 0x143d9;
|
||||
rtw_secmicappend = 0x14419;
|
||||
rtw_secgetmic = 0x14435;
|
||||
rtw_seccalctkipmic = 0x1449d;
|
||||
tkip_phase1 = 0x145a5;
|
||||
tkip_phase2 = 0x14725;
|
||||
tkip_80211_encrypt = 0x14941;
|
||||
tkip_80211_decrypt = 0x149d5;
|
||||
aes1_encrypt = 0x14a8d;
|
||||
aesccmp_construct_mic_iv = 0x14c65;
|
||||
aesccmp_construct_mic_header1 = 0x14ccd;
|
||||
aesccmp_construct_mic_header2 = 0x14d21;
|
||||
aesccmp_construct_ctr_preload = 0x14db5;
|
||||
aes_80211_encrypt = 0x14e29;
|
||||
aes_80211_decrypt = 0x151ad;
|
||||
_sha1_process_message_block = 0x155b9;
|
||||
_sha1_pad_message = 0x15749;
|
||||
rt_sha1_init = 0x157e5;
|
||||
rt_sha1_update = 0x15831;
|
||||
rt_sha1_finish = 0x158a9;
|
||||
rt_hmac_sha1 = 0x15909;
|
||||
rom_aes_128_cbc_encrypt = 0x15a65;
|
||||
rom_aes_128_cbc_decrypt = 0x15ae1;
|
||||
rom_rijndaelKeySetupEnc = 0x15b5d;
|
||||
rom_aes_decrypt_init = 0x15c39;
|
||||
rom_aes_internal_decrypt = 0x15d15;
|
||||
rom_aes_decrypt_deinit = 0x16071;
|
||||
rom_aes_encrypt_init = 0x16085;
|
||||
rom_aes_internal_encrypt = 0x1609d;
|
||||
rom_aes_encrypt_deinit = 0x16451;
|
||||
bignum_init = 0x17b35;
|
||||
bignum_deinit = 0x17b61;
|
||||
bignum_get_unsigned_bin_len = 0x17b81;
|
||||
bignum_get_unsigned_bin = 0x17b85;
|
||||
bignum_set_unsigned_bin = 0x17c21;
|
||||
bignum_cmp = 0x17cd1;
|
||||
bignum_cmp_d = 0x17cd5;
|
||||
bignum_add = 0x17cfd;
|
||||
bignum_sub = 0x17d0d;
|
||||
bignum_mul = 0x17d1d;
|
||||
bignum_exptmod = 0x17d2d;
|
||||
WPS_realloc = 0x17d51;
|
||||
os_zalloc = 0x17d99;
|
||||
rom_hmac_sha256_vector = 0x17dc1;
|
||||
rom_hmac_sha256 = 0x17ebd;
|
||||
rom_sha256_vector = 0x18009;
|
||||
phy_CalculateBitShift = 0x18221;
|
||||
PHY_SetBBReg_8195A = 0x18239;
|
||||
PHY_QueryBBReg_8195A = 0x18279;
|
||||
ROM_odm_QueryRxPwrPercentage = 0x1829d;
|
||||
ROM_odm_EVMdbToPercentage = 0x182bd;
|
||||
ROM_odm_SignalScaleMapping_8195A = 0x182e5;
|
||||
ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
|
||||
ROM_odm_SetEDCCAThreshold = 0x18721;
|
||||
ROM_odm_SetTRxMux = 0x18749;
|
||||
ROM_odm_SetCrystalCap = 0x18771;
|
||||
ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
|
||||
ROM_ODM_CfoTrackingReset = 0x187e9;
|
||||
ROM_odm_CfoTrackingFlow = 0x18811;
|
||||
curve25519_donna = 0x1965d;
|
||||
aes_test_alignment_detection = 0x1a391;
|
||||
aes_mode_reset = 0x1a3ed;
|
||||
aes_ecb_encrypt = 0x1a3f9;
|
||||
aes_ecb_decrypt = 0x1a431;
|
||||
aes_cbc_encrypt = 0x1a469;
|
||||
aes_cbc_decrypt = 0x1a579;
|
||||
aes_cfb_encrypt = 0x1a701;
|
||||
aes_cfb_decrypt = 0x1a9e5;
|
||||
aes_ofb_crypt = 0x1acc9;
|
||||
aes_ctr_crypt = 0x1af7d;
|
||||
aes_encrypt_key128 = 0x1b289;
|
||||
aes_encrypt_key192 = 0x1b2a5;
|
||||
aes_encrypt_key256 = 0x1b2c1;
|
||||
aes_encrypt_key = 0x1b2e1;
|
||||
aes_decrypt_key128 = 0x1b351;
|
||||
aes_decrypt_key192 = 0x1b36d;
|
||||
aes_decrypt_key256 = 0x1b389;
|
||||
aes_decrypt_key = 0x1b3a9;
|
||||
aes_init = 0x1b419;
|
||||
CRYPTO_chacha_20 = 0x1b41d;
|
||||
CRYPTO_poly1305_init = 0x1bc25;
|
||||
CRYPTO_poly1305_update = 0x1bd09;
|
||||
CRYPTO_poly1305_finish = 0x1bd8d;
|
||||
rom_sha512_starts = 0x1ceb5;
|
||||
rom_sha512_update = 0x1d009;
|
||||
rom_sha512_finish = 0x1d011;
|
||||
rom_sha512 = 0x1d261;
|
||||
rom_sha512_hmac_starts = 0x1d299;
|
||||
rom_sha512_hmac_update = 0x1d35d;
|
||||
rom_sha512_hmac_finish = 0x1d365;
|
||||
rom_sha512_hmac_reset = 0x1d3b5;
|
||||
rom_sha512_hmac = 0x1d3d1;
|
||||
rom_sha512_hkdf = 0x1d40d;
|
||||
rom_ed25519_gen_keypair = 0x1d501;
|
||||
rom_ed25519_gen_signature = 0x1d505;
|
||||
rom_ed25519_verify_signature = 0x1d51d;
|
||||
rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
|
||||
rom_ed25519_crypto_sign_detached = 0x1d579;
|
||||
rom_ed25519_crypto_sign_verify_detached = 0x1d655;
|
||||
rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
|
||||
rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
|
||||
rom_ed25519_ge_p3_tobytes = 0x207d5;
|
||||
rom_ed25519_ge_scalarmult_base = 0x20821;
|
||||
rom_ed25519_ge_tobytes = 0x209e1;
|
||||
rom_ed25519_sc_muladd = 0x20a2d;
|
||||
rom_ed25519_sc_reduce = 0x2603d;
|
||||
__rtl_memchr_v1_00 = 0x28a4d;
|
||||
__rtl_memcmp_v1_00 = 0x28ae1;
|
||||
__rtl_memcpy_v1_00 = 0x28b49;
|
||||
__aeabi_memcpy = 0x28b49;
|
||||
__aeabi_memcpy4 = 0x28b49;
|
||||
__rtl_memmove_v1_00 = 0x28bed;
|
||||
__rtl_memset_v1_00 = 0x28cb5;
|
||||
__aeabi_memset = 0x28cb5;
|
||||
__rtl_strcat_v1_00 = 0x28d49;
|
||||
__rtl_strchr_v1_00 = 0x28d91;
|
||||
__rtl_strcmp_v1_00 = 0x28e55;
|
||||
__rtl_strcpy_v1_00 = 0x28ec9;
|
||||
__rtl_strlen_v1_00 = 0x28f15;
|
||||
__rtl_strncat_v1_00 = 0x28f69;
|
||||
__rtl_strncmp_v1_00 = 0x28fc5;
|
||||
__rtl_strncpy_v1_00 = 0x2907d;
|
||||
__rtl_strstr_v1_00 = 0x293cd;
|
||||
__rtl_strsep_v1_00 = 0x2960d;
|
||||
__rtl_strtok_v1_00 = 0x29619;
|
||||
__rtl__strtok_r_v1_00 = 0x2962d;
|
||||
__rtl_strtok_r_v1_00 = 0x29691;
|
||||
__rtl_close_v1_00 = 0x29699;
|
||||
__rtl_fstat_v1_00 = 0x296ad;
|
||||
__rtl_isatty_v1_00 = 0x296c1;
|
||||
__rtl_lseek_v1_00 = 0x296d5;
|
||||
__rtl_open_v1_00 = 0x296e9;
|
||||
__rtl_read_v1_00 = 0x296fd;
|
||||
__rtl_write_v1_00 = 0x29711;
|
||||
__rtl_sbrk_v1_00 = 0x29725;
|
||||
__rtl_ltoa_v1_00 = 0x297bd;
|
||||
__rtl_ultoa_v1_00 = 0x29855;
|
||||
__rtl_dtoi_v1_00 = 0x298c5;
|
||||
__rtl_dtoi64_v1_00 = 0x29945;
|
||||
__rtl_dtoui_v1_00 = 0x299dd;
|
||||
__rtl_ftol_v1_00 = 0x299e5;
|
||||
__rtl_itof_v1_00 = 0x29a51;
|
||||
__rtl_itod_v1_00 = 0x29ae9;
|
||||
__rtl_i64tod_v1_00 = 0x29b79;
|
||||
__rtl_uitod_v1_00 = 0x29c55;
|
||||
__rtl_ftod_v1_00 = 0x29d2d;
|
||||
__rtl_dtof_v1_00 = 0x29de9;
|
||||
__rtl_uitof_v1_00 = 0x29e89;
|
||||
__rtl_fadd_v1_00 = 0x29f65;
|
||||
__rtl_fsub_v1_00 = 0x2a261;
|
||||
__rtl_fmul_v1_00 = 0x2a559;
|
||||
__rtl_fdiv_v1_00 = 0x2a695;
|
||||
__rtl_dadd_v1_00 = 0x2a825;
|
||||
__rtl_dsub_v1_00 = 0x2aed9;
|
||||
__rtl_dmul_v1_00 = 0x2b555;
|
||||
__rtl_ddiv_v1_00 = 0x2b8ad;
|
||||
__rtl_dcmpeq_v1_00 = 0x2be4d;
|
||||
__rtl_dcmplt_v1_00 = 0x2bebd;
|
||||
__rtl_dcmpgt_v1_00 = 0x2bf51;
|
||||
__rtl_dcmple_v1_00 = 0x2c049;
|
||||
__rtl_fcmplt_v1_00 = 0x2c139;
|
||||
__rtl_fcmpgt_v1_00 = 0x2c195;
|
||||
__rtl_cos_f32_v1_00 = 0x2c229;
|
||||
__rtl_sin_f32_v1_00 = 0x2c435;
|
||||
__rtl_fabs_v1_00 = 0x2c639;
|
||||
__rtl_fabsf_v1_00 = 0x2c641;
|
||||
__rtl_dtoa_r_v1_00 = 0x2c77d;
|
||||
__rom_mallocr_init_v1_00 = 0x2d7d1;
|
||||
__rtl_free_r_v1_00 = 0x2d841;
|
||||
__rtl_malloc_r_v1_00 = 0x2da31;
|
||||
__rtl_realloc_r_v1_00 = 0x2df55;
|
||||
__rtl_memalign_r_v1_00 = 0x2e331;
|
||||
__rtl_valloc_r_v1_00 = 0x2e421;
|
||||
__rtl_pvalloc_r_v1_00 = 0x2e42d;
|
||||
__rtl_calloc_r_v1_00 = 0x2e441;
|
||||
__rtl_cfree_r_v1_00 = 0x2e4a9;
|
||||
__rtl_Balloc_v1_00 = 0x2e515;
|
||||
__rtl_Bfree_v1_00 = 0x2e571;
|
||||
__rtl_i2b_v1_00 = 0x2e585;
|
||||
__rtl_multadd_v1_00 = 0x2e599;
|
||||
__rtl_mult_v1_00 = 0x2e629;
|
||||
__rtl_pow5mult_v1_00 = 0x2e769;
|
||||
__rtl_hi0bits_v1_00 = 0x2e809;
|
||||
__rtl_d2b_v1_00 = 0x2e845;
|
||||
__rtl_lshift_v1_00 = 0x2e901;
|
||||
__rtl_cmp_v1_00 = 0x2e9bd;
|
||||
__rtl_diff_v1_00 = 0x2ea01;
|
||||
__rtl_sread_v1_00 = 0x2eae9;
|
||||
__rtl_seofread_v1_00 = 0x2eb39;
|
||||
__rtl_swrite_v1_00 = 0x2eb3d;
|
||||
__rtl_sseek_v1_00 = 0x2ebc1;
|
||||
__rtl_sclose_v1_00 = 0x2ec11;
|
||||
__rtl_sbrk_r_v1_00 = 0x2ec41;
|
||||
__rtl_fflush_r_v1_00 = 0x2ef8d;
|
||||
__rtl_vfprintf_r_v1_00 = 0x2f661;
|
||||
__rtl_fpclassifyd = 0x30c15;
|
||||
CpkClkTbl = 0x30c68;
|
||||
ROM_IMG1_VALID_PATTEN = 0x30c80;
|
||||
SpicCalibrationPattern = 0x30c88;
|
||||
SpicInitCPUCLK = 0x30c98;
|
||||
BAUDRATE = 0x30ca8;
|
||||
OVSR = 0x30d1c;
|
||||
DIV = 0x30d90;
|
||||
OVSR_ADJ = 0x30e04;
|
||||
__AES_rcon = 0x30e78;
|
||||
__AES_Te4 = 0x30ea0;
|
||||
I2CDmaChNo = 0x312a0;
|
||||
_GPIO_PinMap_Chip2IP_8195a = 0x312b4;
|
||||
_GPIO_PinMap_PullCtrl_8195a = 0x3136c;
|
||||
_GPIO_SWPORT_DDR_TBL = 0x31594;
|
||||
_GPIO_EXT_PORT_TBL = 0x31598;
|
||||
_GPIO_SWPORT_DR_TBL = 0x3159c;
|
||||
UartLogRomCmdTable = 0x316a0;
|
||||
_HalRuartOp = 0x31700;
|
||||
_HalGdmaOp = 0x31760;
|
||||
RTW_WPA_OUI_TYPE = 0x3540c;
|
||||
WPA_CIPHER_SUITE_NONE = 0x35410;
|
||||
WPA_CIPHER_SUITE_WEP40 = 0x35414;
|
||||
WPA_CIPHER_SUITE_TKIP = 0x35418;
|
||||
WPA_CIPHER_SUITE_CCMP = 0x3541c;
|
||||
WPA_CIPHER_SUITE_WEP104 = 0x35420;
|
||||
RSN_CIPHER_SUITE_NONE = 0x35424;
|
||||
RSN_CIPHER_SUITE_WEP40 = 0x35428;
|
||||
RSN_CIPHER_SUITE_TKIP = 0x3542c;
|
||||
RSN_CIPHER_SUITE_CCMP = 0x35430;
|
||||
RSN_CIPHER_SUITE_WEP104 = 0x35434;
|
||||
RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
|
||||
RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
|
||||
RSN_VERSION_BSD = 0x3544c;
|
||||
rom_wps_Te0 = 0x35988;
|
||||
rom_wps_rcons = 0x35d88;
|
||||
rom_wps_Td4s = 0x35d94;
|
||||
rom_wps_Td0 = 0x35e94;
|
||||
__rom_b_cut_end__ = 0x4467c;
|
||||
__rom_c_cut_text_start__ = 0x4467c;
|
||||
HalInitPlatformLogUartV02 = 0x4467d;
|
||||
HalReInitPlatformLogUartV02 = 0x4471d;
|
||||
HalInitPlatformTimerV02 = 0x44755;
|
||||
HalShowBuildInfoV02 = 0x447cd;
|
||||
SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
|
||||
HalSpiInitV02 = 0x4488d;
|
||||
HalBootFlowV02 = 0x44a29;
|
||||
HalInitialROMCodeGlobalVarV02 = 0x44ae5;
|
||||
HalResetVsrV02 = 0x44b41;
|
||||
HalI2CSendRtl8195aV02 = 0x44ce1;
|
||||
HalI2CSetCLKRtl8195aV02 = 0x44d59;
|
||||
RtkI2CSendV02 = 0x4508d;
|
||||
RtkI2CReceiveV02 = 0x459a1;
|
||||
HalI2COpInitV02 = 0x461ed;
|
||||
I2CISRHandleV02 = 0x463e9;
|
||||
RtkSalI2COpInitV02 = 0x46be1;
|
||||
SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
|
||||
SpiFlashAppV02 = 0x46c85;
|
||||
SpicInitRtl8195AV02 = 0x46dc5;
|
||||
SpicEraseFlashRtl8195AV02 = 0x46ea1;
|
||||
HalTimerIrq2To7HandleV02 = 0x46f5d;
|
||||
HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
|
||||
HalTimerInitRtl8195aV02 = 0x4706d;
|
||||
HalTimerReadCountRtl8195aV02 = 0x471b5;
|
||||
HalTimerReLoadRtl8195aV02 = 0x471d1;
|
||||
HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
|
||||
HalTimerDeInitRtl8195aV02 = 0x472c1;
|
||||
HalTimerOpInitV02 = 0x472f9;
|
||||
GPIO_LockV02 = 0x47345;
|
||||
GPIO_UnLockV02 = 0x47379;
|
||||
GPIO_Int_Clear_8195aV02 = 0x473a5;
|
||||
HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
|
||||
FindElementIndexV02 = 0x47541;
|
||||
HalRuartInitRtl8195aV02 = 0x4756d;
|
||||
DramInit_rom = 0x47619;
|
||||
ChangeRandSeed_rom = 0x47979;
|
||||
Sdr_Rand2_rom = 0x47985;
|
||||
MemTest_rom = 0x479dd;
|
||||
SdrCalibration_rom = 0x47a45;
|
||||
SdrControllerInit_rom = 0x47d99;
|
||||
SDIO_EnterCritical = 0x47e39;
|
||||
SDIO_ExitCritical = 0x47e85;
|
||||
SDIO_IRQ_Handler_Rom = 0x47ec5;
|
||||
SDIO_Interrupt_Init_Rom = 0x47f31;
|
||||
SDIO_Device_Init_Rom = 0x47f81;
|
||||
SDIO_Interrupt_DeInit_Rom = 0x48215;
|
||||
SDIO_Device_DeInit_Rom = 0x48255;
|
||||
SDIO_Enable_Interrupt_Rom = 0x48281;
|
||||
SDIO_Disable_Interrupt_Rom = 0x482a1;
|
||||
SDIO_Clear_ISR_Rom = 0x482c1;
|
||||
SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
|
||||
SDIO_Free_Rx_Pkt_Rom = 0x48331;
|
||||
SDIO_Recycle_Rx_BD_Rom = 0x48355;
|
||||
SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
|
||||
SDIO_RxTask_Rom = 0x4851d;
|
||||
SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
|
||||
SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
|
||||
SDIO_Process_RPWM_Rom = 0x485b5;
|
||||
SDIO_Reset_Cmd_Rom = 0x485e9;
|
||||
SDIO_Rx_Data_Transaction_Rom = 0x48611;
|
||||
SDIO_Send_C2H_PktMsg_Rom = 0x48829;
|
||||
SDIO_Register_Tx_Callback_Rom = 0x488f5;
|
||||
SDIO_ReadMem_Rom = 0x488fd;
|
||||
SDIO_WriteMem_Rom = 0x489a9;
|
||||
SDIO_SetMem_Rom = 0x48a69;
|
||||
SDIO_TX_Pkt_Handle_Rom = 0x48b29;
|
||||
SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
|
||||
SDIO_IRQ_Handler_BH_Rom = 0x48d95;
|
||||
SDIO_TxTask_Rom = 0x48e9d;
|
||||
SDIO_TaskUp_Rom = 0x48eed;
|
||||
SDIO_Boot_Up = 0x48f55;
|
||||
__rom_c_cut_text_end__ = 0x49070;
|
||||
__rom_c_cut_rodata_start__ = 0x49070;
|
||||
BAUDRATE_v02 = 0x49070;
|
||||
OVSR_v02 = 0x490fc;
|
||||
DIV_v02 = 0x49188;
|
||||
OVSR_ADJ_v02 = 0x49214;
|
||||
SdrDramInfo_rom = 0x492a0;
|
||||
SdrDramTiming_rom = 0x492b4;
|
||||
SdrDramModeReg_rom = 0x492e8;
|
||||
SdrDramDev_rom = 0x49304;
|
||||
__rom_c_cut_rodata_end__ = 0x49314;
|
||||
NewVectorTable = 0x10000000;
|
||||
UserIrqFunTable = 0x10000100;
|
||||
UserIrqDataTable = 0x10000200;
|
||||
__rom_bss_start__ = 0x10000300;
|
||||
CfgSysDebugWarn = 0x10000300;
|
||||
CfgSysDebugInfo = 0x10000304;
|
||||
CfgSysDebugErr = 0x10000308;
|
||||
ConfigDebugWarn = 0x1000030c;
|
||||
ConfigDebugInfo = 0x10000310;
|
||||
ConfigDebugErr = 0x10000314;
|
||||
HalTimerOp = 0x10000318;
|
||||
GPIOState = 0x10000334;
|
||||
gTimerRecord = 0x1000034c;
|
||||
SSI_DBG_CONFIG = 0x10000350;
|
||||
_pHAL_Gpio_Adapter = 0x10000354;
|
||||
Timer2To7VectorTable = 0x10000358;
|
||||
_rand_first = 0x10000370;
|
||||
_rand_z1 = 0x10000374;
|
||||
_rand_z2 = 0x10000378;
|
||||
_rand_z3 = 0x1000037C;
|
||||
_rand_z4 = 0x10000380;
|
||||
pUartLogCtl = 0x10000384;
|
||||
UartLogBuf = 0x10000388;
|
||||
UartLogCtl = 0x10000408;
|
||||
UartLogHistoryBuf = 0x10000430;
|
||||
ArgvArray = 0x100006ac;
|
||||
rom_wlan_ram_map = 0x100006d4;
|
||||
FalseAlmCnt = 0x100006e0;
|
||||
ROMInfo = 0x10000720;
|
||||
DM_CfoTrack = 0x10000738;
|
||||
rom_libgloss_ram_map = 0x10000760;
|
||||
__rtl_errno = 0x10000bc4;
|
||||
_rtl_impure_ptr = 0x10001c60;
|
||||
}
|
||||
|
|
@ -0,0 +1,739 @@
|
|||
SECTIONS
|
||||
{
|
||||
__vectors_table = 0x0;
|
||||
Reset_Handler = 0x101;
|
||||
NMI_Handler = 0x109;
|
||||
HardFault_Handler = 0x10d;
|
||||
MemManage_Handler = 0x121;
|
||||
BusFault_Handler = 0x125;
|
||||
UsageFault_Handler = 0x129;
|
||||
HalLogUartInit = 0x201;
|
||||
HalSerialPutcRtl8195a = 0x2d9;
|
||||
HalSerialGetcRtl8195a = 0x309;
|
||||
HalSerialGetIsrEnRegRtl8195a = 0x329;
|
||||
HalSerialSetIrqEnRegRtl8195a = 0x335;
|
||||
HalCpuClkConfig = 0x341;
|
||||
HalGetCpuClk = 0x355;
|
||||
HalRomInfo = 0x39d;
|
||||
HalGetRomInfo = 0x3b5;
|
||||
HalResetVsr = 0x3c5;
|
||||
HalDelayUs = 0x899;
|
||||
HalNMIHandler = 0x8e1;
|
||||
HalHardFaultHandler = 0x911;
|
||||
HalMemManageHandler = 0xc09;
|
||||
HalBusFaultHandler = 0xc39;
|
||||
HalUsageFaultHandler = 0xc69;
|
||||
HalUart0PinCtrlRtl8195A = 0xcfd;
|
||||
HalUart1PinCtrlRtl8195A = 0xdc9;
|
||||
HalUart2PinCtrlRtl8195A = 0xe9d;
|
||||
HalSPI0PinCtrlRtl8195A = 0xf75;
|
||||
HalSPI1PinCtrlRtl8195A = 0x1015;
|
||||
HalSPI2PinCtrlRtl8195A = 0x10e5;
|
||||
HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
|
||||
HalI2C0PinCtrlRtl8195A = 0x1275;
|
||||
HalI2C1PinCtrlRtl8195A = 0x1381;
|
||||
HalI2C2PinCtrlRtl8195A = 0x1459;
|
||||
HalI2C3PinCtrlRtl8195A = 0x1529;
|
||||
HalI2S0PinCtrlRtl8195A = 0x1639;
|
||||
HalI2S1PinCtrlRtl8195A = 0x176d;
|
||||
HalPCM0PinCtrlRtl8195A = 0x1845;
|
||||
HalPCM1PinCtrlRtl8195A = 0x1949;
|
||||
HalSDIODPinCtrlRtl8195A = 0x1a1d;
|
||||
HalSDIOHPinCtrlRtl8195A = 0x1a6d;
|
||||
HalMIIPinCtrlRtl8195A = 0x1ab9;
|
||||
HalWLLEDPinCtrlRtl8195A = 0x1b51;
|
||||
HalWLANT0PinCtrlRtl8195A = 0x1c0d;
|
||||
HalWLANT1PinCtrlRtl8195A = 0x1c61;
|
||||
HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
|
||||
HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
|
||||
HalNFCPinCtrlRtl8195A = 0x1d59;
|
||||
HalPWM0PinCtrlRtl8195A = 0x1da9;
|
||||
HalPWM1PinCtrlRtl8195A = 0x1ead;
|
||||
HalPWM2PinCtrlRtl8195A = 0x1fb5;
|
||||
HalPWM3PinCtrlRtl8195A = 0x20b1;
|
||||
HalETE0PinCtrlRtl8195A = 0x21b9;
|
||||
HalETE1PinCtrlRtl8195A = 0x22c1;
|
||||
HalETE2PinCtrlRtl8195A = 0x23c9;
|
||||
HalETE3PinCtrlRtl8195A = 0x24d1;
|
||||
HalEGTIMPinCtrlRtl8195A = 0x25d9;
|
||||
HalSPIFlashPinCtrlRtl8195A = 0x2679;
|
||||
HalSDRPinCtrlRtl8195A = 0x2725;
|
||||
HalJTAGPinCtrlRtl8195A = 0x280d;
|
||||
HalTRACEPinCtrlRtl8195A = 0x2861;
|
||||
HalLOGUartPinCtrlRtl8195A = 0x28b9;
|
||||
HalLOGUartIRPinCtrlRtl8195A = 0x291d;
|
||||
HalSICPinCtrlRtl8195A = 0x2981;
|
||||
HalEEPROMPinCtrlRtl8195A = 0x29d9;
|
||||
HalDEBUGPinCtrlRtl8195A = 0x2a31;
|
||||
HalPinCtrlRtl8195A = 0x2b39;
|
||||
SpicRxCmdRtl8195A = 0x2e5d;
|
||||
SpicWaitBusyDoneRtl8195A = 0x2ea5;
|
||||
SpicGetFlashStatusRtl8195A = 0x2eb5;
|
||||
SpicWaitWipDoneRtl8195A = 0x2f55;
|
||||
SpicTxCmdRtl8195A = 0x2f6d;
|
||||
SpicSetFlashStatusRtl8195A = 0x2fc1;
|
||||
SpicCmpDataForCalibrationRtl8195A = 0x3049;
|
||||
SpicLoadInitParaFromClockRtl8195A = 0x3081;
|
||||
SpicInitRtl8195A = 0x30e5;
|
||||
SpicEraseFlashRtl8195A = 0x31bd;
|
||||
SpiFlashApp = 0x3279;
|
||||
HalPeripheralIntrHandle = 0x33b5;
|
||||
HalSysOnIntrHandle = 0x3439;
|
||||
HalWdgIntrHandle = 0x3485;
|
||||
HalTimer0IntrHandle = 0x34d5;
|
||||
HalTimer1IntrHandle = 0x3525;
|
||||
HalI2C3IntrHandle = 0x3575;
|
||||
HalTimer2To7IntrHandle = 0x35c5;
|
||||
HalSpi0IntrHandle = 0x3615;
|
||||
HalGpioIntrHandle = 0x3665;
|
||||
HalUart0IntrHandle = 0x36b5;
|
||||
HalSpiFlashIntrHandle = 0x3705;
|
||||
HalUsbOtgIntrHandle = 0x3755;
|
||||
HalSdioHostIntrHandle = 0x37a5;
|
||||
HalI2s0OrPcm0IntrHandle = 0x37f5;
|
||||
HalI2s1OrPcm1IntrHandle = 0x3845;
|
||||
HalWlDmaIntrHandle = 0x3895;
|
||||
HalWlProtocolIntrHandle = 0x38e5;
|
||||
HalCryptoIntrHandle = 0x3935;
|
||||
HalGmacIntrHandle = 0x3985;
|
||||
HalGdma0Ch0IntrHandle = 0x39d5;
|
||||
HalGdma0Ch1IntrHandle = 0x3a25;
|
||||
HalGdma0Ch2IntrHandle = 0x3a75;
|
||||
HalGdma0Ch3IntrHandle = 0x3ac5;
|
||||
HalGdma0Ch4IntrHandle = 0x3b15;
|
||||
HalGdma0Ch5IntrHandle = 0x3b65;
|
||||
HalGdma1Ch0IntrHandle = 0x3bb5;
|
||||
HalGdma1Ch1IntrHandle = 0x3c05;
|
||||
HalGdma1Ch2IntrHandle = 0x3c55;
|
||||
HalGdma1Ch3IntrHandle = 0x3ca5;
|
||||
HalGdma1Ch4IntrHandle = 0x3cf5;
|
||||
HalGdma1Ch5IntrHandle = 0x3d45;
|
||||
HalSdioDeviceIntrHandle = 0x3d95;
|
||||
VectorTableInitRtl8195A = 0x3de5;
|
||||
txt0123456789ABCDEF = 0x3ec24;
|
||||
VectorTableInitForOSRtl8195A = 0x4019;
|
||||
VectorIrqRegisterRtl8195A = 0x4029;
|
||||
VectorIrqUnRegisterRtl8195A = 0x4091;
|
||||
VectorIrqEnRtl8195A = 0x40f1;
|
||||
VectorIrqDisRtl8195A = 0x418d;
|
||||
_UartRxDmaIrqHandle = 0x422d;
|
||||
HalRuartPutCRtl8195a = 0x4281;
|
||||
HalRuartGetCRtl8195a = 0x429d;
|
||||
HalRuartRTSCtrlRtl8195a = 0x42bd;
|
||||
HalRuartGetDebugValueRtl8195a = 0x42e1;
|
||||
HalRuartGetIMRRtl8195a = 0x43e1;
|
||||
HalRuartSetIMRRtl8195a = 0x442d;
|
||||
_UartIrqHandle = 0x4465;
|
||||
HalRuartDmaInitRtl8195a = 0x4681;
|
||||
HalRuartIntDisableRtl8195a = 0x4845;
|
||||
HalRuartDeInitRtl8195a = 0x4855;
|
||||
HalRuartIntEnableRtl8195a = 0x4985;
|
||||
_UartTxDmaIrqHandle = 0x4995;
|
||||
HalRuartRegIrqRtl8195a = 0x49d1;
|
||||
HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
|
||||
HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
|
||||
HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
|
||||
RuartLock = 0x4cc9;
|
||||
RuartUnLock = 0x4ced;
|
||||
HalRuartIntSendRtl8195a = 0x4d09;
|
||||
HalRuartDmaSendRtl8195a = 0x4e35;
|
||||
HalRuartStopSendRtl8195a = 0x4f89;
|
||||
HalRuartIntRecvRtl8195a = 0x504d;
|
||||
HalRuartDmaRecvRtl8195a = 0x51ad;
|
||||
HalRuartStopRecvRtl8195a = 0x52cd;
|
||||
RuartIsTimeout = 0x5385;
|
||||
HalRuartSendRtl8195a = 0x53b1;
|
||||
HalRuartRecvRtl8195a = 0x5599;
|
||||
RuartResetRxFifoRtl8195a = 0x5751;
|
||||
HalRuartResetRxFifoRtl8195a = 0x5775;
|
||||
HalRuartInitRtl8195a = 0x5829;
|
||||
HalGdmaOnOffRtl8195a = 0x5df1;
|
||||
HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
|
||||
HalGdmaChEnRtl8195a = 0x5e51;
|
||||
HalGdmaChDisRtl8195a = 0x5e6d;
|
||||
HalGdamChInitRtl8195a = 0x5e91;
|
||||
HalGdmaChSetingRtl8195a = 0x5ebd;
|
||||
HalGdmaChBlockSetingRtl8195a = 0x000060dd;
|
||||
HalGdmaChIsrCleanRtl8195a = 0x6419;
|
||||
HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
|
||||
HalGdmaChCleanAutoDstRtl8195a = 0x6501;
|
||||
HalEFUSEPowerSwitch8195AROM = 0x6561;
|
||||
HALEFUSEOneByteReadROM = 0x65f9;
|
||||
HALEFUSEOneByteWriteROM = 0x6699;
|
||||
__rtl_memcmpb_v1_00 = 0x681d;
|
||||
__rtl_random_v1_00 = 0x6861;
|
||||
__rtl_align_to_be32_v1_00 = 0x6881;
|
||||
__rtl_memsetw_v1_00 = 0x6899;
|
||||
__rtl_memsetb_v1_00 = 0x68ad;
|
||||
__rtl_memcpyw_v1_00 = 0x68bd;
|
||||
__rtl_memcpyb_v1_00 = 0x68dd;
|
||||
__rtl_memDump_v1_00 = 0x68f5;
|
||||
__rtl_AES_set_encrypt_key = 0x6901;
|
||||
__rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
|
||||
__rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
|
||||
__rtl_cryptoEngine_init_v1_00 = 0x6ea9;
|
||||
__rtl_cryptoEngine_exit_v1_00 = 0x7055;
|
||||
__rtl_cryptoEngine_reset_v1_00 = 0x70b1;
|
||||
__rtl_cryptoEngine_v1_00 = 0x70ed;
|
||||
__rtl_crypto_cipher_init_v1_00 = 0x7c69;
|
||||
__rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
|
||||
__rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
|
||||
HalSsiPinmuxEnableRtl8195a = 0x7cd5;
|
||||
HalSsiEnableRtl8195a = 0x7e45;
|
||||
HalSsiDisableRtl8195a = 0x7ef9;
|
||||
HalSsiLoadSettingRtl8195a = 0x7fad;
|
||||
HalSsiSetInterruptMaskRtl8195a = 0x8521;
|
||||
HalSsiGetInterruptMaskRtl8195a = 0x85c9;
|
||||
HalSsiSetSclkPolarityRtl8195a = 0x863d;
|
||||
HalSsiSetSclkPhaseRtl8195a = 0x8715;
|
||||
HalSsiWriteRtl8195a = 0x87e9;
|
||||
HalSsiSetDeviceRoleRtl8195a = 0x8861;
|
||||
HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
|
||||
HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
|
||||
HalSsiReadRtl8195a = 0x89b9;
|
||||
HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
|
||||
HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
|
||||
HalSsiGetStatusRtl8195a = 0x8b1d;
|
||||
HalSsiWriteableRtl8195a = 0x8b91;
|
||||
HalSsiReadableRtl8195a = 0x8c09;
|
||||
HalSsiBusyRtl8195a = 0x8c81;
|
||||
HalSsiReadInterruptRtl8195a = 0x8cf9;
|
||||
HalSsiWriteInterruptRtl8195a = 0x8efd;
|
||||
HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
|
||||
HalSsiGetInterruptStatusRtl8195a = 0x90d9;
|
||||
HalSsiInterruptEnableRtl8195a = 0x914d;
|
||||
HalSsiInterruptDisableRtl8195a = 0x9299;
|
||||
HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
|
||||
HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
|
||||
HalSsiInitRtl8195a = 0x94d1;
|
||||
_SsiReadInterrupt = 0x9ba5;
|
||||
_SsiWriteInterrupt = 0x9db1;
|
||||
_SsiIrqHandle = 0x9eb1;
|
||||
HalI2CWrite32 = 0xa061;
|
||||
HalI2CRead32 = 0xa09d;
|
||||
HalI2CDeInit8195a = 0xa0dd;
|
||||
HalI2CSendRtl8195a = 0xa1f1;
|
||||
HalI2CReceiveRtl8195a = 0xa25d;
|
||||
HalI2CEnableRtl8195a = 0xa271;
|
||||
HalI2CIntrCtrl8195a = 0xa389;
|
||||
HalI2CReadRegRtl8195a = 0xa3a1;
|
||||
HalI2CWriteRegRtl8195a = 0xa3b1;
|
||||
HalI2CSetCLKRtl8195a = 0xa3c5;
|
||||
HalI2CMassSendRtl8195a = 0xa6e9;
|
||||
HalI2CClrIntrRtl8195a = 0xa749;
|
||||
HalI2CClrAllIntrRtl8195a = 0xa761;
|
||||
HalI2CInit8195a = 0xa775;
|
||||
HalI2CDMACtrl8195a = 0xaa31;
|
||||
RtkI2CIoCtrl = 0xaa61;
|
||||
RtkI2CPowerCtrl = 0xaa65;
|
||||
HalI2COpInit = 0xaa69;
|
||||
I2CIsTimeout = 0xac65;
|
||||
I2CTXGDMAISRHandle = 0xb435;
|
||||
I2CRXGDMAISRHandle = 0xb4c1;
|
||||
RtkI2CIrqInit = 0xb54d;
|
||||
RtkI2CIrqDeInit = 0xb611;
|
||||
RtkI2CPinMuxInit = 0xb675;
|
||||
RtkI2CPinMuxDeInit = 0xb7c9;
|
||||
RtkI2CDMAInit = 0xb955;
|
||||
RtkI2CInit = 0xbc95;
|
||||
RtkI2CDMADeInit = 0xbdad;
|
||||
RtkI2CDeInit = 0xbe4d;
|
||||
RtkI2CSendUserAddr = 0xbee5;
|
||||
RtkI2CSend = 0xc07d;
|
||||
_RtkI2CReceive = 0x0c6dd;
|
||||
RtkI2CLoadDefault = 0xce51;
|
||||
RtkSalI2COpInit = 0xcf21;
|
||||
HalI2SWrite32 = 0xcf65;
|
||||
HalI2SRead32 = 0xcf85;
|
||||
HalI2SDeInitRtl8195a = 0xcfa9;
|
||||
HalI2STxRtl8195a = 0xcfc9;
|
||||
HalI2SRxRtl8195a = 0xd011;
|
||||
HalI2SEnableRtl8195a = 0xd05d;
|
||||
HalI2SIntrCtrlRtl8195a = 0xd0b1;
|
||||
HalI2SReadRegRtl8195a = 0xd0d1;
|
||||
HalI2SClrIntrRtl8195a = 0xd0dd;
|
||||
HalI2SClrAllIntrRtl8195a = 0xd0fd;
|
||||
HalI2SInitRtl8195a = 0xd11d;
|
||||
GPIO_GetIPPinName_8195a = 0xd2e5;
|
||||
GPIO_GetChipPinName_8195a = 0xd331;
|
||||
GPIO_PullCtrl_8195a = 0xd39d;
|
||||
GPIO_FuncOn_8195a = 0xd421;
|
||||
GPIO_FuncOff_8195a = 0xd481;
|
||||
GPIO_Int_Mask_8195a = 0xd4e9;
|
||||
GPIO_Int_SetType_8195a = 0xd511;
|
||||
HAL_GPIO_IrqHandler_8195a = 0xd5fd;
|
||||
HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
|
||||
HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
|
||||
HAL_GPIO_IntCtrl_8195a = 0xd6cd;
|
||||
HAL_GPIO_Init_8195a = 0xd805;
|
||||
HAL_GPIO_DeInit_8195a = 0xdac1;
|
||||
HAL_GPIO_ReadPin_8195a = 0xdbd1;
|
||||
HAL_GPIO_WritePin_8195a = 0xdc91;
|
||||
HAL_GPIO_RegIrq_8195a = 0xddad;
|
||||
HAL_GPIO_UnRegIrq_8195a = 0xddf5;
|
||||
HAL_GPIO_UserRegIrq_8195a = 0xde15;
|
||||
HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
|
||||
HAL_GPIO_MaskIrq_8195a = 0xdfc1;
|
||||
HAL_GPIO_UnMaskIrq_8195a = 0xe061;
|
||||
HAL_GPIO_IntDebounce_8195a = 0xe101;
|
||||
HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
|
||||
HAL_GPIO_PullCtrl_8195a = 0xe1c9;
|
||||
DumpForOneBytes = 0xe259;
|
||||
CmdRomHelp = 0xe419;
|
||||
CmdWriteWord = 0xe491;
|
||||
CmdDumpHelfWord = 0xe505;
|
||||
CmdDumpWord = 0xe5f1;
|
||||
CmdDumpByte = 0xe6f5;
|
||||
CmdSpiFlashTool = 0xe751;
|
||||
GetRomCmdNum = 0xe7a9;
|
||||
CmdWriteByte = 0xe7ad;
|
||||
Isspace = 0xe7ed;
|
||||
Strtoul = 0xe801;
|
||||
ArrayInitialize = 0xe8b1;
|
||||
GetArgc = 0xe8c9;
|
||||
GetArgv = 0xe8f9;
|
||||
UartLogCmdExecute = 0xe95d;
|
||||
UartLogShowBackSpace = 0xe9fd;
|
||||
UartLogRecallOldCmd = 0xea39;
|
||||
UartLogHistoryCmd = 0xea71;
|
||||
UartLogCmdChk = 0xeadd;
|
||||
UartLogIrqHandle = 0xebf5;
|
||||
RtlConsolInit = 0xecc5;
|
||||
RtlConsolTaskRom = 0xed49;
|
||||
RtlExitConsol = 0xed79;
|
||||
RtlConsolRom = 0xedcd;
|
||||
HalTimerOpInit = 0xee0d;
|
||||
HalTimerIrq2To7Handle = 0xee59;
|
||||
HalGetTimerIdRtl8195a = 0xef09;
|
||||
HalTimerInitRtl8195a = 0xef3d;
|
||||
HalTimerDisRtl8195a = 0xf069; /* error! */
|
||||
HalTimerEnRtl8195a = 0xf089; /* error! */
|
||||
HalTimerReadCountRtl8195a = 0xf0a9;
|
||||
HalTimerIrqClearRtl8195a = 0xf0bd;
|
||||
HalTimerDumpRegRtl8195a = 0xf0d1;
|
||||
VSprintf = 0xf129;
|
||||
DiagPrintf = 0xf39d;
|
||||
DiagSPrintf = 0xf3b9;
|
||||
DiagSnPrintf = 0xf3d1;
|
||||
prvDiagPrintf = 0xf3ed;
|
||||
prvDiagSPrintf = 0xf40d;
|
||||
_memcmp = 0xf429;
|
||||
_memcpy = 0xf465;
|
||||
_memset = 0xf511;
|
||||
Rand = 0xf585;
|
||||
_strncpy = 0xf60d;
|
||||
_strcpy = 0xf629;
|
||||
prvStrCpy = 0xf639;
|
||||
_strlen = 0xf651;
|
||||
_strnlen = 0xf669;
|
||||
prvStrLen = 0xf699;
|
||||
_strcmp = 0xf6b1;
|
||||
_strncmp = 0xf6d1;
|
||||
prvStrCmp = 0xf719;
|
||||
StrUpr = 0xf749;
|
||||
prvAtoi = 0xf769;
|
||||
prvStrStr = 0xf7bd;
|
||||
_strsep = 0xf7d5;
|
||||
skip_spaces = 0xf815;
|
||||
skip_atoi = 0xf831;
|
||||
_parse_integer_fixup_radix = 0xf869;
|
||||
_parse_integer = 0xf8bd;
|
||||
simple_strtoull = 0xf915;
|
||||
simple_strtoll = 0xf945;
|
||||
simple_strtoul = 0xf965;
|
||||
simple_strtol = 0xf96d;
|
||||
_vsscanf = 0xf985;
|
||||
_sscanf = 0xff71;
|
||||
div_u64 = 0xff91;
|
||||
div_s64 = 0xff99;
|
||||
div_u64_rem = 0xffa1;
|
||||
div_s64_rem = 0xffb1;
|
||||
_strpbrk = 0xffc1;
|
||||
_strchr = 0xffed;
|
||||
aes_set_key = 0x10005;
|
||||
aes_encrypt = 0x103d1;
|
||||
aes_decrypt = 0x114a5;
|
||||
AES_WRAP = 0x125c9;
|
||||
AES_UnWRAP = 0x12701;
|
||||
crc32_get = 0x12861;
|
||||
arc4_byte = 0x12895;
|
||||
rt_arc4_init = 0x128bd;
|
||||
rt_arc4_crypt = 0x12901;
|
||||
rt_md5_init = 0x131c1;
|
||||
rt_md5_append = 0x131f5;
|
||||
rt_md5_final = 0x1327d;
|
||||
rt_md5_hmac = 0x132d5;
|
||||
rtw_get_bit_value_from_ieee_value = 0x13449;
|
||||
rtw_is_cckrates_included = 0x13475;
|
||||
rtw_is_cckratesonly_included = 0x134b5;
|
||||
rtw_check_network_type = 0x134dd;
|
||||
rtw_set_fixed_ie = 0x1350d;
|
||||
rtw_set_ie = 0x1352d;
|
||||
rtw_get_ie = 0x1355d;
|
||||
rtw_set_supported_rate = 0x13591;
|
||||
rtw_get_rateset_len = 0x13611;
|
||||
rtw_get_wpa_ie = 0x1362d;
|
||||
rtw_get_wpa2_ie = 0x136c9;
|
||||
rtw_get_wpa_cipher_suite = 0x13701;
|
||||
rtw_get_wpa2_cipher_suite = 0x13769;
|
||||
rtw_parse_wpa_ie = 0x137d1;
|
||||
rtw_parse_wpa2_ie = 0x138ad;
|
||||
rtw_get_sec_ie = 0x13965;
|
||||
rtw_get_wps_ie = 0x13a15;
|
||||
rtw_get_wps_attr = 0x13a99;
|
||||
rtw_get_wps_attr_content = 0x13b49;
|
||||
rtw_ieee802_11_parse_elems = 0x13b91;
|
||||
str_2char2num = 0x13d9d;
|
||||
key_2char2num = 0x13db9;
|
||||
convert_ip_addr = 0x13dd1;
|
||||
rom_psk_PasswordHash = 0x13e9d;
|
||||
rom_psk_CalcGTK = 0x13ed5;
|
||||
rom_psk_CalcPTK = 0x13f69;
|
||||
wep_80211_encrypt = 0x14295;
|
||||
wep_80211_decrypt = 0x142f5;
|
||||
tkip_micappendbyte = 0x14389;
|
||||
rtw_secmicsetkey = 0x143d9;
|
||||
rtw_secmicappend = 0x14419;
|
||||
rtw_secgetmic = 0x14435;
|
||||
rtw_seccalctkipmic = 0x1449d;
|
||||
tkip_phase1 = 0x145a5;
|
||||
tkip_phase2 = 0x14725;
|
||||
tkip_80211_encrypt = 0x14941;
|
||||
tkip_80211_decrypt = 0x149d5;
|
||||
aes1_encrypt = 0x14a8d;
|
||||
aesccmp_construct_mic_iv = 0x14c65;
|
||||
aesccmp_construct_mic_header1 = 0x14ccd;
|
||||
aesccmp_construct_mic_header2 = 0x14d21;
|
||||
aesccmp_construct_ctr_preload = 0x14db5;
|
||||
aes_80211_encrypt = 0x14e29;
|
||||
aes_80211_decrypt = 0x151ad;
|
||||
_sha1_process_message_block = 0x155b9;
|
||||
_sha1_pad_message = 0x15749;
|
||||
rt_sha1_init = 0x157e5;
|
||||
rt_sha1_update = 0x15831;
|
||||
rt_sha1_finish = 0x158a9;
|
||||
rt_hmac_sha1 = 0x15909;
|
||||
rom_aes_128_cbc_encrypt = 0x15a65;
|
||||
rom_aes_128_cbc_decrypt = 0x15ae1;
|
||||
rom_rijndaelKeySetupEnc = 0x15b5d;
|
||||
rom_aes_decrypt_init = 0x15c39;
|
||||
rom_aes_internal_decrypt = 0x15d15;
|
||||
rom_aes_decrypt_deinit = 0x16071;
|
||||
rom_aes_encrypt_init = 0x16085;
|
||||
rom_aes_internal_encrypt = 0x1609d;
|
||||
rom_aes_encrypt_deinit = 0x16451;
|
||||
bignum_init = 0x17b35;
|
||||
bignum_deinit = 0x17b61;
|
||||
bignum_get_unsigned_bin_len = 0x17b81;
|
||||
bignum_get_unsigned_bin = 0x17b85;
|
||||
bignum_set_unsigned_bin = 0x17c21;
|
||||
bignum_cmp = 0x17cd1;
|
||||
bignum_cmp_d = 0x17cd5;
|
||||
bignum_add = 0x17cfd;
|
||||
bignum_sub = 0x17d0d;
|
||||
bignum_mul = 0x17d1d;
|
||||
bignum_exptmod = 0x17d2d;
|
||||
WPS_realloc = 0x17d51;
|
||||
os_zalloc = 0x17d99;
|
||||
rom_hmac_sha256_vector = 0x17dc1;
|
||||
rom_hmac_sha256 = 0x17ebd;
|
||||
rom_sha256_vector = 0x18009;
|
||||
phy_CalculateBitShift = 0x18221;
|
||||
PHY_SetBBReg_8195A = 0x18239;
|
||||
PHY_QueryBBReg_8195A = 0x18279;
|
||||
ROM_odm_QueryRxPwrPercentage = 0x1829d;
|
||||
ROM_odm_EVMdbToPercentage = 0x182bd;
|
||||
ROM_odm_SignalScaleMapping_8195A = 0x182e5;
|
||||
ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
|
||||
ROM_odm_SetEDCCAThreshold = 0x18721;
|
||||
ROM_odm_SetTRxMux = 0x18749;
|
||||
ROM_odm_SetCrystalCap = 0x18771;
|
||||
ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
|
||||
ROM_ODM_CfoTrackingReset = 0x187e9;
|
||||
ROM_odm_CfoTrackingFlow = 0x18811;
|
||||
curve25519_donna = 0x1965d;
|
||||
aes_test_alignment_detection = 0x1a391;
|
||||
aes_mode_reset = 0x1a3ed;
|
||||
aes_ecb_encrypt = 0x1a3f9;
|
||||
aes_ecb_decrypt = 0x1a431;
|
||||
aes_cbc_encrypt = 0x1a469;
|
||||
aes_cbc_decrypt = 0x1a579;
|
||||
aes_cfb_encrypt = 0x1a701;
|
||||
aes_cfb_decrypt = 0x1a9e5;
|
||||
aes_ofb_crypt = 0x1acc9;
|
||||
aes_ctr_crypt = 0x1af7d;
|
||||
aes_encrypt_key128 = 0x1b289;
|
||||
aes_encrypt_key192 = 0x1b2a5;
|
||||
aes_encrypt_key256 = 0x1b2c1;
|
||||
aes_encrypt_key = 0x1b2e1;
|
||||
aes_decrypt_key128 = 0x1b351;
|
||||
aes_decrypt_key192 = 0x1b36d;
|
||||
aes_decrypt_key256 = 0x1b389;
|
||||
aes_decrypt_key = 0x1b3a9;
|
||||
aes_init = 0x1b419;
|
||||
CRYPTO_chacha_20 = 0x1b41d;
|
||||
CRYPTO_poly1305_init = 0x1bc25;
|
||||
CRYPTO_poly1305_update = 0x1bd09;
|
||||
CRYPTO_poly1305_finish = 0x1bd8d;
|
||||
rom_sha512_starts = 0x1ceb5;
|
||||
rom_sha512_update = 0x1d009;
|
||||
rom_sha512_finish = 0x1d011;
|
||||
rom_sha512 = 0x1d261;
|
||||
rom_sha512_hmac_starts = 0x1d299;
|
||||
rom_sha512_hmac_update = 0x1d35d;
|
||||
rom_sha512_hmac_finish = 0x1d365;
|
||||
rom_sha512_hmac_reset = 0x1d3b5;
|
||||
rom_sha512_hmac = 0x1d3d1;
|
||||
rom_sha512_hkdf = 0x1d40d;
|
||||
rom_ed25519_gen_keypair = 0x1d501;
|
||||
rom_ed25519_gen_signature = 0x1d505;
|
||||
rom_ed25519_verify_signature = 0x1d51d;
|
||||
rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
|
||||
rom_ed25519_crypto_sign_detached = 0x1d579;
|
||||
rom_ed25519_crypto_sign_verify_detached = 0x1d655;
|
||||
rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
|
||||
rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
|
||||
rom_ed25519_ge_p3_tobytes = 0x207d5;
|
||||
rom_ed25519_ge_scalarmult_base = 0x20821;
|
||||
rom_ed25519_ge_tobytes = 0x209e1;
|
||||
rom_ed25519_sc_muladd = 0x20a2d;
|
||||
rom_ed25519_sc_reduce = 0x2603d;
|
||||
__rtl_memchr_v1_00 = 0x28a4d;
|
||||
__rtl_memcmp_v1_00 = 0x28ae1;
|
||||
__rtl_memcpy_v1_00 = 0x28b49;
|
||||
__aeabi_memcpy = 0x28b49;
|
||||
__aeabi_memcpy4 = 0x28b49;
|
||||
__rtl_memmove_v1_00 = 0x28bed;
|
||||
__rtl_memset_v1_00 = 0x28cb5;
|
||||
__aeabi_memset = 0x28cb5;
|
||||
__rtl_strcat_v1_00 = 0x28d49;
|
||||
__rtl_strchr_v1_00 = 0x28d91;
|
||||
__rtl_strcmp_v1_00 = 0x28e55;
|
||||
__rtl_strcpy_v1_00 = 0x28ec9;
|
||||
__rtl_strlen_v1_00 = 0x28f15;
|
||||
__rtl_strncat_v1_00 = 0x28f69;
|
||||
__rtl_strncmp_v1_00 = 0x28fc5;
|
||||
__rtl_strncpy_v1_00 = 0x2907d;
|
||||
__rtl_strstr_v1_00 = 0x293cd;
|
||||
__rtl_strsep_v1_00 = 0x2960d;
|
||||
__rtl_strtok_v1_00 = 0x29619;
|
||||
__rtl__strtok_r_v1_00 = 0x2962d;
|
||||
__rtl_strtok_r_v1_00 = 0x29691;
|
||||
__rtl_close_v1_00 = 0x29699;
|
||||
__rtl_fstat_v1_00 = 0x296ad;
|
||||
__rtl_isatty_v1_00 = 0x296c1;
|
||||
__rtl_lseek_v1_00 = 0x296d5;
|
||||
__rtl_open_v1_00 = 0x296e9;
|
||||
__rtl_read_v1_00 = 0x296fd;
|
||||
__rtl_write_v1_00 = 0x29711;
|
||||
__rtl_sbrk_v1_00 = 0x29725;
|
||||
__rtl_ltoa_v1_00 = 0x297bd;
|
||||
__rtl_ultoa_v1_00 = 0x29855;
|
||||
__rtl_dtoi_v1_00 = 0x298c5;
|
||||
__rtl_dtoi64_v1_00 = 0x29945;
|
||||
__rtl_dtoui_v1_00 = 0x299dd;
|
||||
__rtl_ftol_v1_00 = 0x299e5;
|
||||
__rtl_itof_v1_00 = 0x29a51;
|
||||
__rtl_itod_v1_00 = 0x29ae9;
|
||||
__rtl_i64tod_v1_00 = 0x29b79;
|
||||
__rtl_uitod_v1_00 = 0x29c55;
|
||||
__rtl_ftod_v1_00 = 0x29d2d;
|
||||
__rtl_dtof_v1_00 = 0x29de9;
|
||||
__rtl_uitof_v1_00 = 0x29e89;
|
||||
__rtl_fadd_v1_00 = 0x29f65;
|
||||
__rtl_fsub_v1_00 = 0x2a261;
|
||||
__rtl_fmul_v1_00 = 0x2a559;
|
||||
__rtl_fdiv_v1_00 = 0x2a695;
|
||||
__rtl_dadd_v1_00 = 0x2a825;
|
||||
__rtl_dsub_v1_00 = 0x2aed9;
|
||||
__rtl_dmul_v1_00 = 0x2b555;
|
||||
__rtl_ddiv_v1_00 = 0x2b8ad;
|
||||
__rtl_dcmpeq_v1_00 = 0x2be4d;
|
||||
__rtl_dcmplt_v1_00 = 0x2bebd;
|
||||
__rtl_dcmpgt_v1_00 = 0x2bf51;
|
||||
__rtl_dcmple_v1_00 = 0x2c049;
|
||||
__rtl_fcmplt_v1_00 = 0x2c139;
|
||||
__rtl_fcmpgt_v1_00 = 0x2c195;
|
||||
__rtl_cos_f32_v1_00 = 0x2c229;
|
||||
__rtl_sin_f32_v1_00 = 0x2c435;
|
||||
__rtl_fabs_v1_00 = 0x2c639;
|
||||
__rtl_fabsf_v1_00 = 0x2c641;
|
||||
__rtl_dtoa_r_v1_00 = 0x2c77d;
|
||||
__rom_mallocr_init_v1_00 = 0x2d7d1;
|
||||
__rtl_free_r_v1_00 = 0x2d841;
|
||||
__rtl_malloc_r_v1_00 = 0x2da31;
|
||||
__rtl_realloc_r_v1_00 = 0x2df55;
|
||||
__rtl_memalign_r_v1_00 = 0x2e331;
|
||||
__rtl_valloc_r_v1_00 = 0x2e421;
|
||||
__rtl_pvalloc_r_v1_00 = 0x2e42d;
|
||||
__rtl_calloc_r_v1_00 = 0x2e441;
|
||||
__rtl_cfree_r_v1_00 = 0x2e4a9;
|
||||
__rtl_Balloc_v1_00 = 0x2e515;
|
||||
__rtl_Bfree_v1_00 = 0x2e571;
|
||||
__rtl_i2b_v1_00 = 0x2e585;
|
||||
__rtl_multadd_v1_00 = 0x2e599;
|
||||
__rtl_mult_v1_00 = 0x2e629;
|
||||
__rtl_pow5mult_v1_00 = 0x2e769;
|
||||
__rtl_hi0bits_v1_00 = 0x2e809;
|
||||
__rtl_d2b_v1_00 = 0x2e845;
|
||||
__rtl_lshift_v1_00 = 0x2e901;
|
||||
__rtl_cmp_v1_00 = 0x2e9bd;
|
||||
__rtl_diff_v1_00 = 0x2ea01;
|
||||
__rtl_sread_v1_00 = 0x2eae9;
|
||||
__rtl_seofread_v1_00 = 0x2eb39;
|
||||
__rtl_swrite_v1_00 = 0x2eb3d;
|
||||
__rtl_sseek_v1_00 = 0x2ebc1;
|
||||
__rtl_sclose_v1_00 = 0x2ec11;
|
||||
__rtl_sbrk_r_v1_00 = 0x2ec41;
|
||||
__rtl_fflush_r_v1_00 = 0x2ef8d;
|
||||
__rtl_vfprintf_r_v1_00 = 0x2f661;
|
||||
__rtl_fpclassifyd = 0x30c15;
|
||||
CpkClkTbl = 0x30c68;
|
||||
ROM_IMG1_VALID_PATTEN = 0x30c80;
|
||||
SpicCalibrationPattern = 0x30c88;
|
||||
SpicInitCPUCLK = 0x30c98;
|
||||
BAUDRATE = 0x30ca8;
|
||||
OVSR = 0x30d1c;
|
||||
DIV = 0x30d90;
|
||||
OVSR_ADJ = 0x30e04;
|
||||
__AES_rcon = 0x30e78;
|
||||
__AES_Te4 = 0x30ea0;
|
||||
I2CDmaChNo = 0x312a0;
|
||||
_GPIO_PinMap_Chip2IP_8195a = 0x312b4;
|
||||
_GPIO_PinMap_PullCtrl_8195a = 0x3136c;
|
||||
_GPIO_SWPORT_DDR_TBL = 0x31594;
|
||||
_GPIO_EXT_PORT_TBL = 0x31598;
|
||||
_GPIO_SWPORT_DR_TBL = 0x3159c;
|
||||
UartLogRomCmdTable = 0x316a0;
|
||||
_HalRuartOp = 0x31700;
|
||||
_HalGdmaOp = 0x31760;
|
||||
RTW_WPA_OUI_TYPE = 0x3540c;
|
||||
WPA_CIPHER_SUITE_NONE = 0x35410;
|
||||
WPA_CIPHER_SUITE_WEP40 = 0x35414;
|
||||
WPA_CIPHER_SUITE_TKIP = 0x35418;
|
||||
WPA_CIPHER_SUITE_CCMP = 0x3541c;
|
||||
WPA_CIPHER_SUITE_WEP104 = 0x35420;
|
||||
RSN_CIPHER_SUITE_NONE = 0x35424;
|
||||
RSN_CIPHER_SUITE_WEP40 = 0x35428;
|
||||
RSN_CIPHER_SUITE_TKIP = 0x3542c;
|
||||
RSN_CIPHER_SUITE_CCMP = 0x35430;
|
||||
RSN_CIPHER_SUITE_WEP104 = 0x35434;
|
||||
RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
|
||||
RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
|
||||
RSN_VERSION_BSD = 0x3544c;
|
||||
rom_wps_Te0 = 0x35988;
|
||||
rom_wps_rcons = 0x35d88;
|
||||
rom_wps_Td4s = 0x35d94;
|
||||
rom_wps_Td0 = 0x35e94;
|
||||
str_rom_57ch3Dch0A = 0x3ed05; /* "========================================================\n" */
|
||||
str_rom_0123456789ABCDEF = 0x3ec24; /* "0123456789ABCDEF" */
|
||||
str_rom_hex_addr = 0x442D6; /* "[Addr] .0 .1 .2 .3 .4 .5 .6 .7 .8 .9 .A .B .C .D .E .F\r\n" */
|
||||
str_rom_0123456789abcdef = 0x44660; /* "0123456789abcdef" */
|
||||
__rom_b_cut_end__ = 0x4467c;
|
||||
__rom_c_cut_text_start__ = 0x4467c;
|
||||
HalInitPlatformLogUartV02 = 0x4467d;
|
||||
HalReInitPlatformLogUartV02 = 0x4471d;
|
||||
HalInitPlatformTimerV02 = 0x44755;
|
||||
HalShowBuildInfoV02 = 0x447cd;
|
||||
SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
|
||||
HalSpiInitV02 = 0x4488d;
|
||||
HalBootFlowV02 = 0x44a29;
|
||||
HalInitialROMCodeGlobalVarV02 = 0x44ae5;
|
||||
HalResetVsrV02 = 0x44b41;
|
||||
HalI2CSendRtl8195aV02 = 0x44ce1;
|
||||
HalI2CSetCLKRtl8195aV02 = 0x44d59;
|
||||
RtkI2CSendV02 = 0x4508d;
|
||||
RtkI2CReceiveV02 = 0x459a1;
|
||||
HalI2COpInitV02 = 0x461ed;
|
||||
I2CISRHandleV02 = 0x463e9;
|
||||
RtkSalI2COpInitV02 = 0x46be1;
|
||||
SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
|
||||
SpiFlashAppV02 = 0x46c85;
|
||||
SpicInitRtl8195AV02 = 0x46dc5;
|
||||
SpicEraseFlashRtl8195AV02 = 0x46ea1;
|
||||
HalTimerIrq2To7HandleV02 = 0x46f5d;
|
||||
HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
|
||||
HalTimerInitRtl8195aV02 = 0x4706d;
|
||||
HalTimerReadCountRtl8195aV02 = 0x471b5;
|
||||
HalTimerReLoadRtl8195aV02 = 0x471d1;
|
||||
HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
|
||||
HalTimerDeInitRtl8195aV02 = 0x472c1;
|
||||
HalTimerOpInitV02 = 0x472f9;
|
||||
GPIO_LockV02 = 0x47345;
|
||||
GPIO_UnLockV02 = 0x47379;
|
||||
GPIO_Int_Clear_8195aV02 = 0x473a5;
|
||||
HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
|
||||
FindElementIndexV02 = 0x47541;
|
||||
HalRuartInitRtl8195aV02 = 0x4756d;
|
||||
DramInit_rom = 0x47619;
|
||||
ChangeRandSeed_rom = 0x47979;
|
||||
Sdr_Rand2_rom = 0x47985;
|
||||
MemTest_rom = 0x479dd;
|
||||
SdrCalibration_rom = 0x47a45;
|
||||
SdrControllerInit_rom = 0x47d99;
|
||||
SDIO_EnterCritical = 0x47e39;
|
||||
SDIO_ExitCritical = 0x47e85;
|
||||
SDIO_IRQ_Handler_Rom = 0x47ec5;
|
||||
SDIO_Interrupt_Init_Rom = 0x47f31;
|
||||
SDIO_Device_Init_Rom = 0x47f81;
|
||||
SDIO_Interrupt_DeInit_Rom = 0x48215;
|
||||
SDIO_Device_DeInit_Rom = 0x48255;
|
||||
SDIO_Enable_Interrupt_Rom = 0x48281;
|
||||
SDIO_Disable_Interrupt_Rom = 0x482a1;
|
||||
SDIO_Clear_ISR_Rom = 0x482c1;
|
||||
SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
|
||||
SDIO_Free_Rx_Pkt_Rom = 0x48331;
|
||||
SDIO_Recycle_Rx_BD_Rom = 0x48355;
|
||||
SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
|
||||
SDIO_RxTask_Rom = 0x4851d;
|
||||
SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
|
||||
SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
|
||||
SDIO_Process_RPWM_Rom = 0x485b5;
|
||||
SDIO_Reset_Cmd_Rom = 0x485e9;
|
||||
SDIO_Rx_Data_Transaction_Rom = 0x48611;
|
||||
SDIO_Send_C2H_PktMsg_Rom = 0x48829;
|
||||
SDIO_Register_Tx_Callback_Rom = 0x488f5;
|
||||
SDIO_ReadMem_Rom = 0x488fd;
|
||||
SDIO_WriteMem_Rom = 0x489a9;
|
||||
SDIO_SetMem_Rom = 0x48a69;
|
||||
SDIO_TX_Pkt_Handle_Rom = 0x48b29;
|
||||
SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
|
||||
SDIO_IRQ_Handler_BH_Rom = 0x48d95;
|
||||
SDIO_TxTask_Rom = 0x48e9d;
|
||||
SDIO_TaskUp_Rom = 0x48eed;
|
||||
SDIO_Boot_Up = 0x48f55;
|
||||
__rom_c_cut_text_end__ = 0x49070;
|
||||
__rom_c_cut_rodata_start__ = 0x49070;
|
||||
BAUDRATE_v02 = 0x49070;
|
||||
OVSR_v02 = 0x490fc;
|
||||
DIV_v02 = 0x49188;
|
||||
OVSR_ADJ_v02 = 0x49214;
|
||||
SdrDramInfo_rom = 0x492a0; /* DRAM_DEVICE_INFO *DramInfo */
|
||||
SdrDramTiming_rom = 0x492b4;
|
||||
SdrDramModeReg_rom = 0x492e8;
|
||||
SdrDramDev_rom = 0x49304;
|
||||
__rom_c_cut_rodata_end__ = 0x49314;
|
||||
|
||||
/* RAM data used in ROM */
|
||||
|
||||
__ram_image_start__ = 0x10000000;
|
||||
__rom_bss_start__ = 0x10000300;
|
||||
__ram_start_table_start__ = 0x10000bc8;
|
||||
__rom_bss_end__ = 0x10000bc8;
|
||||
|
||||
/* BOOT-LOADER */
|
||||
|
||||
gRamStartFun = 0x10000bc8; /* HalResetVsrV02(), HalResetVsr() */
|
||||
gRamPatchWAKE = 0x10000bcc; /* HalResetVsrV02(), HalResetVsr() */
|
||||
gRamPatchFun0 = 0x10000bd0; /* HalResetVsrV02(), HalResetVsr() */
|
||||
gRamPatchFun1 = 0x10000bd4; /* HalResetVsrV02(), HalResetVsr() */
|
||||
gRamPatchFun2 = 0x10000bd8; /* HalResetVsrV02(), HalResetVsr() */
|
||||
__image1_validate_code__ = 0x10000bdc; /* 8 bytes HalResetVsrV02(), HalResetVsr() */
|
||||
|
||||
|
||||
/* __ram_image_end__ = 0x10002100; */
|
||||
|
||||
/* End RAM data used in ROM */
|
||||
|
||||
/* 1006D000..1006F998: data SDIO_Device_Init_Rom(), SDIO_Boot_Up(), SDIO_TX_Pkt_Handle_Rom(),.. */
|
||||
}
|
||||
|
|
@ -0,0 +1,793 @@
|
|||
SECTIONS
|
||||
{
|
||||
__vectors_table = 0x0;
|
||||
Reset_Handler = 0x101;
|
||||
NMI_Handler = 0x109;
|
||||
HardFault_Handler = 0x10d;
|
||||
MemManage_Handler = 0x121;
|
||||
BusFault_Handler = 0x125;
|
||||
UsageFault_Handler = 0x129;
|
||||
HalLogUartInit = 0x201;
|
||||
HalSerialPutcRtl8195a = 0x2d9;
|
||||
HalSerialGetcRtl8195a = 0x309;
|
||||
HalSerialGetIsrEnRegRtl8195a = 0x329;
|
||||
HalSerialSetIrqEnRegRtl8195a = 0x335;
|
||||
HalCpuClkConfig = 0x341;
|
||||
HalGetCpuClk = 0x355;
|
||||
HalRomInfo = 0x39d;
|
||||
HalGetRomInfo = 0x3b5;
|
||||
HalResetVsr = 0x3c5;
|
||||
HalDelayUs = 0x899;
|
||||
HalNMIHandler = 0x8e1;
|
||||
HalHardFaultHandler = 0x911;
|
||||
HalMemManageHandler = 0xc09;
|
||||
HalBusFaultHandler = 0xc39;
|
||||
HalUsageFaultHandler = 0xc69;
|
||||
HalUart0PinCtrlRtl8195A = 0xcfd;
|
||||
HalUart1PinCtrlRtl8195A = 0xdc9;
|
||||
HalUart2PinCtrlRtl8195A = 0xe9d;
|
||||
HalSPI0PinCtrlRtl8195A = 0xf75;
|
||||
HalSPI1PinCtrlRtl8195A = 0x1015;
|
||||
HalSPI2PinCtrlRtl8195A = 0x10e5;
|
||||
HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
|
||||
HalI2C0PinCtrlRtl8195A = 0x1275;
|
||||
HalI2C1PinCtrlRtl8195A = 0x1381;
|
||||
HalI2C2PinCtrlRtl8195A = 0x1459;
|
||||
HalI2C3PinCtrlRtl8195A = 0x1529;
|
||||
HalI2S0PinCtrlRtl8195A = 0x1639;
|
||||
HalI2S1PinCtrlRtl8195A = 0x176d;
|
||||
HalPCM0PinCtrlRtl8195A = 0x1845;
|
||||
HalPCM1PinCtrlRtl8195A = 0x1949;
|
||||
HalSDIODPinCtrlRtl8195A = 0x1a1d;
|
||||
HalSDIOHPinCtrlRtl8195A = 0x1a6d;
|
||||
HalMIIPinCtrlRtl8195A = 0x1ab9;
|
||||
HalWLLEDPinCtrlRtl8195A = 0x1b51;
|
||||
HalWLANT0PinCtrlRtl8195A = 0x1c0d;
|
||||
HalWLANT1PinCtrlRtl8195A = 0x1c61;
|
||||
HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
|
||||
HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
|
||||
HalNFCPinCtrlRtl8195A = 0x1d59;
|
||||
HalPWM0PinCtrlRtl8195A = 0x1da9;
|
||||
HalPWM1PinCtrlRtl8195A = 0x1ead;
|
||||
HalPWM2PinCtrlRtl8195A = 0x1fb5;
|
||||
HalPWM3PinCtrlRtl8195A = 0x20b1;
|
||||
HalETE0PinCtrlRtl8195A = 0x21b9;
|
||||
HalETE1PinCtrlRtl8195A = 0x22c1;
|
||||
HalETE2PinCtrlRtl8195A = 0x23c9;
|
||||
HalETE3PinCtrlRtl8195A = 0x24d1;
|
||||
HalEGTIMPinCtrlRtl8195A = 0x25d9;
|
||||
HalSPIFlashPinCtrlRtl8195A = 0x2679;
|
||||
HalSDRPinCtrlRtl8195A = 0x2725;
|
||||
HalJTAGPinCtrlRtl8195A = 0x280d;
|
||||
HalTRACEPinCtrlRtl8195A = 0x2861;
|
||||
HalLOGUartPinCtrlRtl8195A = 0x28b9;
|
||||
HalLOGUartIRPinCtrlRtl8195A = 0x291d;
|
||||
HalSICPinCtrlRtl8195A = 0x2981;
|
||||
HalEEPROMPinCtrlRtl8195A = 0x29d9;
|
||||
HalDEBUGPinCtrlRtl8195A = 0x2a31;
|
||||
HalPinCtrlRtl8195A = 0x2b39;
|
||||
SpicRxCmdRtl8195A = 0x2e5d;
|
||||
SpicWaitBusyDoneRtl8195A = 0x2ea5;
|
||||
SpicGetFlashStatusRtl8195A = 0x2eb5;
|
||||
SpicWaitWipDoneRtl8195A = 0x2f55;
|
||||
SpicTxCmdRtl8195A = 0x2f6d;
|
||||
SpicSetFlashStatusRtl8195A = 0x2fc1;
|
||||
SpicCmpDataForCalibrationRtl8195A = 0x3049;
|
||||
SpicLoadInitParaFromClockRtl8195A = 0x3081;
|
||||
SpicInitRtl8195A = 0x30e5;
|
||||
SpicEraseFlashRtl8195A = 0x31bd;
|
||||
SpiFlashApp = 0x3279;
|
||||
HalPeripheralIntrHandle = 0x33b5;
|
||||
HalSysOnIntrHandle = 0x3439;
|
||||
HalWdgIntrHandle = 0x3485;
|
||||
HalTimer0IntrHandle = 0x34d5;
|
||||
HalTimer1IntrHandle = 0x3525;
|
||||
HalI2C3IntrHandle = 0x3575;
|
||||
HalTimer2To7IntrHandle = 0x35c5;
|
||||
HalSpi0IntrHandle = 0x3615;
|
||||
HalGpioIntrHandle = 0x3665;
|
||||
HalUart0IntrHandle = 0x36b5;
|
||||
HalSpiFlashIntrHandle = 0x3705;
|
||||
HalUsbOtgIntrHandle = 0x3755;
|
||||
HalSdioHostIntrHandle = 0x37a5;
|
||||
HalI2s0OrPcm0IntrHandle = 0x37f5;
|
||||
HalI2s1OrPcm1IntrHandle = 0x3845;
|
||||
HalWlDmaIntrHandle = 0x3895;
|
||||
HalWlProtocolIntrHandle = 0x38e5;
|
||||
HalCryptoIntrHandle = 0x3935;
|
||||
HalGmacIntrHandle = 0x3985;
|
||||
HalGdma0Ch0IntrHandle = 0x39d5;
|
||||
HalGdma0Ch1IntrHandle = 0x3a25;
|
||||
HalGdma0Ch2IntrHandle = 0x3a75;
|
||||
HalGdma0Ch3IntrHandle = 0x3ac5;
|
||||
HalGdma0Ch4IntrHandle = 0x3b15;
|
||||
HalGdma0Ch5IntrHandle = 0x3b65;
|
||||
HalGdma1Ch0IntrHandle = 0x3bb5;
|
||||
HalGdma1Ch1IntrHandle = 0x3c05;
|
||||
HalGdma1Ch2IntrHandle = 0x3c55;
|
||||
HalGdma1Ch3IntrHandle = 0x3ca5;
|
||||
HalGdma1Ch4IntrHandle = 0x3cf5;
|
||||
HalGdma1Ch5IntrHandle = 0x3d45;
|
||||
HalSdioDeviceIntrHandle = 0x3d95;
|
||||
VectorTableInitRtl8195A = 0x3de5;
|
||||
txt0123456789ABCDEF = 0x3ec24;
|
||||
VectorTableInitForOSRtl8195A = 0x4019;
|
||||
VectorIrqRegisterRtl8195A = 0x4029;
|
||||
VectorIrqUnRegisterRtl8195A = 0x4091;
|
||||
VectorIrqEnRtl8195A = 0x40f1;
|
||||
VectorIrqDisRtl8195A = 0x418d;
|
||||
_UartRxDmaIrqHandle = 0x422d;
|
||||
HalRuartPutCRtl8195a = 0x4281;
|
||||
HalRuartGetCRtl8195a = 0x429d;
|
||||
HalRuartRTSCtrlRtl8195a = 0x42bd;
|
||||
HalRuartGetDebugValueRtl8195a = 0x42e1;
|
||||
HalRuartGetIMRRtl8195a = 0x43e1;
|
||||
HalRuartSetIMRRtl8195a = 0x442d;
|
||||
_UartIrqHandle = 0x4465;
|
||||
HalRuartDmaInitRtl8195a = 0x4681;
|
||||
HalRuartIntDisableRtl8195a = 0x4845;
|
||||
HalRuartDeInitRtl8195a = 0x4855;
|
||||
HalRuartIntEnableRtl8195a = 0x4985;
|
||||
_UartTxDmaIrqHandle = 0x4995;
|
||||
HalRuartRegIrqRtl8195a = 0x49d1;
|
||||
HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
|
||||
HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
|
||||
HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
|
||||
RuartLock = 0x4cc9;
|
||||
RuartUnLock = 0x4ced;
|
||||
HalRuartIntSendRtl8195a = 0x4d09;
|
||||
HalRuartDmaSendRtl8195a = 0x4e35;
|
||||
HalRuartStopSendRtl8195a = 0x4f89;
|
||||
HalRuartIntRecvRtl8195a = 0x504d;
|
||||
HalRuartDmaRecvRtl8195a = 0x51ad;
|
||||
HalRuartStopRecvRtl8195a = 0x52cd;
|
||||
RuartIsTimeout = 0x5385;
|
||||
HalRuartSendRtl8195a = 0x53b1;
|
||||
HalRuartRecvRtl8195a = 0x5599;
|
||||
RuartResetRxFifoRtl8195a = 0x5751;
|
||||
HalRuartResetRxFifoRtl8195a = 0x5775;
|
||||
HalRuartInitRtl8195a = 0x5829;
|
||||
HalGdmaOnOffRtl8195a = 0x5df1;
|
||||
HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
|
||||
HalGdmaChEnRtl8195a = 0x5e51;
|
||||
HalGdmaChDisRtl8195a = 0x5e6d;
|
||||
HalGdamChInitRtl8195a = 0x5e91;
|
||||
HalGdmaChSetingRtl8195a = 0x5ebd;
|
||||
HalGdmaChBlockSetingRtl8195a = 0x000060dd;
|
||||
HalGdmaChIsrCleanRtl8195a = 0x6419;
|
||||
HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
|
||||
HalGdmaChCleanAutoDstRtl8195a = 0x6501;
|
||||
HalEFUSEPowerSwitch8195AROM = 0x6561;
|
||||
HALEFUSEOneByteReadROM = 0x65f9;
|
||||
HALEFUSEOneByteWriteROM = 0x6699;
|
||||
__rtl_memcmpb_v1_00 = 0x681d;
|
||||
__rtl_random_v1_00 = 0x6861;
|
||||
__rtl_align_to_be32_v1_00 = 0x6881;
|
||||
__rtl_memsetw_v1_00 = 0x6899;
|
||||
__rtl_memsetb_v1_00 = 0x68ad;
|
||||
__rtl_memcpyw_v1_00 = 0x68bd;
|
||||
__rtl_memcpyb_v1_00 = 0x68dd;
|
||||
__rtl_memDump_v1_00 = 0x68f5;
|
||||
__rtl_AES_set_encrypt_key = 0x6901;
|
||||
__rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
|
||||
__rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
|
||||
__rtl_cryptoEngine_init_v1_00 = 0x6ea9;
|
||||
__rtl_cryptoEngine_exit_v1_00 = 0x7055;
|
||||
__rtl_cryptoEngine_reset_v1_00 = 0x70b1;
|
||||
__rtl_cryptoEngine_v1_00 = 0x70ed;
|
||||
__rtl_crypto_cipher_init_v1_00 = 0x7c69;
|
||||
__rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
|
||||
__rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
|
||||
HalSsiPinmuxEnableRtl8195a = 0x7cd5;
|
||||
HalSsiEnableRtl8195a = 0x7e45;
|
||||
HalSsiDisableRtl8195a = 0x7ef9;
|
||||
HalSsiLoadSettingRtl8195a = 0x7fad;
|
||||
HalSsiSetInterruptMaskRtl8195a = 0x8521;
|
||||
HalSsiGetInterruptMaskRtl8195a = 0x85c9;
|
||||
HalSsiSetSclkPolarityRtl8195a = 0x863d;
|
||||
HalSsiSetSclkPhaseRtl8195a = 0x8715;
|
||||
HalSsiWriteRtl8195a = 0x87e9;
|
||||
HalSsiSetDeviceRoleRtl8195a = 0x8861;
|
||||
HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
|
||||
HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
|
||||
HalSsiReadRtl8195a = 0x89b9;
|
||||
HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
|
||||
HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
|
||||
HalSsiGetStatusRtl8195a = 0x8b1d;
|
||||
HalSsiWriteableRtl8195a = 0x8b91;
|
||||
HalSsiReadableRtl8195a = 0x8c09;
|
||||
HalSsiBusyRtl8195a = 0x8c81;
|
||||
HalSsiReadInterruptRtl8195a = 0x8cf9;
|
||||
HalSsiWriteInterruptRtl8195a = 0x8efd;
|
||||
HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
|
||||
HalSsiGetInterruptStatusRtl8195a = 0x90d9;
|
||||
HalSsiInterruptEnableRtl8195a = 0x914d;
|
||||
HalSsiInterruptDisableRtl8195a = 0x9299;
|
||||
HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
|
||||
HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
|
||||
HalSsiInitRtl8195a = 0x94d1;
|
||||
_SsiReadInterrupt = 0x9ba5;
|
||||
_SsiWriteInterrupt = 0x9db1;
|
||||
_SsiIrqHandle = 0x9eb1;
|
||||
HalI2CWrite32 = 0xa061;
|
||||
HalI2CRead32 = 0xa09d;
|
||||
HalI2CDeInit8195a = 0xa0dd;
|
||||
HalI2CSendRtl8195a = 0xa1f1;
|
||||
HalI2CReceiveRtl8195a = 0xa25d;
|
||||
HalI2CEnableRtl8195a = 0xa271;
|
||||
HalI2CIntrCtrl8195a = 0xa389;
|
||||
HalI2CReadRegRtl8195a = 0xa3a1;
|
||||
HalI2CWriteRegRtl8195a = 0xa3b1;
|
||||
HalI2CSetCLKRtl8195a = 0xa3c5;
|
||||
HalI2CMassSendRtl8195a = 0xa6e9;
|
||||
HalI2CClrIntrRtl8195a = 0xa749;
|
||||
HalI2CClrAllIntrRtl8195a = 0xa761;
|
||||
HalI2CInit8195a = 0xa775;
|
||||
HalI2CDMACtrl8195a = 0xaa31;
|
||||
RtkI2CIoCtrl = 0xaa61;
|
||||
RtkI2CPowerCtrl = 0xaa65;
|
||||
HalI2COpInit = 0xaa69;
|
||||
I2CIsTimeout = 0xac65;
|
||||
I2CTXGDMAISRHandle = 0xb435;
|
||||
I2CRXGDMAISRHandle = 0xb4c1;
|
||||
RtkI2CIrqInit = 0xb54d;
|
||||
RtkI2CIrqDeInit = 0xb611;
|
||||
RtkI2CPinMuxInit = 0xb675;
|
||||
RtkI2CPinMuxDeInit = 0xb7c9;
|
||||
RtkI2CDMAInit = 0xb955;
|
||||
RtkI2CInit = 0xbc95;
|
||||
RtkI2CDMADeInit = 0xbdad;
|
||||
RtkI2CDeInit = 0xbe4d;
|
||||
RtkI2CSendUserAddr = 0xbee5;
|
||||
RtkI2CSend = 0xc07d;
|
||||
RtkI2CLoadDefault = 0xce51;
|
||||
RtkSalI2COpInit = 0xcf21;
|
||||
HalI2SWrite32 = 0xcf65;
|
||||
HalI2SRead32 = 0xcf85;
|
||||
HalI2SDeInitRtl8195a = 0xcfa9;
|
||||
HalI2STxRtl8195a = 0xcfc9;
|
||||
HalI2SRxRtl8195a = 0xd011;
|
||||
HalI2SEnableRtl8195a = 0xd05d;
|
||||
HalI2SIntrCtrlRtl8195a = 0xd0b1;
|
||||
HalI2SReadRegRtl8195a = 0xd0d1;
|
||||
HalI2SClrIntrRtl8195a = 0xd0dd;
|
||||
HalI2SClrAllIntrRtl8195a = 0xd0fd;
|
||||
HalI2SInitRtl8195a = 0xd11d;
|
||||
GPIO_GetIPPinName_8195a = 0xd2e5;
|
||||
GPIO_GetChipPinName_8195a = 0xd331;
|
||||
GPIO_PullCtrl_8195a = 0xd39d;
|
||||
GPIO_FuncOn_8195a = 0xd421;
|
||||
GPIO_FuncOff_8195a = 0xd481;
|
||||
GPIO_Int_Mask_8195a = 0xd4e9;
|
||||
GPIO_Int_SetType_8195a = 0xd511;
|
||||
HAL_GPIO_IrqHandler_8195a = 0xd5fd;
|
||||
HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
|
||||
HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
|
||||
HAL_GPIO_IntCtrl_8195a = 0xd6cd;
|
||||
HAL_GPIO_Init_8195a = 0xd805;
|
||||
HAL_GPIO_DeInit_8195a = 0xdac1;
|
||||
HAL_GPIO_ReadPin_8195a = 0xdbd1;
|
||||
HAL_GPIO_WritePin_8195a = 0xdc91;
|
||||
HAL_GPIO_RegIrq_8195a = 0xddad;
|
||||
HAL_GPIO_UnRegIrq_8195a = 0xddf5;
|
||||
HAL_GPIO_UserRegIrq_8195a = 0xde15;
|
||||
HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
|
||||
HAL_GPIO_MaskIrq_8195a = 0xdfc1;
|
||||
HAL_GPIO_UnMaskIrq_8195a = 0xe061;
|
||||
HAL_GPIO_IntDebounce_8195a = 0xe101;
|
||||
HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
|
||||
HAL_GPIO_PullCtrl_8195a = 0xe1c9;
|
||||
DumpForOneBytes = 0xe259;
|
||||
CmdRomHelp = 0xe419;
|
||||
CmdWriteWord = 0xe491;
|
||||
CmdDumpHelfWord = 0xe505;
|
||||
CmdDumpWord = 0xe5f1;
|
||||
CmdDumpByte = 0xe6f5;
|
||||
CmdSpiFlashTool = 0xe751;
|
||||
GetRomCmdNum = 0xe7a9;
|
||||
CmdWriteByte = 0xe7ad;
|
||||
Isspace = 0xe7ed;
|
||||
Strtoul = 0xe801;
|
||||
ArrayInitialize = 0xe8b1;
|
||||
GetArgc = 0xe8c9;
|
||||
GetArgv = 0xe8f9;
|
||||
UartLogCmdExecute = 0xe95d;
|
||||
UartLogShowBackSpace = 0xe9fd;
|
||||
UartLogRecallOldCmd = 0xea39;
|
||||
UartLogHistoryCmd = 0xea71;
|
||||
UartLogCmdChk = 0xeadd;
|
||||
UartLogIrqHandle = 0xebf5;
|
||||
RtlConsolInit = 0xecc5;
|
||||
RtlConsolTaskRom = 0xed49;
|
||||
RtlExitConsol = 0xed79;
|
||||
RtlConsolRom = 0xedcd;
|
||||
HalTimerOpInit = 0xee0d;
|
||||
HalTimerIrq2To7Handle = 0xee59;
|
||||
HalGetTimerIdRtl8195a = 0xef09;
|
||||
HalTimerInitRtl8195a = 0xef3d;
|
||||
HalTimerDisRtl8195a = 0xf069;
|
||||
HalTimerEnRtl8195a = 0xf089;
|
||||
HalTimerReadCountRtl8195a = 0xf0a9;
|
||||
HalTimerIrqClearRtl8195a = 0xf0bd;
|
||||
HalTimerDumpRegRtl8195a = 0xf0d1;
|
||||
VSprintf = 0xf129;
|
||||
DiagPrintf = 0xf39d;
|
||||
DiagSPrintf = 0xf3b9;
|
||||
DiagSnPrintf = 0xf3d1;
|
||||
prvDiagPrintf = 0xf3ed;
|
||||
prvDiagSPrintf = 0xf40d;
|
||||
_memcmp = 0xf429;
|
||||
_memcpy = 0xf465;
|
||||
_memset = 0xf511;
|
||||
Rand = 0xf585;
|
||||
_strncpy = 0xf60d;
|
||||
_strcpy = 0xf629;
|
||||
prvStrCpy = 0xf639;
|
||||
_strlen = 0xf651;
|
||||
_strnlen = 0xf669;
|
||||
prvStrLen = 0xf699;
|
||||
_strcmp = 0xf6b1;
|
||||
_strncmp = 0xf6d1;
|
||||
prvStrCmp = 0xf719;
|
||||
StrUpr = 0xf749;
|
||||
prvAtoi = 0xf769;
|
||||
prvStrStr = 0xf7bd;
|
||||
_strsep = 0xf7d5;
|
||||
skip_spaces = 0xf815;
|
||||
skip_atoi = 0xf831;
|
||||
_parse_integer_fixup_radix = 0xf869;
|
||||
_parse_integer = 0xf8bd;
|
||||
simple_strtoull = 0xf915;
|
||||
simple_strtoll = 0xf945;
|
||||
simple_strtoul = 0xf965;
|
||||
simple_strtol = 0xf96d;
|
||||
_vsscanf = 0xf985;
|
||||
_sscanf = 0xff71;
|
||||
div_u64 = 0xff91;
|
||||
div_s64 = 0xff99;
|
||||
div_u64_rem = 0xffa1;
|
||||
div_s64_rem = 0xffb1;
|
||||
_strpbrk = 0xffc1;
|
||||
_strchr = 0xffed;
|
||||
aes_set_key = 0x10005;
|
||||
aes_encrypt = 0x103d1;
|
||||
aes_decrypt = 0x114a5;
|
||||
AES_WRAP = 0x125c9;
|
||||
AES_UnWRAP = 0x12701;
|
||||
crc32_get = 0x12861;
|
||||
arc4_byte = 0x12895;
|
||||
rt_arc4_init = 0x128bd;
|
||||
rt_arc4_crypt = 0x12901;
|
||||
rt_md5_init = 0x131c1;
|
||||
rt_md5_append = 0x131f5;
|
||||
rt_md5_final = 0x1327d;
|
||||
rt_md5_hmac = 0x132d5;
|
||||
rtw_get_bit_value_from_ieee_value = 0x13449;
|
||||
rtw_is_cckrates_included = 0x13475;
|
||||
rtw_is_cckratesonly_included = 0x134b5;
|
||||
rtw_check_network_type = 0x134dd;
|
||||
rtw_set_fixed_ie = 0x1350d;
|
||||
rtw_set_ie = 0x1352d;
|
||||
rtw_get_ie = 0x1355d;
|
||||
rtw_set_supported_rate = 0x13591;
|
||||
rtw_get_rateset_len = 0x13611;
|
||||
rtw_get_wpa_ie = 0x1362d;
|
||||
rtw_get_wpa2_ie = 0x136c9;
|
||||
rtw_get_wpa_cipher_suite = 0x13701;
|
||||
rtw_get_wpa2_cipher_suite = 0x13769;
|
||||
rtw_parse_wpa_ie = 0x137d1;
|
||||
rtw_parse_wpa2_ie = 0x138ad;
|
||||
rtw_get_sec_ie = 0x13965;
|
||||
rtw_get_wps_ie = 0x13a15;
|
||||
rtw_get_wps_attr = 0x13a99;
|
||||
rtw_get_wps_attr_content = 0x13b49;
|
||||
rtw_ieee802_11_parse_elems = 0x13b91;
|
||||
str_2char2num = 0x13d9d;
|
||||
key_2char2num = 0x13db9;
|
||||
convert_ip_addr = 0x13dd1;
|
||||
rom_psk_PasswordHash = 0x13e9d;
|
||||
rom_psk_CalcGTK = 0x13ed5;
|
||||
rom_psk_CalcPTK = 0x13f69;
|
||||
wep_80211_encrypt = 0x14295;
|
||||
wep_80211_decrypt = 0x142f5;
|
||||
tkip_micappendbyte = 0x14389;
|
||||
rtw_secmicsetkey = 0x143d9;
|
||||
rtw_secmicappend = 0x14419;
|
||||
rtw_secgetmic = 0x14435;
|
||||
rtw_seccalctkipmic = 0x1449d;
|
||||
tkip_phase1 = 0x145a5;
|
||||
tkip_phase2 = 0x14725;
|
||||
tkip_80211_encrypt = 0x14941;
|
||||
tkip_80211_decrypt = 0x149d5;
|
||||
aes1_encrypt = 0x14a8d;
|
||||
aesccmp_construct_mic_iv = 0x14c65;
|
||||
aesccmp_construct_mic_header1 = 0x14ccd;
|
||||
aesccmp_construct_mic_header2 = 0x14d21;
|
||||
aesccmp_construct_ctr_preload = 0x14db5;
|
||||
aes_80211_encrypt = 0x14e29;
|
||||
aes_80211_decrypt = 0x151ad;
|
||||
_sha1_process_message_block = 0x155b9;
|
||||
_sha1_pad_message = 0x15749;
|
||||
rt_sha1_init = 0x157e5;
|
||||
rt_sha1_update = 0x15831;
|
||||
rt_sha1_finish = 0x158a9;
|
||||
rt_hmac_sha1 = 0x15909;
|
||||
rom_aes_128_cbc_encrypt = 0x15a65;
|
||||
rom_aes_128_cbc_decrypt = 0x15ae1;
|
||||
rom_rijndaelKeySetupEnc = 0x15b5d;
|
||||
rom_aes_decrypt_init = 0x15c39;
|
||||
rom_aes_internal_decrypt = 0x15d15;
|
||||
rom_aes_decrypt_deinit = 0x16071;
|
||||
rom_aes_encrypt_init = 0x16085;
|
||||
rom_aes_internal_encrypt = 0x1609d;
|
||||
rom_aes_encrypt_deinit = 0x16451;
|
||||
bignum_init = 0x17b35;
|
||||
bignum_deinit = 0x17b61;
|
||||
bignum_get_unsigned_bin_len = 0x17b81;
|
||||
bignum_get_unsigned_bin = 0x17b85;
|
||||
bignum_set_unsigned_bin = 0x17c21;
|
||||
bignum_cmp = 0x17cd1;
|
||||
bignum_cmp_d = 0x17cd5;
|
||||
bignum_add = 0x17cfd;
|
||||
bignum_sub = 0x17d0d;
|
||||
bignum_mul = 0x17d1d;
|
||||
bignum_exptmod = 0x17d2d;
|
||||
WPS_realloc = 0x17d51;
|
||||
os_zalloc = 0x17d99;
|
||||
rom_hmac_sha256_vector = 0x17dc1;
|
||||
rom_hmac_sha256 = 0x17ebd;
|
||||
rom_sha256_vector = 0x18009;
|
||||
phy_CalculateBitShift = 0x18221;
|
||||
PHY_SetBBReg_8195A = 0x18239;
|
||||
PHY_QueryBBReg_8195A = 0x18279;
|
||||
ROM_odm_QueryRxPwrPercentage = 0x1829d;
|
||||
ROM_odm_EVMdbToPercentage = 0x182bd;
|
||||
ROM_odm_SignalScaleMapping_8195A = 0x182e5;
|
||||
ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
|
||||
ROM_odm_SetEDCCAThreshold = 0x18721;
|
||||
ROM_odm_SetTRxMux = 0x18749;
|
||||
ROM_odm_SetCrystalCap = 0x18771;
|
||||
ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
|
||||
ROM_ODM_CfoTrackingReset = 0x187e9;
|
||||
ROM_odm_CfoTrackingFlow = 0x18811;
|
||||
curve25519_donna = 0x1965d;
|
||||
aes_test_alignment_detection = 0x1a391;
|
||||
aes_mode_reset = 0x1a3ed;
|
||||
aes_ecb_encrypt = 0x1a3f9;
|
||||
aes_ecb_decrypt = 0x1a431;
|
||||
aes_cbc_encrypt = 0x1a469;
|
||||
aes_cbc_decrypt = 0x1a579;
|
||||
aes_cfb_encrypt = 0x1a701;
|
||||
aes_cfb_decrypt = 0x1a9e5;
|
||||
aes_ofb_crypt = 0x1acc9;
|
||||
aes_ctr_crypt = 0x1af7d;
|
||||
aes_encrypt_key128 = 0x1b289;
|
||||
aes_encrypt_key192 = 0x1b2a5;
|
||||
aes_encrypt_key256 = 0x1b2c1;
|
||||
aes_encrypt_key = 0x1b2e1;
|
||||
aes_decrypt_key128 = 0x1b351;
|
||||
aes_decrypt_key192 = 0x1b36d;
|
||||
aes_decrypt_key256 = 0x1b389;
|
||||
aes_decrypt_key = 0x1b3a9;
|
||||
aes_init = 0x1b419;
|
||||
CRYPTO_chacha_20 = 0x1b41d;
|
||||
CRYPTO_poly1305_init = 0x1bc25;
|
||||
CRYPTO_poly1305_update = 0x1bd09;
|
||||
CRYPTO_poly1305_finish = 0x1bd8d;
|
||||
rom_sha512_starts = 0x1ceb5;
|
||||
rom_sha512_update = 0x1d009;
|
||||
rom_sha512_finish = 0x1d011;
|
||||
rom_sha512 = 0x1d261;
|
||||
rom_sha512_hmac_starts = 0x1d299;
|
||||
rom_sha512_hmac_update = 0x1d35d;
|
||||
rom_sha512_hmac_finish = 0x1d365;
|
||||
rom_sha512_hmac_reset = 0x1d3b5;
|
||||
rom_sha512_hmac = 0x1d3d1;
|
||||
rom_sha512_hkdf = 0x1d40d;
|
||||
rom_ed25519_gen_keypair = 0x1d501;
|
||||
rom_ed25519_gen_signature = 0x1d505;
|
||||
rom_ed25519_verify_signature = 0x1d51d;
|
||||
rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
|
||||
rom_ed25519_crypto_sign_detached = 0x1d579;
|
||||
rom_ed25519_crypto_sign_verify_detached = 0x1d655;
|
||||
rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
|
||||
rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
|
||||
rom_ed25519_ge_p3_tobytes = 0x207d5;
|
||||
rom_ed25519_ge_scalarmult_base = 0x20821;
|
||||
rom_ed25519_ge_tobytes = 0x209e1;
|
||||
rom_ed25519_sc_muladd = 0x20a2d;
|
||||
rom_ed25519_sc_reduce = 0x2603d;
|
||||
__rtl_memchr_v1_00 = 0x28a4d;
|
||||
__rtl_memcmp_v1_00 = 0x28ae1;
|
||||
__rtl_memcpy_v1_00 = 0x28b49;
|
||||
__aeabi_memcpy = 0x28b49;
|
||||
__aeabi_memcpy4 = 0x28b49;
|
||||
__rtl_memmove_v1_00 = 0x28bed;
|
||||
__rtl_memset_v1_00 = 0x28cb5;
|
||||
__aeabi_memset = 0x28cb5;
|
||||
__rtl_strcat_v1_00 = 0x28d49;
|
||||
__rtl_strchr_v1_00 = 0x28d91;
|
||||
__rtl_strcmp_v1_00 = 0x28e55;
|
||||
__rtl_strcpy_v1_00 = 0x28ec9;
|
||||
__rtl_strlen_v1_00 = 0x28f15;
|
||||
__rtl_strncat_v1_00 = 0x28f69;
|
||||
__rtl_strncmp_v1_00 = 0x28fc5;
|
||||
__rtl_strncpy_v1_00 = 0x2907d;
|
||||
__rtl_strstr_v1_00 = 0x293cd;
|
||||
__rtl_strsep_v1_00 = 0x2960d;
|
||||
__rtl_strtok_v1_00 = 0x29619;
|
||||
__rtl__strtok_r_v1_00 = 0x2962d;
|
||||
__rtl_strtok_r_v1_00 = 0x29691;
|
||||
__rtl_close_v1_00 = 0x29699;
|
||||
__rtl_fstat_v1_00 = 0x296ad;
|
||||
__rtl_isatty_v1_00 = 0x296c1;
|
||||
__rtl_lseek_v1_00 = 0x296d5;
|
||||
__rtl_open_v1_00 = 0x296e9;
|
||||
__rtl_read_v1_00 = 0x296fd;
|
||||
__rtl_write_v1_00 = 0x29711;
|
||||
__rtl_sbrk_v1_00 = 0x29725;
|
||||
__rtl_ltoa_v1_00 = 0x297bd;
|
||||
__rtl_ultoa_v1_00 = 0x29855;
|
||||
__rtl_dtoi_v1_00 = 0x298c5;
|
||||
__rtl_dtoi64_v1_00 = 0x29945;
|
||||
__rtl_dtoui_v1_00 = 0x299dd;
|
||||
__rtl_ftol_v1_00 = 0x299e5;
|
||||
__rtl_itof_v1_00 = 0x29a51;
|
||||
__rtl_itod_v1_00 = 0x29ae9;
|
||||
__rtl_i64tod_v1_00 = 0x29b79;
|
||||
__rtl_uitod_v1_00 = 0x29c55;
|
||||
__rtl_ftod_v1_00 = 0x29d2d;
|
||||
__rtl_dtof_v1_00 = 0x29de9;
|
||||
__rtl_uitof_v1_00 = 0x29e89;
|
||||
__rtl_fadd_v1_00 = 0x29f65;
|
||||
__rtl_fsub_v1_00 = 0x2a261;
|
||||
__rtl_fmul_v1_00 = 0x2a559;
|
||||
__rtl_fdiv_v1_00 = 0x2a695;
|
||||
__rtl_dadd_v1_00 = 0x2a825;
|
||||
__rtl_dsub_v1_00 = 0x2aed9;
|
||||
__rtl_dmul_v1_00 = 0x2b555;
|
||||
__rtl_ddiv_v1_00 = 0x2b8ad;
|
||||
__rtl_dcmpeq_v1_00 = 0x2be4d;
|
||||
__rtl_dcmplt_v1_00 = 0x2bebd;
|
||||
__rtl_dcmpgt_v1_00 = 0x2bf51;
|
||||
__rtl_dcmple_v1_00 = 0x2c049;
|
||||
__rtl_fcmplt_v1_00 = 0x2c139;
|
||||
__rtl_fcmpgt_v1_00 = 0x2c195;
|
||||
__rtl_cos_f32_v1_00 = 0x2c229;
|
||||
__rtl_sin_f32_v1_00 = 0x2c435;
|
||||
__rtl_fabs_v1_00 = 0x2c639;
|
||||
__rtl_fabsf_v1_00 = 0x2c641;
|
||||
__rtl_dtoa_r_v1_00 = 0x2c77d;
|
||||
__rom_mallocr_init_v1_00 = 0x2d7d1;
|
||||
__rtl_free_r_v1_00 = 0x2d841;
|
||||
__rtl_malloc_r_v1_00 = 0x2da31;
|
||||
__rtl_realloc_r_v1_00 = 0x2df55;
|
||||
__rtl_memalign_r_v1_00 = 0x2e331;
|
||||
__rtl_valloc_r_v1_00 = 0x2e421;
|
||||
__rtl_pvalloc_r_v1_00 = 0x2e42d;
|
||||
__rtl_calloc_r_v1_00 = 0x2e441;
|
||||
__rtl_cfree_r_v1_00 = 0x2e4a9;
|
||||
__rtl_Balloc_v1_00 = 0x2e515;
|
||||
__rtl_Bfree_v1_00 = 0x2e571;
|
||||
__rtl_i2b_v1_00 = 0x2e585;
|
||||
__rtl_multadd_v1_00 = 0x2e599;
|
||||
__rtl_mult_v1_00 = 0x2e629;
|
||||
__rtl_pow5mult_v1_00 = 0x2e769;
|
||||
__rtl_hi0bits_v1_00 = 0x2e809;
|
||||
__rtl_d2b_v1_00 = 0x2e845;
|
||||
__rtl_lshift_v1_00 = 0x2e901;
|
||||
__rtl_cmp_v1_00 = 0x2e9bd;
|
||||
__rtl_diff_v1_00 = 0x2ea01;
|
||||
__rtl_sread_v1_00 = 0x2eae9;
|
||||
__rtl_seofread_v1_00 = 0x2eb39;
|
||||
__rtl_swrite_v1_00 = 0x2eb3d;
|
||||
__rtl_sseek_v1_00 = 0x2ebc1;
|
||||
__rtl_sclose_v1_00 = 0x2ec11;
|
||||
__rtl_sbrk_r_v1_00 = 0x2ec41;
|
||||
__rtl_fflush_r_v1_00 = 0x2ef8d;
|
||||
__rtl_vfprintf_r_v1_00 = 0x2f661;
|
||||
__rtl_fpclassifyd = 0x30c15;
|
||||
CpkClkTbl = 0x30c68;
|
||||
ROM_IMG1_VALID_PATTEN = 0x30c80;
|
||||
SpicCalibrationPattern = 0x30c88;
|
||||
SpicInitCPUCLK = 0x30c98;
|
||||
BAUDRATE = 0x30ca8;
|
||||
OVSR = 0x30d1c;
|
||||
DIV = 0x30d90;
|
||||
OVSR_ADJ = 0x30e04;
|
||||
__AES_rcon = 0x30e78;
|
||||
__AES_Te4 = 0x30ea0;
|
||||
I2CDmaChNo = 0x312a0;
|
||||
_GPIO_PinMap_Chip2IP_8195a = 0x312b4;
|
||||
_GPIO_PinMap_PullCtrl_8195a = 0x3136c;
|
||||
_GPIO_SWPORT_DDR_TBL = 0x31594;
|
||||
_GPIO_EXT_PORT_TBL = 0x31598;
|
||||
_GPIO_SWPORT_DR_TBL = 0x3159c;
|
||||
UartLogRomCmdTable = 0x316a0;
|
||||
_HalRuartOp = 0x31700;
|
||||
_HalGdmaOp = 0x31760;
|
||||
RTW_WPA_OUI_TYPE = 0x3540c;
|
||||
WPA_CIPHER_SUITE_NONE = 0x35410;
|
||||
WPA_CIPHER_SUITE_WEP40 = 0x35414;
|
||||
WPA_CIPHER_SUITE_TKIP = 0x35418;
|
||||
WPA_CIPHER_SUITE_CCMP = 0x3541c;
|
||||
WPA_CIPHER_SUITE_WEP104 = 0x35420;
|
||||
RSN_CIPHER_SUITE_NONE = 0x35424;
|
||||
RSN_CIPHER_SUITE_WEP40 = 0x35428;
|
||||
RSN_CIPHER_SUITE_TKIP = 0x3542c;
|
||||
RSN_CIPHER_SUITE_CCMP = 0x35430;
|
||||
RSN_CIPHER_SUITE_WEP104 = 0x35434;
|
||||
RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
|
||||
RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
|
||||
RSN_VERSION_BSD = 0x3544c;
|
||||
rom_wps_Te0 = 0x35988;
|
||||
rom_wps_rcons = 0x35d88;
|
||||
rom_wps_Td4s = 0x35d94;
|
||||
rom_wps_Td0 = 0x35e94;
|
||||
str_rom_0123456789ABCDEF = 0x3ec24; /* "0123456789ABCDEF" */
|
||||
str_rom_hex_addr = 0x442D6; /* "[Addr] .0 .1 .2 .3 .4 .5 .6 .7 .8 .9 .A .B .C .D .E .F\r\n" */
|
||||
str_rom_0123456789abcdef = 0x44660; /* "0123456789abcdef" */
|
||||
__rom_b_cut_end__ = 0x4467c;
|
||||
__rom_c_cut_text_start__ = 0x4467c;
|
||||
HalInitPlatformLogUartV02 = 0x4467d;
|
||||
HalReInitPlatformLogUartV02 = 0x4471d;
|
||||
HalInitPlatformTimerV02 = 0x44755;
|
||||
HalShowBuildInfoV02 = 0x447cd;
|
||||
SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
|
||||
HalSpiInitV02 = 0x4488d;
|
||||
HalBootFlowV02 = 0x44a29;
|
||||
HalInitialROMCodeGlobalVarV02 = 0x44ae5;
|
||||
HalResetVsrV02 = 0x44b41;
|
||||
HalI2CSendRtl8195aV02 = 0x44ce1;
|
||||
HalI2CSetCLKRtl8195aV02 = 0x44d59;
|
||||
RtkI2CSendV02 = 0x4508d;
|
||||
RtkI2CReceiveV02 = 0x459a1;
|
||||
HalI2COpInitV02 = 0x461ed;
|
||||
I2CISRHandleV02 = 0x463e9;
|
||||
RtkSalI2COpInitV02 = 0x46be1;
|
||||
SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
|
||||
SpiFlashAppV02 = 0x46c85;
|
||||
SpicInitRtl8195AV02 = 0x46dc5;
|
||||
SpicEraseFlashRtl8195AV02 = 0x46ea1;
|
||||
HalTimerIrq2To7HandleV02 = 0x46f5d;
|
||||
HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
|
||||
HalTimerInitRtl8195aV02 = 0x4706d;
|
||||
HalTimerReadCountRtl8195aV02 = 0x471b5;
|
||||
HalTimerReLoadRtl8195aV02 = 0x471d1;
|
||||
HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
|
||||
HalTimerDeInitRtl8195aV02 = 0x472c1;
|
||||
HalTimerOpInitV02 = 0x472f9;
|
||||
GPIO_LockV02 = 0x47345;
|
||||
GPIO_UnLockV02 = 0x47379;
|
||||
GPIO_Int_Clear_8195aV02 = 0x473a5;
|
||||
HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
|
||||
FindElementIndexV02 = 0x47541;
|
||||
HalRuartInitRtl8195aV02 = 0x4756d;
|
||||
DramInit_rom = 0x47619;
|
||||
ChangeRandSeed_rom = 0x47979;
|
||||
Sdr_Rand2_rom = 0x47985;
|
||||
MemTest_rom = 0x479dd;
|
||||
SdrCalibration_rom = 0x47a45;
|
||||
SdrControllerInit_rom = 0x47d99;
|
||||
SDIO_EnterCritical = 0x47e39;
|
||||
SDIO_ExitCritical = 0x47e85;
|
||||
SDIO_IRQ_Handler_Rom = 0x47ec5;
|
||||
SDIO_Interrupt_Init_Rom = 0x47f31;
|
||||
SDIO_Device_Init_Rom = 0x47f81;
|
||||
SDIO_Interrupt_DeInit_Rom = 0x48215;
|
||||
SDIO_Device_DeInit_Rom = 0x48255;
|
||||
SDIO_Enable_Interrupt_Rom = 0x48281;
|
||||
SDIO_Disable_Interrupt_Rom = 0x482a1;
|
||||
SDIO_Clear_ISR_Rom = 0x482c1;
|
||||
SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
|
||||
SDIO_Free_Rx_Pkt_Rom = 0x48331;
|
||||
SDIO_Recycle_Rx_BD_Rom = 0x48355;
|
||||
SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
|
||||
SDIO_RxTask_Rom = 0x4851d;
|
||||
SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
|
||||
SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
|
||||
SDIO_Process_RPWM_Rom = 0x485b5;
|
||||
SDIO_Reset_Cmd_Rom = 0x485e9;
|
||||
SDIO_Rx_Data_Transaction_Rom = 0x48611;
|
||||
SDIO_Send_C2H_PktMsg_Rom = 0x48829;
|
||||
SDIO_Register_Tx_Callback_Rom = 0x488f5;
|
||||
SDIO_ReadMem_Rom = 0x488fd;
|
||||
SDIO_WriteMem_Rom = 0x489a9;
|
||||
SDIO_SetMem_Rom = 0x48a69;
|
||||
SDIO_TX_Pkt_Handle_Rom = 0x48b29;
|
||||
SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
|
||||
SDIO_IRQ_Handler_BH_Rom = 0x48d95;
|
||||
SDIO_TxTask_Rom = 0x48e9d;
|
||||
SDIO_TaskUp_Rom = 0x48eed;
|
||||
SDIO_Boot_Up = 0x48f55;
|
||||
__rom_c_cut_text_end__ = 0x49070;
|
||||
__rom_c_cut_rodata_start__ = 0x49070;
|
||||
BAUDRATE_v02 = 0x49070;
|
||||
OVSR_v02 = 0x490fc;
|
||||
DIV_v02 = 0x49188;
|
||||
OVSR_ADJ_v02 = 0x49214;
|
||||
SdrDramInfo_rom = 0x492a0; /* DRAM_DEVICE_INFO *DramInfo */
|
||||
SdrDramTiming_rom = 0x492b4;
|
||||
SdrDramModeReg_rom = 0x492e8;
|
||||
SdrDramDev_rom = 0x49304;
|
||||
__rom_c_cut_rodata_end__ = 0x49314;
|
||||
|
||||
/* RAM data used in ROM */
|
||||
|
||||
__ram_image_start__ = 0x10000000;
|
||||
NewVectorTable = 0x10000000;
|
||||
UserIrqFunTable = 0x10000100;
|
||||
UserIrqDataTable = 0x10000200;
|
||||
__rom_bss_start__ = 0x10000300;
|
||||
CfgSysDebugWarn = 0x10000300;
|
||||
CfgSysDebugInfo = 0x10000304;
|
||||
CfgSysDebugErr = 0x10000308;
|
||||
ConfigDebugWarn = 0x1000030c;
|
||||
ConfigDebugInfo = 0x10000310;
|
||||
ConfigDebugErr = 0x10000314;
|
||||
HalTimerOp = 0x10000318;
|
||||
GPIOState = 0x10000334; /* HalPinCtrlRtl8195A() */
|
||||
gTimerRecord = 0x1000034c; /* HalGetTimerIdRtl8195a() */
|
||||
SSI_DBG_CONFIG = 0x10000350; /* HalSsiPinmuxEnableRtl8195a() */
|
||||
_pHAL_Gpio_Adapter = 0x10000354; /* GPIO_FuncOn_8195a() */
|
||||
Timer2To7VectorTable = 0x10000358; /* HalTimerIrqUnRegisterRtl8195aV02() */
|
||||
_rand_first = 0x10000370; /* Rand() */
|
||||
_rand_z1 = 0x10000374; /* Rand() */
|
||||
_rand_z2 = 0x10000378; /* Rand() */
|
||||
_rand_z3 = 0x1000037C; /* Rand() */
|
||||
_rand_z4 = 0x10000380; /* Rand() */
|
||||
pUartLogCtl = 0x10000384; /* UartLogIrqHandle() */
|
||||
UartLogBuf = 0x10000388; /* RtlConsolInit() */
|
||||
UartLogCtl = 0x10000408; /* RtlConsolInit() */
|
||||
UartLogHistoryBuf = 0x10000430; /* */
|
||||
ArgvArray = 0x100006ac; /* GetArgv() */
|
||||
rom_wlan_ram_map = 0x100006d4; /* os_zalloc(), WPS_realloc(),.. */
|
||||
FalseAlmCnt = 0x100006e0; /* ROM_odm_FalseAlarmCounterStatistics() */
|
||||
ROMInfo = 0x10000720; /* ROM_odm_GetDefaultCrytaltalCap(), ROM_odm_SetCrystalCap(), ROM_ODM_CfoTrackingReset(),.. */
|
||||
DM_CfoTrack = 0x10000738; /* ROM_odm_CfoTrackingFlow() */
|
||||
rom_libgloss_ram_map = 0x10000760; /* _rtl_fstat_v1_00(), _rtl_lseek_v1_00(),.. */
|
||||
__rtl_malloc_av_ = 0x10000780; /* __rom_mallocr_init_v1_00(), _rtl_free_r_v1_00().. */
|
||||
__rtl_malloc_trim_threshold = 0x10000b88; /* __rom_mallocr_init_v1_00() */
|
||||
__rtl_malloc_top_pad = 0x10000b8c; /* __rom_mallocr_init_v1_00() */
|
||||
__rtl_malloc_sbrk_base = 0x10000b90; /* __rom_mallocr_init_v1_00() */
|
||||
__rtl_malloc_max_sbrked_mem = 0x10000b94; /* __rom_mallocr_init_v1_00() */
|
||||
__rtl_malloc_max_total_mem = 0x10000b98; /* __rom_mallocr_init_v1_00() */
|
||||
__rtl_malloc_current_mallinfo = 0x10000b9c; /* __rom_mallocr_init_v1_00() */
|
||||
__rtl_errno = 0x10000bc4; /* __rtl_sread_v1_00(), __rtl_write_v1_00(), __rtl_lseek_v1_00(), __rtl_close_v1_00(), __rtl_sbrk_v1_00().. */
|
||||
__ram_start_table_start__ = 0x10000bc8;
|
||||
__rom_bss_end__ = 0x10000bc8;
|
||||
|
||||
/* BOOT-LOADER */
|
||||
|
||||
bootloader = 0x10000bc8; /* = gRamStartFun, HalResetVsr() */
|
||||
gRamStartFun = 0x10000bc8; /* HalResetVsrV02(), HalResetVsr() */
|
||||
gRamPatchWAKE = 0x10000bcc; /* HalResetVsrV02(), HalResetVsr() */
|
||||
gRamPatchFun0 = 0x10000bd0; /* HalResetVsrV02(), HalResetVsr() */
|
||||
gRamPatchFun1 = 0x10000bd4; /* HalResetVsrV02(), HalResetVsr() */
|
||||
gRamPatchFun2 = 0x10000bd8; /* HalResetVsrV02(), HalResetVsr() */
|
||||
__image1_validate_code__ = 0x10000bdc; /* 8 bytes HalResetVsrV02(), HalResetVsr() */
|
||||
RAM_IMG1_VALID_PATTEN = 0x10000bdc;
|
||||
rand_x = 0x10000be4; /* ChangeRandSeed_rom().. Sdr_Rand2_rom() */
|
||||
AvaWds = 0x10000be8; /* SdrCalibration_rom() */
|
||||
SdrDramInfo = 0x10001be8; /* SdrCalibration_rom() */
|
||||
SdrDramTiming = 0x10001bfc; /* SdrCalibration_rom() */
|
||||
SdrDramModeReg = 0x10001c30; /* SdrCalibration_rom() */
|
||||
SdrDramDev = 0x10001c4c; /* SdrCalibration_rom() */
|
||||
/* 0x10000be8: buf 0x1000+ bytes SdrCalibration_rom() */
|
||||
_rtl_impure_ptr = 0x10001c60; /* struct _reent * _rtl_impure_ptr = { &impure_reent } (for standard library) */
|
||||
impure_reent = 0x10001c68; /* struct _reent */
|
||||
_rom_unc_data = 0x10002090; /* ? u32 _rom_unc_data[9] */
|
||||
_sdr_rnd2_y = 0x100020b4; /* Sdr_Rand2_rom().. ChangeRandSeed_rom() */
|
||||
_sdr_rnd2_z = 0x100020b8; /* Sdr_Rand2_rom().. ChangeRandSeed_rom() */
|
||||
_sdr_rnd2_c = 0x100020bc; /* Sdr_Rand2_rom().. ChangeRandSeed_rom() */
|
||||
|
||||
__ram_image_end__ = 0x100020C0;
|
||||
|
||||
gBoot_Gpio_Adapter = 0x100020C0;
|
||||
SpicInitParaAllClk = 0x100021ec;
|
||||
/* 0x1000227C [388] */
|
||||
|
||||
/* End RAM data used in ROM */
|
||||
|
||||
/* 1006D000..1006F998: data SDIO_Device_Init_Rom(), SDIO_Boot_Up(), SDIO_TX_Pkt_Handle_Rom(),.. */
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,19 @@
|
|||
set libname=lib_platform
|
||||
del %libname%_new.a
|
||||
md %libname%.lib
|
||||
cd %libname%.lib
|
||||
PATH=D:\MCU\GNU_Tools_ARM_Embedded\5.2_2015q4\bin;%PATH%
|
||||
arm-none-eabi-ar.exe x ..\%libname%.a
|
||||
del hal_efuse.o
|
||||
del hal_common.o
|
||||
del freertos_pmu_8195a.o
|
||||
del hal_soc_ps_monitor.o
|
||||
del app_start.o
|
||||
del hal_log_uart.o
|
||||
del hal_pinmux.o
|
||||
del hal_misc.o
|
||||
del startup.o
|
||||
rem del hal_spi_flash_ram.o
|
||||
arm-none-eabi-ar.exe ru ..\%libname%_new.a *.o
|
||||
cd ..
|
||||
rd /q /s %libname%.lib
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,12 @@
|
|||
set libname=lib_sdcard_v2
|
||||
del %libname%_new.a
|
||||
md %libname%.lib
|
||||
cd %libname%.lib
|
||||
PATH=D:\MCU\GNU_Tools_ARM_Embedded\5.2_2015q4\bin;%PATH%
|
||||
arm-none-eabi-ar.exe x ..\%libname%.a
|
||||
del sd.o
|
||||
del sdio_host.o
|
||||
del hal_sdio_host.o
|
||||
arm-none-eabi-ar.exe ru ..\%libname%_new.a *.o
|
||||
cd ..
|
||||
rem rd /q /s %libname%.lib
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,11 @@
|
|||
set libname=lib_wlan
|
||||
del %libname%_new.a
|
||||
md %libname%.lib
|
||||
cd %libname%.lib
|
||||
PATH=D:\MCU\GNU_Tools_ARM_Embedded\5.2_2015q4\bin;%PATH%
|
||||
rem arm-none-eabi-ar.exe x ..\%libname%.a
|
||||
arm-none-eabi-objcopy.exe --globalize-symbol rtw_flash_map_update.part.12 rtl8195a_hal_init.o
|
||||
rem rtw_flash_map_update
|
||||
arm-none-eabi-ar.exe ru ..\%libname%_new.a *.o
|
||||
cd ..
|
||||
rem rd /q /s %libname%.lib
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,8 @@
|
|||
for %%a in (*.a) do (
|
||||
md %%a.o
|
||||
cd %%a.o
|
||||
arm-none-eabi-ar x ..\%%a
|
||||
for %%o in (*.o) do arm-none-eabi-objdump -S %%o > %%o.asm
|
||||
cd ..
|
||||
)
|
||||
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
INCLUDE "export-rom_v02.txt"
|
||||
|
||||
|
||||
MEMORY
|
||||
{
|
||||
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 65536
|
||||
ROM_USED_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 21560
|
||||
RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 16128
|
||||
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 434176
|
||||
// RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 7936
|
||||
//BD_RAM (rwx) : ORIGIN = 0x10004000, LENGTH = 442368
|
||||
SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
|
||||
}
|
||||
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__rom_bss_start__ = 0x10000300;
|
||||
__rom_bss_end__ = 0x10000bc8;
|
||||
|
||||
/*
|
||||
.ram.start.table :
|
||||
{
|
||||
__ram_image1_text_start__ = .;
|
||||
__ram_start_table_start__ = .;
|
||||
KEEP(*(SORT(.start.ram.data*)))
|
||||
__ram_start_table_end__ = .;
|
||||
|
||||
} > ROM_USED_RAM
|
||||
*/
|
||||
|
||||
/* Add . to assign the start address of the section, *
|
||||
* to prevent the change of the start address by ld doing section alignment */
|
||||
|
||||
|
||||
/* these 4 sections is used by ROM global variable */
|
||||
/* Don't move them and never add RAM code variable to these sections */
|
||||
/*---------------------------
|
||||
.ram_image1.text . :
|
||||
{
|
||||
__image1_validate_code__ = .;
|
||||
KEEP(*(.image1.validate.rodata*))
|
||||
KEEP(*(.infra.ram.data*))
|
||||
KEEP(*(.timer.ram.data*))
|
||||
KEEP(*(.cutb.ram.data*))
|
||||
KEEP(*(.cutc.ram.data*))
|
||||
KEEP(*(.hal.ram.data*))
|
||||
__image1_bss_start__ = .;
|
||||
__image1_bss_end__ = .;
|
||||
__ram_image1_data_end__ = .;
|
||||
|
||||
*(.hal.ram.text*)
|
||||
*(.infra.ram.text*)
|
||||
__ram_image1_text_end__ = .;
|
||||
} > ROM_USED_RAM
|
||||
*/
|
||||
/*
|
||||
.tcm :
|
||||
{
|
||||
__tcm_start__ = .;
|
||||
*(.tcm.heap)
|
||||
*mem.o (.bss)
|
||||
*memp.o (.bss)
|
||||
__tcm_end__ = .;
|
||||
} > TCM
|
||||
----------------------------*/
|
||||
|
||||
.bootloader :
|
||||
{
|
||||
KEEP(*(.loader.data*))
|
||||
} > ROM_USED_RAM
|
||||
|
||||
OVERLAY 0x1FFF0000:
|
||||
{
|
||||
.valid
|
||||
{
|
||||
*mem.o (.bss*)
|
||||
*memp.o (.bss*)
|
||||
*(.tcm.heap)
|
||||
}
|
||||
.dummy
|
||||
{
|
||||
__ram_image1_text_start__ = .;
|
||||
__ram_start_table_start__ = .;
|
||||
KEEP(*(SORT(.start.ram.data*)))
|
||||
__ram_start_table_end__ = .;
|
||||
__image1_validate_code__ = .;
|
||||
KEEP(*(.image1.validate.rodata*))
|
||||
KEEP(*(.infra.ram.data*))
|
||||
KEEP(*(.timer.ram.data*))
|
||||
KEEP(*(.cutb.ram.data*))
|
||||
KEEP(*(.cutc.ram.data*))
|
||||
KEEP(*(.hal.ram.data*))
|
||||
__image1_bss_start__ = .;
|
||||
.ram_image1.bss$$Base = .;
|
||||
__image1_bss_end__ = .;
|
||||
.ram_image1.bss$$Limit = .;
|
||||
__ram_image1_data_end__ = .;
|
||||
|
||||
*(.hal.ram.text*)
|
||||
*(.infra.ram.text*)
|
||||
}
|
||||
} > TCM
|
||||
|
||||
.image2.start.table :
|
||||
{
|
||||
__ram_image2_text_start__ = .;
|
||||
__image2_entry_func__ = .;
|
||||
.image2.start.table1$$Base = .;
|
||||
KEEP(*(SORT(.image2.ram.data*)))
|
||||
__image2_validate_code__ = .;
|
||||
KEEP(*(.image2.validate.rodata*))
|
||||
KEEP(*(.custom.validate.rodata*))
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.text :
|
||||
{
|
||||
KEEP(*(.infra.ram.start*))
|
||||
*(.mon.ram.text*)
|
||||
*(.hal.flash.text*)
|
||||
*(.hal.sdrc.text*)
|
||||
*(.hal.gpio.text*)
|
||||
*(.fwu.text*)
|
||||
*(.text*)
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.rodata :
|
||||
{
|
||||
*(.rodata*)
|
||||
*(.fwu.rodata*)
|
||||
} > BD_RAM
|
||||
|
||||
.ram.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(.data*)
|
||||
__data_end__ = .;
|
||||
__ram_image2_text_end__ = .;
|
||||
} > BD_RAM
|
||||
|
||||
.ram.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
.ram.bss$$Base = .;
|
||||
*(.hal.flash.data*)
|
||||
*(.hal.sdrc.data*)
|
||||
*(.hal.gpio.data*)
|
||||
*(.fwu.data*)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
*(.bdsram.data*)
|
||||
__bss_end__ = .;
|
||||
.ram.bss$$Limit = .;
|
||||
} > BD_RAM
|
||||
|
||||
.bf_data :
|
||||
{
|
||||
__buffer_data_start__ = .;
|
||||
*(.bfsram.data*)
|
||||
__buffer_data_end__ = .;
|
||||
|
||||
} > BD_RAM
|
||||
/*
|
||||
.bf_data2 :
|
||||
{
|
||||
__buffer_data_start2__ = .;
|
||||
__buffer_data_end2__ = .;
|
||||
|
||||
} > RECY_RAM
|
||||
*/
|
||||
.sdr_text :
|
||||
{
|
||||
__sdram_data_start__ = .;
|
||||
*(.sdram.text*)
|
||||
*(.p2p.text*)
|
||||
*(.wps.text*)
|
||||
*(.websocket.text*)
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_rodata :
|
||||
{
|
||||
*(.sdram.rodata*)
|
||||
*(.p2p.rodata*)
|
||||
*(.wps.rodata*)
|
||||
*(.websocket.rodata*)
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_data :
|
||||
{
|
||||
*(.sdram.data*)
|
||||
*(.p2p.data*)
|
||||
*(.wps.data*)
|
||||
*(.websocket.data*)
|
||||
__sdram_data_end__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_bss :
|
||||
{
|
||||
__sdram_bss_start__ = .;
|
||||
*(.sdram.bss*)
|
||||
*(.p2p.bss*)
|
||||
*(.wps.bss*)
|
||||
*(.websocket.bss*)
|
||||
__sdram_bss_end__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.heap :
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > BD_RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy :
|
||||
{
|
||||
*(.stack)
|
||||
} > BD_RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(BD_RAM) + LENGTH(BD_RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
|
||||
.boot.head :
|
||||
{
|
||||
KEEP(*(.loader.head*))
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,246 @@
|
|||
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
INCLUDE "export-rom_v03.txt"
|
||||
|
||||
|
||||
MEMORY
|
||||
{
|
||||
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 65536
|
||||
ROM_USED_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 21560 /* end 0x10006000 */
|
||||
//RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 16128 /* end 0x10006000 */
|
||||
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 434176
|
||||
SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
|
||||
}
|
||||
|
||||
EXTERN(RAM_IMG2_VALID_PATTEN)
|
||||
EXTERN(InfraStart)
|
||||
EXTERN(gImage2EntryFun0)
|
||||
/*EXTERN(VectorTableOverrideRtl8195A)
|
||||
EXTERN(SYSPlatformInit)*/
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__rom_bss_start__ = 0x10000300;
|
||||
__rom_bss_end__ = 0x10000bc8;
|
||||
|
||||
/*
|
||||
.ram.start.table :
|
||||
{
|
||||
__ram_image1_text_start__ = .;
|
||||
__ram_start_table_start__ = .;
|
||||
KEEP(*(SORT(.start.ram.data*)))
|
||||
__ram_start_table_end__ = .;
|
||||
|
||||
} > ROM_USED_RAM
|
||||
*/
|
||||
|
||||
/* Add . to assign the start address of the section, *
|
||||
* to prevent the change of the start address by ld doing section alignment */
|
||||
|
||||
|
||||
/* these 4 sections is used by ROM global variable */
|
||||
/* Don't move them and never add RAM code variable to these sections */
|
||||
/*---------------------------
|
||||
.ram_image1.text . :
|
||||
{
|
||||
__image1_validate_code__ = .;
|
||||
KEEP(*(.image1.validate.rodata*))
|
||||
KEEP(*(.infra.ram.data*))
|
||||
KEEP(*(.timer.ram.data*))
|
||||
KEEP(*(.cutb.ram.data*))
|
||||
KEEP(*(.cutc.ram.data*))
|
||||
KEEP(*(.hal.ram.data*))
|
||||
__image1_bss_start__ = .;
|
||||
__image1_bss_end__ = .;
|
||||
__ram_image1_data_end__ = .;
|
||||
|
||||
*(.hal.ram.text*)
|
||||
*(.infra.ram.text*)
|
||||
__ram_image1_text_end__ = .;
|
||||
} > ROM_USED_RAM
|
||||
*/
|
||||
/*
|
||||
.tcm :
|
||||
{
|
||||
__tcm_start__ = .;
|
||||
*(.tcm.heap)
|
||||
*mem.o (.bss)
|
||||
*memp.o (.bss)
|
||||
__tcm_end__ = .;
|
||||
} > TCM
|
||||
----------------------------*/
|
||||
|
||||
.bootloader :
|
||||
{
|
||||
KEEP(*(.loader.data*))
|
||||
} > ROM_USED_RAM
|
||||
|
||||
OVERLAY 0x1FFF0000:
|
||||
{
|
||||
.valid
|
||||
{
|
||||
*mem.o (.bss*)
|
||||
*memp.o (.bss*)
|
||||
*(.tcm.heap)
|
||||
}
|
||||
.dummy
|
||||
{
|
||||
__ram_image1_text_start__ = .;
|
||||
__ram_start_table_start__ = .;
|
||||
KEEP(*(SORT(.start.ram.data*)))
|
||||
__ram_start_table_end__ = .;
|
||||
__image1_validate_code__ = .;
|
||||
KEEP(*(.image1.validate.rodata*))
|
||||
KEEP(*(.infra.ram.data*))
|
||||
KEEP(*(.timer.ram.data*))
|
||||
KEEP(*(.cutb.ram.data*))
|
||||
KEEP(*(.cutc.ram.data*))
|
||||
KEEP(*(.hal.ram.data*))
|
||||
__image1_bss_start__ = .;
|
||||
.ram_image1.bss$$Base = .;
|
||||
__image1_bss_end__ = .;
|
||||
.ram_image1.bss$$Limit = .;
|
||||
__ram_image1_data_end__ = .;
|
||||
|
||||
*(.hal.ram.text*)
|
||||
*(.infra.ram.text*)
|
||||
}
|
||||
} > TCM
|
||||
|
||||
.image2.start.table :
|
||||
{
|
||||
__ram_image2_text_start__ = .;
|
||||
__image2_entry_func__ = .;
|
||||
.image2.start.table1$$Base = .;
|
||||
KEEP(*(SORT(.image2.ram.data*)))
|
||||
__image2_validate_code__ = .;
|
||||
KEEP(*(.image2.validate.rodata*))
|
||||
KEEP(*(.custom.validate.rodata*))
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.text :
|
||||
{
|
||||
*(.infra.ram.start*)
|
||||
*(.mon.ram.text*)
|
||||
*(.hal.flash.text*)
|
||||
*(.hal.sdrc.text*)
|
||||
*(.hal.gpio.text*)
|
||||
*(.fwu.text*)
|
||||
*(.text*)
|
||||
*(.sdram.text*)
|
||||
*(.p2p.text*)
|
||||
*(.wps.text*)
|
||||
*(.websocket.text*)
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.rodata :
|
||||
{
|
||||
*(.rodata*)
|
||||
*(.fwu.rodata*)
|
||||
*(.sdram.rodata*)
|
||||
*(.p2p.rodata*)
|
||||
*(.wps.rodata*)
|
||||
*(.websocket.rodata*)
|
||||
} > BD_RAM
|
||||
|
||||
.ram.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(.data*)
|
||||
*(.sdram.data*)
|
||||
*(.p2p.data*)
|
||||
*(.wps.data*)
|
||||
*(.websocket.data*)
|
||||
__data_end__ = .;
|
||||
__ram_image2_text_end__ = .;
|
||||
} > BD_RAM
|
||||
|
||||
.ram.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
.ram.bss$$Base = .;
|
||||
*(.hal.flash.data*)
|
||||
*(.hal.sdrc.data*)
|
||||
*(.hal.gpio.data*)
|
||||
*(.fwu.data*)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
*(.bdsram.data*)
|
||||
*(.sdram.bss*)
|
||||
*(.p2p.bss*)
|
||||
*(.wps.bss*)
|
||||
*(.websocket.bss*)
|
||||
__bss_end__ = .;
|
||||
.ram.bss$$Limit = .;
|
||||
} > BD_RAM
|
||||
|
||||
.bf_data :
|
||||
{
|
||||
__buffer_data_start__ = .;
|
||||
*(.bfsram.data*)
|
||||
__buffer_data_end__ = .;
|
||||
|
||||
} > BD_RAM
|
||||
/*
|
||||
.bf_data2 :
|
||||
{
|
||||
__buffer_data_start2__ = .;
|
||||
__buffer_data_end2__ = .;
|
||||
|
||||
} > RECY_RAM
|
||||
*/
|
||||
.sdr_text :
|
||||
{
|
||||
__sdram_data_start__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_rodata :
|
||||
{
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_data :
|
||||
{
|
||||
__sdram_data_end__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_bss :
|
||||
{
|
||||
__sdram_bss_start__ = .;
|
||||
__sdram_bss_end__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.heap :
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > BD_RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy :
|
||||
{
|
||||
*(.stack)
|
||||
} > BD_RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(BD_RAM) + LENGTH(BD_RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
|
||||
.boot.head :
|
||||
{
|
||||
KEEP(*(.loader.head*))
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,256 @@
|
|||
|
||||
ENTRY(Reset_Handler)
|
||||
ENTRY(main)
|
||||
|
||||
INCLUDE "export-rom_v04.txt"
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ROM (rx) : ORIGIN = 0x000000, LENGTH = 1M /* end 0x00100000 */
|
||||
ROM_USED_RAM (rwx): ORIGIN = 0x10000000, LENGTH = 0x2400 /* end 0x10002400 */
|
||||
BOOT_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 21560 /* end 0x10006000 */
|
||||
ROM_HEAP (rwx) : ORIGIN = 0x10002400, LENGTH = 3K /* end 0x10003000 */
|
||||
RAM_HEAP1 (rwx) : ORIGIN = 0x10003000, LENGTH = 12K /* end 0x10006000 */
|
||||
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 424K /* end 0x10070000 */
|
||||
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64K /* end 0x20000000 */
|
||||
TCM_TAB (rwx) : ORIGIN = 0x1FFFFD00, LENGTH = 768 /* end 0x20000000 */
|
||||
SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M /* end 0x30200000 */
|
||||
}
|
||||
|
||||
EXTERN(RAM_IMG2_VALID_PATTEN)
|
||||
EXTERN(InfraStart)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* 0x00000000: ROM */
|
||||
|
||||
.rom :
|
||||
{
|
||||
__rom_image_start__ = .;
|
||||
KEEP(*(.rom));
|
||||
__rom_image_end__ = .;
|
||||
} > ROM
|
||||
|
||||
/* 0x10000000: SRAM */
|
||||
|
||||
.rom_ram : /* use in rom */
|
||||
{
|
||||
__ram_image_start__ = .;
|
||||
KEEP(*(.ram_dedecated_vector_table)) /* 0x10000000: NewVectorTable */
|
||||
KEEP(*(.ram_user_define_irq_table)) /* 0x10000100: UserIrqFunTable */
|
||||
KEEP(*(.ram_user_define_data_table)) /* 0x10000200: UserIrqDataTable */
|
||||
__rom_bss_start__ = .;
|
||||
KEEP(*(.hal.ram.bss)) /* 0x10000300: CfgSysDebugWarn .. _pHAL_Gpio_Adapter */
|
||||
KEEP(*(.timer2_7_vector_table.data)) /* 0x10000358: Timer2To7VectorTable */
|
||||
KEEP(*(.infra.ram.bss)) /* 0x10000370: first .. z4 */
|
||||
KEEP(*(.mon.ram.bss)) /* 0x10000384: pUartLogCtl .. ArgvArray */
|
||||
KEEP(*(.wlan_ram_map)) /* 0x100006d4: rom_wlan_ram_map, FalseAlmCnt, ROMInfo, DM_CfoTrack */
|
||||
KEEP(*(.ram.rom.wlanmap)) /* align(8) */
|
||||
KEEP(*(.libc.ram.bss)) /* 0x10000760: rom_libgloss_ram_map __rtl_malloc_av_ __rtl_errno */
|
||||
__rom_bss_end__ = .;
|
||||
} > ROM_USED_RAM
|
||||
|
||||
/* 0x10000bc8: bootloader */
|
||||
|
||||
.ram_image1.text . : /* use in rom & boot */
|
||||
{
|
||||
/* __ram_start_table_start__ = .; */
|
||||
__ram_image1_text_start__ = .;
|
||||
KEEP(*(.boot.start.ram.data*))
|
||||
/* __image1_validate_code__ = .; */
|
||||
KEEP(*(.image1.validate.rodata))
|
||||
|
||||
KEEP(*(.infra.ram.data*))
|
||||
KEEP(*(.timer.ram.data*))
|
||||
KEEP(*(.cutb.ram.data*))
|
||||
KEEP(*(.cutc.ram.data*))
|
||||
KEEP(*(.libc.reent))
|
||||
KEEP(*(.rom.unc.data))
|
||||
KEEP(*(.sdr.rand2.data))
|
||||
|
||||
PROVIDE (__ram_image_end__ = .); /* 0x100020c0: end */
|
||||
|
||||
/* boot & images data */
|
||||
|
||||
KEEP(*(.hal.ram.data))
|
||||
KEEP(*(.hal.flash.data))
|
||||
KEEP(*(.boot.rodata*))
|
||||
KEEP(*(.boot.text*))
|
||||
KEEP(*(.boot.data*))
|
||||
__image1_bss_start__ = .;
|
||||
KEEP(*(.boot.bss*))
|
||||
__image1_bss_end__ = .;
|
||||
__ram_image1_text_end__ = .;
|
||||
|
||||
} > BOOT_RAM
|
||||
|
||||
.romheap :
|
||||
{
|
||||
__rom_heap_start__ = .;
|
||||
end = __rom_heap_start__;
|
||||
. = ALIGN(0x1000);
|
||||
__rom_heap_end__ = .;
|
||||
} > ROM_HEAP
|
||||
|
||||
.ram_heap1 :
|
||||
{
|
||||
__ram_heap1_start__ = .;
|
||||
/* *(.heap1*) */
|
||||
} > RAM_HEAP1
|
||||
|
||||
.tcm :
|
||||
{
|
||||
__ram_tcm_start__ = .;
|
||||
__tcm_heap_start__ = .;
|
||||
*(.tcm.heap)
|
||||
} > TCM
|
||||
|
||||
.soc_ps_monitor :
|
||||
{
|
||||
__tcm_heap_end__ = .;
|
||||
} > TCM_TAB
|
||||
|
||||
.image2.start.table :
|
||||
{
|
||||
__ram_heap1_end__ = .;
|
||||
__ram_image2_text_start__ = .;
|
||||
__image2_entry_func__ = .;
|
||||
.image2.start.table1$$Base = .;
|
||||
KEEP(*(SORT(.image2.ram.data*)))
|
||||
__image2_validate_code__ = .;
|
||||
KEEP(*(.image2.validate.rodata*))
|
||||
KEEP(*(.custom.validate.rodata*))
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.text :
|
||||
{
|
||||
*(.infra.ram.start*)
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
|
||||
/* init data */
|
||||
. = ALIGN(4);
|
||||
PROVIDE (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE (__init_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE (__fini_array_end = .);
|
||||
|
||||
*(.mon.ram.text*)
|
||||
*(.hal.flash.text*)
|
||||
*(.hal.sdrc.text*)
|
||||
*(.hal.gpio.text*)
|
||||
*(.fwu.text*)
|
||||
*(.otg.rom.text*)
|
||||
*(.text*)
|
||||
*(.sdram.text*)
|
||||
*(.p2p.text*)
|
||||
*(.wps.text*)
|
||||
*(.websocket.text*)
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.rodata :
|
||||
{
|
||||
*(.rodata*)
|
||||
*(.fwu.rodata*)
|
||||
*(.sdram.rodata*)
|
||||
*(.p2p.rodata*)
|
||||
*(.wps.rodata*)
|
||||
*(.websocket.rodata*)
|
||||
. = ALIGN(4);
|
||||
xHeapRegions = .;
|
||||
LONG(__ram_heap1_start__)
|
||||
LONG(__ram_heap1_end__ - __ram_heap1_start__)
|
||||
LONG(__ram_heap2_start__)
|
||||
LONG(__ram_heap2_end__ - __ram_heap2_start__)
|
||||
LONG(__sdram_heap_start__)
|
||||
LONG(__sdram_heap_end__ - __sdram_heap_start__)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
UartLogRamCmdTable = .;
|
||||
KEEP(*(SORT(.mon.tab*)))
|
||||
UartLogRamCmdTable_end = .;
|
||||
LONG(0)
|
||||
} > BD_RAM
|
||||
|
||||
PROVIDE(UartLogRamCmdTableSize = UartLogRamCmdTable_end - UartLogRamCmdTable);
|
||||
|
||||
.ram.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(.data*)
|
||||
*(.p2p.data*)
|
||||
*(.wps.data*)
|
||||
*(.websocket.data*)
|
||||
*(.sdram.data*)
|
||||
__data_end__ = .;
|
||||
__ram_image2_text_end__ = .;
|
||||
} > BD_RAM
|
||||
|
||||
.ram.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
.ram.bss$$Base = .;
|
||||
*(.hal.flash.data*)
|
||||
*(.hal.sdrc.data*)
|
||||
*(.hal.gpio.data*)
|
||||
*(.fwu.data*)
|
||||
*(.bdsram.data*)
|
||||
*(.bfsram.data*)
|
||||
*(COMMON)
|
||||
*(.bss*)
|
||||
*(.sdram.bss*)
|
||||
*(.p2p.bss*)
|
||||
*(.wps.bss*)
|
||||
*(.websocket.bss*)
|
||||
*(.ssl_ram_map*)
|
||||
__bss_end__ = .;
|
||||
.ram.bss$$Limit = .;
|
||||
|
||||
} > BD_RAM
|
||||
|
||||
.ram_heap2 :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__ram_heap2_start__ = .;
|
||||
*(.heap*) /* ucHeap */
|
||||
} > BD_RAM
|
||||
__ram_heap2_end__ = 0x10070000;
|
||||
|
||||
.sdr_text :
|
||||
{
|
||||
__sdram_data_start__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_rodata :
|
||||
{
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_data :
|
||||
{
|
||||
__sdram_data_end__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_bss :
|
||||
{
|
||||
__sdram_bss_start__ = .;
|
||||
__sdram_bss_end__ = .;
|
||||
. = ALIGN(8);
|
||||
__sdram_heap_start__ = .;
|
||||
} > SDRAM_RAM
|
||||
__sdram_heap_end__ = 0x30200000;
|
||||
|
||||
.boot.head :
|
||||
{
|
||||
KEEP(*(.loader.head*))
|
||||
}
|
||||
ASSERT(__ram_image_end__ == 0x100020c0, "Error rom-bios-boot code & data!")
|
||||
}
|
||||
|
|
@ -0,0 +1,256 @@
|
|||
|
||||
ENTRY(Reset_Handler)
|
||||
ENTRY(main)
|
||||
|
||||
INCLUDE "export-rom_v04.txt"
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ROM (rx) : ORIGIN = 0x000000, LENGTH = 1M /* end 0x00100000 */
|
||||
ROM_USED_RAM (rwx): ORIGIN = 0x10000000, LENGTH = 0x2400 /* end 0x10002400 */
|
||||
BOOT_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 21560 /* end 0x10006000 */
|
||||
ROM_HEAP (rwx) : ORIGIN = 0x10002400, LENGTH = 3K /* end 0x10003000 */
|
||||
RAM_HEAP1 (rwx) : ORIGIN = 0x10003000, LENGTH = 12K /* end 0x10006000 */
|
||||
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 424K /* end 0x10070000 */
|
||||
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64K /* end 0x20000000 */
|
||||
TCM_TAB (rwx) : ORIGIN = 0x1FFFFD00, LENGTH = 768 /* end 0x20000000 */
|
||||
SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M /* end 0x30200000 */
|
||||
}
|
||||
|
||||
EXTERN(RAM_IMG2_VALID_PATTEN)
|
||||
EXTERN(InfraStart)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* 0x00000000: ROM */
|
||||
|
||||
.rom :
|
||||
{
|
||||
__rom_image_start__ = .;
|
||||
KEEP(*(.rom));
|
||||
__rom_image_end__ = .;
|
||||
} > ROM
|
||||
|
||||
/* 0x10000000: SRAM */
|
||||
|
||||
.rom_ram : /* use in rom */
|
||||
{
|
||||
__ram_image_start__ = .;
|
||||
KEEP(*(.ram_dedecated_vector_table)) /* 0x10000000: NewVectorTable */
|
||||
KEEP(*(.ram_user_define_irq_table)) /* 0x10000100: UserIrqFunTable */
|
||||
KEEP(*(.ram_user_define_data_table)) /* 0x10000200: UserIrqDataTable */
|
||||
__rom_bss_start__ = .;
|
||||
KEEP(*(.hal.ram.bss)) /* 0x10000300: CfgSysDebugWarn .. _pHAL_Gpio_Adapter */
|
||||
KEEP(*(.timer2_7_vector_table.data)) /* 0x10000358: Timer2To7VectorTable */
|
||||
KEEP(*(.infra.ram.bss)) /* 0x10000370: first .. z4 */
|
||||
KEEP(*(.mon.ram.bss)) /* 0x10000384: pUartLogCtl .. ArgvArray */
|
||||
KEEP(*(.wlan_ram_map)) /* 0x100006d4: rom_wlan_ram_map, FalseAlmCnt, ROMInfo, DM_CfoTrack */
|
||||
KEEP(*(.ram.rom.wlanmap)) /* align(8) */
|
||||
KEEP(*(.libc.ram.bss)) /* 0x10000760: rom_libgloss_ram_map __rtl_malloc_av_ __rtl_errno */
|
||||
__rom_bss_end__ = .;
|
||||
} > ROM_USED_RAM
|
||||
|
||||
/* 0x10000bc8: bootloader */
|
||||
|
||||
.ram_image1.text . : /* use in rom & boot */
|
||||
{
|
||||
/* __ram_start_table_start__ = .; */
|
||||
__ram_image1_text_start__ = .;
|
||||
KEEP(*rtl_boot*.o(.start.ram.data*))
|
||||
/* __image1_validate_code__ = .; */
|
||||
KEEP(*(.image1.validate.rodata))
|
||||
|
||||
KEEP(*(.infra.ram.data*))
|
||||
KEEP(*(.timer.ram.data*))
|
||||
KEEP(*(.cutb.ram.data*))
|
||||
KEEP(*(.cutc.ram.data*))
|
||||
KEEP(*(.libc.reent))
|
||||
KEEP(*(.rom.unc.data))
|
||||
KEEP(*(.sdr.rand2.data))
|
||||
|
||||
PROVIDE (__ram_image_end__ = .); /* 0x100020c0: end */
|
||||
|
||||
/* boot & images data */
|
||||
|
||||
KEEP(*(.hal.ram.data))
|
||||
KEEP(*(.hal.flash.data))
|
||||
KEEP(*rtl_boot*.o(.rodata*))
|
||||
KEEP(*rtl_boot*.o(.text*))
|
||||
KEEP(*rtl_boot*.o(.data*))
|
||||
__image1_bss_start__ = .;
|
||||
KEEP(*rtl_boot*.o(.bss*))
|
||||
__image1_bss_end__ = .;
|
||||
__ram_image1_text_end__ = .;
|
||||
|
||||
} > BOOT_RAM
|
||||
|
||||
.romheap :
|
||||
{
|
||||
__rom_heap_start__ = .;
|
||||
end = __rom_heap_start__;
|
||||
. = ALIGN(0x1000);
|
||||
__rom_heap_end__ = .;
|
||||
} > ROM_HEAP
|
||||
|
||||
.ram_heap1 :
|
||||
{
|
||||
__ram_heap1_start__ = .;
|
||||
/* *(.heap1*) */
|
||||
} > RAM_HEAP1
|
||||
|
||||
.tcm :
|
||||
{
|
||||
__ram_tcm_start__ = .;
|
||||
__tcm_heap_start__ = .;
|
||||
*(.tcm.heap)
|
||||
} > TCM
|
||||
|
||||
.soc_ps_monitor :
|
||||
{
|
||||
__tcm_heap_end__ = .;
|
||||
} > TCM_TAB
|
||||
|
||||
.image2.start.table :
|
||||
{
|
||||
__ram_heap1_end__ = .;
|
||||
__ram_image2_text_start__ = .;
|
||||
__image2_entry_func__ = .;
|
||||
.image2.start.table1$$Base = .;
|
||||
KEEP(*(SORT(.image2.ram.data*)))
|
||||
__image2_validate_code__ = .;
|
||||
KEEP(*(.image2.validate.rodata*))
|
||||
KEEP(*(.custom.validate.rodata*))
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.text :
|
||||
{
|
||||
*(.infra.ram.start*)
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
|
||||
/* init data */
|
||||
. = ALIGN(4);
|
||||
PROVIDE (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE (__init_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE (__fini_array_end = .);
|
||||
|
||||
*(.mon.ram.text*)
|
||||
*(.hal.flash.text*)
|
||||
*(.hal.sdrc.text*)
|
||||
*(.hal.gpio.text*)
|
||||
*(.fwu.text*)
|
||||
*(.otg.rom.text*)
|
||||
*(.text*)
|
||||
*(.sdram.text*)
|
||||
*(.p2p.text*)
|
||||
*(.wps.text*)
|
||||
*(.websocket.text*)
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.rodata :
|
||||
{
|
||||
*(.rodata*)
|
||||
*(.fwu.rodata*)
|
||||
*(.sdram.rodata*)
|
||||
*(.p2p.rodata*)
|
||||
*(.wps.rodata*)
|
||||
*(.websocket.rodata*)
|
||||
. = ALIGN(4);
|
||||
xHeapRegions = .;
|
||||
LONG(__ram_heap1_start__)
|
||||
LONG(__ram_heap1_end__ - __ram_heap1_start__)
|
||||
LONG(__ram_heap2_start__)
|
||||
LONG(__ram_heap2_end__ - __ram_heap2_start__)
|
||||
LONG(__sdram_heap_start__)
|
||||
LONG(__sdram_heap_end__ - __sdram_heap_start__)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
UartLogRamCmdTable = .;
|
||||
KEEP(*(SORT(.mon.tab*)))
|
||||
UartLogRamCmdTable_end = .;
|
||||
LONG(0)
|
||||
} > BD_RAM
|
||||
|
||||
PROVIDE(UartLogRamCmdTableSize = UartLogRamCmdTable_end - UartLogRamCmdTable);
|
||||
|
||||
.ram.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(.data*)
|
||||
*(.p2p.data*)
|
||||
*(.wps.data*)
|
||||
*(.websocket.data*)
|
||||
*(.sdram.data*)
|
||||
__data_end__ = .;
|
||||
__ram_image2_text_end__ = .;
|
||||
} > BD_RAM
|
||||
|
||||
.ram.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
.ram.bss$$Base = .;
|
||||
*(.hal.flash.data*)
|
||||
*(.hal.sdrc.data*)
|
||||
*(.hal.gpio.data*)
|
||||
*(.fwu.data*)
|
||||
*(.bdsram.data*)
|
||||
*(.bfsram.data*)
|
||||
*(COMMON)
|
||||
*(.bss*)
|
||||
*(.sdram.bss*)
|
||||
*(.p2p.bss*)
|
||||
*(.wps.bss*)
|
||||
*(.websocket.bss*)
|
||||
*(.ssl_ram_map*)
|
||||
__bss_end__ = .;
|
||||
.ram.bss$$Limit = .;
|
||||
|
||||
} > BD_RAM
|
||||
|
||||
.ram_heap2 :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__ram_heap2_start__ = .;
|
||||
*(.heap*) /* ucHeap */
|
||||
} > BD_RAM
|
||||
__ram_heap2_end__ = 0x10070000;
|
||||
|
||||
.sdr_text :
|
||||
{
|
||||
__sdram_data_start__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_rodata :
|
||||
{
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_data :
|
||||
{
|
||||
__sdram_data_end__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_bss :
|
||||
{
|
||||
__sdram_bss_start__ = .;
|
||||
__sdram_bss_end__ = .;
|
||||
. = ALIGN(8);
|
||||
__sdram_heap_start__ = .;
|
||||
} > SDRAM_RAM
|
||||
__sdram_heap_end__ = 0x30200000;
|
||||
|
||||
.boot.head :
|
||||
{
|
||||
KEEP(*(.loader.head*))
|
||||
}
|
||||
ASSERT(__ram_image_end__ == 0x100020c0, "Error rom-bios-boot code & data!")
|
||||
}
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
|
||||
/* ENTRY(Reset_Handler) */
|
||||
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 1M
|
||||
SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 448K
|
||||
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 65K
|
||||
SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.rom :
|
||||
{
|
||||
__rom_image_start__ = .;
|
||||
KEEP(*(.rom));
|
||||
__rom_image_end__ = .;
|
||||
|
||||
} > ROM
|
||||
|
||||
.sram : /* use in rom */
|
||||
{
|
||||
__ram_image_start__ = .;
|
||||
KEEP(*(.ram_dedecated_vector_table)) /* 0x10000000: NewVectorTable */
|
||||
KEEP(*(.ram_user_define_irq_table)) /* 0x10000100: UserIrqFunTable */
|
||||
KEEP(*(.ram_user_define_data_table)) /* 0x10000200: UserIrqDataTable */
|
||||
/* __rom_bss_start__ = .; */
|
||||
KEEP(*(.hal.ram.bss)) /* 0x10000300: CfgSysDebugWarn .. _pHAL_Gpio_Adapter */
|
||||
KEEP(*(.timer2_7_vector_table.data)) /* 0x10000358: Timer2To7VectorTable */
|
||||
KEEP(*(.infra.ram.bss)) /* 0x10000370: first .. z4 */
|
||||
KEEP(*(.mon.ram.bss)) /* 0x10000384: pUartLogCtl .. ArgvArray */
|
||||
KEEP(*(.wlan_ram_map)) /* 0x100006d4: rom_wlan_ram_map, FalseAlmCnt, ROMInfo, DM_CfoTrack */
|
||||
KEEP(*(.ram.rom.wlanmap)) /* align(8) */
|
||||
KEEP(*(.libc.ram.bss)) /* 0x10000760: rom_libgloss_ram_map __rtl_malloc_av_ __rtl_errno */
|
||||
/* __rom_bss_end__ = .; */
|
||||
/* __ram_start_table_start__ = .; */
|
||||
/* 0x10000bc8: bootloader */
|
||||
KEEP(*(SORT(.start.ram.data*)))
|
||||
/* __image1_validate_code__ = .; */
|
||||
KEEP(*(.image1.validate.rodata))
|
||||
|
||||
KEEP(*(.infra.ram.data*))
|
||||
KEEP(*(.timer.ram.data*))
|
||||
KEEP(*(.cutb.ram.data*))
|
||||
KEEP(*(.cutc.ram.data*))
|
||||
KEEP(*(.data));
|
||||
KEEP(*(.hal.ram.data)) /* 0x10001c60: _reent *rtl_impure_ptr */ /* 0x10001c68: _reent impure_data */
|
||||
KEEP(*(.libc.reent))
|
||||
KEEP(*(.rom.unc.data))
|
||||
KEEP(*(.sdr.rand2.data)) /* Sdr_Rand2() y,z,c */
|
||||
/* KEEP(*(.hal.flash.data)) */
|
||||
/* 0x100020c0: end ram-rom */
|
||||
__ram_image_end__ = .;
|
||||
} > SRAM
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__rom_bss_start__ = 0x10000300; /* use in rom */
|
||||
__rom_bss_end__ = 0x10000bc8; /* use in rom */
|
||||
__ram_start_table_start__ = 0x10000bc8; /* use in rom */
|
||||
__image1_validate_code__ = 0x10000bdc; /* needed by ram code */
|
||||
_rtl_impure_ptr = 0x10001c60; /* for standard library */
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,240 @@
|
|||
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
INCLUDE "export-rom_v04.txt"
|
||||
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ROM (rx) : ORIGIN = 0x000000, LENGTH = 1M
|
||||
ROM_RAM1 (rwx): ORIGIN = 0x10000000, LENGTH = 0x2100 /* end 0x10002100 */
|
||||
BOOT_RAM (rwx): ORIGIN = 0x10000bc8, LENGTH = 13368 /* end 0x10006000 */
|
||||
RECY_RAM (rwx): ORIGIN = 0x10002100, LENGTH = 0x3F00 /* end 0x10006000 */
|
||||
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 424K /* end 0x10070000 */
|
||||
ROM_RAM3 (rwx): ORIGIN = 0x1006D000, LENGTH = 12K /* end 0x10070000 */
|
||||
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64K /* end 0x20000000 */
|
||||
SDRAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M /* end 0x30200000 */
|
||||
}
|
||||
|
||||
EXTERN(PreProcessForVendor)
|
||||
EXTERN(RtlBootToSram)
|
||||
EXTERN(_rtl_impure_ptr)
|
||||
EXTERN(impure_data)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* 0x00000000: ROM */
|
||||
|
||||
.rom :
|
||||
{
|
||||
__rom_image_start__ = .;
|
||||
KEEP(*(.rom));
|
||||
__rom_image_end__ = .;
|
||||
} > ROM
|
||||
|
||||
/* 0x10000000: SRAM */
|
||||
|
||||
.rom_ram : /* use in rom */
|
||||
{
|
||||
__ram_image_start__ = .;
|
||||
KEEP(*(.ram_dedecated_vector_table)) /* 0x10000000: NewVectorTable */
|
||||
KEEP(*(.ram_user_define_irq_table)) /* 0x10000100: UserIrqFunTable */
|
||||
KEEP(*(.ram_user_define_data_table)) /* 0x10000200: UserIrqDataTable */
|
||||
/* __rom_bss_start__ = .; */
|
||||
KEEP(*(.hal.ram.bss)) /* 0x10000300: CfgSysDebugWarn .. _pHAL_Gpio_Adapter */
|
||||
KEEP(*(.timer2_7_vector_table.data)) /* 0x10000358: Timer2To7VectorTable */
|
||||
KEEP(*(.infra.ram.bss)) /* 0x10000370: first .. z4 */
|
||||
KEEP(*(.mon.ram.bss)) /* 0x10000384: pUartLogCtl .. ArgvArray */
|
||||
KEEP(*(.wlan_ram_map)) /* 0x100006d4: rom_wlan_ram_map, FalseAlmCnt, ROMInfo, DM_CfoTrack */
|
||||
KEEP(*(.ram.rom.wlanmap)) /* align(8) */
|
||||
KEEP(*(.libc.ram.bss)) /* 0x10000760: rom_libgloss_ram_map __rtl_malloc_av_ __rtl_errno */
|
||||
/* __rom_bss_end__ = .; */
|
||||
} > ROM_RAM1
|
||||
|
||||
/* 0x10000bc8: bootloader */
|
||||
.ram_image1.text . : /* use in rom & boot */
|
||||
{
|
||||
/* __ram_start_table_start__ = .; */
|
||||
__ram_image1_text_start__ = .;
|
||||
KEEP(*(SORT(.start.ram.data*)))
|
||||
/* __image1_validate_code__ = .; */
|
||||
KEEP(*(.image1.validate.rodata))
|
||||
|
||||
KEEP(*(.infra.ram.data*))
|
||||
KEEP(*(.timer.ram.data*))
|
||||
KEEP(*(.cutb.ram.data*))
|
||||
KEEP(*(.cutc.ram.data*))
|
||||
KEEP(*(.data));
|
||||
KEEP(*(.hal.ram.data))
|
||||
KEEP(*(.libc.reent))
|
||||
KEEP(*(.rom.unc.data))
|
||||
KEEP(*(.sdr.rand2.data))
|
||||
build/obj/project/src/user/rtl_bios_data.o (.rodata*)
|
||||
__ram_image_end__ = .;
|
||||
/* 0x100020c0: end */
|
||||
build/obj/project/src/user/rtl_boot.o (.text* .rodata*)
|
||||
__image1_bss_start__ = .;
|
||||
__image1_bss_end__ = .;
|
||||
__ram_image1_text_end__ = .;
|
||||
} > BOOT_RAM
|
||||
|
||||
.tcm :
|
||||
{
|
||||
__tcm_start__ = .;
|
||||
*(.tcm.heap)
|
||||
__tcm_end__ = .;
|
||||
} > TCM
|
||||
|
||||
.image2.start.table :
|
||||
{
|
||||
__ram_image2_text_start__ = .;
|
||||
__image2_entry_func__ = .;
|
||||
.image2.start.table1$$Base = .;
|
||||
KEEP(*(SORT(.image2.ram.data*)))
|
||||
__image2_validate_code__ = .;
|
||||
KEEP(*(.image2.validate.rodata*))
|
||||
KEEP(*(.custom.validate.rodata*))
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.text :
|
||||
{
|
||||
*(.infra.ram.start*)
|
||||
*(.mon.ram.text*)
|
||||
*(.hal.flash.text*)
|
||||
*(.hal.sdrc.text*)
|
||||
*(.hal.gpio.text*)
|
||||
*(.fwu.text*)
|
||||
*(.text*)
|
||||
*(.sdram.text*)
|
||||
*(.p2p.text*)
|
||||
*(.wps.text*)
|
||||
*(.websocket.text*)
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.rodata :
|
||||
{
|
||||
*(.rodata*)
|
||||
*(.fwu.rodata*)
|
||||
*(.sdram.rodata*)
|
||||
*(.p2p.rodata*)
|
||||
*(.wps.rodata*)
|
||||
*(.websocket.rodata*)
|
||||
} > BD_RAM
|
||||
|
||||
.ram.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(.data*)
|
||||
*(.sdram.data*)
|
||||
*(.p2p.data*)
|
||||
*(.wps.data*)
|
||||
*(.websocket.data*)
|
||||
__data_end__ = .;
|
||||
__ram_image2_text_end__ = .;
|
||||
} > BD_RAM
|
||||
|
||||
.ram.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
.ram.bss$$Base = .;
|
||||
*(.hal.flash.data*)
|
||||
*(.hal.sdrc.data*)
|
||||
*(.hal.gpio.data*)
|
||||
*(.fwu.data*)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
*(.bdsram.data*)
|
||||
*(.sdram.bss*)
|
||||
*(.p2p.bss*)
|
||||
*(.wps.bss*)
|
||||
*(.websocket.bss*)
|
||||
__bss_end__ = .;
|
||||
.ram.bss$$Limit = .;
|
||||
} > BD_RAM
|
||||
|
||||
.bf_data :
|
||||
{
|
||||
__buffer_data_start__ = .;
|
||||
*(.bfsram.data*)
|
||||
__buffer_data_end__ = .;
|
||||
} > BD_RAM
|
||||
|
||||
.bf_data2 :
|
||||
{
|
||||
__buffer_data_start2__ = .;
|
||||
__buffer_data_end2__ = .;
|
||||
|
||||
} > RECY_RAM
|
||||
|
||||
.sdr_text :
|
||||
{
|
||||
__sdram_data_start__ = .;
|
||||
} > SDRAM
|
||||
|
||||
.sdr_rodata :
|
||||
{
|
||||
} > SDRAM
|
||||
|
||||
.sdr_data :
|
||||
{
|
||||
__sdram_data_end__ = .;
|
||||
} > SDRAM
|
||||
|
||||
.sdr_bss :
|
||||
{
|
||||
__sdram_bss_start__ = .;
|
||||
__sdram_bss_end__ = .;
|
||||
} > SDRAM
|
||||
|
||||
.heap :
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > BD_RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy :
|
||||
{
|
||||
*(.stack)
|
||||
} > BD_RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(BD_RAM) + LENGTH(BD_RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
|
||||
.boot.head :
|
||||
{
|
||||
KEEP(*(.loader.head*))
|
||||
}
|
||||
|
||||
.image1.head :
|
||||
{
|
||||
KEEP(*(SORT(.image1.head*)))
|
||||
}
|
||||
|
||||
.image2.head :
|
||||
{
|
||||
KEEP(*(SORT(.image2.head*)))
|
||||
}
|
||||
|
||||
.image3.head :
|
||||
{
|
||||
KEEP(*(SORT(.image3.head*)))
|
||||
}
|
||||
|
||||
.image4.head :
|
||||
{
|
||||
KEEP(*(SORT(.image4.head*)))
|
||||
}
|
||||
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
sdk/component/soc/realtek/8195a/misc/bsp/lib/va0/rom.a
Normal file
BIN
sdk/component/soc/realtek/8195a/misc/bsp/lib/va0/rom.a
Normal file
Binary file not shown.
46
sdk/component/soc/realtek/8195a/misc/driver/low_level_io.c
Normal file
46
sdk/component/soc/realtek/8195a/misc/driver/low_level_io.c
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
#include <stdio.h>
|
||||
#include "hal_api.h"
|
||||
|
||||
#if !defined (__ICCARM__)
|
||||
extern u8 RAM_IMG1_VALID_PATTEN[];
|
||||
void *tmp = RAM_IMG1_VALID_PATTEN;
|
||||
#endif
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
size_t __write(int Handle, const unsigned char * Buf, size_t Bufsize)
|
||||
{
|
||||
int nChars = 0;
|
||||
/* Check for stdout and stderr
|
||||
(only necessary if file descriptors are enabled.) */
|
||||
if (Handle != 1 && Handle != 2)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
for (/*Empty */; Bufsize > 0; --Bufsize)
|
||||
{
|
||||
DiagPutChar(*Buf++);
|
||||
++nChars;
|
||||
}
|
||||
return nChars;
|
||||
}
|
||||
|
||||
size_t __read(int Handle, unsigned char * Buf, size_t Bufsize)
|
||||
{
|
||||
int nChars = 0;
|
||||
/* Check for stdin
|
||||
(only necessary if FILE descriptors are enabled) */
|
||||
if (Handle != 0)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
for (/*Empty*/; Bufsize > 0; --Bufsize)
|
||||
{
|
||||
int c = DiagGetChar(_FALSE);
|
||||
if (c < 0)
|
||||
break;
|
||||
*(Buf++) = c;
|
||||
++nChars;
|
||||
}
|
||||
return nChars;
|
||||
}
|
||||
#endif
|
||||
365
sdk/component/soc/realtek/8195a/misc/driver/rtl_consol.c
Normal file
365
sdk/component/soc/realtek/8195a/misc/driver/rtl_consol.c
Normal file
|
|
@ -0,0 +1,365 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
#include "rtl8195a.h"
|
||||
//#include <stdarg.h>
|
||||
#include "rtl_bios_data.h"
|
||||
//#include "rtl_consol.h"
|
||||
#include "osdep_api.h"
|
||||
#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1)
|
||||
#include "freertos_pmu.h"
|
||||
#endif
|
||||
#include "tcm_heap.h"
|
||||
|
||||
//MON_RAM_BSS_SECTION UART_LOG_CTL UartLogCtl;
|
||||
//MON_RAM_BSS_SECTION UART_LOG_CTL *pUartLogCtl;
|
||||
//MON_RAM_BSS_SECTION u8 *ArgvArray[MAX_ARGV];
|
||||
//MON_RAM_BSS_SECTION UART_LOG_BUF UartLogBuf;
|
||||
|
||||
|
||||
#ifdef CONFIG_UART_LOG_HISTORY
|
||||
//MON_RAM_BSS_SECTION u8 UartLogHistoryBuf[UART_LOG_HISTORY_LEN][UART_LOG_CMD_BUFLEN];
|
||||
#endif
|
||||
|
||||
_LONG_CALL_
|
||||
extern u8
|
||||
UartLogCmdChk(
|
||||
IN u8 RevData,
|
||||
IN UART_LOG_CTL *prvUartLogCtl,
|
||||
IN u8 EchoFlag
|
||||
);
|
||||
|
||||
_LONG_CALL_
|
||||
extern VOID
|
||||
ArrayInitialize(
|
||||
IN u8 *pArrayToInit,
|
||||
IN u8 ArrayLen,
|
||||
IN u8 InitValue
|
||||
);
|
||||
|
||||
_LONG_CALL_
|
||||
extern VOID
|
||||
UartLogHistoryCmd(
|
||||
IN u8 RevData,
|
||||
IN UART_LOG_CTL *prvUartLogCtl,
|
||||
IN u8 EchoFlag
|
||||
);
|
||||
|
||||
_LONG_CALL_
|
||||
extern VOID
|
||||
UartLogCmdExecute(
|
||||
IN PUART_LOG_CTL pUartLogCtlExe
|
||||
);
|
||||
|
||||
|
||||
|
||||
//=================================================
|
||||
|
||||
|
||||
/* Minimum and maximum values a `signed long int' can hold.
|
||||
(Same as `int'). */
|
||||
#ifndef __LONG_MAX__
|
||||
#if defined (__alpha__) || (defined (__sparc__) && defined(__arch64__)) || defined (__sparcv9) || defined (__s390x__)
|
||||
#define __LONG_MAX__ 9223372036854775807L
|
||||
#else
|
||||
#define __LONG_MAX__ 2147483647L
|
||||
#endif /* __alpha__ || sparc64 */
|
||||
#endif
|
||||
#undef LONG_MIN
|
||||
#define LONG_MIN (-LONG_MAX-1)
|
||||
#undef LONG_MAX
|
||||
#define LONG_MAX __LONG_MAX__
|
||||
|
||||
/* Maximum value an `unsigned long int' can hold. (Minimum is 0). */
|
||||
#undef ULONG_MAX
|
||||
#define ULONG_MAX (LONG_MAX * 2UL + 1)
|
||||
|
||||
#ifndef __LONG_LONG_MAX__
|
||||
#define __LONG_LONG_MAX__ 9223372036854775807LL
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
//======================================================
|
||||
//<Function>: UartLogIrqHandleRam
|
||||
//<Usage >: To deal with Uart-Log RX IRQ
|
||||
//<Argus >: VOID
|
||||
//<Return >: VOID
|
||||
//<Notes >: NA
|
||||
//======================================================
|
||||
MON_RAM_TEXT_SECTION
|
||||
VOID
|
||||
UartLogIrqHandleRam
|
||||
(
|
||||
VOID * Data
|
||||
)
|
||||
{
|
||||
u8 UartReceiveData = 0;
|
||||
//For Test
|
||||
BOOL PullMode = _FALSE;
|
||||
|
||||
u32 IrqEn = DiagGetIsrEnReg();
|
||||
|
||||
DiagSetIsrEnReg(0);
|
||||
|
||||
UartReceiveData = DiagGetChar(PullMode);
|
||||
if (UartReceiveData == 0) {
|
||||
goto exit;
|
||||
}
|
||||
|
||||
//KB_ESC chk is for cmd history, it's a special case here.
|
||||
if (UartReceiveData == KB_ASCII_ESC) {
|
||||
//4 Esc detection is only valid in the first stage of boot sequence (few seconds)
|
||||
if (pUartLogCtl->ExecuteEsc != _TRUE)
|
||||
{
|
||||
pUartLogCtl->ExecuteEsc = _TRUE;
|
||||
(*pUartLogCtl).EscSTS = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
//4 the input commands are valid only when the task is ready to execute commands
|
||||
if ((pUartLogCtl->BootRdy == 1)
|
||||
#ifdef CONFIG_KERNEL
|
||||
||(pUartLogCtl->TaskRdy == 1)
|
||||
#endif
|
||||
)
|
||||
{
|
||||
if ((*pUartLogCtl).EscSTS==0)
|
||||
{
|
||||
(*pUartLogCtl).EscSTS = 1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
(*pUartLogCtl).EscSTS = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if ((*pUartLogCtl).EscSTS==1){
|
||||
if (UartReceiveData != KB_ASCII_LBRKT){
|
||||
(*pUartLogCtl).EscSTS = 0;
|
||||
}
|
||||
else{
|
||||
(*pUartLogCtl).EscSTS = 2;
|
||||
}
|
||||
}
|
||||
|
||||
else{
|
||||
if ((*pUartLogCtl).EscSTS==2){
|
||||
(*pUartLogCtl).EscSTS = 0;
|
||||
#ifdef CONFIG_UART_LOG_HISTORY
|
||||
if ((UartReceiveData=='A')|| UartReceiveData=='B'){
|
||||
UartLogHistoryCmd(UartReceiveData,(UART_LOG_CTL *)pUartLogCtl,1);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else{
|
||||
if (UartLogCmdChk(UartReceiveData,(UART_LOG_CTL *)pUartLogCtl,1)==2)
|
||||
{
|
||||
//4 check UartLog buffer to prevent from incorrect access
|
||||
if (pUartLogCtl->pTmpLogBuf != NULL)
|
||||
{
|
||||
pUartLogCtl->ExecuteCmd = _TRUE;
|
||||
#if defined(CONFIG_KERNEL) && !TASK_SCHEDULER_DISABLED
|
||||
if (pUartLogCtl->TaskRdy)
|
||||
RtlUpSemaFromISR((_Sema *)&pUartLogCtl->Sema);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
ArrayInitialize((u8 *)pUartLogCtl->pTmpLogBuf->UARTLogBuf, UART_LOG_CMD_BUFLEN, '\0');
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
exit:
|
||||
DiagSetIsrEnReg(IrqEn);
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
MON_RAM_TEXT_SECTION
|
||||
VOID
|
||||
RtlConsolInitRam(
|
||||
IN u32 Boot,
|
||||
IN u32 TBLSz,
|
||||
IN VOID *pTBL
|
||||
)
|
||||
{
|
||||
UartLogBuf.BufCount = 0;
|
||||
ArrayInitialize(&UartLogBuf.UARTLogBuf[0],UART_LOG_CMD_BUFLEN,'\0');
|
||||
pUartLogCtl = &UartLogCtl;
|
||||
|
||||
pUartLogCtl->NewIdx = 0;
|
||||
pUartLogCtl->SeeIdx = 0;
|
||||
pUartLogCtl->RevdNo = 0;
|
||||
pUartLogCtl->EscSTS = 0;
|
||||
pUartLogCtl->BootRdy = 0;
|
||||
pUartLogCtl->pTmpLogBuf = &UartLogBuf;
|
||||
#ifdef CONFIG_UART_LOG_HISTORY
|
||||
pUartLogCtl->CRSTS = 0;
|
||||
pUartLogCtl->pHistoryBuf = &UartLogHistoryBuf[0];
|
||||
#endif
|
||||
pUartLogCtl->pfINPUT = (VOID*)&DiagPrintf;
|
||||
pUartLogCtl->pCmdTbl = (PCOMMAND_TABLE) pTBL;
|
||||
pUartLogCtl->CmdTblSz = TBLSz;
|
||||
#ifdef CONFIG_KERNEL
|
||||
pUartLogCtl->TaskRdy = 0;
|
||||
#endif
|
||||
//executing boot sequence
|
||||
if (Boot == ROM_STAGE)
|
||||
{
|
||||
pUartLogCtl->ExecuteCmd = _FALSE;
|
||||
pUartLogCtl->ExecuteEsc = _FALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
pUartLogCtl->ExecuteCmd = _FALSE;
|
||||
pUartLogCtl->ExecuteEsc= _TRUE; //don't check Esc anymore
|
||||
#if defined(CONFIG_KERNEL)
|
||||
/* Create a Semaphone */
|
||||
RtlInitSema((_Sema*)&(pUartLogCtl->Sema), 0);
|
||||
pUartLogCtl->TaskRdy = 0;
|
||||
#ifdef PLATFORM_FREERTOS
|
||||
#define LOGUART_STACK_SIZE 200 //USE_MIN_STACK_SIZE modify from 512 to 128
|
||||
#if 0 //CONFIG_USE_TCM_HEAP
|
||||
{
|
||||
int ret = 0;
|
||||
void *stack_addr = tcm_heap_malloc(LOGUART_STACK_SIZE*sizeof(int));
|
||||
//void *stack_addr = rtw_malloc(stack_size*sizeof(int));
|
||||
if(stack_addr == NULL){
|
||||
DiagPrintf("Out of TCM heap in \"LOGUART_TASK\" ");
|
||||
}
|
||||
ret = xTaskGenericCreate(
|
||||
RtlConsolTaskRam,
|
||||
(const char *)"log_uart",
|
||||
LOGUART_STACK_SIZE,
|
||||
NULL,
|
||||
tskIDLE_PRIORITY + 5 + PRIORITIE_OFFSET, // +5
|
||||
NULL,
|
||||
stack_addr,
|
||||
NULL);
|
||||
if (pdTRUE != ret)
|
||||
{
|
||||
DiagPrintf("Create Log UART Task Err!\n");
|
||||
}
|
||||
}
|
||||
#else
|
||||
if (pdTRUE != xTaskCreate( RtlConsolTaskRam, (const signed char * const)"log_uart", LOGUART_STACK_SIZE, NULL, tskIDLE_PRIORITY + 5 + PRIORITIE_OFFSET, NULL))
|
||||
{
|
||||
DiagPrintf("Create Log UART Task Err!\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
CONSOLE_8195A();
|
||||
}
|
||||
|
||||
#if SUPPORT_LOG_SERVICE
|
||||
extern char log_buf[LOG_SERVICE_BUFLEN];
|
||||
extern xSemaphoreHandle log_rx_interrupt_sema;
|
||||
#endif
|
||||
//======================================================
|
||||
void console_cmd_exec(PUART_LOG_CTL pUartLogCtlExe)
|
||||
{
|
||||
u8 CmdCnt = 0;
|
||||
u8 argc = 0;
|
||||
u8 **argv;
|
||||
//u32 CmdNum;
|
||||
PUART_LOG_BUF pUartLogBuf = pUartLogCtlExe->pTmpLogBuf;
|
||||
#if SUPPORT_LOG_SERVICE
|
||||
strncpy(log_buf, (const u8*)&(*pUartLogBuf).UARTLogBuf[0], LOG_SERVICE_BUFLEN-1);
|
||||
#endif
|
||||
argc = GetArgc((const u8*)&((*pUartLogBuf).UARTLogBuf[0]));
|
||||
argv = GetArgv((const u8*)&((*pUartLogBuf).UARTLogBuf[0]));
|
||||
|
||||
if(argc > 0){
|
||||
#if SUPPORT_LOG_SERVICE
|
||||
// if(log_handler(argv[0]) == NULL)
|
||||
// legency_interactive_handler(argc, argv);
|
||||
RtlUpSema((_Sema *)&log_rx_interrupt_sema);
|
||||
#endif
|
||||
ArrayInitialize(argv[0], sizeof(argv[0]) ,0);
|
||||
}else{
|
||||
#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1)
|
||||
acquire_wakelock(WAKELOCK_LOGUART);
|
||||
#endif
|
||||
CONSOLE_8195A(); // for null command
|
||||
}
|
||||
|
||||
(*pUartLogBuf).BufCount = 0;
|
||||
ArrayInitialize(&(*pUartLogBuf).UARTLogBuf[0], UART_LOG_CMD_BUFLEN, '\0');
|
||||
}
|
||||
//======================================================
|
||||
// overload original RtlConsolTaskRam
|
||||
MON_RAM_TEXT_SECTION
|
||||
VOID
|
||||
RtlConsolTaskRam(
|
||||
VOID *Data
|
||||
)
|
||||
{
|
||||
#if SUPPORT_LOG_SERVICE
|
||||
log_service_init();
|
||||
#else
|
||||
#ifdef CONFIG_AT_USR
|
||||
at_user_init();
|
||||
#endif
|
||||
#endif
|
||||
//4 Set this for UartLog check cmd history
|
||||
#ifdef CONFIG_KERNEL
|
||||
pUartLogCtl->TaskRdy = 1;
|
||||
#else
|
||||
pUartLogCtl->BootRdy = 1;
|
||||
#endif
|
||||
do{
|
||||
#if defined(CONFIG_KERNEL) && !TASK_SCHEDULER_DISABLED
|
||||
RtlDownSema((_Sema *)&pUartLogCtl->Sema);
|
||||
#endif
|
||||
if (pUartLogCtl->ExecuteCmd) {
|
||||
// Add command handler here
|
||||
console_cmd_exec((PUART_LOG_CTL)pUartLogCtl);
|
||||
//UartLogCmdExecute((PUART_LOG_CTL)pUartLogCtl);
|
||||
pUartLogCtl->ExecuteCmd = _FALSE;
|
||||
}
|
||||
}while(1);
|
||||
}
|
||||
extern void * UartLogRomCmdTable;
|
||||
//======================================================
|
||||
void console_init(void)
|
||||
{
|
||||
IRQ_HANDLE UartIrqHandle;
|
||||
|
||||
//4 Register Log Uart Callback function
|
||||
UartIrqHandle.Data = 0;//(u32)&UartAdapter;
|
||||
UartIrqHandle.IrqNum = UART_LOG_IRQ;
|
||||
UartIrqHandle.IrqFun = (IRQ_FUN) UartLogIrqHandleRam;
|
||||
UartIrqHandle.Priority = 0; // ??
|
||||
|
||||
|
||||
//4 Register Isr handle
|
||||
InterruptUnRegister(&UartIrqHandle);
|
||||
InterruptRegister(&UartIrqHandle);
|
||||
#if !TASK_SCHEDULER_DISABLED
|
||||
// RtlConsolInitRam((u32)ROM_STAGE,(u32)0,(VOID*)NULL);
|
||||
RtlConsolInitRam((u32)RAM_STAGE,(u32)6,(VOID*)UartLogRomCmdTable); // ); NULL);
|
||||
#else
|
||||
RtlConsolInitRam((u32)RAM_STAGE,(u32)6,(VOID*)UartLogRomCmdTable); // ); NULL);
|
||||
// RtlConsolInitRam((u32)ROM_STAGE,(u32)0,(VOID*)NULL);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
136
sdk/component/soc/realtek/8195a/misc/driver/rtl_consol.h
Normal file
136
sdk/component/soc/realtek/8195a/misc/driver/rtl_consol.h
Normal file
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
#ifndef _RTK_CONSOL_H_
|
||||
#define _RTK_CONSOL_H_
|
||||
/*
|
||||
* Include user defined options first. Anything not defined in these files
|
||||
* will be set to standard values. Override anything you dont like!
|
||||
*/
|
||||
#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
|
||||
#include "platform_opts.h"
|
||||
#endif
|
||||
|
||||
#include "osdep_api.h"
|
||||
#include "hal_diag.h"
|
||||
|
||||
#define CONSOLE_PREFIX "#"
|
||||
|
||||
|
||||
//Log UART
|
||||
//UART_LOG_CMD_BUFLEN: only 126 bytes could be used for keeping input
|
||||
// cmd, the last byte is for string end ('\0').
|
||||
#define UART_LOG_CMD_BUFLEN 127
|
||||
#define MAX_ARGV 10
|
||||
|
||||
//extern COMMAND_TABLE UartLogRomCmdTable[6]; // in ROM (hal_diag.h)
|
||||
|
||||
typedef u32 (*ECHOFUNC)(IN u8*,...); //UART LOG echo-function type.
|
||||
|
||||
typedef struct _UART_LOG_BUF_ {
|
||||
u8 BufCount; //record the input cmd char number.
|
||||
u8 UARTLogBuf[UART_LOG_CMD_BUFLEN]; //record the input command.
|
||||
} UART_LOG_BUF, *PUART_LOG_BUF;
|
||||
|
||||
|
||||
typedef struct _UART_LOG_CTL_ {
|
||||
u8 NewIdx; //+0x00
|
||||
u8 SeeIdx; //+0x01
|
||||
u8 RevdNo; //+0x02
|
||||
u8 EscSTS; //+0x03
|
||||
u8 ExecuteCmd; //+0x04
|
||||
u8 ExecuteEsc; //+0x05
|
||||
u8 BootRdy; //+0x06
|
||||
u8 Resvd; //+0x07
|
||||
PUART_LOG_BUF pTmpLogBuf; //+0x08 = UartLogBuf
|
||||
VOID *pfINPUT; //+0x0C = DiagPrintf
|
||||
PCOMMAND_TABLE pCmdTbl; //+0x10
|
||||
u32 CmdTblSz; //+0x14
|
||||
#ifdef CONFIG_UART_LOG_HISTORY
|
||||
u32 CRSTS; //+0x18
|
||||
u8 (*pHistoryBuf)[UART_LOG_CMD_BUFLEN]; //+0x1C UartLogHistoryBuf[UART_LOG_HISTORY_LEN][UART_LOG_CMD_BUFLEN]
|
||||
#endif
|
||||
#ifdef CONFIG_KERNEL
|
||||
u32 TaskRdy; //+0x20
|
||||
_Sema Sema; //+0x24
|
||||
#else
|
||||
// Since ROM code will reference this typedef, so keep the typedef same size
|
||||
u32 TaskRdy;
|
||||
void *Sema;
|
||||
#endif
|
||||
} UART_LOG_CTL, *PUART_LOG_CTL;
|
||||
|
||||
|
||||
#define KB_ASCII_NUL 0x00
|
||||
#define KB_ASCII_BS 0x08
|
||||
#define KB_ASCII_TAB 0x09
|
||||
#define KB_ASCII_LF 0x0A
|
||||
#define KB_ASCII_CR 0x0D
|
||||
#define KB_ASCII_ESC 0x1B
|
||||
#define KB_ASCII_SP 0x20
|
||||
#define KB_ASCII_BS_7F 0x7F
|
||||
#define KB_ASCII_LBRKT 0x5B //[
|
||||
|
||||
#define KB_SPACENO_TAB 1
|
||||
|
||||
#ifdef CONFIG_UART_LOG_HISTORY
|
||||
#define UART_LOG_HISTORY_LEN 5
|
||||
#endif
|
||||
|
||||
#if CONFIG_DEBUG_LOG > 0
|
||||
#define _ConsolePrint DiagPrintf
|
||||
#else
|
||||
#define _ConsolePrint
|
||||
#endif
|
||||
|
||||
#ifndef CONSOLE_PREFIX
|
||||
#define CONSOLE_PREFIX "<RTL8195A>"
|
||||
#endif
|
||||
|
||||
#define CONSOLE_8195A(...) do {\
|
||||
_ConsolePrint("\r"CONSOLE_PREFIX __VA_ARGS__);\
|
||||
}while(0)
|
||||
|
||||
|
||||
_LONG_CALL_ VOID
|
||||
RtlConsolInit(
|
||||
IN u32 Boot,
|
||||
IN u32 TBLSz,
|
||||
IN VOID *pTBL
|
||||
);
|
||||
|
||||
#if defined(CONFIG_KERNEL)
|
||||
_LONG_CALL_ VOID
|
||||
RtlConsolTaskRam(
|
||||
VOID *Data
|
||||
);
|
||||
#endif
|
||||
|
||||
_LONG_CALL_ VOID
|
||||
RtlConsolTaskRom(
|
||||
VOID *Data
|
||||
);
|
||||
|
||||
|
||||
_LONG_CALL_ u32
|
||||
Strtoul(
|
||||
IN const u8 *nptr,
|
||||
IN u8 **endptr,
|
||||
IN u32 base
|
||||
);
|
||||
|
||||
_LONG_CALL_ extern VOID UartLogIrqHandle(VOID * Data); // in ROM
|
||||
|
||||
void console_init(void);
|
||||
|
||||
extern _LONG_CALL_ROM_ int GetArgc(const u8 *string);
|
||||
extern _LONG_CALL_ROM_ u8** GetArgv(const u8 *string);
|
||||
|
||||
|
||||
#endif //_RTK_CONSOL_H_
|
||||
340
sdk/component/soc/realtek/8195a/misc/driver/rtl_console_new.c
Normal file
340
sdk/component/soc/realtek/8195a/misc/driver/rtl_console_new.c
Normal file
|
|
@ -0,0 +1,340 @@
|
|||
/*
|
||||
* console_api.c
|
||||
*
|
||||
* Created on: 24/02/17
|
||||
* Author: pvvx
|
||||
*/
|
||||
//======================================================
|
||||
#ifndef LOGUART_STACK_SIZE
|
||||
#define LOGUART_STACK_SIZE 400 // USE_MIN_STACK_SIZE modify from 512 to 128
|
||||
#endif
|
||||
#define CONSOLE_PRIORITY 0
|
||||
//======================================================
|
||||
#include "rtl8195a.h"
|
||||
#include "rtl_bios_data.h"
|
||||
#include "osdep_api.h"
|
||||
#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1)
|
||||
#include "freertos_pmu.h"
|
||||
#else
|
||||
#error "Define configUSE_WAKELOCK_PMU = 1 & configUSE_WAKELOCK_PMU = 1!"
|
||||
#endif
|
||||
#if defined(CONFIG_KERNEL) && !TASK_SCHEDULER_DISABLED
|
||||
#else
|
||||
#error "Define CONFIG_KERNEL & TASK_SCHEDULER_DISABLED = 0!"
|
||||
#endif
|
||||
#ifndef CONFIG_UART_LOG_HISTORY
|
||||
#error "Define CONFIG_UART_LOG_HISTORY!"
|
||||
#endif
|
||||
//======================================================
|
||||
// #define USE_ROM_CONSOLE
|
||||
//======================================================
|
||||
_LONG_CALL_ extern u8 UartLogCmdChk(
|
||||
IN u8 RevData, IN UART_LOG_CTL *prvUartLogCtl,
|
||||
IN u8 EchoFlag);
|
||||
|
||||
_LONG_CALL_ extern void ArrayInitialize(
|
||||
IN u8 *pArrayToInit,
|
||||
IN u8 ArrayLen,
|
||||
IN u8 InitValue);
|
||||
|
||||
_LONG_CALL_ extern void UartLogHistoryCmd(
|
||||
IN u8 RevData, IN UART_LOG_CTL *prvUartLogCtl,
|
||||
IN u8 EchoFlag);
|
||||
|
||||
//_LONG_CALL_ extern void UartLogCmdExecute(IN PUART_LOG_CTL pUartLogCtlExe);
|
||||
//======================================================
|
||||
extern PCOMMAND_TABLE UartLogRamCmdTable[];
|
||||
extern UartLogRamCmdTableSize;
|
||||
//======================================================
|
||||
//<Function>: UartLogIrqHandleRam
|
||||
//<Usage >: To deal with Uart-Log RX IRQ
|
||||
//<Argus >: void
|
||||
//<Return >: void
|
||||
//<Notes >: NA
|
||||
//======================================================
|
||||
// overload original UartLogIrqHandle
|
||||
MON_RAM_TEXT_SECTION
|
||||
void UartLogIrqHandleRam(void * Data) {
|
||||
uint32 IrqEn = DiagGetIsrEnReg(); // HAL_UART_READ32(UART_INTERRUPT_EN_REG_OFF)
|
||||
DiagSetIsrEnReg(0); // HAL_UART_WRITE32(UART_INTERRUPT_EN_REG_OFF, 0)
|
||||
uint8 UartReceiveData = DiagGetChar(_FALSE); // if(flg) while(!(HAL_UART_READ32(UART_LINE_STATUS_REG_OFF)&1)); return HAL_UART_READ32(UART_REV_BUF_OFF);
|
||||
if (UartReceiveData == 0) {
|
||||
goto exit;
|
||||
}
|
||||
PUART_LOG_CTL p = pUartLogCtl;
|
||||
//KB_ESC chk is for cmd history, it's a special case here.
|
||||
if (UartReceiveData == KB_ASCII_ESC) {
|
||||
// Esc detection is only valid in the first stage of boot sequence (few seconds)
|
||||
if (p->ExecuteEsc != _TRUE) {
|
||||
p->ExecuteEsc = _TRUE;
|
||||
p->EscSTS = 0;
|
||||
} else {
|
||||
//4 the input commands are valid only when the task is ready to execute commands
|
||||
if (p->BootRdy == 1 || p->TaskRdy == 1) {
|
||||
if (p->EscSTS == 0) {
|
||||
p->EscSTS = 1;
|
||||
}
|
||||
} else {
|
||||
p->EscSTS = 0;
|
||||
}
|
||||
}
|
||||
} else if (p->EscSTS == 1) {
|
||||
if (UartReceiveData != KB_ASCII_LBRKT) { // '['
|
||||
p->EscSTS = 0;
|
||||
} else {
|
||||
p->EscSTS = 2;
|
||||
}
|
||||
} else {
|
||||
if (p->EscSTS == 2) {
|
||||
p->EscSTS = 0;
|
||||
if (UartReceiveData == 'A' || UartReceiveData == 'B') {
|
||||
// if(UartReceiveData == ...) set pUartLogCtl->SeeIdx ...
|
||||
// prvStrCpy(pUartLogCtl->pTmpLogBuf->UARTLogBuf, pUartLogCtl->pHistoryBuf[pUartLogCtl->SeeIdx]);
|
||||
// pUartLogCtl->pTmpLogBuf->BufCount = prvStrLen(pUartLogCtl->pTmpLogBuf->UARTLogBuf);
|
||||
// if(EchoFlag) pUartLogCtl->pfINPUT(pUartLogCtl->pTmpLogBuf->UARTLogBuf);
|
||||
UartLogHistoryCmd(UartReceiveData, (UART_LOG_CTL *) pUartLogCtl,
|
||||
1);
|
||||
}
|
||||
} else {
|
||||
if (UartLogCmdChk(UartReceiveData, (UART_LOG_CTL *) pUartLogCtl, 1)
|
||||
== 2) {
|
||||
// check UartLog buffer to prevent from incorrect access
|
||||
if (p->pTmpLogBuf != NULL) {
|
||||
p->ExecuteCmd = _TRUE;
|
||||
if (p->TaskRdy) {
|
||||
RtlUpSemaFromISR((_Sema *) &pUartLogCtl->Sema);
|
||||
}
|
||||
} else {
|
||||
ArrayInitialize((u8 *) pUartLogCtl->pTmpLogBuf->UARTLogBuf,
|
||||
UART_LOG_CMD_BUFLEN, '\0');
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
exit:
|
||||
DiagSetIsrEnReg(IrqEn); // HAL_UART_WRITE32(UART_INTERRUPT_EN_REG_OFF, IrqEn)
|
||||
}
|
||||
//======================================================
|
||||
//<Function>: GetArgvRam
|
||||
//<Usage >: парсигн аргументов строки
|
||||
//<Argus >: pstr - указатель на строку
|
||||
//<Return >: кол-во аргументов
|
||||
//<Notes >: 2 формата:
|
||||
// 1) cmd=arg1,arg2,...
|
||||
// 2) cmd arg1 arg2
|
||||
// arg может быть обрамлен '"' или '\''
|
||||
// для передачи ' ' или ','.
|
||||
// Начальные пробелы cmd или arg удаляются.
|
||||
//======================================================
|
||||
int GetArgvRam(IN u8 *pstr, u8** argv) {
|
||||
int arvc = 0;
|
||||
// u8** argv = ArgvArray;
|
||||
u8* p = pstr;
|
||||
u8 t, n = ' ';
|
||||
int m = 0;
|
||||
while(*p != 0
|
||||
&& *p != '\r'
|
||||
&& *p != '\n'
|
||||
&& arvc < MAX_ARGV
|
||||
&& p < &pstr[UART_LOG_CMD_BUFLEN-1]) {
|
||||
switch(m) {
|
||||
case 0: // wait cmd
|
||||
if(*p == ' ') {
|
||||
// *p = 0;
|
||||
break;
|
||||
}
|
||||
*argv++ = p;
|
||||
arvc++;
|
||||
m++;
|
||||
break;
|
||||
case 1: // test end cmd, type format parm
|
||||
if(*p == ' ') { // format cmd arg1 arg2 ...
|
||||
m++;
|
||||
*p = 0;
|
||||
} else if(*p == '=') { // "at" format cmd=arg1,arg2,...
|
||||
n = ',';
|
||||
m++;
|
||||
*p = 0;
|
||||
}
|
||||
break;
|
||||
case 2: // wait start arg
|
||||
if(*p == ' ') {
|
||||
*p = 0;
|
||||
break;
|
||||
}
|
||||
if(*p == '"' || *p == '\'') {
|
||||
t = *p;
|
||||
m = 4;
|
||||
*p = 0;
|
||||
break;
|
||||
}
|
||||
*argv++ = p;
|
||||
arvc++;
|
||||
m++;
|
||||
case 3: // end arg
|
||||
if(*p == n) { // ' ' or ','
|
||||
m = 2;
|
||||
*p = 0;
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
*argv++ = p;
|
||||
arvc++;
|
||||
m++;
|
||||
case 5:
|
||||
if(*p == t) { // '\'' or '"'
|
||||
m = 3;
|
||||
*p = 0;
|
||||
}
|
||||
break;
|
||||
}
|
||||
p++;
|
||||
}
|
||||
return arvc;
|
||||
}
|
||||
//======================================================
|
||||
//<Function>: RtlConsolTaskRam
|
||||
//<Usage >: overload original RtlConsolTaskRam
|
||||
//<Argus >: Data - указатель PUART_LOG_CTL
|
||||
//<Return >: none
|
||||
//<Notes >:
|
||||
//======================================================
|
||||
MON_RAM_TEXT_SECTION void RtlConsolTaskRam(void *Data) {
|
||||
PUART_LOG_CTL p = pUartLogCtl;
|
||||
#ifdef USE_ROM_CONSOLE // show Help
|
||||
p->pTmpLogBuf->UARTLogBuf[0] = '?';
|
||||
p->pTmpLogBuf->BufCount = 1;
|
||||
p->ExecuteCmd = _TRUE;
|
||||
#endif
|
||||
do {
|
||||
p->TaskRdy = _TRUE;
|
||||
RtlDownSema(&p->Sema);
|
||||
if (p->ExecuteCmd) {
|
||||
// UartLogCmdExecute(pUartLogCtl);
|
||||
int argc = GetArgvRam(p->pTmpLogBuf->UARTLogBuf, ArgvArray);
|
||||
if(argc) {
|
||||
StrUpr(ArgvArray[0]);
|
||||
PCOMMAND_TABLE pcmd = p->pCmdTbl;
|
||||
int flg = 1;
|
||||
#ifdef USE_ROM_CONSOLE
|
||||
for(int i = 0; i < p->CmdTblSz; i++) {
|
||||
#else
|
||||
while(pcmd->cmd) {
|
||||
#endif
|
||||
if(prvStrCmp(ArgvArray[0], pcmd->cmd) == 0) {
|
||||
flg = 0;
|
||||
if(pcmd->ArgvCnt < argc) {
|
||||
#ifdef USE_ROM_CONSOLE
|
||||
pcmd->func(argc-1, &ArgvArray[1]);
|
||||
#else
|
||||
pcmd->func(argc, &ArgvArray);
|
||||
#endif
|
||||
} else {
|
||||
#ifdef USE_ROM_CONSOLE
|
||||
DiagPrintf(pcmd->msg);
|
||||
#else
|
||||
DiagPrintf("%s%s\n", pcmd->cmd, pcmd->msg);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
pcmd++;
|
||||
}
|
||||
if(flg) DiagPrintf("cmd: %s - nothing!\n", ArgvArray[0]);
|
||||
#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1)
|
||||
release_wakelock(WAKELOCK_LOGUART);
|
||||
#endif
|
||||
}
|
||||
#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1)
|
||||
else acquire_wakelock(WAKELOCK_LOGUART);
|
||||
#endif
|
||||
p->pTmpLogBuf->BufCount = 0;
|
||||
p->pTmpLogBuf->UARTLogBuf[0] = 0;
|
||||
HalSerialPutcRtl8195a('\r');
|
||||
HalSerialPutcRtl8195a('>');
|
||||
p->ExecuteCmd = _FALSE;
|
||||
}
|
||||
} while (1);
|
||||
}
|
||||
//======================================================
|
||||
//<Function>: console_init
|
||||
//<Usage >: Initialize rtl console
|
||||
//<Argus >: none
|
||||
//<Return >: none
|
||||
//<Notes >: delete rtl_concole.h from project
|
||||
//======================================================
|
||||
MON_RAM_TEXT_SECTION void console_init(void) {
|
||||
IRQ_HANDLE UartIrqHandle;
|
||||
// Register Log Uart Callback function
|
||||
UartIrqHandle.Data = 0; // (u32)&UartAdapter;
|
||||
UartIrqHandle.IrqNum = UART_LOG_IRQ;
|
||||
UartIrqHandle.IrqFun = (IRQ_FUN) UartLogIrqHandleRam;
|
||||
UartIrqHandle.Priority = 0; // ??
|
||||
// Register Isr handle
|
||||
InterruptUnRegister(&UartIrqHandle);
|
||||
#ifdef USE_ROM_CONSOLE // use ROM Consol init & printf "<RTL8195A>"
|
||||
RtlConsolInit(RAM_STAGE, (u32) 6, (void*) UartLogRomCmdTable);
|
||||
#else
|
||||
UartLogBuf.BufCount = 0;
|
||||
ArrayInitialize(&UartLogBuf.UARTLogBuf[0], UART_LOG_CMD_BUFLEN, '\0');
|
||||
pUartLogCtl = &UartLogCtl;
|
||||
pUartLogCtl->NewIdx = 0;
|
||||
pUartLogCtl->SeeIdx = 0;
|
||||
pUartLogCtl->EscSTS = 0;
|
||||
pUartLogCtl->BootRdy = 0;
|
||||
pUartLogCtl->pTmpLogBuf = &UartLogBuf;
|
||||
pUartLogCtl->CRSTS = 0;
|
||||
pUartLogCtl->pHistoryBuf = UartLogHistoryBuf;
|
||||
pUartLogCtl->pfINPUT = (void*) &DiagPrintf;
|
||||
pUartLogCtl->pCmdTbl = (PCOMMAND_TABLE) UartLogRamCmdTable;
|
||||
pUartLogCtl->CmdTblSz = UartLogRamCmdTableSize/16; //6; // GetRomCmdNum()
|
||||
pUartLogCtl->TaskRdy = 0;
|
||||
#endif
|
||||
pUartLogCtl->RevdNo = UART_LOG_HISTORY_LEN;
|
||||
// Create a Semaphone
|
||||
RtlInitSema(&pUartLogCtl->Sema, 1);
|
||||
// executing boot sequence
|
||||
pUartLogCtl->ExecuteCmd = _FALSE;
|
||||
pUartLogCtl->ExecuteEsc = _TRUE; //don't check Esc anymore
|
||||
InterruptRegister(&UartIrqHandle);
|
||||
if (pdTRUE
|
||||
!= xTaskCreate(RtlConsolTaskRam,
|
||||
(const signed char * const )"loguart", LOGUART_STACK_SIZE,
|
||||
NULL, tskIDLE_PRIORITY + CONSOLE_PRIORITY + PRIORITIE_OFFSET, NULL)) {
|
||||
DiagPrintf("Create Log UART Task Err!!\n");
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef USE_ROM_CONSOLE
|
||||
//======================================================
|
||||
//<Function>: console_help
|
||||
//<Usage >: Initialize rtl console
|
||||
//<Argus >: argc - кол-во аргуметов, argv - список аргументов
|
||||
//<Return >: none
|
||||
//<Notes >:
|
||||
//======================================================
|
||||
extern char str_rom_57ch3Dch0A[]; // "=========================================================\n" 57 шт
|
||||
_WEAK void console_help(int argc, char *argv[]) { // Help
|
||||
DiagPrintf("CONSOLE COMMAND SET:\n");
|
||||
DiagPrintf(&str_rom_57ch3Dch0A[25]); // DiagPrintf("==============================\n");
|
||||
PCOMMAND_TABLE pcmdtab = UartLogRamCmdTable;
|
||||
while(pcmdtab->cmd) {
|
||||
#ifdef USE_ROM_CONSOLE
|
||||
DiagPrintf(pcmdtab->msg);
|
||||
#else
|
||||
DiagPrintf("%s%s\n", pcmdtab->cmd, pcmdtab->msg);
|
||||
#endif
|
||||
pcmdtab++;
|
||||
}
|
||||
DiagPrintf(&str_rom_57ch3Dch0A[25]); // DiagPrintf("==============================\n");
|
||||
}
|
||||
LOCAL void print_on(int argc, char *argv[])
|
||||
{
|
||||
print_off = argv[1][0]!='1';
|
||||
}
|
||||
// (!) размещается в специальном сегменте '.mon.tab*' (см. *.ld файл)
|
||||
MON_RAM_TAB_SECTION COMMAND_TABLE console_commands[] = {
|
||||
{"PR", 1, print_on, "=<1/0>: Printf on/off"}, // Help
|
||||
{"?", 0, console_help, ": This Help"} // Help
|
||||
// {"HELP", 0, console_help, ": Help"} // Help
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
#!/bin/sh
|
||||
|
||||
#===============================================================================
|
||||
CURRENT_UTILITY_DIR=$(pwd)
|
||||
GDBSCPTFILE="../../../component/soc/realtek/8195a/misc/gcc_utility/rtl_gdb_flash_write.txt"
|
||||
|
||||
#===============================================================================
|
||||
RLXSTS=$(ps -W | grep "rlx_probe_driver.exe" | grep -v "grep" | wc -l)
|
||||
echo $RLXSTS
|
||||
JLKSTS=$(ps -W | grep "JLinkGDBServer.exe" | grep -v "grep" | wc -l)
|
||||
echo $JLKSTS
|
||||
|
||||
echo $CURRENT_UTILITY_DIR
|
||||
|
||||
#===============================================================================
|
||||
#make the new string for being written
|
||||
if [ $RLXSTS = 1 ]
|
||||
then
|
||||
echo "probe get"
|
||||
|
||||
#-------------------------------------------
|
||||
LINE_NUMBER=$(grep -n "monitor reset " $GDBSCPTFILE | awk -F":" '{print $1}')
|
||||
DEFAULT_STR=$(grep -n "monitor reset " $GDBSCPTFILE | awk -F":" '{print $2}')
|
||||
#echo $LINE_NUMBER
|
||||
echo $DEFAULT_STR
|
||||
STRLEN_DFT=$(expr length "$DEFAULT_STR")
|
||||
DEFAULT_STR="#monitor reset 1"
|
||||
echo $DEFAULT_STR
|
||||
#-------------------------------------------
|
||||
SED_PARA="$LINE_NUMBER""c""$DEFAULT_STR"
|
||||
sed -i "$SED_PARA" $GDBSCPTFILE
|
||||
|
||||
#===========================================
|
||||
LINE_NUMBER=$(grep -n "monitor sleep " $GDBSCPTFILE | awk -F":" '{print $1}')
|
||||
DEFAULT_STR=$(grep -n "monitor sleep " $GDBSCPTFILE | awk -F":" '{print $2}')
|
||||
#echo $LINE_NUMBER
|
||||
echo $DEFAULT_STR
|
||||
STRLEN_DFT=$(expr length "$DEFAULT_STR")
|
||||
DEFAULT_STR="#monitor sleep 20"
|
||||
echo $DEFAULT_STR
|
||||
#-------------------------------------------
|
||||
SED_PARA="$LINE_NUMBER""c""$DEFAULT_STR"
|
||||
sed -i "$SED_PARA" $GDBSCPTFILE
|
||||
else
|
||||
|
||||
if [ $JLKSTS = 1 ]
|
||||
then
|
||||
echo "jlink get"
|
||||
|
||||
#-------------------------------------------
|
||||
LINE_NUMBER=$(grep -n "monitor reset " $GDBSCPTFILE | awk -F":" '{print $1}')
|
||||
DEFAULT_STR=$(grep -n "monitor reset " $GDBSCPTFILE | awk -F":" '{print $2}')
|
||||
#echo $LINE_NUMBER
|
||||
echo $DEFAULT_STR
|
||||
STRLEN_DFT=$(expr length "$DEFAULT_STR")
|
||||
DEFAULT_STR="monitor reset 1"
|
||||
echo $DEFAULT_STR
|
||||
#-------------------------------------------
|
||||
SED_PARA="$LINE_NUMBER""c""$DEFAULT_STR"
|
||||
sed -i "$SED_PARA" $GDBSCPTFILE
|
||||
|
||||
#===========================================
|
||||
LINE_NUMBER=$(grep -n "monitor sleep " $GDBSCPTFILE | awk -F":" '{print $1}')
|
||||
DEFAULT_STR=$(grep -n "monitor sleep " $GDBSCPTFILE | awk -F":" '{print $2}')
|
||||
#echo $LINE_NUMBER
|
||||
echo $DEFAULT_STR
|
||||
STRLEN_DFT=$(expr length "$DEFAULT_STR")
|
||||
DEFAULT_STR="monitor sleep 20"
|
||||
echo $DEFAULT_STR
|
||||
#-------------------------------------------
|
||||
SED_PARA="$LINE_NUMBER""c""$DEFAULT_STR"
|
||||
sed -i "$SED_PARA" $GDBSCPTFILE
|
||||
|
||||
fi
|
||||
fi
|
||||
|
||||
#===============================================================================
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
#!/bin/sh
|
||||
|
||||
#===============================================================================
|
||||
CURRENT_UTILITY_DIR=$(pwd)
|
||||
echo "..."
|
||||
echo $CURRENT_UTILITY_DIR
|
||||
RAMFILENAME="./application/Debug/bin/ram_all.bin"
|
||||
echo $RAMFILENAME
|
||||
#RAMFILENAME="ram_2.bin"
|
||||
GDBSCPTFILE="../../../component/soc/realtek/8195a/misc/gcc_utility/rtl_gdb_flash_write.txt"
|
||||
|
||||
#===============================================================================
|
||||
#get file size
|
||||
RAM_FILE_SIZE=$(stat -c %s $RAMFILENAME)
|
||||
RAM_FILE_SIZE_HEX=`echo "obase=16; $RAM_FILE_SIZE"|bc`
|
||||
|
||||
echo "size "$RAM_FILE_SIZE" --> 0x"$RAM_FILE_SIZE_HEX
|
||||
|
||||
echo "set \$RamFileSize = 0x$RAM_FILE_SIZE_HEX" > fwsize.gdb
|
||||
exit
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
# Main file for Ameba1 series Cortex-M3 parts
|
||||
#
|
||||
# !!!!!!
|
||||
#
|
||||
|
||||
set CHIPNAME rtl8195a
|
||||
set CHIPSERIES ameba1
|
||||
|
||||
# Adapt based on what transport is active.
|
||||
source [find target/swj-dp.tcl]
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
error "CHIPNAME not set. Please do not include ameba1.cfg directly."
|
||||
}
|
||||
|
||||
if { [info exists CHIPSERIES] } {
|
||||
# Validate chip series is supported
|
||||
if { $CHIPSERIES != "ameba1" } {
|
||||
error "Unsupported chip series specified."
|
||||
}
|
||||
set _CHIPSERIES $CHIPSERIES
|
||||
} else {
|
||||
error "CHIPSERIES not set. Please do not include ameba1.cfg directly."
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
# Allow user override
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
# Ameba1 use a Cortex M3 core.
|
||||
if { $_CHIPSERIES == "ameba1" } {
|
||||
if { [using_jtag] } {
|
||||
set _CPUTAPID 0x4ba00477
|
||||
} {
|
||||
set _CPUTAPID 0x2ba01477
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
|
||||
|
||||
|
||||
# Run with *real slow* clock by default since the
|
||||
# boot rom could have been playing with the PLL, so
|
||||
# we have no idea what clock the target is running at.
|
||||
adapter_khz 1000
|
||||
|
||||
# delays on reset lines
|
||||
adapter_nsrst_delay 200
|
||||
if {[using_jtag]} {
|
||||
jtag_ntrst_delay 200
|
||||
}
|
||||
|
||||
|
||||
# Ameba1 (Cortex M3 core) support SYSRESETREQ
|
||||
if {![using_hla]} {
|
||||
# if srst is not fitted use SYSRESETREQ to
|
||||
# perform a soft reset
|
||||
cortex_m reset_config sysresetreq
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-init {ameba1_init}
|
||||
|
||||
# Ameba1 SDRAM enable
|
||||
proc ameba1_init { } {
|
||||
# init System
|
||||
mww 0x40000014 0x00000021
|
||||
sleep 10
|
||||
mww 0x40000304 0x1fc00002
|
||||
sleep 10
|
||||
mww 0x40000250 0x00000400
|
||||
sleep 10
|
||||
mww 0x40000340 0x00000000
|
||||
sleep 10
|
||||
mww 0x40000230 0x0000dcc4
|
||||
sleep 10
|
||||
mww 0x40000210 0x00011117
|
||||
sleep 10
|
||||
mww 0x40000210 0x00011157
|
||||
sleep 10
|
||||
mww 0x400002c0 0x00110011
|
||||
sleep 10
|
||||
mww 0x40000320 0xffffffff
|
||||
sleep 10
|
||||
# init SDRAM
|
||||
mww 0x40000040 0x00fcc702
|
||||
sleep 10
|
||||
mdw 0x40000040
|
||||
mww 0x40005224 0x00000001
|
||||
sleep 10
|
||||
mww 0x40005004 0x00000208
|
||||
sleep 10
|
||||
mww 0x40005008 0xffffd000
|
||||
sleep 13
|
||||
mww 0x40005020 0x00000022
|
||||
sleep 13
|
||||
mww 0x40005010 0x09006201
|
||||
sleep 13
|
||||
mww 0x40005014 0x00002611
|
||||
sleep 13
|
||||
mww 0x40005018 0x00068413
|
||||
sleep 13
|
||||
mww 0x4000501c 0x00000042
|
||||
sleep 13
|
||||
mww 0x4000500c 0x700 ;# set Idle
|
||||
sleep 20
|
||||
mww 0x40005000 0x1 ;# start init
|
||||
sleep 100
|
||||
mdw 0x40005000
|
||||
mww 0x4000500c 0x600 ;# enter memory mode
|
||||
sleep 30
|
||||
|
||||
mww 0x40005008 0x00000000 ;# 0xf00
|
||||
;# mww 0x40005008 0x00000f00
|
||||
sleep 3
|
||||
mww 0x40000300 0x0006005e ;# 0x5e
|
||||
;# mww 0x40000300 0x0000005e
|
||||
sleep 3
|
||||
}
|
||||
BIN
sdk/component/soc/realtek/8195a/misc/gcc_utility/ram_all.bin
Normal file
BIN
sdk/component/soc/realtek/8195a/misc/gcc_utility/ram_all.bin
Normal file
Binary file not shown.
|
|
@ -0,0 +1,57 @@
|
|||
# GDB script for loading ram.bin process
|
||||
|
||||
#===============================================================================
|
||||
#set GDB connection
|
||||
set remotetimeout 100000
|
||||
target remote :2331
|
||||
|
||||
#===============================================================================
|
||||
#Message display setting
|
||||
#disable all messages
|
||||
|
||||
set verbose off
|
||||
set complaints 0
|
||||
set confirm off
|
||||
set exec-done-display off
|
||||
show exec-done-display
|
||||
set trace-commands off
|
||||
#set debug aix-thread off
|
||||
#set debug dwarf2-die 0
|
||||
set debug displaced off
|
||||
set debug expression 0
|
||||
set debug frame 0
|
||||
set debug infrun 0
|
||||
set debug observer 0
|
||||
set debug overload 0
|
||||
set debugvarobj 0
|
||||
set pagination off
|
||||
set print address off
|
||||
set print symbol-filename off
|
||||
set print symbol off
|
||||
set print pretty off
|
||||
set print object off
|
||||
#set debug notification off
|
||||
set debug parser off
|
||||
set debug remote 0
|
||||
|
||||
#===============================================================================
|
||||
monitor reset 1
|
||||
monitor sleep 20
|
||||
monitor clrbp
|
||||
#===============================================================================
|
||||
#Load flash download file
|
||||
file ./application/Debug/bin/application.axf
|
||||
|
||||
#skip sdram init, it has been init in openocd config
|
||||
set {int}0x40000210=0x211157
|
||||
#x /1xw 0x40000210
|
||||
|
||||
b main
|
||||
continue
|
||||
clear main
|
||||
#Load the file
|
||||
#lo
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
# GDB script for loading ram.bin process
|
||||
|
||||
#===============================================================================
|
||||
#set GDB connection
|
||||
set remotetimeout 100000
|
||||
target remote :2331
|
||||
|
||||
#===============================================================================
|
||||
#Message display setting
|
||||
#disable all messages
|
||||
|
||||
set verbose off
|
||||
set complaints 0
|
||||
set confirm off
|
||||
set exec-done-display off
|
||||
show exec-done-display
|
||||
set trace-commands off
|
||||
#set debug aix-thread off
|
||||
#set debug dwarf2-die 0
|
||||
set debug displaced off
|
||||
set debug expression 0
|
||||
set debug frame 0
|
||||
set debug infrun 0
|
||||
set debug observer 0
|
||||
set debug overload 0
|
||||
set debugvarobj 0
|
||||
set pagination off
|
||||
set print address off
|
||||
set print symbol-filename off
|
||||
set print symbol off
|
||||
set print pretty off
|
||||
set print object off
|
||||
#set debug notification off
|
||||
set debug parser off
|
||||
set debug remote 0
|
||||
|
||||
#===============================================================================
|
||||
monitor reset 1
|
||||
monitor sleep 20
|
||||
monitor clrbp
|
||||
#===============================================================================
|
||||
#Load flash download file
|
||||
file ./application/Debug/bin/application.axf
|
||||
|
||||
#skip sdram init, it has been init in openocd config
|
||||
set {int}0x40000210=0x211157
|
||||
#x /1xw 0x40000210
|
||||
|
||||
b main
|
||||
continue
|
||||
clear main
|
||||
#Load the file
|
||||
#lo
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
# GDB script for loading ram.bin process
|
||||
|
||||
#===============================================================================
|
||||
#set GDB connection
|
||||
set remotetimeout 100000
|
||||
target remote :3333
|
||||
|
||||
#===============================================================================
|
||||
#Message display setting
|
||||
#disable all messages
|
||||
|
||||
set verbose off
|
||||
set complaints 0
|
||||
set confirm off
|
||||
set exec-done-display off
|
||||
show exec-done-display
|
||||
set trace-commands off
|
||||
#set debug aix-thread off
|
||||
#set debug dwarf2-die 0
|
||||
set debug displaced off
|
||||
set debug expression 0
|
||||
set debug frame 0
|
||||
set debug infrun 0
|
||||
set debug observer 0
|
||||
set debug overload 0
|
||||
set debugvarobj 0
|
||||
set pagination off
|
||||
set print address off
|
||||
set print symbol-filename off
|
||||
set print symbol off
|
||||
set print pretty off
|
||||
set print object off
|
||||
#set debug notification off
|
||||
set debug parser off
|
||||
set debug remote 0
|
||||
|
||||
#===============================================================================
|
||||
monitor reset init
|
||||
monitor sleep 20
|
||||
monitor halt
|
||||
#===============================================================================
|
||||
#Load flash download file
|
||||
file ./application/Debug/bin/application.axf
|
||||
|
||||
#skip sdram init, it has been init in openocd config
|
||||
set {int}0x40000210=0x211157
|
||||
#x /1xw 0x40000210
|
||||
|
||||
b main
|
||||
continue
|
||||
clear main
|
||||
#Load the file
|
||||
#lo
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
# GDB script for loading ram.bin process
|
||||
|
||||
#===============================================================================
|
||||
#set GDB connection
|
||||
set remotetimeout 100000
|
||||
target remote :2331
|
||||
|
||||
#===============================================================================
|
||||
#set file path
|
||||
set $BINFILE = "./application/Debug/bin/ram_all.bin"
|
||||
|
||||
#===============================================================================
|
||||
#Message display setting
|
||||
#disable all messages
|
||||
|
||||
set verbose off
|
||||
set complaints 0
|
||||
set confirm off
|
||||
set exec-done-display off
|
||||
show exec-done-display
|
||||
set trace-commands off
|
||||
#set debug aix-thread off
|
||||
#set debug dwarf2-die 0
|
||||
set debug displaced off
|
||||
set debug expression 0
|
||||
set debug frame 0
|
||||
set debug infrun 0
|
||||
set debug observer 0
|
||||
set debug overload 0
|
||||
set debugvarobj 0
|
||||
set pagination off
|
||||
set print address off
|
||||
set print symbol-filename off
|
||||
set print symbol off
|
||||
set print pretty off
|
||||
set print object off
|
||||
#set debug notification off
|
||||
set debug parser off
|
||||
set debug remote 0
|
||||
|
||||
#===============================================================================
|
||||
#set JTAG and external SRAM
|
||||
monitor reset 1
|
||||
monitor sleep 20
|
||||
monitor clrbp
|
||||
#===============================================================================
|
||||
#Variables declaration (1)
|
||||
#binary file size
|
||||
set $RamFileSize = 0x0000
|
||||
source fwsize.gdb
|
||||
printf "-------------------------------\n"
|
||||
printf "RamFileSize: %x\n",$RamFileSize
|
||||
printf "-------------------------------\n"
|
||||
|
||||
#===============================================================================
|
||||
set $FLASHDATBUFSIZE = 0x800
|
||||
|
||||
#===============================================================================
|
||||
#define PERI_ON_BASE 0x40000000
|
||||
set $PERI_ON_BASE = 0x40000000
|
||||
#define REG_SOC_PERI_FUNC0_EN 0x0218
|
||||
set $REG_SOC_PERI_FUNC0_EN = 0x0210
|
||||
|
||||
#define SPI_FLASH_BASE 0x4000000
|
||||
set $SPI_FLASH_BASE = 0x98000000
|
||||
|
||||
#------------------------------------------------------------------
|
||||
set $Temp = 0x0
|
||||
|
||||
#===============================================================================
|
||||
#Load flash download file
|
||||
file ../../../component/soc/realtek/8195a/misc/gcc_utility/target_NORMAL.axf
|
||||
|
||||
#Load the file
|
||||
lo
|
||||
|
||||
printf "Load flash controller.\n"
|
||||
|
||||
#===============================================================================
|
||||
#Set for executing flash controller funciton
|
||||
set $Temp = {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN)
|
||||
p /x $Temp
|
||||
|
||||
set $Temp = ($Temp | (0x01 << 27))
|
||||
p /x $Temp
|
||||
|
||||
set {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN) = $Temp
|
||||
printf "....\n"
|
||||
printf "wakeup bit(%x):%x\n", ($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN), {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN)
|
||||
#===============================================================================
|
||||
#Direct the startup wake function to flash program function
|
||||
#the function pointer address
|
||||
#set $testpointer = 0x200006b4
|
||||
#set $testpointer2 = 0x200006b8
|
||||
#set $FuntionPointer = 0x200006c4
|
||||
#set $FPTemp = 0x200a08e9
|
||||
#set {int}($FuntionPointer) = $FPTemp
|
||||
#printf "testpointer(%x):%x\n", $testpointer, {int}$testpointer
|
||||
#printf "testpointer2(%x):%x\n", $testpointer2, {int}$testpointer2
|
||||
#printf "FuntionPointer(%x):%x\n", $FuntionPointer, {int}$FuntionPointer
|
||||
|
||||
#===============================================================================
|
||||
#Load file
|
||||
# restore filename [binary] bias start end
|
||||
# Restore the contents of file filename into memory.
|
||||
# The restore command can automatically recognize any known bfd file format, except for raw binary.
|
||||
# To restore a raw binary file you must specify the optional keyword binary after the filename.
|
||||
#===============================================================================
|
||||
|
||||
set $LoopNum = ($RamFileSize / $FLASHDATBUFSIZE)
|
||||
printf "LoopNum = %x\n", $LoopNum
|
||||
set $TailSize = ($RamFileSize % $FLASHDATBUFSIZE)
|
||||
printf "TailSize = %x\n", $TailSize
|
||||
|
||||
printf "global variables\n"
|
||||
|
||||
set $FLASHDATSRC = 0x0
|
||||
set $FILESTARTADDR = 0X0
|
||||
set $FILEENDADDR = $FILESTARTADDR + $FLASHDATBUFSIZE
|
||||
|
||||
#b RtlFlashProgram:StartOfFlashBlockWrite
|
||||
b rtl_flash_download.c:489
|
||||
b rtl_flash_download.c:524
|
||||
#b Rtl_flash_control.c:RtlFlashProgram
|
||||
|
||||
#continue to 489
|
||||
c
|
||||
|
||||
# Mode 0: erase full chip, Mode 1: skip calibration section and erase to firmware size
|
||||
set EraseMode=1
|
||||
print EraseMode
|
||||
set FirmwareSize=$RamFileSize
|
||||
print FirmwareSize
|
||||
|
||||
#continue to 524
|
||||
c
|
||||
|
||||
#printf "...\n"
|
||||
set $FLASHDATSRC = FlashDatSrc
|
||||
printf "FlashDatSrc:%x\n", $FLASHDATSRC
|
||||
|
||||
printf "FlashBlockWriteSize "
|
||||
set FlashBlockWriteSize = $FLASHDATBUFSIZE
|
||||
#p /x FlashBlockWriteSize
|
||||
printf "FlashBlockWriteSize:%x\n", FlashBlockWriteSize
|
||||
|
||||
printf "FlashAddrForWrite"
|
||||
set FlashAddrForWrite = 0x0
|
||||
|
||||
|
||||
|
||||
printf "Flash write start...\n"
|
||||
set $LoopCnt = 0
|
||||
while ($LoopCnt < $LoopNum)
|
||||
p /x FlashAddrForWrite
|
||||
restore ./application/Debug/bin/ram_all.bin binary ($FLASHDATSRC-$FILESTARTADDR) $FILESTARTADDR $FILEENDADDR
|
||||
c
|
||||
|
||||
printf "FILEENDADDR"
|
||||
p /x $FILEENDADDR
|
||||
set FlashBlockWriteSize = $FLASHDATBUFSIZE
|
||||
set FlashAddrForWrite = $FILEENDADDR
|
||||
set $FILESTARTADDR = $FILEENDADDR
|
||||
set $FILEENDADDR = $FILESTARTADDR + $FLASHDATBUFSIZE
|
||||
|
||||
set $LoopCnt = $LoopCnt + 0x01
|
||||
end
|
||||
|
||||
#set FlashBlockWriteSize = $FLASHDATBUFSIZE
|
||||
#set FlashAddrForWrite = $FILEENDADDR
|
||||
#set $FILESTARTADDR = $FILEENDADDR
|
||||
set $FILEENDADDR = $FILESTARTADDR + $TailSize
|
||||
restore ./application/Debug/bin/ram_all.bin binary ($FLASHDATSRC-$FILESTARTADDR) $FILESTARTADDR $FILEENDADDR
|
||||
c
|
||||
|
||||
#Set complete flas
|
||||
set FlashWriteComplete = 0x1
|
||||
|
||||
printf "dump for check\n"
|
||||
|
||||
set $LoopCnt = 0
|
||||
set $dumpaddr = 0
|
||||
|
||||
set $dumpstartaddr = $SPI_FLASH_BASE
|
||||
set $dumpendaddr = $SPI_FLASH_BASE + $RamFileSize
|
||||
printf "start addr of dumping"
|
||||
p /x $dumpstartaddr
|
||||
printf "end addr of dumping"
|
||||
p /x $dumpendaddr
|
||||
dump binary memory ./application/Debug/bin/dump.bin $dumpstartaddr $dumpendaddr
|
||||
|
||||
|
||||
delete
|
||||
b rtl_flash_download.c:556
|
||||
c
|
||||
|
||||
quit
|
||||
#===============================================================================
|
||||
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
# GDB script for loading ram.bin process
|
||||
|
||||
#===============================================================================
|
||||
#set GDB connection
|
||||
set remotetimeout 100000
|
||||
target remote :2331
|
||||
|
||||
#===============================================================================
|
||||
#set file path
|
||||
set $BINFILE = "./application/Debug/bin/ram_all.bin"
|
||||
|
||||
#===============================================================================
|
||||
#Message display setting
|
||||
#disable all messages
|
||||
|
||||
set verbose off
|
||||
set complaints 0
|
||||
set confirm off
|
||||
set exec-done-display off
|
||||
show exec-done-display
|
||||
set trace-commands off
|
||||
#set debug aix-thread off
|
||||
#set debug dwarf2-die 0
|
||||
set debug displaced off
|
||||
set debug expression 0
|
||||
set debug frame 0
|
||||
set debug infrun 0
|
||||
set debug observer 0
|
||||
set debug overload 0
|
||||
set debugvarobj 0
|
||||
set pagination off
|
||||
set print address off
|
||||
set print symbol-filename off
|
||||
set print symbol off
|
||||
set print pretty off
|
||||
set print object off
|
||||
#set debug notification off
|
||||
set debug parser off
|
||||
set debug remote 0
|
||||
|
||||
#===============================================================================
|
||||
#set JTAG and external SRAM
|
||||
monitor reset 1
|
||||
monitor sleep 20
|
||||
monitor clrbp
|
||||
#===============================================================================
|
||||
#Variables declaration (1)
|
||||
#binary file size
|
||||
set $RamFileSize = 0x0000
|
||||
source fwsize.gdb
|
||||
printf "-------------------------------\n"
|
||||
printf "RamFileSize: %x\n",$RamFileSize
|
||||
printf "-------------------------------\n"
|
||||
|
||||
#===============================================================================
|
||||
set $FLASHDATBUFSIZE = 0x800
|
||||
|
||||
#===============================================================================
|
||||
#define PERI_ON_BASE 0x40000000
|
||||
set $PERI_ON_BASE = 0x40000000
|
||||
#define REG_SOC_PERI_FUNC0_EN 0x0218
|
||||
set $REG_SOC_PERI_FUNC0_EN = 0x0210
|
||||
|
||||
#define SPI_FLASH_BASE 0x4000000
|
||||
set $SPI_FLASH_BASE = 0x98000000
|
||||
|
||||
#------------------------------------------------------------------
|
||||
set $Temp = 0x0
|
||||
|
||||
#===============================================================================
|
||||
#Load flash download file
|
||||
file ../../../component/soc/realtek/8195a/misc/gcc_utility/target_NORMAL.axf
|
||||
|
||||
#Load the file
|
||||
lo
|
||||
|
||||
printf "Load flash controller.\n"
|
||||
|
||||
#===============================================================================
|
||||
#Set for executing flash controller funciton
|
||||
set $Temp = {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN)
|
||||
p /x $Temp
|
||||
|
||||
set $Temp = ($Temp | (0x01 << 27))
|
||||
p /x $Temp
|
||||
|
||||
set {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN) = $Temp
|
||||
printf "....\n"
|
||||
printf "wakeup bit(%x):%x\n", ($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN), {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN)
|
||||
#===============================================================================
|
||||
#Direct the startup wake function to flash program function
|
||||
#the function pointer address
|
||||
#set $testpointer = 0x200006b4
|
||||
#set $testpointer2 = 0x200006b8
|
||||
#set $FuntionPointer = 0x200006c4
|
||||
#set $FPTemp = 0x200a08e9
|
||||
#set {int}($FuntionPointer) = $FPTemp
|
||||
#printf "testpointer(%x):%x\n", $testpointer, {int}$testpointer
|
||||
#printf "testpointer2(%x):%x\n", $testpointer2, {int}$testpointer2
|
||||
#printf "FuntionPointer(%x):%x\n", $FuntionPointer, {int}$FuntionPointer
|
||||
|
||||
#===============================================================================
|
||||
#Load file
|
||||
# restore filename [binary] bias start end
|
||||
# Restore the contents of file filename into memory.
|
||||
# The restore command can automatically recognize any known bfd file format, except for raw binary.
|
||||
# To restore a raw binary file you must specify the optional keyword binary after the filename.
|
||||
#===============================================================================
|
||||
|
||||
set $LoopNum = ($RamFileSize / $FLASHDATBUFSIZE)
|
||||
printf "LoopNum = %x\n", $LoopNum
|
||||
set $TailSize = ($RamFileSize % $FLASHDATBUFSIZE)
|
||||
printf "TailSize = %x\n", $TailSize
|
||||
|
||||
printf "global variables\n"
|
||||
|
||||
set $FLASHDATSRC = 0x0
|
||||
set $FILESTARTADDR = 0X0
|
||||
set $FILEENDADDR = $FILESTARTADDR + $FLASHDATBUFSIZE
|
||||
|
||||
#b RtlFlashProgram:StartOfFlashBlockWrite
|
||||
b rtl_flash_download.c:489
|
||||
b rtl_flash_download.c:524
|
||||
#b Rtl_flash_control.c:RtlFlashProgram
|
||||
|
||||
#continue to 489
|
||||
c
|
||||
|
||||
# Mode 0: erase full chip, Mode 1: skip calibration section and erase to firmware size
|
||||
set EraseMode=1
|
||||
print EraseMode
|
||||
set FirmwareSize=$RamFileSize
|
||||
print FirmwareSize
|
||||
|
||||
#continue to 524
|
||||
c
|
||||
|
||||
#printf "...\n"
|
||||
set $FLASHDATSRC = FlashDatSrc
|
||||
printf "FlashDatSrc:%x\n", $FLASHDATSRC
|
||||
|
||||
printf "FlashBlockWriteSize "
|
||||
set FlashBlockWriteSize = $FLASHDATBUFSIZE
|
||||
#p /x FlashBlockWriteSize
|
||||
printf "FlashBlockWriteSize:%x\n", FlashBlockWriteSize
|
||||
|
||||
printf "FlashAddrForWrite"
|
||||
set FlashAddrForWrite = 0x0
|
||||
|
||||
|
||||
|
||||
printf "Flash write start...\n"
|
||||
set $LoopCnt = 0
|
||||
while ($LoopCnt < $LoopNum)
|
||||
p /x FlashAddrForWrite
|
||||
restore ./application/Debug/bin/ram_all.bin binary ($FLASHDATSRC-$FILESTARTADDR) $FILESTARTADDR $FILEENDADDR
|
||||
c
|
||||
|
||||
printf "FILEENDADDR"
|
||||
p /x $FILEENDADDR
|
||||
set FlashBlockWriteSize = $FLASHDATBUFSIZE
|
||||
set FlashAddrForWrite = $FILEENDADDR
|
||||
set $FILESTARTADDR = $FILEENDADDR
|
||||
set $FILEENDADDR = $FILESTARTADDR + $FLASHDATBUFSIZE
|
||||
|
||||
set $LoopCnt = $LoopCnt + 0x01
|
||||
end
|
||||
|
||||
#set FlashBlockWriteSize = $FLASHDATBUFSIZE
|
||||
#set FlashAddrForWrite = $FILEENDADDR
|
||||
#set $FILESTARTADDR = $FILEENDADDR
|
||||
set $FILEENDADDR = $FILESTARTADDR + $TailSize
|
||||
restore ./application/Debug/bin/ram_all.bin binary ($FLASHDATSRC-$FILESTARTADDR) $FILESTARTADDR $FILEENDADDR
|
||||
c
|
||||
|
||||
#Set complete flas
|
||||
set FlashWriteComplete = 0x1
|
||||
|
||||
printf "dump for check\n"
|
||||
|
||||
set $LoopCnt = 0
|
||||
set $dumpaddr = 0
|
||||
|
||||
set $dumpstartaddr = $SPI_FLASH_BASE
|
||||
set $dumpendaddr = $SPI_FLASH_BASE + $RamFileSize
|
||||
printf "start addr of dumping"
|
||||
p /x $dumpstartaddr
|
||||
printf "end addr of dumping"
|
||||
p /x $dumpendaddr
|
||||
dump binary memory ./application/Debug/bin/dump.bin $dumpstartaddr $dumpendaddr
|
||||
|
||||
|
||||
delete
|
||||
b rtl_flash_download.c:556
|
||||
c
|
||||
|
||||
quit
|
||||
#===============================================================================
|
||||
|
||||
|
|
@ -0,0 +1,198 @@
|
|||
# GDB script for loading ram.bin process
|
||||
|
||||
#===============================================================================
|
||||
#set GDB connection
|
||||
set remotetimeout 100000
|
||||
target remote :3333
|
||||
|
||||
#===============================================================================
|
||||
#set file path
|
||||
set $BINFILE = "./application/Debug/bin/ram_all.bin"
|
||||
|
||||
#===============================================================================
|
||||
#Message display setting
|
||||
#disable all messages
|
||||
|
||||
set verbose off
|
||||
set complaints 0
|
||||
set confirm off
|
||||
set exec-done-display off
|
||||
show exec-done-display
|
||||
set trace-commands off
|
||||
#set debug aix-thread off
|
||||
#set debug dwarf2-die 0
|
||||
set debug displaced off
|
||||
set debug expression 0
|
||||
set debug frame 0
|
||||
set debug infrun 0
|
||||
set debug observer 0
|
||||
set debug overload 0
|
||||
set debugvarobj 0
|
||||
set pagination off
|
||||
set print address off
|
||||
set print symbol-filename off
|
||||
set print symbol off
|
||||
set print pretty off
|
||||
set print object off
|
||||
#set debug notification off
|
||||
set debug parser off
|
||||
set debug remote 0
|
||||
|
||||
#===============================================================================
|
||||
#set JTAG and external SRAM
|
||||
monitor reset init
|
||||
monitor halt
|
||||
monitor sleep 20
|
||||
#===============================================================================
|
||||
#Variables declaration (1)
|
||||
#binary file size
|
||||
set $RamFileSize = 0x0000
|
||||
source fwsize.gdb
|
||||
printf "-------------------------------\n"
|
||||
printf "RamFileSize: %x\n",$RamFileSize
|
||||
printf "-------------------------------\n"
|
||||
|
||||
#===============================================================================
|
||||
set $FLASHDATBUFSIZE = 0x800
|
||||
|
||||
#===============================================================================
|
||||
#define PERI_ON_BASE 0x40000000
|
||||
set $PERI_ON_BASE = 0x40000000
|
||||
#define REG_SOC_PERI_FUNC0_EN 0x0218
|
||||
set $REG_SOC_PERI_FUNC0_EN = 0x0210
|
||||
|
||||
#define SPI_FLASH_BASE 0x4000000
|
||||
set $SPI_FLASH_BASE = 0x98000000
|
||||
|
||||
#------------------------------------------------------------------
|
||||
set $Temp = 0x0
|
||||
|
||||
#===============================================================================
|
||||
#Load flash download file
|
||||
file ../../../component/soc/realtek/8195a/misc/gcc_utility/target_NORMAL.axf
|
||||
|
||||
#Load the file
|
||||
lo
|
||||
|
||||
printf "Load flash controller.\n"
|
||||
#===============================================================================
|
||||
#Set for executing flash controller funciton
|
||||
set $Temp = {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN)
|
||||
p /x $Temp
|
||||
|
||||
set $Temp = ($Temp | (0x01 << 27))
|
||||
p /x $Temp
|
||||
|
||||
set {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN) = $Temp
|
||||
printf "....\n"
|
||||
printf "wakeup bit(%x):%x\n", ($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN), {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN)
|
||||
#===============================================================================
|
||||
#Direct the startup wake function to flash program function
|
||||
#the function pointer address
|
||||
#set $testpointer = 0x200006b4
|
||||
#set $testpointer2 = 0x200006b8
|
||||
#set $FuntionPointer = 0x200006c4
|
||||
#set $FPTemp = 0x200a08e9
|
||||
#set {int}($FuntionPointer) = $FPTemp
|
||||
#printf "testpointer(%x):%x\n", $testpointer, {int}$testpointer
|
||||
#printf "testpointer2(%x):%x\n", $testpointer2, {int}$testpointer2
|
||||
#printf "FuntionPointer(%x):%x\n", $FuntionPointer, {int}$FuntionPointer
|
||||
|
||||
#===============================================================================
|
||||
#Load file
|
||||
# restore filename [binary] bias start end
|
||||
# Restore the contents of file filename into memory.
|
||||
# The restore command can automatically recognize any known bfd file format, except for raw binary.
|
||||
# To restore a raw binary file you must specify the optional keyword binary after the filename.
|
||||
#===============================================================================
|
||||
|
||||
set $LoopNum = ($RamFileSize / $FLASHDATBUFSIZE)
|
||||
printf "LoopNum = %x\n", $LoopNum
|
||||
set $TailSize = ($RamFileSize % $FLASHDATBUFSIZE)
|
||||
printf "TailSize = %x\n", $TailSize
|
||||
|
||||
printf "global variables\n"
|
||||
|
||||
set $FLASHDATSRC = 0x0
|
||||
set $FILESTARTADDR = 0X0
|
||||
set $FILEENDADDR = $FILESTARTADDR + $FLASHDATBUFSIZE
|
||||
|
||||
#b RtlFlashProgram:StartOfFlashBlockWrite
|
||||
b rtl_flash_download.c:489
|
||||
b rtl_flash_download.c:524
|
||||
#b Rtl_flash_control.c:RtlFlashProgram
|
||||
|
||||
#continue to 489
|
||||
c
|
||||
|
||||
# Mode 0: erase full chip, Mode 1: skip calibration section and erase to firmware size
|
||||
set EraseMode=1
|
||||
print EraseMode
|
||||
set FirmwareSize=$RamFileSize
|
||||
print FirmwareSize
|
||||
|
||||
#continue to 524
|
||||
c
|
||||
|
||||
#printf "...\n"
|
||||
set $FLASHDATSRC = FlashDatSrc
|
||||
printf "FlashDatSrc:%x\n", $FLASHDATSRC
|
||||
|
||||
printf "FlashBlockWriteSize "
|
||||
set FlashBlockWriteSize = $FLASHDATBUFSIZE
|
||||
#p /x FlashBlockWriteSize
|
||||
printf "FlashBlockWriteSize:%x\n", FlashBlockWriteSize
|
||||
|
||||
printf "FlashAddrForWrite"
|
||||
set FlashAddrForWrite = 0x0
|
||||
|
||||
|
||||
|
||||
printf "Flash write start...\n"
|
||||
set $LoopCnt = 0
|
||||
while ($LoopCnt < $LoopNum)
|
||||
p /x FlashAddrForWrite
|
||||
restore ./application/Debug/bin/ram_all.bin binary ($FLASHDATSRC-$FILESTARTADDR) $FILESTARTADDR $FILEENDADDR
|
||||
c
|
||||
|
||||
printf "FILEENDADDR"
|
||||
p /x $FILEENDADDR
|
||||
set FlashBlockWriteSize = $FLASHDATBUFSIZE
|
||||
set FlashAddrForWrite = $FILEENDADDR
|
||||
set $FILESTARTADDR = $FILEENDADDR
|
||||
set $FILEENDADDR = $FILESTARTADDR + $FLASHDATBUFSIZE
|
||||
|
||||
set $LoopCnt = $LoopCnt + 0x01
|
||||
end
|
||||
|
||||
#set FlashBlockWriteSize = $FLASHDATBUFSIZE
|
||||
#set FlashAddrForWrite = $FILEENDADDR
|
||||
#set $FILESTARTADDR = $FILEENDADDR
|
||||
set $FILEENDADDR = $FILESTARTADDR + $TailSize
|
||||
restore ./application/Debug/bin/ram_all.bin binary ($FLASHDATSRC-$FILESTARTADDR) $FILESTARTADDR $FILEENDADDR
|
||||
c
|
||||
|
||||
#Set complete flas
|
||||
set FlashWriteComplete = 0x1
|
||||
|
||||
printf "dump for check\n"
|
||||
|
||||
set $LoopCnt = 0
|
||||
set $dumpaddr = 0
|
||||
|
||||
set $dumpstartaddr = $SPI_FLASH_BASE
|
||||
set $dumpendaddr = $SPI_FLASH_BASE + $RamFileSize
|
||||
printf "start addr of dumping"
|
||||
p /x $dumpstartaddr
|
||||
printf "end addr of dumping"
|
||||
p /x $dumpendaddr
|
||||
dump binary memory ./application/Debug/bin/dump.bin $dumpstartaddr $dumpendaddr
|
||||
|
||||
|
||||
delete
|
||||
b rtl_flash_download.c:556
|
||||
c
|
||||
|
||||
quit
|
||||
#===============================================================================
|
||||
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
# GDB script for loading ram.bin process
|
||||
|
||||
#===============================================================================
|
||||
#set GDB connection
|
||||
set remotetimeout 100000
|
||||
target remote :2331
|
||||
|
||||
#===============================================================================
|
||||
#Message display setting
|
||||
#disable all messages
|
||||
|
||||
set verbose off
|
||||
set complaints 0
|
||||
set confirm off
|
||||
set exec-done-display off
|
||||
show exec-done-display
|
||||
set trace-commands off
|
||||
#set debug aix-thread off
|
||||
#set debug dwarf2-die 0
|
||||
set debug displaced off
|
||||
set debug expression 0
|
||||
set debug frame 0
|
||||
set debug infrun 0
|
||||
set debug observer 0
|
||||
set debug overload 0
|
||||
set debugvarobj 0
|
||||
set pagination off
|
||||
set print address off
|
||||
set print symbol-filename off
|
||||
set print symbol off
|
||||
set print pretty off
|
||||
set print object off
|
||||
#set debug notification off
|
||||
set debug parser off
|
||||
set debug remote 0
|
||||
|
||||
#===============================================================================
|
||||
monitor reset 1
|
||||
monitor sleep 20
|
||||
monitor clrbp
|
||||
#===============================================================================
|
||||
#Init SDRAM here
|
||||
# init System
|
||||
monitor MemU32 0x40000014=0x00000021
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000304=0x1fc00002
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000250=0x00000400
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000340=0x00000000
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000230=0x0000dcc4
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000210=0x00011117
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000210=0x00011157
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x400002c0=0x00110011
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000320=0xffffffff
|
||||
monitor sleep 10
|
||||
# init SDRAM
|
||||
monitor MemU32 0x40000040=0x00fcc702
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000040
|
||||
monitor MemU32 0x40005224=0x00000001
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40005004=0x00000208
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40005008=0xffffd000
|
||||
monitor sleep 13
|
||||
monitor MemU32 0x40005020=0x00000022
|
||||
monitor sleep 13
|
||||
monitor MemU32 0x40005010=0x09006201
|
||||
monitor sleep 13
|
||||
monitor MemU32 0x40005014=0x00002611
|
||||
monitor sleep 13
|
||||
monitor MemU32 0x40005018=0x00068413
|
||||
monitor sleep 13
|
||||
monitor MemU32 0x4000501c=0x00000042
|
||||
monitor sleep 13
|
||||
monitor MemU32 0x4000500c=0x700
|
||||
monitor sleep 20
|
||||
monitor MemU32 0x40005000=0x1
|
||||
monitor sleep 100
|
||||
monitor MemU32 0x40005000
|
||||
monitor MemU32 0x4000500c=0x600
|
||||
monitor sleep 30
|
||||
|
||||
monitor MemU32 0x40005008=0x00000000
|
||||
monitor sleep 3
|
||||
monitor MemU32 0x40000300=0x0006005e
|
||||
monitor sleep 3
|
||||
#===============================================================================
|
||||
#Load flash download file
|
||||
file ./application/Debug/bin/application.axf
|
||||
|
||||
#boot from ram, igonore loading flash
|
||||
monitor MemU32 0x40000210=0x8011157
|
||||
|
||||
#Load the file
|
||||
lo
|
||||
|
||||
#Run to main
|
||||
b main
|
||||
continue
|
||||
clear main
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
# GDB script for loading ram.bin process
|
||||
|
||||
#===============================================================================
|
||||
#set GDB connection
|
||||
set remotetimeout 100000
|
||||
target remote :2331
|
||||
|
||||
#===============================================================================
|
||||
#Message display setting
|
||||
#disable all messages
|
||||
|
||||
set verbose off
|
||||
set complaints 0
|
||||
set confirm off
|
||||
set exec-done-display off
|
||||
show exec-done-display
|
||||
set trace-commands off
|
||||
#set debug aix-thread off
|
||||
#set debug dwarf2-die 0
|
||||
set debug displaced off
|
||||
set debug expression 0
|
||||
set debug frame 0
|
||||
set debug infrun 0
|
||||
set debug observer 0
|
||||
set debug overload 0
|
||||
set debugvarobj 0
|
||||
set pagination off
|
||||
set print address off
|
||||
set print symbol-filename off
|
||||
set print symbol off
|
||||
set print pretty off
|
||||
set print object off
|
||||
#set debug notification off
|
||||
set debug parser off
|
||||
set debug remote 0
|
||||
|
||||
#===============================================================================
|
||||
monitor reset 1
|
||||
monitor sleep 20
|
||||
monitor clrbp
|
||||
#===============================================================================
|
||||
#Init SDRAM here
|
||||
# init System
|
||||
monitor MemU32 0x40000014=0x00000021
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000304=0x1fc00002
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000250=0x00000400
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000340=0x00000000
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000230=0x0000dcc4
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000210=0x00011117
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000210=0x00011157
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x400002c0=0x00110011
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000320=0xffffffff
|
||||
monitor sleep 10
|
||||
# init SDRAM
|
||||
monitor MemU32 0x40000040=0x00fcc702
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40000040
|
||||
monitor MemU32 0x40005224=0x00000001
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40005004=0x00000208
|
||||
monitor sleep 10
|
||||
monitor MemU32 0x40005008=0xffffd000
|
||||
monitor sleep 13
|
||||
monitor MemU32 0x40005020=0x00000022
|
||||
monitor sleep 13
|
||||
monitor MemU32 0x40005010=0x09006201
|
||||
monitor sleep 13
|
||||
monitor MemU32 0x40005014=0x00002611
|
||||
monitor sleep 13
|
||||
monitor MemU32 0x40005018=0x00068413
|
||||
monitor sleep 13
|
||||
monitor MemU32 0x4000501c=0x00000042
|
||||
monitor sleep 13
|
||||
monitor MemU32 0x4000500c=0x700
|
||||
monitor sleep 20
|
||||
monitor MemU32 0x40005000=0x1
|
||||
monitor sleep 100
|
||||
monitor MemU32 0x40005000
|
||||
monitor MemU32 0x4000500c=0x600
|
||||
monitor sleep 30
|
||||
|
||||
monitor MemU32 0x40005008=0x00000000
|
||||
monitor sleep 3
|
||||
monitor MemU32 0x40000300=0x0006005e
|
||||
monitor sleep 3
|
||||
#===============================================================================
|
||||
#Load flash download file
|
||||
file ./application/Debug/bin/application.axf
|
||||
|
||||
#boot from ram, igonore loading flash
|
||||
monitor MemU32 0x40000210=0x8011157
|
||||
|
||||
#Load the file
|
||||
lo
|
||||
|
||||
#Run to main
|
||||
b main
|
||||
continue
|
||||
clear main
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
# GDB script for loading ram.bin process
|
||||
|
||||
#===============================================================================
|
||||
#set GDB connection
|
||||
set remotetimeout 100000
|
||||
target remote :3333
|
||||
|
||||
#===============================================================================
|
||||
#Message display setting
|
||||
#disable all messages
|
||||
|
||||
set verbose off
|
||||
set complaints 0
|
||||
set confirm off
|
||||
set exec-done-display off
|
||||
show exec-done-display
|
||||
set trace-commands off
|
||||
#set debug aix-thread off
|
||||
#set debug dwarf2-die 0
|
||||
set debug displaced off
|
||||
set debug expression 0
|
||||
set debug frame 0
|
||||
set debug infrun 0
|
||||
set debug observer 0
|
||||
set debug overload 0
|
||||
set debugvarobj 0
|
||||
set pagination off
|
||||
set print address off
|
||||
set print symbol-filename off
|
||||
set print symbol off
|
||||
set print pretty off
|
||||
set print object off
|
||||
#set debug notification off
|
||||
set debug parser off
|
||||
set debug remote 0
|
||||
|
||||
#===============================================================================
|
||||
monitor reset init
|
||||
monitor sleep 20
|
||||
monitor halt
|
||||
#===============================================================================
|
||||
#Load flash download file
|
||||
file ./application/Debug/bin/application.axf
|
||||
|
||||
#boot from ram, igonore loading flash
|
||||
set {int}0x40000210=0x8011157
|
||||
|
||||
#Load the file
|
||||
lo
|
||||
|
||||
#Run to main
|
||||
b main
|
||||
continue
|
||||
clear main
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
sdk/component/soc/realtek/8195a/misc/iar_utility/common/tools/checksum
Executable file
BIN
sdk/component/soc/realtek/8195a/misc/iar_utility/common/tools/checksum
Executable file
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
sdk/component/soc/realtek/8195a/misc/iar_utility/common/tools/padding
Executable file
BIN
sdk/component/soc/realtek/8195a/misc/iar_utility/common/tools/padding
Executable file
Binary file not shown.
Binary file not shown.
BIN
sdk/component/soc/realtek/8195a/misc/iar_utility/common/tools/pick
Executable file
BIN
sdk/component/soc/realtek/8195a/misc/iar_utility/common/tools/pick
Executable file
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,136 @@
|
|||
// pick.cpp : main project file.
|
||||
|
||||
#include "stdafx.h"
|
||||
|
||||
using namespace System;
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
//#include <unistd.h>
|
||||
#include <sys/stat.h>
|
||||
#include <fcntl.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#define PATTERN_1 0x96969999
|
||||
#define PATTERN_2 0xFC66CC3F
|
||||
#define PATTERN_3 0x03CC33C0
|
||||
#define PATTERN_4 0x6231DCE5
|
||||
|
||||
unsigned int fw_head[4] = { PATTERN_1, PATTERN_2, PATTERN_3, PATTERN_4 };
|
||||
unsigned int seg_head[4] = { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF };
|
||||
/*
|
||||
int main(array<System::String ^> ^args)
|
||||
{
|
||||
Console::WriteLine(L"Hello World");
|
||||
return 0;
|
||||
}
|
||||
*/
|
||||
int main(int argc, char* argv[])
|
||||
{
|
||||
int arg_num = 6;
|
||||
|
||||
if ((argc>5) && (strstr(argv[5], "head"))) arg_num++;
|
||||
|
||||
if (argc != arg_num){
|
||||
printf("Usage: pick.exe <start addr> <end addr> <input name> <output name> <body[+reset_offset][+sig], head[+reset_offset] [image2_start]>\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
unsigned char *buf;
|
||||
|
||||
unsigned int start;//=atoi(argv[1]);
|
||||
unsigned int end;// = atoi(argv[2]);
|
||||
unsigned int base;
|
||||
|
||||
int is_raw = 0;
|
||||
int is_sig = 0;
|
||||
|
||||
char *inf = argv[3];
|
||||
char *outf = argv[4];
|
||||
|
||||
int size;
|
||||
FILE *ifp, *ofp;
|
||||
|
||||
//if(argv[1][0]=='0'&&(argv[1][1]=='x'||argv[1][1]=='X'))
|
||||
// sscanf(argv[1], "0x%x", &start);
|
||||
//else
|
||||
// start=atoi(argv[1]);
|
||||
start = strtol(argv[1], NULL, 0);
|
||||
|
||||
//if(argv[2][0]=='0'&&(argv[2][1]=='x'||argv[2][1]=='X'))
|
||||
// sscanf(argv[2], "0x%x", &end);
|
||||
//else
|
||||
// end=atoi(argv[2]);
|
||||
end = strtol(argv[2], NULL, 0);
|
||||
|
||||
base = start & 0xFFFF0000;
|
||||
|
||||
if (strstr(argv[5], "reset_offset")){
|
||||
base = start;
|
||||
}
|
||||
|
||||
if (strstr(argv[5], "raw")){
|
||||
is_raw = 1;
|
||||
}
|
||||
else
|
||||
is_raw = 0;
|
||||
|
||||
if (strstr(argv[5], "sig")){
|
||||
is_sig = 1;
|
||||
}
|
||||
else
|
||||
is_sig = 0;
|
||||
|
||||
printf("b:%d s:%d e:%d\n", base, start, end);
|
||||
//printf("%s %s\n", inf, outf);
|
||||
|
||||
ifp = fopen(inf, "rb");
|
||||
if (!ifp) return -2;
|
||||
ofp = fopen(outf, "wb");
|
||||
if (!ofp) return -3;
|
||||
|
||||
fseek(ifp, 0, SEEK_END);
|
||||
size = ftell(ifp);
|
||||
|
||||
printf("size %d\n", size);
|
||||
buf = (unsigned char *)malloc(size);
|
||||
if (!buf) return -4;
|
||||
|
||||
if (end == 0) end = base + size;
|
||||
|
||||
if (end - start + 1 > 0){
|
||||
fseek(ifp, start - base, SEEK_SET);
|
||||
fread(buf, end - start, 1, ifp);
|
||||
if (is_raw == 0){
|
||||
if (strstr(argv[5], "head")){
|
||||
int offset = strtol(argv[6], NULL, 0);
|
||||
printf("append fw head %x\n", offset);
|
||||
fwrite(fw_head, 4, sizeof(unsigned int), ofp);
|
||||
seg_head[2] = (0xFFFF0000 | (offset / 1024));
|
||||
}
|
||||
else{
|
||||
if (is_sig){
|
||||
seg_head[2] = 0x35393138;
|
||||
seg_head[3] = 0x31313738;
|
||||
}
|
||||
else{
|
||||
seg_head[2] = 0xFFFFFFFF;
|
||||
seg_head[3] = 0xFFFFFFFF;
|
||||
}
|
||||
}
|
||||
seg_head[0] = end - start;
|
||||
seg_head[1] = start;
|
||||
fwrite(seg_head, 4, sizeof(unsigned int), ofp);
|
||||
}
|
||||
fwrite(buf, end - start, 1, ofp);
|
||||
|
||||
}
|
||||
printf("copy size %d\n", end - start);
|
||||
fclose(ifp);
|
||||
fclose(ofp);
|
||||
free(buf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Binary file not shown.
|
|
@ -0,0 +1,256 @@
|
|||
/*
|
||||
* rtl_lib.h
|
||||
*
|
||||
* Definitions for RTL library functions
|
||||
*/
|
||||
|
||||
#ifndef _RTL_LIB_ROM_H_
|
||||
#define _RTL_LIB_ROM_H_
|
||||
|
||||
|
||||
#include <basic_types.h>
|
||||
#include <diag.h>
|
||||
|
||||
#include <reent.h>
|
||||
|
||||
#include "../libc/rom/string/rom_libc_string.h"
|
||||
#include "../libgloss/rtl8195a/rom/rom_libgloss_retarget.h"
|
||||
|
||||
#ifndef _PTR
|
||||
#define _PTR void *
|
||||
#endif
|
||||
|
||||
#ifndef _AND
|
||||
#define _AND ,
|
||||
#endif
|
||||
|
||||
#ifndef _NOARGS
|
||||
#define _NOARGS void
|
||||
#endif
|
||||
|
||||
#ifndef _CONST
|
||||
#define _CONST const
|
||||
#endif
|
||||
|
||||
#ifndef _VOLATILE
|
||||
#define _VOLATILE volatile
|
||||
#endif
|
||||
|
||||
#ifndef _SIGNED
|
||||
#define _SIGNED signed
|
||||
#endif
|
||||
|
||||
#ifndef _DOTS
|
||||
#define _DOTS , ...
|
||||
#endif
|
||||
|
||||
#ifndef _VOID
|
||||
#define _VOID void
|
||||
#endif
|
||||
|
||||
|
||||
//
|
||||
// RTL library functions in ROM
|
||||
//
|
||||
|
||||
#define __rtl_memset __rtl_memset_v1_00
|
||||
#define __rtl_memchr __rtl_memchr_v1_00
|
||||
#define __rtl_memmove __rtl_memmove_v1_00
|
||||
#define __rtl_strcmp __rtl_strcmp_v1_00
|
||||
#define __rtl_memcpy __rtl_memcpy_v1_00
|
||||
|
||||
|
||||
|
||||
extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
|
||||
extern _LONG_CALL_ void * __rtl_memchr_v1_00(const void * src_void , int c , size_t length);
|
||||
extern _LONG_CALL_ void * __rtl_memmove_v1_00( void * dst_void , const void * src_void , size_t length);
|
||||
extern _LONG_CALL_ int __rtl_strcmp_v1_00(const char *s1 , const char *s2);
|
||||
extern _LONG_CALL_ void * __rtl_memcpy_v1_00(void * __restrict dst0 , const void * __restrict src0 , size_t len0);
|
||||
|
||||
|
||||
//
|
||||
// rtl eabi functions
|
||||
//
|
||||
|
||||
#define __rtl_itod __rtl_itod_v1_00
|
||||
#define __rtl_dtoi __rtl_dtoi_v1_00
|
||||
#define __rtl_uitof __rtl_uitof_v1_00
|
||||
#define __rtl_uitod __rtl_uitod_v1_00
|
||||
|
||||
|
||||
|
||||
#define __rtl_dcmpeq __rtl_dcmpeq_v1_00
|
||||
#define __rtl_dcmplt __rtl_dcmplt_v1_00
|
||||
#define __rtl_dcmpgt __rtl_dcmpgt_v1_00
|
||||
|
||||
|
||||
#define __rtl_dadd __rtl_dadd_v1_00
|
||||
#define __rtl_dsub __rtl_dsub_v1_00
|
||||
#define __rtl_dmul __rtl_dmul_v1_00
|
||||
#define __rtl_ddiv __rtl_ddiv_v1_00
|
||||
|
||||
extern _LONG_CALL_ double __rtl_itod_v1_00(int lval);
|
||||
extern _LONG_CALL_ int __rtl_dtoi_v1_00(double d);
|
||||
extern _LONG_CALL_ float __rtl_uitof_v1_00(unsigned int lval);
|
||||
extern _LONG_CALL_ double __rtl_uitod_v1_00(unsigned int lval);
|
||||
|
||||
|
||||
extern _LONG_CALL_ int __rtl_dcmpeq_v1_00(double a, double b);
|
||||
extern _LONG_CALL_ int __rtl_dcmplt_v1_00(double a, double b);
|
||||
extern _LONG_CALL_ int __rtl_dcmpgt_v1_00(double a, double b);
|
||||
|
||||
|
||||
extern _LONG_CALL_ double __rtl_dadd_v1_00(double a, double b);
|
||||
extern _LONG_CALL_ double __rtl_dsub_v1_00(double a, double b);
|
||||
extern _LONG_CALL_ double __rtl_dmul_v1_00(double a, double b);
|
||||
extern _LONG_CALL_ double __rtl_ddiv_v1_00(double a, double b);
|
||||
|
||||
|
||||
//
|
||||
// mprec
|
||||
//
|
||||
|
||||
#include <reent.h>
|
||||
|
||||
|
||||
typedef struct _Bigint _Bigint;
|
||||
|
||||
|
||||
#define __rtl_Balloc __rtl_Balloc_v1_00
|
||||
#define __rtl_Bfree __rtl_Bfree_v1_00
|
||||
#define __rtl_d2b __rtl_d2b_v1_00
|
||||
#define __rtl_i2b __rtl_i2b_v1_00
|
||||
#define __rtl_pow5mult __rtl_pow5mult_v1_00
|
||||
#define __rtl_multadd __rtl_multadd_v1_00
|
||||
#define __rtl_mult __rtl_mult_v1_00
|
||||
#define __rtl_hi0bits __rtl_hi0bits_v1_00
|
||||
#define __rtl_lshift __rtl_lshift_v1_00
|
||||
#define __rtl_cmp __rtl_cmp_v1_00
|
||||
#define __rtl_diff __rtl_diff_v1_00
|
||||
|
||||
|
||||
extern _LONG_CALL_ _Bigint * __rtl_Balloc_v1_00(struct _reent *ptr, int k);
|
||||
|
||||
extern _LONG_CALL_ void __rtl_Bfree_v1_00(struct _reent *ptr, _Bigint * v);
|
||||
|
||||
extern _LONG_CALL_ _Bigint * __rtl_d2b_v1_00(struct _reent * ptr, double _d, int *e, int *bits);
|
||||
extern _LONG_CALL_ _Bigint * __rtl_i2b_v1_00(struct _reent *ptr, int i );
|
||||
extern _LONG_CALL_ _Bigint * __rtl_pow5mult_v1_00(struct _reent * ptr, _Bigint *b, int k);
|
||||
extern _LONG_CALL_ _Bigint * __rtl_multadd_v1_00(struct _reent *ptr, _Bigint * b, int m, int a);
|
||||
extern _LONG_CALL_ _Bigint * __rtl_mult_v1_00(struct _reent *ptr, _Bigint *a, _Bigint *b);
|
||||
extern _LONG_CALL_ int __rtl_hi0bits_v1_00(register __ULong x);
|
||||
extern _LONG_CALL_ _Bigint *__rtl_lshift_v1_00(struct _reent *ptr, _Bigint *b, int k);
|
||||
extern _LONG_CALL_ int __rtl_cmp_v1_00(_Bigint *a, _Bigint *b);
|
||||
extern _LONG_CALL_ _Bigint *__rtl_diff_v1_00(struct _reent* ptr, _Bigint *a, _Bigint *b);
|
||||
|
||||
//
|
||||
// dtoa
|
||||
//
|
||||
|
||||
#define __rtl_dtoa_r __rtl_dtoa_r_v1_00
|
||||
|
||||
extern char * __rtl_dtoa_r_v1_00(struct _reent *ptr, double _d, int mode, int ndigits, int *decpt, int *sign, char **rve);
|
||||
|
||||
//
|
||||
// mallocr
|
||||
//
|
||||
#include <sys/config.h>
|
||||
#include <reent.h>
|
||||
|
||||
|
||||
|
||||
#define __rom_mallocr_init __rom_mallocr_init_v1_00
|
||||
|
||||
#define __rtl_calloc_r __rtl_calloc_r_v1_00
|
||||
#define __rtl_cfree_r __rtl_cfree_r_v1_00
|
||||
#define __rtl_malloc_r __rtl_malloc_r_v1_00
|
||||
#define __rtl_free_r __rtl_free_r_v1_00
|
||||
#define __rtl_realloc_r __rtl_realloc_r_v1_00
|
||||
#define __rtl_memalign_r __rtl_memalign_r_v1_00
|
||||
#define __rtl_valloc_r __rtl_valloc_r_v1_00
|
||||
#define __rtl_pvalloc_r __rtl_pvalloc_r_v1_00
|
||||
|
||||
|
||||
extern _LONG_CALL_ void __rom_mallocr_init_v1_00(void);
|
||||
|
||||
|
||||
#define RARG struct _reent *reent_ptr,
|
||||
extern _LONG_CALL_ void* __rtl_calloc_r_v1_00(RARG size_t n, size_t elem_size);
|
||||
extern _LONG_CALL_ void __rtl_cfree_r_v1_00(void *mem);
|
||||
extern _LONG_CALL_ void* __rtl_malloc_r_v1_00(RARG size_t bytes);
|
||||
extern _LONG_CALL_ void __rtl_free_r_v1_00(RARG void* mem);
|
||||
extern _LONG_CALL_ void* __rtl_realloc_r_v1_00(RARG void* oldmem, size_t bytes);
|
||||
extern _LONG_CALL_ void* __rtl_memalign_r_v1_00(RARG size_t alignment, size_t bytes);
|
||||
extern _LONG_CALL_ void* __rtl_valloc_r_v1_00(RARG size_t bytes);
|
||||
extern _LONG_CALL_ void* __rtl_pvalloc_r_v1_00(RARG size_t bytes);
|
||||
|
||||
|
||||
//
|
||||
// stdio
|
||||
//
|
||||
extern int __rtl_errno;
|
||||
|
||||
#ifndef _READ_WRITE_RETURN_TYPE
|
||||
#define _READ_WRITE_RETURN_TYPE _ssize_t
|
||||
#endif
|
||||
|
||||
#ifndef _READ_WRITE_BUFSIZE_TYPE
|
||||
#define _READ_WRITE_BUFSIZE_TYPE int
|
||||
#endif
|
||||
|
||||
#define __rtl_sread __rtl_sread_v1_00
|
||||
#define __rtl_swrite __rtl_swrite_v1_00
|
||||
#define __rtl_seofread __rtl_seofread_v1_00
|
||||
#define __rtl_sseek __rtl_sseek_v1_00
|
||||
#define __rtl_sclose __rtl_sclose_v1_00
|
||||
#define __rtl_sbrk_r __rtl_sbrk_r_v1_00
|
||||
|
||||
extern _LONG_CALL_ _READ_WRITE_RETURN_TYPE __rtl_sread_v1_00(
|
||||
struct _reent *ptr,
|
||||
void *cookie,
|
||||
char *buf,
|
||||
_READ_WRITE_BUFSIZE_TYPE n);
|
||||
|
||||
extern _LONG_CALL_ _READ_WRITE_RETURN_TYPE __rtl_swrite_v1_00(
|
||||
struct _reent *ptr,
|
||||
void *cookie,
|
||||
char const *buf,
|
||||
_READ_WRITE_BUFSIZE_TYPE n);
|
||||
|
||||
extern _LONG_CALL_ _READ_WRITE_RETURN_TYPE __rtl_seofread_v1_00(
|
||||
struct _reent *_ptr,
|
||||
_PTR cookie,
|
||||
char *buf,
|
||||
_READ_WRITE_BUFSIZE_TYPE len);
|
||||
|
||||
extern _LONG_CALL_ _fpos_t __rtl_sseek_v1_00(
|
||||
struct _reent *ptr _AND
|
||||
void *cookie _AND
|
||||
_fpos_t offset _AND
|
||||
int whence);
|
||||
|
||||
extern _LONG_CALL_ int __rtl_sclose_v1_00(
|
||||
struct _reent *ptr _AND
|
||||
void *cookie);
|
||||
|
||||
extern _LONG_CALL_ void * __rtl_sbrk_r_v1_00(
|
||||
struct _reent *ptr,
|
||||
ptrdiff_t incr);
|
||||
|
||||
//
|
||||
// vfprintf
|
||||
//
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdarg.h>
|
||||
|
||||
#define __rtl_vfprintf_r __rtl_vfprintf_r_v1_00
|
||||
|
||||
extern _LONG_CALL_ int __rtl_vfprintf_r_v1_00(struct _reent *, FILE *, const char *, va_list);
|
||||
|
||||
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
|
||||
#define __rtl_fflush_r __rtl_fflush_r_v1_00
|
||||
extern _LONG_CALL_ int __rtl_fflush_r_v1_00(struct _reent *ptr, register FILE * fp);
|
||||
#endif
|
||||
|
||||
#endif /* _RTL_LIB_ROM_H_ */
|
||||
|
|
@ -0,0 +1,234 @@
|
|||
/*
|
||||
* rtl_bios_data.h
|
||||
*
|
||||
* Created on: 12/02/2017
|
||||
* Author: pvvx
|
||||
*
|
||||
* This variables declared in ROM code!
|
||||
* Variables use fixed addresses!
|
||||
* (see *.ld script)
|
||||
*/
|
||||
|
||||
#ifndef _RTL_BIOS_DATA_H_
|
||||
#define _RTL_BIOS_DATA_H_
|
||||
|
||||
#include "platform_autoconf.h"
|
||||
#include <stdarg.h>
|
||||
#include <stddef.h>
|
||||
#include <stdio.h>
|
||||
#include <sys/reent.h>
|
||||
// component/soc/realtek/common/bsp/
|
||||
#include "basic_types.h"
|
||||
// component/soc/realtek/8195a/fwlib/
|
||||
#include "rtl8195a/rtl8195a.h"
|
||||
#include "hal_gpio.h"
|
||||
#include "hal_irqn.h"
|
||||
#include "hal_timer.h"
|
||||
#include "hal_sdr_controller.h"
|
||||
// component/soc/realtek/8195a/fwlib/
|
||||
#include "ram_lib/wlan/realtek/wlan_ram_map/rom/rom_wlan_ram_map.h"
|
||||
// component/soc/realtek/8195a/misc/driver/
|
||||
#include "rtl_consol.h"
|
||||
// component/soc/realtek/8195a/misc/rtl_std_lib/
|
||||
#include "include/rtl_lib.h"
|
||||
#include "include/rt_lib_rom.h"
|
||||
#include "libc/rom/string/rom_libc_string.h"
|
||||
#include "libgloss/rtl8195a/rom/rom_libgloss_retarget.h"
|
||||
|
||||
//#include "rom/rom_libgloss_retarget.h"
|
||||
|
||||
typedef void (*START_FUNC)(void);
|
||||
|
||||
/* ROM + startup.c */
|
||||
extern IRQ_FUN NewVectorTable[64]; // 10000000
|
||||
extern IRQ_FUN UserIrqFunTable[64]; // 10000100
|
||||
extern u32 UserIrqDataTable[64]; // 10000200
|
||||
|
||||
/* ROM + diag.h */
|
||||
extern u32 CfgSysDebugWarn; // 10000300
|
||||
extern u32 CfgSysDebugInfo; // 10000304
|
||||
extern u32 CfgSysDebugErr; // 10000308
|
||||
extern u32 ConfigDebugWarn; // 1000030c
|
||||
extern u32 ConfigDebugInfo; // 10000310
|
||||
extern u32 ConfigDebugErr; // 10000314
|
||||
|
||||
|
||||
/* ROM + hal_timer.h & .. */
|
||||
extern HAL_TIMER_OP HalTimerOp; // 10000318
|
||||
extern u16 GPIOState[11]; // 10000334
|
||||
extern u32 gTimerRecord; // 1000034C
|
||||
/* ROM + hal_ssi.h */
|
||||
extern u32 SSI_DBG_CONFIG; // 10000350
|
||||
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter; // 10000354
|
||||
|
||||
/* ROM + rtl8195a_timer.c */
|
||||
extern IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM]; // 10000358
|
||||
|
||||
/* ROM + Rand() */
|
||||
extern u32 _rand_z4, _rand_z3, _rand_z2, _rand_z1, _rand_first; // 10000370..
|
||||
|
||||
/* ROM + rtl_consol.c */
|
||||
extern volatile UART_LOG_CTL *pUartLogCtl; // 10000384
|
||||
extern UART_LOG_BUF UartLogBuf; // 10000388
|
||||
extern volatile UART_LOG_CTL UartLogCtl; // 10000408
|
||||
extern u8 UartLogHistoryBuf[UART_LOG_HISTORY_LEN][UART_LOG_CMD_BUFLEN]; // 10000430 UartLogHistoryBuf[5][127] !
|
||||
extern u8 *ArgvArray[MAX_ARGV]; // 100006AC *ArgvArray[10] !
|
||||
|
||||
/* ROM + ?? */
|
||||
extern struct _rom_wlan_ram_map rom_wlan_ram_map; // 100006D4
|
||||
typedef struct _FALSE_ALARM_STATISTICS {
|
||||
u32 Cnt_Parity_Fail;
|
||||
u32 Cnt_Rate_Illegal;
|
||||
u32 Cnt_Crc8_fail;
|
||||
u32 Cnt_Mcs_fail;
|
||||
u32 Cnt_Ofdm_fail;
|
||||
u32 Cnt_Ofdm_fail_pre;
|
||||
u32 Cnt_Cck_fail;
|
||||
u32 Cnt_all;
|
||||
u32 Cnt_Fast_Fsync;
|
||||
u32 Cnt_SB_Search_fail;
|
||||
u32 Cnt_OFDM_CCA;
|
||||
u32 Cnt_CCK_CCA;
|
||||
u32 Cnt_CCA_all;
|
||||
u32 Cnt_BW_USC;
|
||||
u32 Cnt_BW_LSC;
|
||||
} FALSE_ALARM_STATISTICS;
|
||||
extern FALSE_ALARM_STATISTICS FalseAlmCnt; // 100006E0
|
||||
|
||||
typedef struct _rom_info {
|
||||
u8 EEPROMVersion;
|
||||
u8 CrystalCap;
|
||||
u64 DebugComponents;
|
||||
u32 DebugLevel;
|
||||
} ROM_INFO;
|
||||
extern ROM_INFO ROMInfo; // 10000720
|
||||
|
||||
typedef struct _CFO_TRACKING_ {
|
||||
BOOL bATCStatus;
|
||||
BOOL largeCFOHit;
|
||||
BOOL bAdjust;
|
||||
u8 CrystalCap;
|
||||
u8 DefXCap;
|
||||
u32 CFO_tail[2];
|
||||
u32 CFO_ave_pre;
|
||||
u32 packetCount;
|
||||
u32 packetCount_pre;
|
||||
BOOL bForceXtalCap;
|
||||
BOOL bReset;
|
||||
u8 CFO_TH_XTAL_HIGH;
|
||||
u8 CFO_TH_XTAL_LOW;
|
||||
u8 CFO_TH_ATC;
|
||||
}CFO_TRACKING;
|
||||
extern CFO_TRACKING DM_CfoTrack; // 10000738
|
||||
|
||||
/* in rom_libgloss_retarget.h
|
||||
struct _rom_libgloss_ram_map {
|
||||
int (*libgloss_close)(int fildes);
|
||||
int (*libgloss_fstat)(int fildes , struct stat *st);
|
||||
int (*libgloss_isatty)(int file);
|
||||
int (*libgloss_lseek)(int file , int ptr , int dir);
|
||||
int (*libgloss_open)(char *file , int flags , int mode);
|
||||
int (*libgloss_read)(int file , char *ptr , int len);
|
||||
int (*libgloss_write)(int file , const char *ptr , int len);
|
||||
void* (*libgloss_sbrk)(int incr);
|
||||
};
|
||||
*/
|
||||
extern struct _rom_libgloss_ram_map rom_libgloss_ram_map; // 10000760
|
||||
struct malloc_chunk
|
||||
{
|
||||
size_t prev_size;
|
||||
size_t size;
|
||||
struct malloc_chunk *fd;
|
||||
struct malloc_chunk *bk;
|
||||
};
|
||||
extern struct malloc_chunk * __rtl_malloc_av_[258]; // 10000780 __rom_mallocr_init_v1_00(), _rtl_free_r_v1_00()..
|
||||
extern u32 __rtl_malloc_trim_threshold; // 10000b88 __rom_mallocr_init_v1_00()
|
||||
extern u32 __rtl_malloc_top_pad; // 10000b8c __rom_mallocr_init_v1_00()
|
||||
extern u8 * __rtl_malloc_sbrk_base; // 10000b90 __rom_mallocr_init_v1_00()
|
||||
extern u32 __rtl_malloc_max_sbrked_mem; // 10000b94 __rom_mallocr_init_v1_00()
|
||||
extern u32 __rtl_malloc_max_total_mem; // 10000b98 __rom_mallocr_init_v1_00()
|
||||
struct mallinfo
|
||||
{
|
||||
int arena;
|
||||
int ordblks;
|
||||
int smblks;
|
||||
int hblks;
|
||||
int hblkhd;
|
||||
int usmblks;
|
||||
int fsmblks;
|
||||
int uordblks;
|
||||
int fordblks;
|
||||
int keepcost;
|
||||
};
|
||||
extern struct mallinfo __rtl_malloc_current_mallinfo; // 10000b9c __rom_mallocr_init_v1_00()
|
||||
|
||||
/* IMAGE1 HEAD: ROM + startup.c (bootloader) */
|
||||
extern RAM_START_FUNCTION gRamStartFun; // 10000bc8 = { PreProcessForVendor + 1 };
|
||||
extern RAM_START_FUNCTION gRamPatchWAKE; // 10000bcc = { RtlBootToSram + 1 };
|
||||
extern RAM_START_FUNCTION gRamPatchFun0; // 10000bd0 = { RtlBootToSram + 1 };
|
||||
extern RAM_START_FUNCTION gRamPatchFun1; // 10000bd4 = { RtlBootToSram + 1 };
|
||||
extern RAM_START_FUNCTION gRamPatchFun2; // 10000bd8 = { RtlBootToSram + 1 };
|
||||
//extern uint8 RAM_IMG1_VALID_PATTEN[8]; // 10000bdc = { 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff };
|
||||
|
||||
/* ROM + hal_sdr_controller.c */
|
||||
extern u32 rand_x; // 10000be4: ChangeRandSeed_rom(), Sdr_Rand2_rom()
|
||||
#define REC_NUM 512
|
||||
extern u32 AvaWds[2][REC_NUM]; // 10000be8
|
||||
extern DRAM_DEVICE_INFO SdrDramInfo; // 10001be8
|
||||
#define DRAM_DEVICE_INFO_INIT() { \
|
||||
&SdrDramDev, \
|
||||
&SdrDramModeReg, \
|
||||
&SdrDramTiming, \
|
||||
DRAM_TIMING_TCK, \
|
||||
DFI_RATIO_1 }
|
||||
extern DRAM_TIMING_INFO SdrDramTiming; // 10001bfc
|
||||
#define DRAM_TIMING_INFO_INIT() { \
|
||||
DRAM_TIMING_TRFC, /* TrfcPs; */ \
|
||||
DRAM_TIMING_TREFI, /* TrefiPs; */ \
|
||||
DRAM_TIMING_TWRMAXTCK, /* WrMaxTck; */\
|
||||
DRAM_TIMING_TRCD, /* TrcdPs; */ \
|
||||
DRAM_TIMING_TRP, /* TrpPs; */ \
|
||||
DRAM_TIMING_TRAS, /* TrasPs; */ \
|
||||
DRAM_TIMING_TRRD, /* TrrdTck; */ \
|
||||
DRAM_TIMING_TWR, /* TwrPs; */ \
|
||||
DRAM_TIMING_TWTR, /* TwtrTck; */ \
|
||||
/* 13090, */ /* TrtpPs; */ \
|
||||
DRAM_TIMING_TMRD, /* TmrdTck; */ \
|
||||
DRAM_TIMING_TRTP, /* TrtpTck; */ \
|
||||
DRAM_TIMING_TCCD, /* TccdTck; */ \
|
||||
DRAM_TIMING_TRC } /* TrcPs; */
|
||||
extern DRAM_MODE_REG_INFO SdrDramModeReg; // 10001c30
|
||||
#define DRAM_MODE_REG_INFO_INIT() { \
|
||||
BST_LEN_4, \
|
||||
SENQUENTIAL, \
|
||||
0x3, /* Mode0Cas: 3 */ \
|
||||
0x0, /* Mode0Wr */ \
|
||||
0, /* Mode1DllEnN */ \
|
||||
0, /* Mode1AllLat */ \
|
||||
0 } /* Mode2Cwl */
|
||||
extern DRAM_INFO SdrDramDev; // 10001c4c
|
||||
#define DRAM_INFO_INIT() { DRAM_INFO_TYPE, DRAM_INFO_COL_ADDR_WTH,DRAM_INFO_BANK_SZ, DRAM_INFO_DQ_WTH }
|
||||
extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90]
|
||||
|
||||
/* ROM + "C" standard library */
|
||||
extern struct _reent * _rtl_impure_ptr; // 10001c60 = { &impure_reent };
|
||||
extern struct _reent impure_reent; // 10001c68 = _REENT_INIT(impure_reent);
|
||||
|
||||
/* ROM ? UserData? */
|
||||
extern u32 _rom_unc_data[9]; // 100020e8
|
||||
|
||||
/* ROM + hal_sdr_controller.c: Sdr_Rand2() */
|
||||
extern u32 _sdr_rnd2_c, _sdr_rnd2_z, _sdr_rnd2_y; // 100020BC, 100020B8, 100020B4
|
||||
|
||||
/* *.ld */
|
||||
extern u8 __rom_bss_start__, __rom_bss_end__;
|
||||
extern u8 __image1_bss_start__, __image1_bss_end__;
|
||||
extern START_FUNC __image2_entry_func__;
|
||||
//extern RAM_START_FUNCTION __image2_entry_func__;
|
||||
extern u8 __image2_validate_code__;
|
||||
|
||||
#ifndef STACK_TOP
|
||||
#define STACK_TOP 0x1ffffffc
|
||||
#endif
|
||||
|
||||
#endif /* _RTL_BIOS_DATA_H_ */
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
/*
|
||||
* rtl_lib.h
|
||||
*
|
||||
* Definitions for RTL library functions
|
||||
*/
|
||||
|
||||
#ifndef _RTL_LIB_H_
|
||||
#define _RTL_LIB_H_
|
||||
|
||||
|
||||
#include <basic_types.h>
|
||||
#include <diag.h>
|
||||
#include <stdarg.h>
|
||||
|
||||
|
||||
extern int __rtl_errno;
|
||||
|
||||
|
||||
void init_rom_libgloss_ram_map(void);
|
||||
|
||||
|
||||
//
|
||||
// RTL library functions for Libc::stdio
|
||||
//
|
||||
|
||||
extern int rtl_printf(IN const char* fmt, ...);
|
||||
extern int rtl_vprintf(const char *fmt, va_list param);
|
||||
extern int rtl_sprintf(char* str, const char* fmt, ...);
|
||||
extern int rtl_snprintf(char* str, size_t size, const char* fmt, ...);
|
||||
extern int rtl_vsnprintf(char *str, size_t size, const char *fmt, va_list param);
|
||||
|
||||
//
|
||||
// RTL library functions for string
|
||||
//
|
||||
|
||||
extern void * rtl_memchr(const void * src_void , int c , size_t length);
|
||||
extern int rtl_memcmp(const void * m1 , const void * m2 , size_t n);
|
||||
extern void * rtl_memcpy(void * dst0 , const void * src0 , size_t len0);
|
||||
extern void * rtl_memmove( void * dst_void , const void * src_void , size_t length);
|
||||
extern void * rtl_memset(void * m , int c , size_t n);
|
||||
extern char * rtl_strcat(char * s1 , const char * s2);
|
||||
extern char * rtl_strchr(const char *s1 , int i);
|
||||
extern int rtl_strcmp(const char *s1 , const char *s2);
|
||||
extern char* rtl_strcpy(char *dst0 , const char *src0);
|
||||
extern size_t rtl_strlen(const char *str);
|
||||
extern char * rtl_strncat(char * s1 , const char * s2 , size_t n);
|
||||
extern int rtl_strncmp(const char *s1 , const char *s2 , size_t n);
|
||||
extern char * rtl_strncpy(char * dst0 , const char * src0 , size_t count);
|
||||
extern char * rtl_strstr(const char *searchee , const char *lookfor);
|
||||
extern char * rtl_strsep(char **source_ptr , const char *delim);
|
||||
extern char * rtl_strtok(char * s , const char * delim);
|
||||
|
||||
//
|
||||
// RTL library functions for math
|
||||
//
|
||||
|
||||
|
||||
extern double rtl_fabs(double);
|
||||
extern float rtl_fabsf(float a);
|
||||
extern float rtl_cos_f32(float a);
|
||||
extern float rtl_sin_f32(float a);
|
||||
|
||||
extern float rtl_fadd(float a, float b);
|
||||
extern float rtl_fsub(float a, float b);
|
||||
extern float rtl_fmul(float a, float b);
|
||||
extern float rtl_fdiv(float a, float b);
|
||||
|
||||
extern int rtl_fcmplt(float a, float b);
|
||||
extern int rtl_fcmpgt(float a, float b);
|
||||
|
||||
|
||||
//
|
||||
// RTL eabi functions
|
||||
|
||||
extern double rtl_ftod(float f);
|
||||
|
||||
extern double rtl_ddiv(double a, double b);
|
||||
|
||||
|
||||
//
|
||||
// Macro Library Functions
|
||||
//
|
||||
|
||||
typedef union
|
||||
{
|
||||
float value;
|
||||
u32 word;
|
||||
} ieee_float_shape_type;
|
||||
|
||||
/* Get a 32 bit int from a float. */
|
||||
|
||||
#define GET_FLOAT_WORD(i,d) \
|
||||
do { \
|
||||
ieee_float_shape_type gf_u; \
|
||||
gf_u.value = (d); \
|
||||
(i) = gf_u.word; \
|
||||
} while (0)
|
||||
|
||||
/* Set a float from a 32 bit int. */
|
||||
|
||||
#define SET_FLOAT_WORD(d,i) \
|
||||
do { \
|
||||
ieee_float_shape_type sf_u; \
|
||||
sf_u.word = (i); \
|
||||
(d) = sf_u.value; \
|
||||
} while (0)
|
||||
|
||||
static inline
|
||||
float rtl_nanf(void)
|
||||
{
|
||||
float x;
|
||||
|
||||
SET_FLOAT_WORD(x,0x7fc00000);
|
||||
return x;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// Library Test functions
|
||||
//
|
||||
|
||||
extern int rtl_lib_test(IN u16 argc, IN u8 *argv[]);
|
||||
extern int rtl_math_test(IN u16 argc, IN u8 *argv[]);
|
||||
extern int rtl_string_test(IN u16 argc, IN u8 *argv[]);
|
||||
|
||||
|
||||
//
|
||||
// Macro functions
|
||||
//
|
||||
|
||||
#undef dbg_printf
|
||||
#define dbg_printf(fmt, args...) \
|
||||
rtl_printf("%s():%d : " fmt "\n", __FUNCTION__, __LINE__, ##args);
|
||||
|
||||
|
||||
#undef err_printf
|
||||
#define err_printf(fmt, args...) \
|
||||
rtl_printf("%s():%d : " fmt "\n", __FUNCTION__, __LINE__, ##args);
|
||||
|
||||
|
||||
#endif /* _RTL_LIB_H_ */
|
||||
|
|
@ -0,0 +1,166 @@
|
|||
/*
|
||||
* RAM->ROM Calls
|
||||
*/
|
||||
|
||||
#ifndef _INC_RTL_RR_LIBC_
|
||||
#define _INC_RTL_RR_LIBC_
|
||||
|
||||
//#undef malloc
|
||||
#define malloc(size) pvPortMalloc(size)
|
||||
//#undef free
|
||||
#define free(pbuf) vPortFree(pbuf)
|
||||
//extern void* pvPortReAlloc( void *pv, size_t xWantedSize )
|
||||
#define realloc(pv, xWantedSize) pvPortReAlloc(pv, xWantedSize)
|
||||
|
||||
#define calloc(nelements, elementSize) calloc_freertos(nelements, elementSize)
|
||||
|
||||
#define snprintf rtl_snprintf
|
||||
#define sprintf rtl_sprintf
|
||||
#define printf rtl_printf
|
||||
#define vprintf rtl_vprintf
|
||||
#define vsnprintf rtl_vsnprintf
|
||||
#define vfprintf rtl_vfprintf
|
||||
#define memchr rtl_memchr
|
||||
#define memcmp rtl_memcmp
|
||||
#define memcpy rtl_memcpy
|
||||
#define memmove rtl_memmove
|
||||
#define memset rtl_memset
|
||||
#define strcat rtl_strcat
|
||||
#define strchr rtl_strchr
|
||||
#define strcmp rtl_strcmp
|
||||
#define strcpy rtl_strcpy
|
||||
#define strlen rtl_strlen
|
||||
#define strncat rtl_strncat
|
||||
#define strncmp rtl_strncmp
|
||||
#define strncpy rtl_strncpy
|
||||
#define strstr rtl_strstr
|
||||
#define strsep rtl_strsep
|
||||
#define strtok rtl_strtok
|
||||
|
||||
#if 0 // __aeabi_
|
||||
#define dtoi rtl_dtoi
|
||||
#define dtoui rtl_dtoui
|
||||
#define i2f rtl_i2f
|
||||
#define i2d rtl_i2d
|
||||
#define ui2f rtl_ui2f
|
||||
#define ui2d rtl_ui2d
|
||||
#define itoa rtl_itoa
|
||||
#define ltoa rtl_ltoa
|
||||
#define utoa rtl_utoa
|
||||
#define ultoa rtl_ultoa
|
||||
#define ftol rtl_ftol
|
||||
#define ftod rtl_ftod
|
||||
#define dtof rtl_dtof
|
||||
#define fadd rtl_fadd
|
||||
#define fsub rtl_fsub
|
||||
#define fmul rtl_fmul
|
||||
#define fdiv rtl_fdiv
|
||||
#define dadd rtl_dadd
|
||||
#define dsub rtl_dsub
|
||||
#define dmul rtl_dmul
|
||||
#define ddiv rtl_ddiv
|
||||
#define dcmpeq rtl_dcmpeq
|
||||
#define dcmplt rtl_dcmplt
|
||||
#define dcmple rtl_dcmple
|
||||
#define dcmpgt rtl_dcmpgt
|
||||
#define fcmplt rtl_fcmplt
|
||||
#define fcmpgt rtl_fcmpgt
|
||||
|
||||
#define fabsf rtl_fabsf
|
||||
#define fabs rtl_fabs
|
||||
#define cos_f32 rtl_cos_f32
|
||||
#define sin_f32 rtl_sin_f32
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
extern void *calloc_freertos(size_t nelements, size_t elementSize);
|
||||
// ram_libc.c
|
||||
extern void rtl_libc_init(void);
|
||||
extern int rtl_snprintf(char *str, size_t size, const char *fmt, ...);
|
||||
extern int rtl_sprintf(char *str, const char *fmt, ...);
|
||||
extern int rtl_printf(const char *fmt, ...);
|
||||
extern int rtl_vprintf(const char *fmt, void *param);
|
||||
extern int rtl_vsnprintf(char *str, size_t size, const char *fmt, void *param);
|
||||
extern int rtl_vfprintf(FILE *fp, const char *fmt0, va_list ap);
|
||||
extern void * rtl_memchr(const void * src_void , int c , size_t length);
|
||||
extern int rtl_memcmp(const void *m1, const void *m2, size_t n);
|
||||
extern void * rtl_memcpy(void *dst0, const void *src0, size_t len0);
|
||||
extern void * rtl_memmove(void *dst_void, const void *src_void, size_t length);
|
||||
extern void * rtl_memset(void *m, int c, size_t n);
|
||||
extern char * rtl_strcat(char *s1, const char *s2);
|
||||
extern char * rtl_strchr(const char *s1, int i);
|
||||
extern int rtl_strcmp(const char *s1, const char *s2);
|
||||
extern char * rtl_strcpy(char *dst0, const char *src0);
|
||||
extern size_t rtl_strlen(const char *str);
|
||||
extern char * rtl_strncat(char *s1, const char *s2, size_t n);
|
||||
extern int rtl_strncmp(const char *s1, const char *s2, size_t n);
|
||||
extern char * rtl_strncpy(char *dst0, const char *src0, size_t count);
|
||||
extern char * rtl_strstr(const char *searchee, const char *lookfor);
|
||||
extern char * rtl_strsep(char **source_ptr, const char *delim);
|
||||
extern char * rtl_strtok(char *s, const char *delim);
|
||||
|
||||
//rtl_eabi_cast_ram.c
|
||||
extern int rtl_dtoi(double d);
|
||||
extern int rtl_dtoui(double d);
|
||||
extern float rtl_i2f(int val);
|
||||
extern int rtl_i2d(int val);
|
||||
extern float rtl_ui2f(unsigned int val);
|
||||
extern int rtl_ui2d(unsigned int val);
|
||||
extern char *rtl_itoa(int value, char *string, int radix);
|
||||
extern char *rtl_ltoa(int value, char *string, int radix);
|
||||
extern char *rtl_utoa(unsigned int value, char *string, int radix);
|
||||
extern char *rtl_ultoa(unsigned int value, char *string, int radix);
|
||||
extern int rtl_ftol(float f);
|
||||
extern int rtl_ftod(float f);
|
||||
extern float rtl_dtof(double d);
|
||||
extern float rtl_fadd(float a, float b);
|
||||
extern float rtl_fsub(float a, float b);
|
||||
extern float rtl_fmul(float a, float b);
|
||||
extern float rtl_fdiv(float a, float b);
|
||||
extern int rtl_dadd(double a, double b);
|
||||
extern int rtl_dsub(double a, double b);
|
||||
extern int rtl_dmul(double a, double b);
|
||||
extern int rtl_ddiv(double a, double b);
|
||||
extern int rtl_dcmpeq(double a, double b);
|
||||
extern int rtl_dcmplt(double a, double b);
|
||||
extern int rtl_dcmple(double a, double b);
|
||||
extern int rtl_dcmpgt(double a, double b);
|
||||
extern int rtl_fcmplt(float a, float b);
|
||||
extern int rtl_fcmpgt(float a, float b);
|
||||
|
||||
// rtl_math_ram.c
|
||||
extern float rtl_fabsf(float a);
|
||||
extern int rtl_fabs(double a);
|
||||
extern float rtl_cos_f32(float a);
|
||||
extern float rtl_sin_f32(float a);
|
||||
|
||||
// ram_pvvx_libc.c
|
||||
extern int snprintf(char *str, size_t size, const char *fmt, ...);
|
||||
extern int sprintf(char *str, const char *fmt, ...);
|
||||
extern int printf(const char *fmt, ...);
|
||||
extern int vprintf(const char * fmt, __VALIST param);
|
||||
extern int vsnprintf(char *str, size_t size, const char *fmt, __VALIST param);
|
||||
extern int vfprintf(FILE *fp, const char *fmt0, va_list ap);
|
||||
extern void * memchr(const void * src_void , int c , size_t length);
|
||||
extern int memcmp(const void *m1, const void *m2, size_t n);
|
||||
extern void * memcpy(void *dst0, const void *src0, size_t len0);
|
||||
extern void * memmove(void *dst_void, const void *src_void, size_t length);
|
||||
extern void * memset(void *m, int c, size_t n);
|
||||
extern char * strcat(char *s1, const char *s2);
|
||||
extern char * strchr(const char *s1, int i);
|
||||
extern int strcmp(const char *s1, const char *s2);
|
||||
extern char * strcpy(char *dst0, const char *src0);
|
||||
extern size_t strlen(const char *str);
|
||||
extern char * strncat(char *s1, const char *s2, size_t n);
|
||||
extern int strncmp(const char *s1, const char *s2, size_t n);
|
||||
extern char * strncpy(char *dst0, const char *src0, size_t count);
|
||||
extern char * strstr(const char *searchee, const char *lookfor);
|
||||
extern char * strsep(char **source_ptr, const char *delim);
|
||||
extern char * strtok(char *s, const char *delim);
|
||||
extern int sscanf(const char *buf, const char *fmt, ...);
|
||||
extern char toupper(char ch);
|
||||
extern int _stricmp (const char *s1, const char *s2);
|
||||
extern unsigned long long __aeabi_llsr(unsigned long long val, unsigned int shift);
|
||||
#endif
|
||||
|
||||
#endif // _INC_RTL_RR_LIBC_
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,292 @@
|
|||
/*
|
||||
* ram_libc.o
|
||||
* pvvx 2016
|
||||
*/
|
||||
|
||||
#include "rtl_bios_data.h"
|
||||
#include "va_list.h"
|
||||
|
||||
#define CHECK_LIBC_INIT 0
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Function declarations
|
||||
#if 0
|
||||
void rtl_libc_init(void);
|
||||
int rtl_snprintf(char *str, size_t size, const char *fmt, ...);
|
||||
int rtl_sprintf(char *str, const char *fmt, ...);
|
||||
int rtl_printf(const char *fmt, ...);
|
||||
int rtl_vprintf(const char *fmt, void *param);
|
||||
int rtl_vsnprintf(char *str, size_t size, const char *fmt, void *param);
|
||||
int rtl_vfprintf(FILE *fp, const char *fmt0, va_list ap);
|
||||
void * rtl_memchr(const void * src_void , int c , size_t length);
|
||||
int rtl_memcmp(const void *m1, const void *m2, size_t n);
|
||||
void * rtl_memcpy(void *dst0, const void *src0, size_t len0);
|
||||
void * rtl_memmove(void *dst_void, const void *src_void, size_t length);
|
||||
void * rtl_memset(void *m, int c, size_t n);
|
||||
char * rtl_strcat(char *s1, const char *s2);
|
||||
char * rtl_strchr(const char *s1, int i);
|
||||
int rtl_strcmp(const char *s1, const char *s2);
|
||||
char * rtl_strcpy(char *dst0, const char *src0);
|
||||
size_t rtl_strlen(const char *str);
|
||||
char * rtl_strncat(char *s1, const char *s2, size_t n);
|
||||
int rtl_strncmp(const char *s1, const char *s2, size_t n);
|
||||
char * rtl_strncpy(char *dst0, const char *src0, size_t count);
|
||||
char * rtl_strstr(const char *searchee, const char *lookfor);
|
||||
char * rtl_strsep(char **source_ptr, const char *delim);
|
||||
char * rtl_strtok(char *s, const char *delim);
|
||||
#endif
|
||||
// Extern Calls:
|
||||
// extern int init_rom_libgloss_ram_map(_DWORD)
|
||||
// extern int _rom_mallocr_init_v1_00(void)
|
||||
// extern int __rtl_vfprintf_r_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_fflush_r_v1_00(_DWORD, _DWORD)
|
||||
// extern int __rtl_memchr_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_memcmp_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_memcpy_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_memmove_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_memset_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_strcat_v1_00(_DWORD, _DWORD)
|
||||
// extern int __rtl_strchr_v1_00(_DWORD, _DWORD)
|
||||
// extern int __rtl_strcmp_v1_00(_DWORD, _DWORD)
|
||||
// extern int __rtl_strcpy_v1_00(_DWORD, _DWORD)
|
||||
// extern int __rtl_strlen_v1_00(_DWORD)
|
||||
// extern int __rtl_strncat_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_strncmp_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_strncpy_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_strstr_v1_00(_DWORD, _DWORD)
|
||||
// extern int __rtl_strsep_v1_00(_DWORD, _DWORD)
|
||||
// extern int __rtl_strtok_v1_00(_DWORD, _DWORD)
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Data declarations
|
||||
|
||||
extern struct _reent * _rtl_impure_ptr;
|
||||
|
||||
char libc_has_init;
|
||||
char print_off;
|
||||
// extern rtl_impure_ptr
|
||||
// extern impure_ptr
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Function
|
||||
|
||||
//----- rtl_libc_init()
|
||||
void rtl_libc_init(void) {
|
||||
__rom_mallocr_init_v1_00();
|
||||
init_rom_libgloss_ram_map();
|
||||
libc_has_init = 1;
|
||||
}
|
||||
|
||||
//----- rtl_snprintf()
|
||||
int rtl_snprintf(char *str, size_t size, const char *fmt, ...) {
|
||||
va_list args;
|
||||
va_start (args, fmt);
|
||||
int result;
|
||||
int w;
|
||||
FILE f;
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
rtl_libc_init();
|
||||
}
|
||||
#endif
|
||||
if (size >= 0) {
|
||||
f._flags = 520;
|
||||
if (size)
|
||||
w = size - 1;
|
||||
else
|
||||
w = 0;
|
||||
f._w = w; /* write space left for putc() */
|
||||
f._bf._size = w;
|
||||
f._file = -1; /* fileno, if Unix descriptor, else -1 */
|
||||
f._p = str; /* current position in (some) buffer */
|
||||
f._bf._base = str;
|
||||
result = __rtl_vfprintf_r_v1_00(_rtl_impure_ptr, &f, fmt, args);
|
||||
if (result + 1 < 0)
|
||||
_rtl_impure_ptr->_errno = 139;
|
||||
if (size)
|
||||
*f._p = 0;
|
||||
} else {
|
||||
_rtl_impure_ptr->_errno = 139;
|
||||
result = -1;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
//----- rtl_sprintf()
|
||||
int rtl_sprintf(char *str, const char *fmt, ...) {
|
||||
FILE f;
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
rtl_libc_init();
|
||||
}
|
||||
#endif
|
||||
f._flags = 520;
|
||||
f._w = 0x7FFFFFFF;
|
||||
f._bf._size = 0x7FFFFFFF;
|
||||
f._file = -1;
|
||||
f._p = str;
|
||||
f._bf._base = str;
|
||||
va_list args;
|
||||
va_start (args, fmt);
|
||||
int result = __rtl_vfprintf_r_v1_00(_rtl_impure_ptr, &f, fmt, args);
|
||||
*f._p = 0;
|
||||
// va_end (args);
|
||||
return result;
|
||||
}
|
||||
|
||||
//----- rtl_printf()
|
||||
int rtl_printf(const char *fmt, ...) {
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
rtl_libc_init();
|
||||
}
|
||||
#endif
|
||||
if(!print_off) {
|
||||
va_list args;
|
||||
va_start (args, fmt);
|
||||
int result = __rtl_vfprintf_r_v1_00(_rtl_impure_ptr,
|
||||
_rtl_impure_ptr->_stdout, fmt, args);
|
||||
__rtl_fflush_r_v1_00(_rtl_impure_ptr, _rtl_impure_ptr->_stdout);
|
||||
// va_end (args);
|
||||
return result;
|
||||
}
|
||||
else return 0;
|
||||
}
|
||||
|
||||
//----- rtl_vprintf()
|
||||
int rtl_vprintf(const char *fmt, va_list param) {
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
rtl_libc_init();
|
||||
}
|
||||
#endif
|
||||
int result = __rtl_vfprintf_r_v1_00(_rtl_impure_ptr,
|
||||
_rtl_impure_ptr->_stdout, fmt, param);
|
||||
__rtl_fflush_r_v1_00(_rtl_impure_ptr, _rtl_impure_ptr->_stdout);
|
||||
return result;
|
||||
}
|
||||
|
||||
//----- rtl_vsnprintf()
|
||||
int rtl_vsnprintf(char *str, size_t size, const char *fmt, va_list param) {
|
||||
int result;
|
||||
int w;
|
||||
int v11;
|
||||
FILE f;
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
rtl_libc_init();
|
||||
}
|
||||
#endif
|
||||
if (size >= 0) {
|
||||
if (size)
|
||||
w = size - 1;
|
||||
else
|
||||
w = 0;
|
||||
f._flags = 520;
|
||||
f._p = str;
|
||||
f._bf._base = str;
|
||||
f._w = w;
|
||||
f._bf._size = w;
|
||||
f._file = -1;
|
||||
result = __rtl_vfprintf_r_v1_00(_rtl_impure_ptr, &f, fmt, param);
|
||||
if (result + 1 < 0)
|
||||
_rtl_impure_ptr->_errno = 139;
|
||||
if (size)
|
||||
*f._p = 0;
|
||||
} else {
|
||||
_rtl_impure_ptr->_errno = 139;
|
||||
result = -1;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
//----- rtl_vfprintf()
|
||||
int rtl_vfprintf(FILE *fp, const char *fmt0, va_list ap) {
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
rtl_libc_init();
|
||||
}
|
||||
#endif
|
||||
return __rtl_vfprintf_r_v1_00(_rtl_impure_ptr, fp, fmt0, ap);
|
||||
}
|
||||
|
||||
//----- rtl_memchr()
|
||||
void * rtl_memchr(const void * src_void , int c , size_t length) {
|
||||
return __rtl_memchr_v1_00(src_void, c, length);
|
||||
}
|
||||
|
||||
//----- rtl_memcmp()
|
||||
int rtl_memcmp(const void *m1, const void *m2, size_t n) {
|
||||
return __rtl_memcmp_v1_00(m1, m2, n);
|
||||
}
|
||||
|
||||
//----- rtl_memcpy()
|
||||
void * rtl_memcpy(void *dst0, const void *src0, size_t len0) {
|
||||
return __rtl_memcpy_v1_00(dst0, src0, len0);
|
||||
}
|
||||
|
||||
//----- rtl_memmove()
|
||||
void * rtl_memmove(void *dst_void, const void *src_void, size_t length) {
|
||||
return __rtl_memmove_v1_00(dst_void, src_void, length);
|
||||
}
|
||||
|
||||
//----- rtl_memset()
|
||||
void * rtl_memset(void *m, int c, size_t n) {
|
||||
return __rtl_memset_v1_00(m, c, n);
|
||||
}
|
||||
|
||||
//----- rtl_strcat()
|
||||
char * rtl_strcat(char *s1, const char *s2) {
|
||||
return (char *) __rtl_strcat_v1_00(s1, s2);
|
||||
}
|
||||
|
||||
//----- rtl_strchr()
|
||||
char * rtl_strchr(const char *s1, int i) {
|
||||
return (char *) __rtl_strchr_v1_00(s1, i);
|
||||
}
|
||||
|
||||
//----- rtl_strcmp()
|
||||
int rtl_strcmp(const char *s1, const char *s2) {
|
||||
return __rtl_strcmp_v1_00(s1, s2);
|
||||
}
|
||||
|
||||
//----- rtl_strcpy()
|
||||
char * rtl_strcpy(char *dst0, const char *src0) {
|
||||
return (char *) __rtl_strcpy_v1_00(dst0, src0);
|
||||
}
|
||||
|
||||
//----- rtl_strlen()
|
||||
size_t rtl_strlen(const char *str) {
|
||||
return __rtl_strlen_v1_00(str);
|
||||
}
|
||||
|
||||
//----- rtl_strncat()
|
||||
char * rtl_strncat(char *s1, const char *s2, size_t n) {
|
||||
return (char *) __rtl_strncat_v1_00(s1, s2, n);
|
||||
}
|
||||
|
||||
//----- rtl_strncmp()
|
||||
int rtl_strncmp(const char *s1, const char *s2, size_t n) {
|
||||
return __rtl_strncmp_v1_00(s1, s2, n);
|
||||
}
|
||||
|
||||
//----- rtl_strncpy()
|
||||
char * rtl_strncpy(char *dst0, const char *src0, size_t count) {
|
||||
return (char *) __rtl_strncpy_v1_00(dst0, src0, count);
|
||||
}
|
||||
|
||||
//----- rtl_strstr()
|
||||
char * rtl_strstr(const char *searchee, const char *lookfor) {
|
||||
return (char *) __rtl_strstr_v1_00(searchee, lookfor);
|
||||
}
|
||||
|
||||
//----- rtl_strsep()
|
||||
char * rtl_strsep(char **source_ptr, const char *delim) {
|
||||
return (char *) __rtl_strsep_v1_00(source_ptr, delim);
|
||||
}
|
||||
|
||||
//----- rtl_strtok()
|
||||
char * rtl_strtok(char *s, const char *delim) {
|
||||
return (char *) __rtl_strtok_v1_00(s, delim);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
/*
|
||||
* ram_libgloss_retarget.o
|
||||
* pvvx 2016
|
||||
*/
|
||||
|
||||
#include "rtl_bios_data.h"
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Function declarations
|
||||
|
||||
int ram_libgloss_close(int fildes);
|
||||
int ram_libgloss_fstat(int fildes, struct stat *st);
|
||||
int ram_libgloss_isatty(int file);
|
||||
int ram_libgloss_lseek(int file, int ptr, int dir);
|
||||
int ram_libgloss_read(int file, char *ptr, int len);
|
||||
char *ram_libgloss_sbrk(int incr);
|
||||
int ram_libgloss_write(int file, const char *ptr, int len);
|
||||
int ram_libgloss_open(char *file, int flags, int mode);
|
||||
void init_rom_libgloss_ram_map(void);
|
||||
// Extern Calls:
|
||||
//extern int HalSerialPutcRtl8195a();
|
||||
//extern int rtl_strcmp();
|
||||
extern char end;
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Data declarations
|
||||
static char *rheap_end;
|
||||
// extern __rtl_errno;
|
||||
// extern end;
|
||||
// extern rom_libgloss_ram_map;
|
||||
|
||||
//----- ram_libgloss_close()
|
||||
int ram_libgloss_close(int fildes) {
|
||||
__rtl_errno = 88;
|
||||
return -1;
|
||||
}
|
||||
|
||||
//----- ram_libgloss_fstat()
|
||||
int ram_libgloss_fstat(int fildes, struct stat *st) {
|
||||
int result;
|
||||
|
||||
if ((unsigned int) fildes > 2) {
|
||||
__rtl_errno = 9;
|
||||
result = -1;
|
||||
} else {
|
||||
st->st_mode = 0x2000;
|
||||
result = 0;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
//----- ram_libgloss_isatty()
|
||||
int ram_libgloss_isatty(int file) {
|
||||
int result;
|
||||
|
||||
if (file <= 2)
|
||||
result = 1;
|
||||
else
|
||||
result = -1;
|
||||
return result;
|
||||
}
|
||||
|
||||
//----- ram_libgloss_lseek()
|
||||
int ram_libgloss_lseek(int file, int ptr, int dir) {
|
||||
__rtl_errno = 88;
|
||||
return -1;
|
||||
}
|
||||
|
||||
//----- ram_libgloss_read()
|
||||
int ram_libgloss_read(int file, char *ptr, int len) {
|
||||
__rtl_errno = 88;
|
||||
return -1;
|
||||
}
|
||||
|
||||
//----- ram_libgloss_sbrk()
|
||||
char *ram_libgloss_sbrk(int incr) {
|
||||
char *prev_heap_end;
|
||||
|
||||
if (!rheap_end)
|
||||
rheap_end = (char *) &end;
|
||||
prev_heap_end = rheap_end;
|
||||
rheap_end += incr;
|
||||
#if CONFIG_DEBUG_LOG > 4
|
||||
DBG_8195A("ROM_heap = %p[%d], end = %p\n", prev_heap_end, incr, rheap_end);
|
||||
#endif
|
||||
return prev_heap_end;
|
||||
}
|
||||
|
||||
//----- ram_libgloss_write()
|
||||
int ram_libgloss_write(int file, const char *ptr, int len) {
|
||||
int i;
|
||||
for (i = 0; i < len; ++i)
|
||||
HalSerialPutcRtl8195a(ptr[i]);
|
||||
return len;
|
||||
}
|
||||
|
||||
//----- ram_libgloss_open()
|
||||
int ram_libgloss_open(char *file, int flags, int mode) {
|
||||
// file->_p
|
||||
int result = rtl_strcmp(file, "/stdin");
|
||||
|
||||
if (result) {
|
||||
if (rtl_strcmp(file, "/stdout")) {
|
||||
if (rtl_strcmp(file, "/stderr"))
|
||||
result = -1;
|
||||
else
|
||||
result = 2;
|
||||
} else {
|
||||
result = 1;
|
||||
}
|
||||
} else
|
||||
result = 0;
|
||||
return result;
|
||||
}
|
||||
|
||||
//----- init_rom_libgloss_ram_map()
|
||||
void init_rom_libgloss_ram_map(void) {
|
||||
rom_libgloss_ram_map.libgloss_close = ram_libgloss_close;
|
||||
rom_libgloss_ram_map.libgloss_fstat = ram_libgloss_fstat;
|
||||
rom_libgloss_ram_map.libgloss_isatty = ram_libgloss_isatty;
|
||||
rom_libgloss_ram_map.libgloss_lseek = ram_libgloss_lseek;
|
||||
rom_libgloss_ram_map.libgloss_open = ram_libgloss_open;
|
||||
rom_libgloss_ram_map.libgloss_read = ram_libgloss_read;
|
||||
rom_libgloss_ram_map.libgloss_write = ram_libgloss_write;
|
||||
rom_libgloss_ram_map.libgloss_sbrk = ram_libgloss_sbrk;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,536 @@
|
|||
/*
|
||||
* RTL871x1Ax: RAM libc
|
||||
* Created on: 22/02/2017
|
||||
* Author: pvvx
|
||||
*/
|
||||
|
||||
#include "rtl_bios_data.h"
|
||||
#include "va_list.h"
|
||||
|
||||
#define CHECK_LIBC_INIT 0
|
||||
//-------------------------------------------------------------------------
|
||||
// Function declarations
|
||||
|
||||
//void libc_init();
|
||||
#if 0
|
||||
int snprintf(char *str, size_t size, const char *fmt, ...);
|
||||
int sprintf(char *str, const char *fmt, ...);
|
||||
int printf(const char *fmt, ...);
|
||||
int vprintf(const char * fmt, __VALIST param);
|
||||
int vsnprintf(char *str, size_t size, const char *fmt, __VALIST param);
|
||||
int vfprintf(FILE *fp, const char *fmt0, va_list ap);
|
||||
void * memchr(const void * src_void , int c , size_t length);
|
||||
int memcmp(const void *m1, const void *m2, size_t n);
|
||||
void * memcpy(void *dst0, const void *src0, size_t len0);
|
||||
void * memmove(void *dst_void, const void *src_void, size_t length);
|
||||
void * memset(void *m, int c, size_t n);
|
||||
char * strcat(char *s1, const char *s2);
|
||||
char * strchr(const char *s1, int i);
|
||||
int strcmp(const char *s1, const char *s2);
|
||||
char * strcpy(char *dst0, const char *src0);
|
||||
size_t strlen(const char *str);
|
||||
char * strncat(char *s1, const char *s2, size_t n);
|
||||
int strncmp(const char *s1, const char *s2, size_t n);
|
||||
char * strncpy(char *dst0, const char *src0, size_t count);
|
||||
char * strstr(const char *searchee, const char *lookfor);
|
||||
char * strsep(char **source_ptr, const char *delim);
|
||||
char * strtok(char *s, const char *delim);
|
||||
int sscanf(const char *buf, const char *fmt, ...);
|
||||
char toupper(char ch);
|
||||
int _stricmp (const char *s1, const char *s2);
|
||||
unsigned long long __aeabi_llsr(unsigned long long val, unsigned int shift);
|
||||
#endif
|
||||
// Extern Calls:
|
||||
// extern int init_rom_libgloss_ram_map(_DWORD)
|
||||
// extern int _rom_mallocr_init_v1_00(void)
|
||||
// extern int __rtl_vfprintf_r_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_fflush_r_v1_00(_DWORD, _DWORD)
|
||||
// extern int __rtl_memchr_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_memcmp_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_memcpy_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_memmove_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_memset_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_strcat_v1_00(_DWORD, _DWORD)
|
||||
// extern int __rtl_strchr_v1_00(_DWORD, _DWORD)
|
||||
// extern int __rtl_strcmp_v1_00(_DWORD, _DWORD)
|
||||
// extern int __rtl_strcpy_v1_00(_DWORD, _DWORD)
|
||||
// extern int __rtl_strlen_v1_00(_DWORD)
|
||||
// extern int __rtl_strncat_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_strncmp_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_strncpy_v1_00(_DWORD, _DWORD, _DWORD)
|
||||
// extern int __rtl_strstr_v1_00(_DWORD, _DWORD)
|
||||
// extern int __rtl_strsep_v1_00(_DWORD, _DWORD)
|
||||
// extern int __rtl_strtok_v1_00(_DWORD, _DWORD)
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Data declarations
|
||||
|
||||
extern struct _reent * _rtl_impure_ptr;
|
||||
|
||||
extern char libc_has_init;
|
||||
extern char print_off;
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Function
|
||||
//----- snprintf()
|
||||
int snprintf(char *str, size_t size, const char *fmt, ...) {
|
||||
va_list args;
|
||||
va_start (args, fmt);
|
||||
int result;
|
||||
int w;
|
||||
FILE f;
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
rtl_libc_init();
|
||||
}
|
||||
#endif
|
||||
if (size >= 0) {
|
||||
f._flags = 520;
|
||||
if (size)
|
||||
w = size - 1;
|
||||
else
|
||||
w = 0;
|
||||
f._w = w; /* write space left for putc() */
|
||||
f._bf._size = w;
|
||||
f._file = -1; /* fileno, if Unix descriptor, else -1 */
|
||||
f._p = str; /* current position in (some) buffer */
|
||||
f._bf._base = str;
|
||||
result = __rtl_vfprintf_r_v1_00(_rtl_impure_ptr, &f, fmt, args);
|
||||
if (result + 1 < 0)
|
||||
_rtl_impure_ptr->_errno = 139;
|
||||
if (size)
|
||||
*f._p = 0;
|
||||
} else {
|
||||
_rtl_impure_ptr->_errno = 139;
|
||||
result = -1;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
#ifndef ENAC_FLOAT
|
||||
//----- sprintf()
|
||||
int sprintf(char *str, const char *fmt, ...) {
|
||||
FILE f;
|
||||
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
rtl_libc_init();
|
||||
}
|
||||
#endif
|
||||
f._flags = 520;
|
||||
f._w = 0x7FFFFFFF;
|
||||
f._bf._size = 0x7FFFFFFF;
|
||||
f._file = -1;
|
||||
f._p = str;
|
||||
f._bf._base = str;
|
||||
va_list args;
|
||||
va_start (args, fmt);
|
||||
int result = __rtl_vfprintf_r_v1_00(_rtl_impure_ptr, &f, fmt, args);
|
||||
*f._p = 0;
|
||||
// va_end (args);
|
||||
return result;
|
||||
}
|
||||
|
||||
//----- printf()
|
||||
int printf(const char *fmt, ...) {
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
rtl_libc_init();
|
||||
}
|
||||
#endif
|
||||
if(!print_off) {
|
||||
|
||||
va_list args;
|
||||
va_start (args, fmt);
|
||||
int result = __rtl_vfprintf_r_v1_00(_rtl_impure_ptr,
|
||||
_rtl_impure_ptr->_stdout, fmt, args);
|
||||
__rtl_fflush_r_v1_00(_rtl_impure_ptr, _rtl_impure_ptr->_stdout);
|
||||
// va_end (args);
|
||||
return result;
|
||||
}
|
||||
else return 0;
|
||||
}
|
||||
|
||||
//----- vprintf()
|
||||
int vprintf(const char * fmt, __VALIST param) {
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
rtl_libc_init();
|
||||
}
|
||||
#endif
|
||||
int result = __rtl_vfprintf_r_v1_00(_rtl_impure_ptr,
|
||||
_rtl_impure_ptr->_stdout, fmt, param);
|
||||
__rtl_fflush_r_v1_00(_rtl_impure_ptr, _rtl_impure_ptr->_stdout);
|
||||
return result;
|
||||
}
|
||||
#endif // ENAC_FLOAT
|
||||
|
||||
//----- vsnprintf()
|
||||
int vsnprintf(char *str, size_t size, const char *fmt, __VALIST param) {
|
||||
int result;
|
||||
int w;
|
||||
int v11;
|
||||
FILE f;
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
rtl_libc_init();
|
||||
}
|
||||
#endif
|
||||
if (size >= 0) {
|
||||
if (size)
|
||||
w = size - 1;
|
||||
else
|
||||
w = 0;
|
||||
f._flags = 520;
|
||||
f._p = str;
|
||||
f._bf._base = str;
|
||||
f._w = w;
|
||||
f._bf._size = w;
|
||||
f._file = -1;
|
||||
result = __rtl_vfprintf_r_v1_00(_rtl_impure_ptr, &f, fmt, param);
|
||||
if (result + 1 < 0)
|
||||
_rtl_impure_ptr->_errno = 139;
|
||||
if (size)
|
||||
*f._p = 0;
|
||||
} else {
|
||||
_rtl_impure_ptr->_errno = 139;
|
||||
result = -1;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
//----- vfprintf()
|
||||
int vfprintf(FILE *fp, const char *fmt0, va_list ap) {
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
rtl_libc_init();
|
||||
}
|
||||
#endif
|
||||
return __rtl_vfprintf_r_v1_00(_rtl_impure_ptr, fp, fmt0, ap);
|
||||
}
|
||||
|
||||
//----- memchr()
|
||||
void * memchr(const void * src_void , int c , size_t length) {
|
||||
return __rtl_memchr_v1_00(src_void, c, length);
|
||||
}
|
||||
|
||||
//----- memcmp()
|
||||
int memcmp(const void *m1, const void *m2, size_t n) {
|
||||
return __rtl_memcmp_v1_00(m1, m2, n);
|
||||
}
|
||||
|
||||
//----- memcpy()
|
||||
void * memcpy(void *dst0, const void *src0, size_t len0) {
|
||||
return __rtl_memcpy_v1_00(dst0, src0, len0);
|
||||
}
|
||||
|
||||
//----- memmove()
|
||||
void * memmove(void *dst_void, const void *src_void, size_t length) {
|
||||
return __rtl_memmove_v1_00(dst_void, src_void, length);
|
||||
}
|
||||
|
||||
//----- memset()
|
||||
void * memset(void *m, int c, size_t n) {
|
||||
return __rtl_memset_v1_00(m, c, n);
|
||||
}
|
||||
|
||||
//----- strcat()
|
||||
char * strcat(char *s1, const char *s2) {
|
||||
return (char *) __rtl_strcat_v1_00(s1, s2);
|
||||
}
|
||||
|
||||
//----- strchr()
|
||||
char * strchr(const char *s1, int i) {
|
||||
return (char *) __rtl_strchr_v1_00(s1, i);
|
||||
}
|
||||
|
||||
//----- strcmp()
|
||||
int strcmp(const char *s1, const char *s2) {
|
||||
return __rtl_strcmp_v1_00(s1, s2);
|
||||
}
|
||||
|
||||
//----- strcpy()
|
||||
char * strcpy(char *dst0, const char *src0) {
|
||||
return (char *) __rtl_strcpy_v1_00(dst0, src0);
|
||||
}
|
||||
|
||||
//----- strlen()
|
||||
size_t strlen(const char *str) {
|
||||
return __rtl_strlen_v1_00(str);
|
||||
}
|
||||
|
||||
//----- strncat()
|
||||
char * strncat(char *s1, const char *s2, size_t n) {
|
||||
return (char *) __rtl_strncat_v1_00(s1, s2, n);
|
||||
}
|
||||
|
||||
//----- strncmp()
|
||||
int strncmp(const char *s1, const char *s2, size_t n) {
|
||||
return __rtl_strncmp_v1_00(s1, s2, n);
|
||||
}
|
||||
|
||||
//----- strncpy()
|
||||
char * strncpy(char *dst0, const char *src0, size_t count) {
|
||||
return (char *) __rtl_strncpy_v1_00(dst0, src0, count);
|
||||
}
|
||||
|
||||
//----- strstr()
|
||||
char * strstr(const char *searchee, const char *lookfor) {
|
||||
return (char *) __rtl_strstr_v1_00(searchee, lookfor);
|
||||
}
|
||||
|
||||
//----- strsep()
|
||||
char * strsep(char **source_ptr, const char *delim) {
|
||||
return (char *) __rtl_strsep_v1_00(source_ptr, delim);
|
||||
}
|
||||
|
||||
//----- strtok()
|
||||
char * strtok(char *s, const char *delim) {
|
||||
return (char *) __rtl_strtok_v1_00(s, delim);
|
||||
}
|
||||
|
||||
int sscanf(const char *buf, const char *fmt, ...) {
|
||||
va_list args;
|
||||
int i;
|
||||
|
||||
va_start(args, fmt);
|
||||
i = _vsscanf(buf, fmt, args);
|
||||
va_end(args);
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
char toupper(char ch) {
|
||||
return ((ch >= 'a' && ch <= 'z') ? ch - 'a' + 'A' : ch);
|
||||
};
|
||||
|
||||
int _stricmp (const char *s1, const char *s2)
|
||||
{
|
||||
while (*s2 != 0 && toupper(*s1) == toupper(*s2))
|
||||
s1++, s2++;
|
||||
return (int) (toupper(*s1) - toupper(*s2));
|
||||
}
|
||||
|
||||
unsigned long long __aeabi_llsr(unsigned long long val, unsigned int shift)
|
||||
{
|
||||
u32 lo = ((u32)val >> shift) | ((u32)(val >> 32) << (32 - shift));
|
||||
u32 hi = (u32)val >> shift;
|
||||
|
||||
return ((unsigned long long)hi << 32) | lo;
|
||||
}
|
||||
|
||||
/*
|
||||
#undef __VFP_FP__
|
||||
|
||||
#if defined(__VFP_FP__)
|
||||
typedef long __jmp_buf[10 + 8 + 1]; // d8-d15 fpu + fpscr
|
||||
#else
|
||||
typedef long __jmp_buf[10];
|
||||
#endif
|
||||
|
||||
int setjmp(__jmp_buf buf) __attribute__ ((noinline));
|
||||
int setjmp(__jmp_buf buf)
|
||||
{
|
||||
register void * r0 __asm__("r0") = buf;
|
||||
__asm__(
|
||||
"mov %%ip, %%sp\n"
|
||||
"stmia %[store]!, {%%r4-%%r9, %%sl, %%fp, %%ip, %%lr}\n"
|
||||
#if defined(__VFP_FP__)
|
||||
"vstmia %[store]!, {%%d8-%%d15}\n"
|
||||
"vmrs %%r1, fpscr\n"
|
||||
"str %%r1, [%[store]], #4\n"
|
||||
#endif
|
||||
"mov.w %r0, #0\n"
|
||||
: : [store] "r" (r0) :);
|
||||
}
|
||||
|
||||
void longjmp(__jmp_buf buf, long value) __attribute__((noreturn));
|
||||
void longjmp(__jmp_buf buf, long value)
|
||||
{
|
||||
__asm__(
|
||||
"ldmia %[load]!, {%%r4-%%r9, %%sl, %%fp, %%ip, %%lr}\n"
|
||||
#if defined(__VFP_FP__)
|
||||
"vldmia %[load]!, {%%d8-%%d15}\n"
|
||||
"ldr %%r0, [%[load]], #4\n"
|
||||
"vmsr fpscr, %%r0\n"
|
||||
#endif
|
||||
"mov %%sp, %%ip\n"
|
||||
"movs %%r0, %%r1\n"
|
||||
"it eq\n"
|
||||
"moveq %%r0, #1\n"
|
||||
"bx lr\n"
|
||||
: : [load] "r" (buf), [value] "r" (value):);
|
||||
__builtin_unreachable();
|
||||
}
|
||||
*/
|
||||
|
||||
extern __attribute__ ((long_call)) unsigned int Rand(void);
|
||||
|
||||
unsigned int rand(void)
|
||||
{
|
||||
return Rand();
|
||||
}
|
||||
|
||||
|
||||
|
||||
//----- rtl_dtoi()
|
||||
int __aeabi_dtoi(double d)
|
||||
{
|
||||
return __rtl_dtoi_v1_00(d);
|
||||
}
|
||||
|
||||
//----- __aeabi_dtoui()
|
||||
int __aeabi_dtoui(double d)
|
||||
{
|
||||
return __rtl_dtoui_v1_00(d);
|
||||
}
|
||||
|
||||
//----- __aeabi_i2f()
|
||||
float __aeabi_i2f(int val)
|
||||
{
|
||||
return __rtl_itof_v1_00(val);
|
||||
}
|
||||
|
||||
//----- __aeabi_i2d()
|
||||
int __aeabi_i2d(int val)
|
||||
{
|
||||
return __rtl_itod_v1_00(val);
|
||||
}
|
||||
|
||||
//----- __aeabi_ui2f()
|
||||
float __aeabi_ui2f(unsigned int val)
|
||||
{
|
||||
return __rtl_uitof_v1_00(val);
|
||||
}
|
||||
|
||||
//----- __aeabi_ui2d()
|
||||
int __aeabi_ui2d(unsigned int val)
|
||||
{
|
||||
return __rtl_uitod_v1_00(val);
|
||||
}
|
||||
|
||||
//----- __aeabi_itoa()
|
||||
char * __aeabi_itoa(int value, char *string, int radix)
|
||||
{
|
||||
return (char *)__rtl_ltoa_v1_00(value, string, radix);
|
||||
}
|
||||
|
||||
//----- __aeabi_ltoa()
|
||||
char * __aeabi_ltoa(int value, char *string, int radix)
|
||||
{
|
||||
return (char *)__rtl_ltoa_v1_00(value, string, radix);
|
||||
}
|
||||
|
||||
//----- __aeabi_utoa()
|
||||
char * __aeabi_utoa(unsigned int value, char *string, int radix)
|
||||
{
|
||||
return (char *)__rtl_ultoa_v1_00(value, string, radix);
|
||||
}
|
||||
|
||||
//----- __aeabi_ultoa()
|
||||
char * __aeabi_ultoa(unsigned int value, char *string, int radix)
|
||||
{
|
||||
return (char *)__rtl_ultoa_v1_00(value, string, radix);
|
||||
}
|
||||
|
||||
//----- __aeabi_ftol()
|
||||
int __aeabi_ftol(float f)
|
||||
{
|
||||
return __rtl_ftol_v1_00(f);
|
||||
}
|
||||
|
||||
//----- __aeabi_ftod()
|
||||
int __aeabi_ftod(float f)
|
||||
{
|
||||
return __rtl_ftod_v1_00(f);
|
||||
}
|
||||
|
||||
//----- __aeabi_dtof()
|
||||
float __aeabi_dtof(double d)
|
||||
{
|
||||
return __rtl_dtof_v1_00(d);
|
||||
}
|
||||
|
||||
//----- __aeabi_fadd()
|
||||
float __aeabi_fadd(float a, float b)
|
||||
{
|
||||
return __rtl_fadd_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- __aeabi_fsub()
|
||||
float __aeabi_fsub(float a, float b)
|
||||
{
|
||||
return __rtl_fsub_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- __aeabi_fmul()
|
||||
float __aeabi_fmul(float a, float b)
|
||||
{
|
||||
return __rtl_fmul_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- __aeabi_fdiv()
|
||||
float __aeabi_fdiv(float a, float b)
|
||||
{
|
||||
return __rtl_fdiv_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- __aeabi_dadd()
|
||||
int __aeabi_dadd(double a, double b)
|
||||
{
|
||||
return __rtl_dadd_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- __aeabi_dsub()
|
||||
int __aeabi_dsub(double a, double b)
|
||||
{
|
||||
return __rtl_dsub_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- __aeabi_dmul()
|
||||
int __aeabi_dmul(double a, double b)
|
||||
{
|
||||
return __rtl_dmul_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- __aeabi_ddiv()
|
||||
int __aeabi_ddiv(double a, double b)
|
||||
{
|
||||
return __rtl_ddiv_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- __aeabi_dcmpeq()
|
||||
int __aeabi_dcmpeq(double a, double b)
|
||||
{
|
||||
return __rtl_dcmpeq_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- __aeabi_dcmplt()
|
||||
int __aeabi_dcmplt(double a, double b)
|
||||
{
|
||||
return __rtl_dcmplt_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- __aeabi_dcmple()
|
||||
int __aeabi_dcmple(double a, double b)
|
||||
{
|
||||
return __rtl_dcmple_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- __aeabi_dcmpgt()
|
||||
int __aeabi_dcmpgt(double a, double b)
|
||||
{
|
||||
return __rtl_dcmpgt_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- __aeabi_fcmplt()
|
||||
int __aeabi_fcmplt(float a, float b)
|
||||
{
|
||||
return __rtl_fcmplt_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- __aeabi_fcmpgt()
|
||||
int __aeabi_fcmpgt(float a, float b)
|
||||
{
|
||||
return __rtl_fcmpgt_v1_00(a, b);
|
||||
}
|
||||
|
|
@ -0,0 +1,228 @@
|
|||
/*
|
||||
* rtl_eabi_cast_ram.o
|
||||
* pvvx 2016
|
||||
*/
|
||||
|
||||
#include "basic_types.h"
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Function declarations
|
||||
|
||||
int rtl_dtoi(double d);
|
||||
int rtl_dtoui(double d);
|
||||
float rtl_i2f(int val);
|
||||
int rtl_i2d(int val);
|
||||
float rtl_ui2f(unsigned int val);
|
||||
int rtl_ui2d(unsigned int val);
|
||||
char *rtl_itoa(int value, char *string, int radix);
|
||||
char *rtl_ltoa(int value, char *string, int radix);
|
||||
char *rtl_utoa(unsigned int value, char *string, int radix);
|
||||
char *rtl_ultoa(unsigned int value, char *string, int radix);
|
||||
int rtl_ftol(float f);
|
||||
int rtl_ftod(float f);
|
||||
float rtl_dtof(double d);
|
||||
float rtl_fadd(float a, float b);
|
||||
float rtl_fsub(float a, float b);
|
||||
float rtl_fmul(float a, float b);
|
||||
float rtl_fdiv(float a, float b);
|
||||
int rtl_dadd(double a, double b);
|
||||
int rtl_dsub(double a, double b);
|
||||
int rtl_dmul(double a, double b);
|
||||
int rtl_ddiv(double a, double b);
|
||||
int rtl_dcmpeq(double a, double b);
|
||||
int rtl_dcmplt(double a, double b);
|
||||
int rtl_dcmple(double a, double b);
|
||||
int rtl_dcmpgt(double a, double b);
|
||||
int rtl_fcmplt(float a, float b);
|
||||
int rtl_fcmpgt(float a, float b);
|
||||
|
||||
// Extern Calls:
|
||||
|
||||
// int __rtl_dtoi_v1_00();
|
||||
// int __rtl_dtoui_v1_00();
|
||||
// int __rtl_itof_v1_00();
|
||||
// int __rtl_itod_v1_00();
|
||||
// int __rtl_uitof_v1_00();
|
||||
// int __rtl_uitod_v1_00();
|
||||
// int __rtl_ltoa_v1_00();
|
||||
// int __rtl_ultoa_v1_00();
|
||||
// int __rtl_ftol_v1_00();
|
||||
// int __rtl_ftod_v1_00();
|
||||
// int __rtl_dtof_v1_00();
|
||||
// int __rtl_fadd_v1_00();
|
||||
// int __rtl_fsub_v1_00();
|
||||
// int __rtl_fmul_v1_00();
|
||||
// int __rtl_fdiv_v1_00();
|
||||
// int __rtl_dadd_v1_00();
|
||||
// int __rtl_dsub_v1_00();
|
||||
// int __rtl_dmul_v1_00();
|
||||
// int __rtl_ddiv_v1_00();
|
||||
// int __rtl_dcmpeq_v1_00();
|
||||
// int __rtl_dcmplt_v1_00();
|
||||
// int __rtl_dcmple_v1_00();
|
||||
// int __rtl_dcmpgt_v1_00();
|
||||
// int __rtl_fcmplt_v1_00();
|
||||
// int __rtl_fcmpgt_v1_00();
|
||||
|
||||
|
||||
//----- rtl_dtoi()
|
||||
int rtl_dtoi(double d)
|
||||
{
|
||||
return __rtl_dtoi_v1_00(d);
|
||||
}
|
||||
|
||||
//----- rtl_dtoui()
|
||||
int rtl_dtoui(double d)
|
||||
{
|
||||
return __rtl_dtoui_v1_00(d);
|
||||
}
|
||||
|
||||
//----- rtl_i2f()
|
||||
float rtl_i2f(int val)
|
||||
{
|
||||
return __rtl_itof_v1_00(val);
|
||||
}
|
||||
|
||||
//----- rtl_i2d()
|
||||
int rtl_i2d(int val)
|
||||
{
|
||||
return __rtl_itod_v1_00(val);
|
||||
}
|
||||
|
||||
//----- rtl_ui2f()
|
||||
float rtl_ui2f(unsigned int val)
|
||||
{
|
||||
return __rtl_uitof_v1_00(val);
|
||||
}
|
||||
|
||||
//----- rtl_ui2d()
|
||||
int rtl_ui2d(unsigned int val)
|
||||
{
|
||||
return __rtl_uitod_v1_00(val);
|
||||
}
|
||||
|
||||
//----- rtl_itoa()
|
||||
char *rtl_itoa(int value, char *string, int radix)
|
||||
{
|
||||
return (char *)__rtl_ltoa_v1_00(value, string, radix);
|
||||
}
|
||||
|
||||
//----- rtl_ltoa()
|
||||
char *rtl_ltoa(int value, char *string, int radix)
|
||||
{
|
||||
return (char *)__rtl_ltoa_v1_00(value, string, radix);
|
||||
}
|
||||
|
||||
//----- rtl_utoa()
|
||||
char *rtl_utoa(unsigned int value, char *string, int radix)
|
||||
{
|
||||
return (char *)__rtl_ultoa_v1_00(value, string, radix);
|
||||
}
|
||||
|
||||
//----- rtl_ultoa()
|
||||
char *rtl_ultoa(unsigned int value, char *string, int radix)
|
||||
{
|
||||
return (char *)__rtl_ultoa_v1_00(value, string, radix);
|
||||
}
|
||||
|
||||
//----- rtl_ftol()
|
||||
int rtl_ftol(float f)
|
||||
{
|
||||
return __rtl_ftol_v1_00(f);
|
||||
}
|
||||
|
||||
//----- rtl_ftod()
|
||||
int rtl_ftod(float f)
|
||||
{
|
||||
return __rtl_ftod_v1_00(f);
|
||||
}
|
||||
|
||||
//----- rtl_dtof()
|
||||
float rtl_dtof(double d)
|
||||
{
|
||||
return __rtl_dtof_v1_00(d);
|
||||
}
|
||||
|
||||
//----- rtl_fadd()
|
||||
float rtl_fadd(float a, float b)
|
||||
{
|
||||
return __rtl_fadd_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- rtl_fsub()
|
||||
float rtl_fsub(float a, float b)
|
||||
{
|
||||
return __rtl_fsub_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- rtl_fmul()
|
||||
float rtl_fmul(float a, float b)
|
||||
{
|
||||
return __rtl_fmul_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- rtl_fdiv()
|
||||
float rtl_fdiv(float a, float b)
|
||||
{
|
||||
return __rtl_fdiv_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- rtl_dadd()
|
||||
int rtl_dadd(double a, double b)
|
||||
{
|
||||
return __rtl_dadd_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- rtl_dsub()
|
||||
int rtl_dsub(double a, double b)
|
||||
{
|
||||
return __rtl_dsub_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- rtl_dmul()
|
||||
int rtl_dmul(double a, double b)
|
||||
{
|
||||
return __rtl_dmul_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- rtl_ddiv()
|
||||
int rtl_ddiv(double a, double b)
|
||||
{
|
||||
return __rtl_ddiv_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- rtl_dcmpeq()
|
||||
int rtl_dcmpeq(double a, double b)
|
||||
{
|
||||
return __rtl_dcmpeq_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- rtl_dcmplt()
|
||||
int rtl_dcmplt(double a, double b)
|
||||
{
|
||||
return __rtl_dcmplt_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- rtl_dcmple()
|
||||
int rtl_dcmple(double a, double b)
|
||||
{
|
||||
return __rtl_dcmple_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- rtl_dcmpgt()
|
||||
int rtl_dcmpgt(double a, double b)
|
||||
{
|
||||
return __rtl_dcmpgt_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- rtl_fcmplt()
|
||||
int rtl_fcmplt(float a, float b)
|
||||
{
|
||||
return __rtl_fcmplt_v1_00(a, b);
|
||||
}
|
||||
|
||||
//----- rtl_fcmpgt()
|
||||
int rtl_fcmpgt(float a, float b)
|
||||
{
|
||||
return __rtl_fcmpgt_v1_00(a, b);
|
||||
}
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* rtl_math_ram..o
|
||||
* pvvx 2016
|
||||
*/
|
||||
|
||||
#include "basic_types.h"
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Function declarations
|
||||
|
||||
float rtl_fabsf(float a);
|
||||
int rtl_fabs(double a);
|
||||
float rtl_cos_f32(float a);
|
||||
float rtl_sin_f32(float a);
|
||||
|
||||
// Extern Calls:
|
||||
|
||||
// int __rtl_fabsf_v1_00();
|
||||
// int __rtl_fabs_v1_00();
|
||||
// int __rtl_cos_f32_v1_00();
|
||||
// int __rtl_sin_f32_v1_00();
|
||||
|
||||
|
||||
//----- rtl_fabsf()
|
||||
float rtl_fabsf(float a)
|
||||
{
|
||||
return __rtl_fabsf_v1_00(a);
|
||||
}
|
||||
|
||||
//----- rtl_fabs()
|
||||
int rtl_fabs(double a)
|
||||
{
|
||||
return __rtl_fabs_v1_00(a);
|
||||
}
|
||||
|
||||
//----- rtl_cos_f32()
|
||||
float rtl_cos_f32(float a)
|
||||
{
|
||||
return __rtl_cos_f32_v1_00(a);
|
||||
}
|
||||
|
||||
//----- rtl_sin_f32()
|
||||
float rtl_sin_f32(float a)
|
||||
{
|
||||
return __rtl_sin_f32_v1_00(a);
|
||||
}
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* rom_libc_string.h
|
||||
*
|
||||
* Definitions for standard library - libc functions.
|
||||
*/
|
||||
#ifndef _ROM_LIBC_STRING_H_
|
||||
#define _ROM_LIBC_STRING_H_
|
||||
|
||||
#include <basic_types.h>
|
||||
|
||||
#define __rtl_memchr __rtl_memchr_v1_00
|
||||
#define __rtl_memcmp __rtl_memcmp_v1_00
|
||||
#define __rtl_memcpy __rtl_memcpy_v1_00
|
||||
#define __rtl_memmove __rtl_memmove_v1_00
|
||||
#define __rtl_memset __rtl_memset_v1_00
|
||||
#define __rtl_strcat __rtl_strcat_v1_00
|
||||
#define __rtl_strchr __rtl_strchr_v1_00
|
||||
#define __rtl_strcmp __rtl_strcmp_v1_00
|
||||
#define __rtl_strcpy __rtl_strcpy_v1_00
|
||||
#define __rtl_strlen __rtl_strlen_v1_00
|
||||
#define __rtl_strncat __rtl_strncat_v1_00
|
||||
#define __rtl_strncmp __rtl_strncmp_v1_00
|
||||
#define __rtl_strncpy __rtl_strncpy_v1_00
|
||||
#define __rtl_strstr __rtl_strstr_v1_00
|
||||
#define __rtl_strsep __rtl_strsep_v1_00
|
||||
#define __rtl_strtok __rtl_strtok_v1_00
|
||||
|
||||
#define __rtl_critical_factorization __rtl_critical_factorization_v1_00
|
||||
#define __rtl_two_way_short_needle __rtl_two_way_short_needle_v1_00
|
||||
#define __rtl_two_way_long_needle __rtl_two_way_long_needle_v1_00
|
||||
|
||||
extern _LONG_CALL_ void * __rtl_memchr_v1_00(const void * src_void , int c , size_t length);
|
||||
extern _LONG_CALL_ int __rtl_memcmp_v1_00(const void * m1 , const void * m2 , size_t n);
|
||||
extern _LONG_CALL_ void * __rtl_memcpy_v1_00(void * __restrict dst0 , const void * __restrict src0 , size_t len0);
|
||||
extern _LONG_CALL_ void * __rtl_memmove_v1_00( void * dst_void , const void * src_void , size_t length);
|
||||
extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
|
||||
extern _LONG_CALL_ char * __rtl_strcat_v1_00(char *__restrict s1 , const char *__restrict s2);
|
||||
extern _LONG_CALL_ char * __rtl_strchr_v1_00(const char *s1 , int i);
|
||||
extern _LONG_CALL_ int __rtl_strcmp_v1_00(const char *s1 , const char *s2);
|
||||
extern _LONG_CALL_ char* __rtl_strcpy_v1_00(char *dst0 , const char *src0);
|
||||
extern _LONG_CALL_ size_t __rtl_strlen_v1_00(const char *str);
|
||||
extern _LONG_CALL_ char * __rtl_strncat_v1_00(char *__restrict s1 , const char *__restrict s2 , size_t n);
|
||||
extern _LONG_CALL_ int __rtl_strncmp_v1_00(const char *s1 , const char *s2 , size_t n);
|
||||
extern _LONG_CALL_ char * __rtl_strncpy_v1_00(char *__restrict dst0 , const char *__restrict src0 , size_t count);
|
||||
extern _LONG_CALL_ char * __rtl_strstr_v1_00(const char *searchee , const char *lookfor);
|
||||
extern _LONG_CALL_ char * __rtl_strsep_v1_00(register char **source_ptr , register const char *delim);
|
||||
extern _LONG_CALL_ char * __rtl_strtok_v1_00(register char *__restrict s , register const char *__restrict delim);
|
||||
|
||||
#endif /* _ROM_LIBC_STRING_H_ */
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
#ifndef ROM_LIBGLOSS_RETARGET_H
|
||||
#define ROM_LIBGLOSS_RETARGET_H
|
||||
|
||||
#include <sys/stat.h>
|
||||
#include <basic_types.h>
|
||||
|
||||
#define __rtl_close __rtl_close_v1_00
|
||||
#define __rtl_fstat __rtl_fstat_v1_00
|
||||
#define __rtl_isatty __rtl_isatty_v1_00
|
||||
#define __rtl_lseek __rtl_lseek_v1_00
|
||||
#define __rtl_open __rtl_open_v1_00
|
||||
#define __rtl_read __rtl_read_v1_00
|
||||
#define __rtl_write __rtl_write_v1_00
|
||||
#define __rtl_sbrk __rtl_sbrk_v1_00
|
||||
|
||||
extern _LONG_CALL_ int __rtl_close_v1_00(int fildes);
|
||||
extern _LONG_CALL_ int __rtl_fstat_v1_00(int fildes , struct stat *st);
|
||||
extern _LONG_CALL_ int __rtl_isatty_v1_00(int file);
|
||||
extern _LONG_CALL_ int __rtl_lseek_v1_00(int file , int ptr , int dir);
|
||||
extern _LONG_CALL_ int __rtl_open_v1_00(char *file , int flags , int mode);
|
||||
extern _LONG_CALL_ int __rtl_read_v1_00(int file , char *ptr , int len);
|
||||
extern _LONG_CALL_ int __rtl_write_v1_00(int file , const char *ptr , int len);
|
||||
extern _LONG_CALL_ void* __rtl_sbrk_v1_00(int incr);
|
||||
|
||||
|
||||
struct _rom_libgloss_ram_map {
|
||||
int (*libgloss_close)(int fildes);
|
||||
int (*libgloss_fstat)(int fildes , struct stat *st);
|
||||
int (*libgloss_isatty)(int file);
|
||||
int (*libgloss_lseek)(int file , int ptr , int dir);
|
||||
int (*libgloss_open)(char *file , int flags , int mode);
|
||||
int (*libgloss_read)(int file , char *ptr , int len);
|
||||
int (*libgloss_write)(int file , const char *ptr , int len);
|
||||
void* (*libgloss_sbrk)(int incr);
|
||||
};
|
||||
|
||||
#endif /* ROM_LIBGLOSS_RETARGET_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue