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update
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commit
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12 changed files with 38 additions and 22 deletions
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@ -108,6 +108,9 @@
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#include <string.h>
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#include <stdlib.h>
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#include "diag.h"
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#include "platform_autoconf.h"
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#include "hal_misc.h"
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/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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all the API functions to use the MPU wrappers. That should only be done when
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@ -167,7 +170,7 @@ static size_t xBlockAllocatedBit = 0;
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//TODO: remove section when combine BD and BF
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#if (defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B))
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#include "section_config.h"
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SRAM_BF_DATA_SECTION
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SRAM_HEAP_SECTION
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#endif
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unsigned char ucHeap[configTOTAL_HEAP_SIZE];
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@ -520,17 +523,16 @@ uint32_t ulAddress;
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const HeapRegion_t *pxHeapRegion;
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#if defined(CONFIG_PLATFORM_8195A)
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/* xHeapRegions[0].pucStartAddress = (uint8_t*)&__ram_heap1_start__;
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/*
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xHeapRegions[0].pucStartAddress = (uint8_t*)&__ram_heap1_start__;
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xHeapRegions[0].xSizeInBytes = (u32)&__ram_heap1_end__ - (u32)xHeapRegions[0].pucStartAddress;
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xHeapRegions[1].pucStartAddress = &ucHeap; // (uint8_t*)&__ram_heap2_start__;
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xHeapRegions[1].xSizeInBytes = (u32)0x10070000 - (u32)xHeapRegions[1].pucStartAddress;
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xHeapRegions[2].pucStartAddress = (uint8_t*)&__sdram_data_start__; */
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if(*((uint32 *)0x40000210) & BIT(21)) xHeapRegions[2].xSizeInBytes = 0;
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/* #ifdef CONFIG_SDR_EN
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xHeapRegions[2].pucStartAddress = (uint8_t*)&__sdram_data_start__;
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xHeapRegions[2].xSizeInBytes = (u32)0x30200000 - (u32)xHeapRegions[2].pucStartAddress;
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#else
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xHeapRegions[2].xSizeInBytes = 0;
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#endif */
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*/
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int chip_id = HalGetChipId();
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if (chip_id >= CHIP_ID_8711AN && chip_id <= CHIP_ID_8711AF) xHeapRegions[2].xSizeInBytes = 0;
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#endif
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/* Can only call once! */
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configASSERT( pxEnd == NULL );
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@ -539,9 +541,9 @@ const HeapRegion_t *pxHeapRegion;
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while( pxHeapRegion->xSizeInBytes > 0 )
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{
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DBG_8195A("Init Heap Region: %p[%d]\n", pxHeapRegion->pucStartAddress, pxHeapRegion->xSizeInBytes);
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#if CONFIG_DEBUG_LOG > 4
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DBG_8195A("Set Heap Region: %p[%d]\n", pxHeapRegion->pucStartAddress, pxHeapRegion->xSizeInBytes);
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rtl_memset(pxHeapRegion->pucStartAddress, 0, pxHeapRegion->xSizeInBytes);
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// rtl_memset(pxHeapRegion->pucStartAddress, 0, pxHeapRegion->xSizeInBytes);
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#endif
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xTotalRegionSize = pxHeapRegion->xSizeInBytes;
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/* Ensure the heap region starts on a correctly aligned boundary. */
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@ -764,7 +764,7 @@ SECTIONS
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gRamPatchFun2 = 0x10000bd8; /* HalResetVsrV02(), HalResetVsr() */
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__image1_validate_code__ = 0x10000bdc; /* 8 bytes HalResetVsrV02(), HalResetVsr() */
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RAM_IMG1_VALID_PATTEN = 0x10000bdc;
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_RandSeed = 0x10000be4; /* ChangeRandSeed_rom().. Sdr_Rand2_rom() */
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rand_x = 0x10000be4; /* ChangeRandSeed_rom().. Sdr_Rand2_rom() */
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AvaWds = 0x10000be8; /* SdrCalibration_rom() */
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SdrDramInfo = 0x10001be8; /* SdrCalibration_rom() */
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SdrDramTiming = 0x10001bfc; /* SdrCalibration_rom() */
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@ -9,11 +9,11 @@ MEMORY
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{
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ROM_USED_RAM (rwx): ORIGIN = 0x10000bc8, LENGTH = 21560 /* end 0x10006000 */
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ROM_HEAP (rwx) : ORIGIN = 0x10002400, LENGTH = 3K /* end 0x10003000 */
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RAM_HEAP1 (rwx) : ORIGIN = 0x10003000, LENGTH = 12k /* end 0x10006000 */
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RAM_HEAP1 (rwx) : ORIGIN = 0x10003000, LENGTH = 12K /* end 0x10006000 */
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BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 424K /* end 0x10070000 */
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TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64K /* end 0x20000000 */
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TCM_TAB (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64K /* end 0x20000000 */
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SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 0 /*2M end 0x30200000 */
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TCM_TAB (rwx) : ORIGIN = 0x1FFFFD00, LENGTH = 768 /* end 0x20000000 */
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SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M /* end 0x30200000 */
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}
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EXTERN(RAM_IMG2_VALID_PATTEN)
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@ -21,6 +21,7 @@ EXTERN(main)
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EXTERN(InfraStart)
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EXTERN(gImage2EntryFun0)
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SECTIONS
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{
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__rom_bss_start__ = 0x10000300;
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@ -51,7 +52,8 @@ SECTIONS
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{
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__ram_tcm_start__ = .;
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*mem.o (.bss*)
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*memp.o (.bss*)
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*memp.o (.bss*)
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__tcm_heap_start__ = .;
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*(.tcm.heap)
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}
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.dummy
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@ -78,6 +80,11 @@ SECTIONS
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}
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} > TCM
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.soc_ps_monitor :
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{
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__tcm_heap_end__ = .;
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} > TCM_TAB
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.image2.start.table :
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{
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__ram_heap1_end__ = .;
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@ -116,11 +123,11 @@ SECTIONS
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. = ALIGN(4);
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xHeapRegions = .;
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LONG(__ram_heap1_start__)
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LONG(ORIGIN(RAM_HEAP1) + LENGTH(RAM_HEAP1) - __ram_heap1_start__)
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LONG(__ram_heap1_end__ - __ram_heap1_start__)
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LONG(__ram_heap2_start__)
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LONG(ORIGIN(BD_RAM) + LENGTH(BD_RAM) - __ram_heap2_start__)
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LONG(__ram_heap2_end__ - __ram_heap2_start__)
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LONG(__sdram_heap_start__)
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LONG(ORIGIN(SDRAM_RAM) + LENGTH(SDRAM_RAM) - __sdram_heap_start__)
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LONG(__sdram_heap_end__ - __sdram_heap_start__)
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LONG(0)
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LONG(0)
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} > BD_RAM
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@ -148,20 +155,23 @@ SECTIONS
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*(.bss*)
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*(COMMON)
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*(.bdsram.data*)
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*(.bfsram.data*)
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*(.sdram.bss*)
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*(.p2p.bss*)
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*(.wps.bss*)
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*(.websocket.bss*)
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__bss_end__ = .;
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.ram.bss$$Limit = .;
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} > BD_RAM
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.ram_heap2 :
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{
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. = ALIGN(8);
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__ram_heap2_start__ = .;
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KEEP(*(.bfsram.data*)) /* ucHeap */
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KEEP(*(.heap*)) /* ucHeap */
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} > BD_RAM
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__ram_heap2_end__ = 0x10070000;
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.sdr_text :
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{
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@ -184,6 +194,7 @@ SECTIONS
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. = ALIGN(8);
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__sdram_heap_start__ = .;
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} > SDRAM_RAM
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__sdram_heap_end__ = 0x30200000;
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.boot.head :
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{
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@ -210,7 +210,7 @@
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#define SDIO_ROM_BSS_SECTION \
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SECTION(".sdio.rom.bss")
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#define SDIO_ROM_TEXT_SECTION \
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SECTION(".sdio.rom.text")
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SECTION(".sdio.rom.text")
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//3 SRAM Config Section
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#define SRAM_BD_DATA_SECTION \
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#define SRAM_BF_DATA_SECTION \
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SECTION(".bfsram.data")
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#define SRAM_HEAP_SECTION \
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SECTION(".sram.heap")
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#define START_RAM_FUN_SECTION \
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SECTION(".start.ram.data")
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@ -277,7 +280,7 @@
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#define IMAGE2_START_RAM_FUN_SECTION \
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SECTION(".image2.ram.data")
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SECTION(".image2.ram.data")
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#define SDRAM_DATA_SECTION \
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SECTION(".sdram.data")
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@ -108,7 +108,7 @@ void fATW2(void *arg){
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// Test
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void fATST(void *arg){
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AT_PRINTK("[ATS#]: _AT_SYSTEM_TEST_");
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// AT_PRINTK("[ATS#]: _AT_SYSTEM_TEST_");
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DBG_8195A("\nCLK CPU\t\t%d Hz\nRAM heap\t%d bytes\nTCM heap\t%d bytes\n",
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HalGetCpuClk(), xPortGetFreeHeapSize(), tcm_heap_freeSpace());
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dump_mem_block_list();
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