This commit is contained in:
pvvx 2017-02-18 07:46:36 +03:00
parent 4d4f8c1b29
commit e423a86f64
12 changed files with 38 additions and 22 deletions

View file

@ -108,6 +108,9 @@
#include <string.h>
#include <stdlib.h>
#include "diag.h"
#include "platform_autoconf.h"
#include "hal_misc.h"
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
all the API functions to use the MPU wrappers. That should only be done when
@ -167,7 +170,7 @@ static size_t xBlockAllocatedBit = 0;
//TODO: remove section when combine BD and BF
#if (defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B))
#include "section_config.h"
SRAM_BF_DATA_SECTION
SRAM_HEAP_SECTION
#endif
unsigned char ucHeap[configTOTAL_HEAP_SIZE];
@ -520,17 +523,16 @@ uint32_t ulAddress;
const HeapRegion_t *pxHeapRegion;
#if defined(CONFIG_PLATFORM_8195A)
/* xHeapRegions[0].pucStartAddress = (uint8_t*)&__ram_heap1_start__;
/*
xHeapRegions[0].pucStartAddress = (uint8_t*)&__ram_heap1_start__;
xHeapRegions[0].xSizeInBytes = (u32)&__ram_heap1_end__ - (u32)xHeapRegions[0].pucStartAddress;
xHeapRegions[1].pucStartAddress = &ucHeap; // (uint8_t*)&__ram_heap2_start__;
xHeapRegions[1].xSizeInBytes = (u32)0x10070000 - (u32)xHeapRegions[1].pucStartAddress;
xHeapRegions[2].pucStartAddress = (uint8_t*)&__sdram_data_start__; */
if(*((uint32 *)0x40000210) & BIT(21)) xHeapRegions[2].xSizeInBytes = 0;
/* #ifdef CONFIG_SDR_EN
xHeapRegions[2].pucStartAddress = (uint8_t*)&__sdram_data_start__;
xHeapRegions[2].xSizeInBytes = (u32)0x30200000 - (u32)xHeapRegions[2].pucStartAddress;
#else
xHeapRegions[2].xSizeInBytes = 0;
#endif */
*/
int chip_id = HalGetChipId();
if (chip_id >= CHIP_ID_8711AN && chip_id <= CHIP_ID_8711AF) xHeapRegions[2].xSizeInBytes = 0;
#endif
/* Can only call once! */
configASSERT( pxEnd == NULL );
@ -539,9 +541,9 @@ const HeapRegion_t *pxHeapRegion;
while( pxHeapRegion->xSizeInBytes > 0 )
{
DBG_8195A("Init Heap Region: %p[%d]\n", pxHeapRegion->pucStartAddress, pxHeapRegion->xSizeInBytes);
#if CONFIG_DEBUG_LOG > 4
DBG_8195A("Set Heap Region: %p[%d]\n", pxHeapRegion->pucStartAddress, pxHeapRegion->xSizeInBytes);
rtl_memset(pxHeapRegion->pucStartAddress, 0, pxHeapRegion->xSizeInBytes);
// rtl_memset(pxHeapRegion->pucStartAddress, 0, pxHeapRegion->xSizeInBytes);
#endif
xTotalRegionSize = pxHeapRegion->xSizeInBytes;
/* Ensure the heap region starts on a correctly aligned boundary. */

View file

@ -764,7 +764,7 @@ SECTIONS
gRamPatchFun2 = 0x10000bd8; /* HalResetVsrV02(), HalResetVsr() */
__image1_validate_code__ = 0x10000bdc; /* 8 bytes HalResetVsrV02(), HalResetVsr() */
RAM_IMG1_VALID_PATTEN = 0x10000bdc;
_RandSeed = 0x10000be4; /* ChangeRandSeed_rom().. Sdr_Rand2_rom() */
rand_x = 0x10000be4; /* ChangeRandSeed_rom().. Sdr_Rand2_rom() */
AvaWds = 0x10000be8; /* SdrCalibration_rom() */
SdrDramInfo = 0x10001be8; /* SdrCalibration_rom() */
SdrDramTiming = 0x10001bfc; /* SdrCalibration_rom() */

View file

@ -9,11 +9,11 @@ MEMORY
{
ROM_USED_RAM (rwx): ORIGIN = 0x10000bc8, LENGTH = 21560 /* end 0x10006000 */
ROM_HEAP (rwx) : ORIGIN = 0x10002400, LENGTH = 3K /* end 0x10003000 */
RAM_HEAP1 (rwx) : ORIGIN = 0x10003000, LENGTH = 12k /* end 0x10006000 */
RAM_HEAP1 (rwx) : ORIGIN = 0x10003000, LENGTH = 12K /* end 0x10006000 */
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 424K /* end 0x10070000 */
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64K /* end 0x20000000 */
TCM_TAB (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64K /* end 0x20000000 */
SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 0 /*2M end 0x30200000 */
TCM_TAB (rwx) : ORIGIN = 0x1FFFFD00, LENGTH = 768 /* end 0x20000000 */
SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M /* end 0x30200000 */
}
EXTERN(RAM_IMG2_VALID_PATTEN)
@ -21,6 +21,7 @@ EXTERN(main)
EXTERN(InfraStart)
EXTERN(gImage2EntryFun0)
SECTIONS
{
__rom_bss_start__ = 0x10000300;
@ -52,6 +53,7 @@ SECTIONS
__ram_tcm_start__ = .;
*mem.o (.bss*)
*memp.o (.bss*)
__tcm_heap_start__ = .;
*(.tcm.heap)
}
.dummy
@ -78,6 +80,11 @@ SECTIONS
}
} > TCM
.soc_ps_monitor :
{
__tcm_heap_end__ = .;
} > TCM_TAB
.image2.start.table :
{
__ram_heap1_end__ = .;
@ -116,11 +123,11 @@ SECTIONS
. = ALIGN(4);
xHeapRegions = .;
LONG(__ram_heap1_start__)
LONG(ORIGIN(RAM_HEAP1) + LENGTH(RAM_HEAP1) - __ram_heap1_start__)
LONG(__ram_heap1_end__ - __ram_heap1_start__)
LONG(__ram_heap2_start__)
LONG(ORIGIN(BD_RAM) + LENGTH(BD_RAM) - __ram_heap2_start__)
LONG(__ram_heap2_end__ - __ram_heap2_start__)
LONG(__sdram_heap_start__)
LONG(ORIGIN(SDRAM_RAM) + LENGTH(SDRAM_RAM) - __sdram_heap_start__)
LONG(__sdram_heap_end__ - __sdram_heap_start__)
LONG(0)
LONG(0)
} > BD_RAM
@ -148,20 +155,23 @@ SECTIONS
*(.bss*)
*(COMMON)
*(.bdsram.data*)
*(.bfsram.data*)
*(.sdram.bss*)
*(.p2p.bss*)
*(.wps.bss*)
*(.websocket.bss*)
__bss_end__ = .;
.ram.bss$$Limit = .;
} > BD_RAM
.ram_heap2 :
{
. = ALIGN(8);
__ram_heap2_start__ = .;
KEEP(*(.bfsram.data*)) /* ucHeap */
KEEP(*(.heap*)) /* ucHeap */
} > BD_RAM
__ram_heap2_end__ = 0x10070000;
.sdr_text :
{
@ -184,6 +194,7 @@ SECTIONS
. = ALIGN(8);
__sdram_heap_start__ = .;
} > SDRAM_RAM
__sdram_heap_end__ = 0x30200000;
.boot.head :
{

View file

@ -210,7 +210,7 @@
#define SDIO_ROM_BSS_SECTION \
SECTION(".sdio.rom.bss")
#define SDIO_ROM_TEXT_SECTION \
SECTION(".sdio.rom.text")
SECTION(".sdio.rom.text")
//3 SRAM Config Section
#define SRAM_BD_DATA_SECTION \
@ -219,6 +219,9 @@
#define SRAM_BF_DATA_SECTION \
SECTION(".bfsram.data")
#define SRAM_HEAP_SECTION \
SECTION(".sram.heap")
#define START_RAM_FUN_SECTION \
SECTION(".start.ram.data")
@ -277,7 +280,7 @@
#define IMAGE2_START_RAM_FUN_SECTION \
SECTION(".image2.ram.data")
SECTION(".image2.ram.data")
#define SDRAM_DATA_SECTION \
SECTION(".sdram.data")

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@ -108,7 +108,7 @@ void fATW2(void *arg){
// Test
void fATST(void *arg){
AT_PRINTK("[ATS#]: _AT_SYSTEM_TEST_");
// AT_PRINTK("[ATS#]: _AT_SYSTEM_TEST_");
DBG_8195A("\nCLK CPU\t\t%d Hz\nRAM heap\t%d bytes\nTCM heap\t%d bytes\n",
HalGetCpuClk(), xPortGetFreeHeapSize(), tcm_heap_freeSpace());
dump_mem_block_list();