mirror of
https://github.com/drasko/open-ameba.git
synced 2024-11-21 21:44:19 +00:00
add & fix
This commit is contained in:
pvvx
parent
a75e59b360
commit
d60fd166b1
19 changed files with 287 additions and 170 deletions
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@ -945,62 +945,70 @@ void fATSU(void *arg) {
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return;
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}
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if ((argc = parse_param(arg, argv)) != 7) {
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AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR,
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"[ATSU] Usage: ATSU=<baud>,<databits>,<stopbits>,<parity>,<flowcontrol>,<configmode>");
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at_printf("\r\n[ATSU] ERROR:1");
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return;
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if(argv[1][0] == '?') {
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read_uart_atcmd_setting_from_system_data(&uartconf);
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at_printf("\r\n");
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at_printf( "AT_UART_CONF: %d,%d,%d,%d,%d",
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uartconf.BaudRate, uartconf.DataBits, uartconf.StopBits,
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uartconf.Parity, uartconf.FlowControl);
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// return;
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}
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else {
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AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR,
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"[ATSU] Usage: ATSU=<baud>,<databits>,<stopbits>,<parity>,<flowcontrol>,<configmode>");
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at_printf("\r\n[ATSU] ERROR:1");
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return;
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}
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}
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else {
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baud = atoi(argv[1]);
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databits = atoi(argv[2]);
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stopbits = atoi(argv[3]);
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parity = atoi(argv[4]);
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flowcontrol = atoi(argv[5]);
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configmode = atoi(argv[6]);
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/*
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// Check Baud rate
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for (i=0; log_uart_support_rate[i]!=0xFFFFFF; i++) {
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if (log_uart_support_rate[i] == baud) {
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break;
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}
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}
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baud = atoi(argv[1]);
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databits = atoi(argv[2]);
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stopbits = atoi(argv[3]);
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parity = atoi(argv[4]);
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flowcontrol = atoi(argv[5]);
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configmode = atoi(argv[6]);
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/*
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// Check Baud rate
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for (i=0; log_uart_support_rate[i]!=0xFFFFFF; i++) {
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if (log_uart_support_rate[i] == baud) {
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break;
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}
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}
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if (log_uart_support_rate[i]== 0xFFFFFF) {
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at_printf("\r\n[ATSU] ERROR:2");
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return;
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}
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*/
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if (((databits < 5) || (databits > 8)) || ((stopbits < 1) || (stopbits > 2))
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|| ((parity < 0) || (parity > 2))
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|| ((flowcontrol < 0) || (flowcontrol > 1))
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|| ((configmode < 0) || (configmode > 3))\
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) {
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at_printf("\r\n[ATSU] ERROR:2");
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return;
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if (log_uart_support_rate[i]== 0xFFFFFF) {
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at_printf("\r\n[ATSU] ERROR:2");
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return;
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}
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*/
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if (((databits < 5) || (databits > 8)) || ((stopbits < 1) || (stopbits > 2))
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|| ((parity < 0) || (parity > 2))
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|| ((flowcontrol < 0) || (flowcontrol > 1))
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|| ((configmode < 0) || (configmode > 3)) ) {
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at_printf("\r\n[ATSU] ERROR:2");
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return;
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}
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memset((void*) &uartconf, 0, sizeof(UART_LOG_CONF));
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uartconf.BaudRate = baud;
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uartconf.DataBits = databits;
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uartconf.StopBits = stopbits;
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uartconf.Parity = parity;
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uartconf.FlowControl = flowcontrol;
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AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ALWAYS, "AT_UART_CONF: %d,%d,%d,%d,%d",
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uartconf.BaudRate, uartconf.DataBits, uartconf.StopBits,
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uartconf.Parity, uartconf.FlowControl);
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switch (configmode) {
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case 0: // set current configuration, won't save
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uart_atcmd_reinit(&uartconf);
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break;
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case 1: // set current configuration, and save
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write_uart_atcmd_setting_to_system_data(&uartconf);
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uart_atcmd_reinit(&uartconf);
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break;
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case 2: // set configuration, reboot to take effect
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write_uart_atcmd_setting_to_system_data(&uartconf);
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break;
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}
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}
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memset((void*) &uartconf, 0, sizeof(UART_LOG_CONF));
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uartconf.BaudRate = baud;
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uartconf.DataBits = databits;
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uartconf.StopBits = stopbits;
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uartconf.Parity = parity;
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uartconf.FlowControl = flowcontrol;
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AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ALWAYS, "AT_UART_CONF: %d,%d,%d,%d,%d",
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uartconf.BaudRate, uartconf.DataBits, uartconf.StopBits,
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uartconf.Parity, uartconf.FlowControl);
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switch (configmode) {
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case 0: // set current configuration, won't save
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uart_atcmd_reinit(&uartconf);
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break;
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case 1: // set current configuration, and save
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write_uart_atcmd_setting_to_system_data(&uartconf);
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uart_atcmd_reinit(&uartconf);
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break;
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case 2: // set configuration, reboot to take effect
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write_uart_atcmd_setting_to_system_data(&uartconf);
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break;
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}
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at_printf("\r\n[ATSU] OK");
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}
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#endif //#if CONFIG_EXAMPLE_UART_ATCMD
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@ -1372,7 +1380,7 @@ log_item_t at_sys_items[] = {
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{ "ATSE", fATSE }, // enable and disable echo
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#if CONFIG_WLAN
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#if CONFIG_WEBSERVER
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{ "ATSW", fATSW}, // start webserver
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{ "ATSW", fATSW}, // start webserver
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#endif
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{ "ATSY", fATSY }, // factory reset
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#if CONFIG_OTA_UPDATE
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@ -244,7 +244,7 @@ HAL_GPIO_IP_DeInit(
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extern u16 GPIOState[_PORT_MAX-1]; // побитно 16 бит для каждого порта (A..K), бит=номер задействованного пина в порту на периферию.
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//extern u16 GPIOState[_PORT_MAX-1]; // побитно 16 бит для каждого порта (A..K), бит=номер задействованного пина в порту на периферию.
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#endif // end of "#define _HAL_GPIO_H_"
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@ -10,7 +10,7 @@
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#ifndef _HAL_SDR_CONTROLLER_H_
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#define _HAL_SDR_CONTROLLER_H_
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#ifdef CONFIG_SDR_EN
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#if 1 // def CONFIG_SDR_EN
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typedef enum _DRAM_TYPE_ {
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DRAM_DDR_1 = 1,
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@ -187,5 +187,5 @@ typedef struct _DRAM_DEVICE_INFO_ {
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#define HAL_SDRAM_READ8(addr) HAL_READ8(SDR_SDRAM_BASE, addr)
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#endif // CONFIG_SDR_EN
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extern unsigned int rand_x;
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// extern unsigned int rand_x; // in rtl_bios_data.h
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#endif // end of "#ifndef _HAL_SDR_CONTROLLER_H_"
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@ -15,6 +15,7 @@
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#include "rtl8195a/rtl8195a_peri_on.h"
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#include "hal_peri_on.h"
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#include "wifi_conf.h"
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#include "rtl_consol.h"
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#ifndef USE_SRC_ONLY_BOOT
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#define USE_SRC_ONLY_BOOT 0
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@ -26,12 +27,12 @@
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#define rtl_memcpy _memcpy
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#endif
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#define VREG32(addr) ((u32)(*((volatile u32*)(addr))))
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#define VREG32(addr) (*((volatile u32*)(addr)))
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typedef void (*START_FUNC)(void);
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#define DEFAULT_BAUDRATE UART_BAUD_RATE_38400
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#define StartupSpicBitMode SpicDualBitMode // SpicOneBitMode //
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#define StartupSpicBitMode SpicDualBitMode // SpicOneBitMode
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#define StartupSpicBaudRate 0
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//-------------------------------------------------------------------------
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@ -84,38 +85,69 @@ extern u32 * NewVectorTable; // LD: NewVectorTable = 0x10000000;
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extern u8 __bss_start__, __bss_end__;
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#endif
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//extern volatile UART_LOG_CTL * pUartLogCtl;
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extern int UartLogCmdExecute(volatile u8 *);
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/*
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typedef struct __RAM_IMG2_VALID_PATTEN__ {
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char rtkwin[7];
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u8 x[13];
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} _RAM_IMG2_VALID_PATTEN, *_PRAM_IMG2_VALID_PATTEN;
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const uint8_t __attribute__((section(".image1.validate.rodata"))) RAM_IMG1_VALID_PATTEN[8] =
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*/
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const uint8_t IMAGE1_VALID_PATTEN_SECTION RAM_IMG1_VALID_PATTEN[8] =
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{ 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff };
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PRAM_FUNCTION_START_TABLE __attribute__((section(".data.pRamStartFun"))) pRamStartFun =
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(PRAM_FUNCTION_START_TABLE) 0x10000BC8;
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RAM_START_FUNCTION __attribute__((section(".start.ram.data.a"))) gRamStartFun =
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#include <reent.h>
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struct _reent __attribute__((section(".libc.reent"))) impure_reent = _REENT_INIT(impure_reent);
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//struct _reent * __attribute__((section(".libc.reent"))) _rtl_impure_ptr = { &impure_data };
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//struct _reent * __attribute__((at(0x1098))) __attribute__((section(".libc.reent"))) _rtl_impure_ptr = { &impure_data };
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struct _reent * __attribute__((at(0x10001c60))) __attribute__((section(".libc.reent"))) _rtl_impure_ptr = { &impure_reent };
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/* ROM */
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MON_RAM_BSS_SECTION
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volatile UART_LOG_CTL *pUartLogCtl;
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MON_RAM_BSS_SECTION
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UART_LOG_BUF UartLogBuf;
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MON_RAM_BSS_SECTION
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volatile UART_LOG_CTL UartLogCtl;
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MON_RAM_BSS_SECTION
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u8 *ArgvArray[MAX_ARGV]; // *ArgvArray[10] !
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MON_RAM_BSS_SECTION
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u8 UartLogHistoryBuf[UART_LOG_HISTORY_LEN][UART_LOG_CMD_BUFLEN]; // UartLogHistoryBuf[5][127] !
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RAM_START_FUNCTION START_RAM_FUN_A_SECTION gRamStartFun =
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{ PreProcessForVendor + 1 };
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RAM_START_FUNCTION __attribute__((section(".start.ram.data.b"))) gRamPatchWAKE =
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RAM_START_FUNCTION START_RAM_FUN_B_SECTION gRamPatchWAKE =
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{ RtlBootToSram + 1 };
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RAM_START_FUNCTION __attribute__((section(".start.ram.data.c"))) gRamPatchFun0 =
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RAM_START_FUNCTION START_RAM_FUN_C_SECTION gRamPatchFun0 =
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{ RtlBootToSram + 1 };
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RAM_START_FUNCTION __attribute__((section(".start.ram.data.d"))) gRamPatchFun1 =
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RAM_START_FUNCTION START_RAM_FUN_D_SECTION gRamPatchFun1 =
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{ RtlBootToSram + 1 };
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RAM_START_FUNCTION __attribute__((section(".start.ram.data.e"))) gRamPatchFun2 =
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RAM_START_FUNCTION START_RAM_FUN_E_SECTION gRamPatchFun2 =
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{ RtlBootToSram + 1 };
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#if !USE_SRC_ONLY_BOOT
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RAM_START_FUNCTION __attribute__((section(".image2.ram.data"))) gImage2EntryFun0 =
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RAM_START_FUNCTION IMAGE2_START_RAM_FUN_SECTION gImage2EntryFun0 =
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{ InfraStart + 1 };
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#else
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RAM_START_FUNCTION __attribute__((section(".image2.ram.data"))) gImage2EntryFun0 =
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{ 1 };
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RAM_START_FUNCTION IMAGE2_START_RAM_FUN_SECTION gImage2EntryFun0 =
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{ 0x100 };
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#endif // !USE_SRC_ONLY_BOOT
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_RAM_IMG2_VALID_PATTEN __attribute__((section(".image2.validate.rodata"))) RAM_IMG2_VALID_PATTEN =
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_RAM_IMG2_VALID_PATTEN IMAGE2_VALID_PATTEN_SECTION RAM_IMG2_VALID_PATTEN =
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{ { IMG2_SIGN_TXT }, { 0xff, 0, 1, 1, 0, 0x95, 0x81, 1, 1, 0, 0, 0, 0 } }; // "RTKWin"
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HAL_GPIO_ADAPTER __attribute__((section(".hal.ram.data"))) gBoot_Gpio_Adapter;
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HAL_GPIO_ADAPTER PINMUX_RAM_DATA_SECTION gBoot_Gpio_Adapter;
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#pragma arm section code = ".hal.ram.text"
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#pragma arm section rodata = ".hal.ram.rodata", rwdata = ".hal.ram.data", zidata = ".hal.ram.bss"
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#if !USE_SRC_ONLY_BOOT
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//----- HalNMIHandler_Patch
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@ -126,6 +158,51 @@ void HalNMIHandler_Patch(void) {
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}
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#endif // !USE_SRC_ONLY_BOOT
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void __attribute__((section(".hal.ram.text"))) SetDebugFlgs() {
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#if CONFIG_DEBUG_LOG > 2
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ConfigDebugErr = -1;
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ConfigDebugWarn = -1;
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ConfigDebugInfo = -1;
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#elif CONFIG_DEBUG_LOG > 1
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ConfigDebugErr = -1;
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ConfigDebugWarn = -1;
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ConfigDebugInfo = 0;
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#elif CONFIG_DEBUG_LOG > 0
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ConfigDebugErr = -1;
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ConfigDebugWarn = 0;
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ConfigDebugInfo = 0;
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#else
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ConfigDebugErr = 0;
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ConfigDebugWarn = 0;
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ConfigDebugInfo = 0;
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#endif
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}
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void __attribute__((section(".hal.ram.text"))) InitSpic(void)
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{
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VREG32(0x40006000) = 0x01000300;
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VREG32(0x40006004) = 0x1;
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VREG32(0x400060E0) = 0x0B;
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VREG32(0x400060E4) = 0x3B;
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VREG32(0x400060E8) = 0x3B;
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VREG32(0x400060EC) = 0x6B;
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VREG32(0x400060F0) = 0xEB;
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VREG32(0x400060F4) = 0x02;
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VREG32(0x400060F8) = 0xA2;
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VREG32(0x400060FC) = 0xA2;
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VREG32(0x40006100) = 0x32;
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VREG32(0x40006104) = 0x38;
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VREG32(0x40006108) = 0x06;
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VREG32(0x4000610C) = 0x05;
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VREG32(0x40006110) = 0x51;
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VREG32(0x40006114) = 0x01;
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VREG32(0x40006118) = 0x03;
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VREG32(0x4000611C) = 0x20030013;
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VREG32(0x40006120) = 0x202;
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VREG32(0x40006124) = 0x0E;
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}
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//----- StartupHalLogUartInit
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u32 __attribute__((section(".hal.ram.text"))) StartupHalLogUartInit(u32 uart_irq) {
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HAL_UART_WRITE32(UART_DLH_OFF, 0);
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@ -136,6 +213,7 @@ u32 __attribute__((section(".hal.ram.text"))) StartupHalLogUartInit(u32 uart_irq
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u32 Remaind = ((SysClock * 10) / SampleRate) - (Divisor * 10);
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if (Remaind > 4) Divisor++;
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// set DLAB bit to 1
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// HAL_UART_WRITE32(UART_INTERRUPT_EN_REG_OFF, 0);
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HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, RUART_LINE_CTL_REG_DLAB_ENABLE);
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HAL_UART_WRITE32(UART_DLL_OFF, Divisor & 0xff);
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HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, 3);
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@ -147,7 +225,7 @@ u32 __attribute__((section(".hal.ram.text"))) StartupHalLogUartInit(u32 uart_irq
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// Cortex-M3 SCB->AIRCR
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HAL_WRITE32(0xE000ED00, 0x0C,
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(HAL_READ32(0xE000ED00, 0x0C) & 0x0F8FF) | 0x5FA0300);
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HAL_WRITE32(0xE000E100,0x313,0xFFFFFFE0); // HAL_WRITE8(0xE000E100, 0x313, 0xE0);
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HAL_WRITE8(0xE000E100, 0x313, 0xE0); // HAL_WRITE8(0xE000E100, 0x313, 0xE0);
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HAL_WRITE32(0xE000E100, 0, 0x80000); // NVIC enable external interrupt[?] ?
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}
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return 0;
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@ -156,75 +234,79 @@ u32 __attribute__((section(".hal.ram.text"))) StartupHalLogUartInit(u32 uart_irq
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//----- StartupHalInitPlatformLogUart
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void __attribute__((section(".hal.ram.text"))) StartupHalInitPlatformLogUart(
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void) {
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HAL_UART_READ32(UART_REV_BUF_OFF);
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
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HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (~(BIT_SOC_LOG_UART_EN))); // 40000210 &= 0xFFFFEFFF; // ~(1<<12)
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
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HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_LOG_UART_EN); // 40000210 |= 0x1000u;
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HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL,
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HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_LOG_UART_EN); // 40000230 |= 0x1000u;
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ACTCK_LOG_UART_CCTRL(ON); // 40000230 |= 0x1000u;
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StartupHalLogUartInit(IER_ERBFI | IER_ELSI);
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}
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extern volatile u8 * pUartLogCtl;
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extern int UartLogCmdExecute(volatile u8 *);
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void __attribute__((section(".hal.ram.text"))) RtlConsolRam(void)
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{
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DiagPrintf("\r\nRTL Console ROM: Start - press 'ESC' key, Help '?'\r\n");
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// __asm__ __volatile__ ("cpsid f\n");
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while(pUartLogCtl[5] != 1);
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pUartLogCtl[3] = 0;
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pUartLogCtl[6] = 1;
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DiagPrintf("\r<RTL>");
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// HalCpuClkConfig(0); // 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
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// ConfigDebugErr = -1;
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// VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC);
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// HalInitPlatformLogUartV02();
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// HalReInitPlatformLogUartV02();
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// HalInitPlatformTimerV02();
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__asm__ __volatile__ ("cpsie f\n");
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DiagPrintf("\r\nRTL Console ROM: Start - press 'ESC' key, Help '?'\r\n");
|
||||
while(!pUartLogCtl->ExecuteEsc);
|
||||
pUartLogCtl->EscSTS = 0;
|
||||
pUartLogCtl->BootRdy = 1;
|
||||
DiagPrintf("\r<RTL>");
|
||||
while(1) {
|
||||
while(pUartLogCtl[4] != 1 );
|
||||
while(!pUartLogCtl->ExecuteCmd);
|
||||
UartLogCmdExecute(pUartLogCtl);
|
||||
DiagPrintf("\r<RTL>");
|
||||
pUartLogCtl[4] = 0;
|
||||
pUartLogCtl->ExecuteCmd = 0;
|
||||
}
|
||||
}
|
||||
|
||||
extern SPIC_INIT_PARA SpicInitParaAllClk[3][CPU_CLK_TYPE_NO];
|
||||
|
||||
//----- RtlBootToSram
|
||||
void __attribute__((section(".hal.ram.text"))) RtlBootToSram(void) {
|
||||
TIMER_ADAPTER tim_adapter;
|
||||
|
||||
// memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__);
|
||||
|
||||
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL,
|
||||
HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_SLPCK_VENDOR_REG_EN | BIT_SOC_ACTCK_VENDOR_REG_EN); // 40000230 |= 0x40u; 40000230 |= 0x80u;
|
||||
/* JTAG On */
|
||||
ACTCK_VENDOR_CCTRL(ON);
|
||||
SLPCK_VENDOR_CCTRL(ON);
|
||||
HalPinCtrlRtl8195A(JTAG, 0, 1);
|
||||
|
||||
memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__);
|
||||
|
||||
/* Flash & LogUart On */
|
||||
HAL_PERI_ON_WRITE32(REG_GPIO_SHTDN_CTRL, 0x7FF);
|
||||
SPI_FLASH_PIN_FCTRL(ON);
|
||||
HAL_PERI_ON_WRITE32(REG_CPU_PERIPHERAL_CTRL,
|
||||
HAL_PERI_ON_READ32(REG_CPU_PERIPHERAL_CTRL) | BIT_SPI_FLSH_PIN_EN | BIT_LOG_UART_PIN_EN); // 400002C0 |= 0x100000u;
|
||||
HAL_PERI_ON_READ32(REG_CPU_PERIPHERAL_CTRL) | BIT_SPI_FLSH_PIN_EN); // 400002C0 |= 0x1u;
|
||||
HAL_PERI_ON_WRITE32(REG_CPU_PERIPHERAL_CTRL,
|
||||
HAL_PERI_ON_READ32(REG_CPU_PERIPHERAL_CTRL) | BIT_LOG_UART_PIN_EN); // 400002C0 |= 0x100000u;
|
||||
|
||||
VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC
|
||||
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
|
||||
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_FLASH_EN); // 40000210 |= 0x10u;
|
||||
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL,
|
||||
HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_SLPCK_FLASH_EN | BIT_SOC_ACTCK_FLASH_EN); // 40000230 |= 0x100u; 40000230) |= 0x200u;
|
||||
|
||||
ACTCK_FLASH_CCTRL(ON);
|
||||
SLPCK_FLASH_CCTRL(ON);
|
||||
HalPinCtrlRtl8195A(SPI_FLASH, 0, 1);
|
||||
|
||||
SpicNVMCalLoadAll();
|
||||
|
||||
HAL_SYS_CTRL_WRITE32(REG_SYS_CLK_CTRL1,
|
||||
HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) & 0x8F); // VREG32(0x40000014) &= 0x8F;
|
||||
|
||||
ConfigDebugErr = -1;
|
||||
ConfigDebugWarn = 0;
|
||||
ConfigDebugInfo = 0;
|
||||
SetDebugFlgs();
|
||||
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
|
||||
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (~(BIT_SOC_LOG_UART_EN))); // 40000210 &= 0xFFFFEFFF; // ~(1<<12)
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
|
||||
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_LOG_UART_EN); // 40000210 |= 0x1000u;
|
||||
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL,
|
||||
HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_LOG_UART_EN); // 40000230 |= 0x1000u;
|
||||
|
||||
ACTCK_LOG_UART_CCTRL(ON);
|
||||
// SLPCK_LOG_UART_CCTRL(ON);
|
||||
|
||||
tim_adapter.IrqHandle.IrqFun = &UartLogIrqHandle;
|
||||
tim_adapter.IrqHandle.IrqNum = UART_LOG_IRQ;
|
||||
|
|
@ -240,8 +322,9 @@ void __attribute__((section(".hal.ram.text"))) RtlBootToSram(void) {
|
|||
HAL_PERI_ON_READ32(REG_OSC32K_CTRL) | BIT_32K_POW_CKGEN_EN); // VREG32(0x40000270) |= 1u;
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
|
||||
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_GTIMER_EN); // VREG32(0x40000210) |= 0x10000u;
|
||||
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL,
|
||||
HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_TIMER_EN | BIT_SOC_SLPCK_TIMER_EN); // VREG32(0x40000230) |= 0x4000u; VREG32(0x40000230) |= 0x8000u;
|
||||
|
||||
ACTCK_TIMER_CCTRL(ON);
|
||||
SLPCK_TIMER_CCTRL(ON);
|
||||
|
||||
tim_adapter.TimerIrqPriority = 0;
|
||||
tim_adapter.TimerLoadValueUs = 0;
|
||||
|
|
@ -250,24 +333,23 @@ void __attribute__((section(".hal.ram.text"))) RtlBootToSram(void) {
|
|||
tim_adapter.TimerId = 1;
|
||||
HalTimerInitRtl8195a((PTIMER_ADAPTER) &tim_adapter);
|
||||
|
||||
SpicInitRtl8195A(StartupSpicBaudRate, StartupSpicBitMode); // InitBaudRate 1, SpicBitMode 1
|
||||
SpicFlashInitRtl8195A(StartupSpicBitMode); // SpicBitMode 1
|
||||
SpicInitRtl8195A(1, StartupSpicBitMode); // StartupSpicBaudRate InitBaudRate 1, SpicBitMode 1 StartupSpicBitMode
|
||||
SpicFlashInitRtl8195A(StartupSpicBitMode); // SpicBitMode 1 StartupSpicBitMode
|
||||
DBG_8195A("==*== Enter Image 1.5 ====\nImg2 Sign: %s, InfaStart @ 0x%08x\n",
|
||||
&__image2_validate_code__, __image2_entry_func__);
|
||||
if (strcmp((const char * )&__image2_validate_code__, IMG2_SIGN_TXT)) {
|
||||
DBG_MISC_ERR("Invalid Image2 Signature!\n");
|
||||
RtlConsolRam();
|
||||
// __asm__ __volatile__ ("cpsie f\n");
|
||||
// RtlConsolRom(10000); // ROM: RtlConsolRom = 0xedcd;
|
||||
}
|
||||
// InitSpic();
|
||||
__image2_entry_func__();
|
||||
}
|
||||
|
||||
//----- SYSCpuClkConfig
|
||||
void __attribute__((section(".hal.ram.text"))) SYSCpuClkConfig(int ChipID, int SysCpuClk) {
|
||||
int flg = 0;
|
||||
DBG_SPIF_INFO("%s(0x%x)\n", "SYSCpuClkConfig", SysCpuClk);
|
||||
if(HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN){
|
||||
DBG_SPIF_INFO("SYSCpuClkConfig(0x%x)\n", SysCpuClk);
|
||||
if(HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) {
|
||||
SpicWaitWipRtl8195A(); //_SpicWaitWipDoneRefinedRtl8195A(); ???
|
||||
flg = 1;
|
||||
}
|
||||
|
|
@ -276,11 +358,12 @@ void __attribute__((section(".hal.ram.text"))) SYSCpuClkConfig(int ChipID, int S
|
|||
HalDelayUs(1000);
|
||||
StartupHalInitPlatformLogUart();
|
||||
if (flg) {
|
||||
// SpicOneBitCalibrationRtl8195A(SysCpuClk); // extern u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk);
|
||||
// Disable SPI_FLASH User Mode
|
||||
SpicOneBitCalibrationRtl8195A(SysCpuClk); // extern u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk);
|
||||
/*
|
||||
// Disable SPI_FLASH User Mode
|
||||
HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0);
|
||||
HAL_SPI_WRITE32(REG_SPIC_VALID_CMD,
|
||||
(HAL_SPI_READ32(REG_SPIC_VALID_CMD)|(FLASH_VLD_DUAL_CMDS)));
|
||||
(HAL_SPI_READ32(REG_SPIC_VALID_CMD)|(FLASH_VLD_DUAL_CMDS))); */
|
||||
SpicCalibrationRtl8195A(StartupSpicBitMode, 0);
|
||||
}
|
||||
}
|
||||
|
|
@ -329,35 +412,45 @@ void __attribute__((section(".hal.ram.text"))) StartupHalSpicInit(
|
|||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
|
||||
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT4); // HAL_SYS_CTRL_READ32
|
||||
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL,
|
||||
HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_FLASH_EN);
|
||||
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL,
|
||||
HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_SLPCK_FLASH_EN);
|
||||
HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_FLASH_EN | BIT_SOC_SLPCK_FLASH_EN);
|
||||
HalPinCtrlRtl8195A(SPI_FLASH,
|
||||
((HAL_SYS_CTRL_READ32(REG_SYS_SYSTEM_CFG1) & 0xF0000000)
|
||||
== 0x30000000), 1);
|
||||
SpicInitRtl8195A(InitBaudRate, StartupSpicBitMode);
|
||||
}
|
||||
|
||||
|
||||
void __attribute__((section(".hal.ram.text"))) flashcpy(u32 raddr, u32 faddr, s32 size) {
|
||||
while(size > 0) {
|
||||
HAL_WRITE32(0, raddr, HAL_READ32(SPI_FLASH_BASE, faddr));
|
||||
raddr+=4;
|
||||
faddr+=4;
|
||||
size-=4;
|
||||
}
|
||||
}
|
||||
//----- PreProcessForVendor
|
||||
void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(void) {
|
||||
START_FUNC entry_func;
|
||||
u32 run_image;
|
||||
u32 Image2Addr;
|
||||
u32 Image2Addr = *(u32 *)(0x1006FFFC);
|
||||
u32 v16 = 0, v17;
|
||||
#if 0
|
||||
u8 efuse0xD3_data;
|
||||
HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xD3,
|
||||
&efuse0xD3_data, L25EOUTVOLTAGE);
|
||||
if (efuse0xD3_data & 1) v16 = HalPinCtrlRtl8195A(JTAG, 0, 1);
|
||||
if (efuse0xD3_data & 1)
|
||||
#endif
|
||||
HalPinCtrlRtl8195A(JTAG, 0, 1);
|
||||
SetDebugFlgs();
|
||||
int chip_id = _GetChipId();
|
||||
int flash_enable = HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN; // v6 = ...
|
||||
int spic_init = 0;
|
||||
/// InitSpic();
|
||||
if (flash_enable) {
|
||||
entry_func = &__image2_entry_func__;
|
||||
flash_enable = 1;
|
||||
spic_init = 1;
|
||||
} else {
|
||||
memcpy(&Image2Addr, (const void *) 0x1006FFFC, 4); // ???
|
||||
entry_func = Image2Addr;
|
||||
entry_func = (START_FUNC) Image2Addr;
|
||||
if (chip_id != CHIP_ID_8711AN) { // 0xFB
|
||||
StartupHalSpicInit(StartupSpicBaudRate); // BaudRate 1
|
||||
spic_init = 1;
|
||||
|
|
@ -368,7 +461,6 @@ void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(void) {
|
|||
&__image1_bss_end__ - &__image1_bss_start__);
|
||||
HalDelayUs(1000);
|
||||
int sdr_enable = 0;
|
||||
// if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) << 10) < 0 ) v1 = 0; // BIT(21)
|
||||
|
||||
#ifdef CONFIG_SDR_EN
|
||||
if (chip_id > CHIP_ID_8711AF || chip_id == CHIP_ID_8710AM) {
|
||||
|
|
@ -384,9 +476,6 @@ void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(void) {
|
|||
LDO25M_CTRL(OFF);
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21));
|
||||
#endif
|
||||
ConfigDebugErr = -1;
|
||||
ConfigDebugWarn = -1;
|
||||
ConfigDebugInfo = -1;
|
||||
|
||||
if (spic_init) SpicNVMCalLoadAll();
|
||||
SYSCpuClkConfig(chip_id, 0);
|
||||
|
|
@ -401,6 +490,7 @@ void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(void) {
|
|||
if (sdr_enable) SdrControllerInit();
|
||||
#endif
|
||||
if (flash_enable) {
|
||||
|
||||
u32 img1size = (*(u16 *) (SPI_FLASH_BASE + 0x18)) << 10; // size in 1024 bytes
|
||||
if (img1size == 0 || img1size >= 0x3FFFC00)
|
||||
img1size = *(u32 *) (SPI_FLASH_BASE + 0x10) + 32;
|
||||
|
|
@ -458,12 +548,10 @@ LABEL_41: if (IsForceLoadDefaultImg2()) {
|
|||
LABEL_55: prdflash = run_image + SPI_FLASH_BASE;
|
||||
u32 img_size = *prdflash++;
|
||||
u32 Image2Addr = *prdflash;
|
||||
DBG_8195A("Flash Image2: Addr 0x%x, Len %d, Load to SRAM 0x%x\n",
|
||||
run_image, img_size, Image2Addr);
|
||||
/// memcpy(Image2Addr, run_image + SPI_FLASH_BASE + 16, img_size);
|
||||
SpicUserReadFourByteRtl8195A(img_size, run_image + 16, Image2Addr, StartupSpicBitMode); // SpicDualBitMode
|
||||
prdflash = run_image + img_size + SPI_FLASH_BASE
|
||||
+ 16;
|
||||
DBG_8195A("Flash Image2: Addr 0x%x, Len %d, Load to SRAM 0x%x\n", run_image, img_size, Image2Addr); // debug!
|
||||
flashcpy(Image2Addr, run_image+16, img_size);
|
||||
// SpicUserReadFourByteRtl8195A(img_size, run_image + 16, Image2Addr, StartupSpicBitMode); // SpicDualBitMode
|
||||
prdflash = run_image + img_size + SPI_FLASH_BASE + 16;
|
||||
u32 sdram_image_size = *prdflash++; // +0x10
|
||||
u32 sdram_load_addr = *prdflash; // +0x14
|
||||
DBG_8195A("Image3 length: 0x%x, Image3 Addr: 0x%x\n",
|
||||
|
|
@ -476,7 +564,7 @@ LABEL_55: prdflash = run_image + SPI_FLASH_BASE;
|
|||
}
|
||||
DBG_8195A("Image3 length: 0x%x, Image3 Addr: 0x%x\n",
|
||||
sdram_image_size, sdram_load_addr);
|
||||
SpicUserReadRtl8195A(sdram_image_size, run_image + img_size + 32, SDR_SDRAM_BASE, StartupSpicBitMode);
|
||||
// SpicUserReadRtl8195A(sdram_image_size, run_image + img_size + 32, SDR_SDRAM_BASE, StartupSpicBitMode);
|
||||
} else DBG_8195A("No Image3\n");
|
||||
|
||||
entry_func = *(u32 *)Image2Addr;
|
||||
|
|
@ -488,6 +576,11 @@ LABEL_55: prdflash = run_image + SPI_FLASH_BASE;
|
|||
DBG_MISC_ERR("Invalid Image2 Signature\n");
|
||||
RtlConsolRam();
|
||||
}
|
||||
#if 0
|
||||
DBG_8195A("CLK CPU: %d Hz\n", HalGetCpuClk());
|
||||
RtlConsolRam();
|
||||
#else
|
||||
#endif
|
||||
(void) (entry_func)();
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,8 +3,6 @@
|
|||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
#ifndef _HAL_8195A_H_
|
||||
#define _HAL_8195A_H_
|
||||
|
|
@ -169,4 +167,37 @@
|
|||
#define IMG_SIGN2_SWP IMG_SIGN2_RUN // "8711"
|
||||
#define IMG2_SIGN_TXT "RTKWin"
|
||||
|
||||
typedef struct _RAM_FUNCTION_START_TABLE_ {
|
||||
VOID (*RamStartFun) (VOID); // Run for Init console, Run if ( v40000210 & 0x4000000 )
|
||||
VOID (*RamWakeupFun) (VOID); // Run if ( v40000210 & 0x20000000 )
|
||||
VOID (*RamPatchFun0) (VOID); // Run if ( v40000210 & 0x10000000 )
|
||||
VOID (*RamPatchFun1) (VOID); // Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
|
||||
VOID (*RamPatchFun2) (VOID); // Run for Init console, if ( v40000210 & 0x4000000 )
|
||||
}RAM_FUNCTION_START_TABLE, *PRAM_FUNCTION_START_TABLE;
|
||||
// START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__ =
|
||||
// {RamStartFun + 1, RamWakeupFun + 1, RamPatchFun0 + 1, RamPatchFun1 + 1, RamPatchFun2 + 1 };
|
||||
|
||||
#define IMG1_VALID_PATTEN_INIT() { 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff }
|
||||
// IMAGE1_VALID_PATTEN_SECTION uint8 RAM_IMG1_VALID_PATTEN[8] = IMG1_VALID_PATTEN_INIT();
|
||||
|
||||
typedef struct _RAM_START_FUNCTION_ {
|
||||
VOID (*RamStartFun) (VOID);
|
||||
}RAM_START_FUNCTION, *PRAM_START_FUNCTION;
|
||||
// IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 = { InfraStart + 1 };
|
||||
|
||||
typedef struct __RAM_IMG2_VALID_PATTEN__ {
|
||||
char rtkwin[7];
|
||||
u8 x[13];
|
||||
} _RAM_IMG2_VALID_PATTEN, *_PRAM_IMG2_VALID_PATTEN;
|
||||
|
||||
// IMAGE2_VALID_PATTEN_SECTION _RAM_IMG2_VALID_PATTEN RAM_IMG2_VALID_PATTEN = RAM_IMG2_VALID_PATTEN_INIT();
|
||||
#define RAM_IMG2_VALID_PATTEN_INIT() { \
|
||||
{ IMG2_SIGN_TXT }, { 0xff, \
|
||||
(FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff), \
|
||||
(FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff), \
|
||||
(FW_CHIP_ID&0xff), ((FW_CHIP_ID >> 8)&0xff), \
|
||||
(FW_CHIP_VER), (FW_BUS_TYPE), \
|
||||
(FW_INFO_RSV1), (FW_INFO_RSV2), (FW_INFO_RSV3), (FW_INFO_RSV4)}}
|
||||
|
||||
|
||||
#endif //_HAL_8195A_H_
|
||||
|
|
|
|||
|
|
@ -15,20 +15,16 @@
|
|||
#include "freertos_pmu.h"
|
||||
#endif
|
||||
#include "tcm_heap.h"
|
||||
#include "rtl_bios_data.h"
|
||||
|
||||
MON_RAM_BSS_SECTION
|
||||
volatile UART_LOG_CTL UartLogCtl;
|
||||
MON_RAM_BSS_SECTION
|
||||
volatile UART_LOG_CTL *pUartLogCtl;
|
||||
MON_RAM_BSS_SECTION
|
||||
u8 *ArgvArray[MAX_ARGV];
|
||||
MON_RAM_BSS_SECTION
|
||||
UART_LOG_BUF UartLogBuf;
|
||||
//MON_RAM_BSS_SECTION UART_LOG_CTL UartLogCtl;
|
||||
//MON_RAM_BSS_SECTION UART_LOG_CTL *pUartLogCtl;
|
||||
//MON_RAM_BSS_SECTION u8 *ArgvArray[MAX_ARGV];
|
||||
//MON_RAM_BSS_SECTION UART_LOG_BUF UartLogBuf;
|
||||
|
||||
|
||||
#ifdef CONFIG_UART_LOG_HISTORY
|
||||
MON_RAM_BSS_SECTION
|
||||
u8 UartLogHistoryBuf[UART_LOG_HISTORY_LEN][UART_LOG_CMD_BUFLEN];
|
||||
//MON_RAM_BSS_SECTION u8 UartLogHistoryBuf[UART_LOG_HISTORY_LEN][UART_LOG_CMD_BUFLEN];
|
||||
#endif
|
||||
|
||||
_LONG_CALL_
|
||||
|
|
|
|||
|
|
@ -510,7 +510,7 @@ typedef unsigned char BOOLEAN,*PBOOLEAN;
|
|||
#define __extension__ /* Ignore */
|
||||
#define __restrict /* Ignore */
|
||||
#endif
|
||||
|
||||
/* in rtl8155a.h
|
||||
typedef struct _RAM_START_FUNCTION_ {
|
||||
VOID (*RamStartFun) (VOID);
|
||||
}RAM_START_FUNCTION, *PRAM_START_FUNCTION;
|
||||
|
|
@ -522,5 +522,5 @@ typedef struct _RAM_FUNCTION_START_TABLE_ {
|
|||
VOID (*RamPatchFun1) (VOID);
|
||||
VOID (*RamPatchFun2) (VOID);
|
||||
}RAM_FUNCTION_START_TABLE, *PRAM_FUNCTION_START_TABLE;
|
||||
|
||||
*/
|
||||
#endif// __BASIC_TYPES_H__
|
||||
|
|
|
|||
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|
@ -108,30 +108,12 @@ void fATW2(void *arg){
|
|||
|
||||
// Test
|
||||
void fATST(void *arg){
|
||||
extern u8 __HeapLimit, __StackTop;
|
||||
extern struct Heap g_tcm_heap;
|
||||
//DBG_INFO_MSG_ON(_DBG_TCM_HEAP_); // On Debug TCM MEM
|
||||
#if DEBUG_AT_USER_LEVEL > 1
|
||||
printf("ATST: Mem info:\n");
|
||||
#endif
|
||||
// vPortFree(pvPortMalloc(4)); // Init RAM heap
|
||||
printf("\nCLK CPU\t\t%d Hz\nRAM heap\t%d bytes\nRAM free\t%d bytes\nTCM heap\t%d bytes\n",
|
||||
HalGetCpuClk(), xPortGetFreeHeapSize(), (int)&__StackTop - (int)&__HeapLimit, tcm_heap_freeSpace());
|
||||
printf("TCM ps_monitor\t%d bytes\n", 0x20000000 - (u32)&tcm_heap - tcm_heap_size);
|
||||
dump_mem_block_list();
|
||||
u32 saved = ConfigDebugInfo;
|
||||
DBG_INFO_MSG_ON(_DBG_TCM_HEAP_); // On Debug TCM MEM
|
||||
tcm_heap_dump();
|
||||
ConfigDebugInfo = saved;
|
||||
printf("\n");
|
||||
#if (configGENERATE_RUN_TIME_STATS == 1)
|
||||
char *cBuffer = pvPortMalloc(512);
|
||||
if(cBuffer != NULL) {
|
||||
vTaskGetRunTimeStats((char *)cBuffer);
|
||||
printf("%s", cBuffer);
|
||||
}
|
||||
vPortFree(cBuffer);
|
||||
#endif
|
||||
AT_PRINTK("[ATS#]: _AT_SYSTEM_TEST_");
|
||||
DBG_8195A("\nCLK CPU\t\t%d Hz\nRAM heap\t%d bytes\nTCM heap\t%d bytes\n",
|
||||
HalGetCpuClk(), xPortGetFreeHeapSize(), tcm_heap_freeSpace());
|
||||
dump_mem_block_list();
|
||||
tcm_heap_dump();
|
||||
DBG_8195A("\n");
|
||||
}
|
||||
|
||||
int mp3_cfg_read(void)
|
||||
|
|
|
|||
|
|
@ -500,7 +500,13 @@ void main(void) {
|
|||
if ( rtl_cryptoEngine_init() != 0 ) DBG_8195A("crypto engine init failed\r\n");
|
||||
*/
|
||||
#if defined(CONFIG_CPU_CLK)
|
||||
HalCpuClkConfig(CPU_CLOCK_SEL_VALUE); // 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
|
||||
#if 1 // 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
|
||||
HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) & (~(1<<17)));
|
||||
HalCpuClkConfig(CPU_CLOCK_SEL_VALUE); // 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
|
||||
#else // 0 - 200000000 Hz, 1 - 10000000 Hz, 2 - 50000000 Hz, 3 - 25000000 Hz, 4 - 12500000 Hz, 5 - 4000000 Hz
|
||||
HalCpuClkConfig(1);
|
||||
HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) | (1<<17));
|
||||
#endif
|
||||
HAL_LOG_UART_ADAPTER pUartAdapter;
|
||||
pUartAdapter.BaudRate = RUART_BAUD_RATE_38400;
|
||||
HalLogUartSetBaudRate(&pUartAdapter);
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ INCLUDES += sdk/component/soc/realtek/8195a/cmsis
|
|||
INCLUDES += sdk/component/soc/realtek/8195a/cmsis/device
|
||||
INCLUDES += sdk/component/soc/realtek/8195a/fwlib
|
||||
INCLUDES += sdk/component/soc/realtek/8195a/fwlib/rtl8195a
|
||||
INCLUDES += sdk/component/soc/realtek/8195a/misc/rtl_std_lib
|
||||
INCLUDES += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/include
|
||||
INCLUDES += sdk/component/common/drivers
|
||||
INCLUDES += sdk/component/common/drivers/wlan/realtek/include
|
||||
|
|
|
|||
Loading…
Reference in a new issue