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fix set UART BaudRate
This commit is contained in:
parent
3f4d5c4454
commit
c8ebe27a6b
2 changed files with 13 additions and 10 deletions
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@ -223,7 +223,7 @@ typedef enum {
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#define UART_OVSR_POOL_MAX 2090
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#define UART_OVSR_POOL_MAX 2090
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#define DIVISOR_RESOLUTION 10
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#define DIVISOR_RESOLUTION 10
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#define JITTER_LIMIT 100
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#define JITTER_LIMIT 100
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#define UART_SCLK (200000000*5/12)
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#define UART_SCLK ((HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) & (1<<17))? (100000000) : (200000000*5/12))
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typedef struct _RUART_SPEED_SETTING_ {
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typedef struct _RUART_SPEED_SETTING_ {
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u32 BaudRate;
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u32 BaudRate;
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@ -154,7 +154,7 @@ HalRuartGenBaudRateRtl8195a(
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u32 uart_ovsr_mod;
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u32 uart_ovsr_mod;
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u32 min_uart_ovsr; // ovsr with mini err
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u32 min_uart_ovsr; // ovsr with mini err
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u32 min_uart_ovsr_mod;
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u32 min_uart_ovsr_mod;
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u32 uart_clock;
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u64 uart_clock;
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u32 divisor_temp;
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u32 divisor_temp;
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u32 max_jitter_temp;
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u32 max_jitter_temp;
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u32 err_temp;
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u32 err_temp;
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@ -168,17 +168,17 @@ HalRuartGenBaudRateRtl8195a(
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baud_rate = pBaudSetting->BaudRate;
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baud_rate = pBaudSetting->BaudRate;
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if (baud_rate >= 1000000) {
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if (baud_rate >= 1000000) {
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baud_rate /= 100;
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baud_rate /= 100;
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uart_clock = pBaudSetting->sclk;
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uart_clock = (u64)pBaudSetting->sclk;
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} else {
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} else {
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baud_rate /= 2;
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baud_rate /= 2;
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uart_clock = pBaudSetting->sclk*50; // UART clock is 1/2 CPU clock
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uart_clock = (u64)pBaudSetting->sclk * 50; // UART clock is 1/2 CPU clock
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}
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}
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div_res = pBaudSetting->divisor_resolution;
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div_res = pBaudSetting->divisor_resolution;
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while ((min_err > pBaudSetting->max_err) && (div_res > 0)) {
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while ((min_err > pBaudSetting->max_err) && (div_res > 0)) {
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uart_ovsr = pBaudSetting->Ovsr_max;
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uart_ovsr = pBaudSetting->Ovsr_max;
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while(uart_ovsr >= pBaudSetting->Ovsr_min) {
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while(uart_ovsr >= pBaudSetting->Ovsr_min) {
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divisor_temp = ((uart_clock/baud_rate)/uart_ovsr);
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divisor_temp = (uart_clock/baud_rate)/uart_ovsr;
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max_jitter_temp = 0;
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max_jitter_temp = 0;
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if (divisor_temp > 0) {
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if (divisor_temp > 0) {
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max_jitter_temp = 100000/uart_ovsr;
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max_jitter_temp = 100000/uart_ovsr;
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@ -242,8 +242,8 @@ HalRuartGenBaudRateRtl8195a(
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pBaudSetting->Ovsr_adj = ovsr_adj;
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pBaudSetting->Ovsr_adj = ovsr_adj;
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pBaudSetting->Ovsr_adj_bits = adj_bits;
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pBaudSetting->Ovsr_adj_bits = adj_bits;
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DBG_UART_INFO("HalRuartGenBaudRateRtl8195a: BaudRate=%d ovsr=%d divisor=%d ovsr_adj=0x%x\r\n",
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DBG_UART_INFO("%sBaudRateRtl8195a: BaudRate:%d Divisor:%d Ovsr:%d Ovsr_ADj:0x%x\n",
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pBaudSetting->BaudRate, uart_ovsrs_actual, min_divisor, ovsr_adj);
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"HalRuartGen", pBaudSetting->BaudRate, min_divisor, uart_ovsrs_actual, ovsr_adj);
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return HAL_OK;
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return HAL_OK;
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}
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}
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@ -409,6 +409,8 @@ HalRuartSetBaudRateRtl8195a(
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// Verify again
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// Verify again
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cpu_clk = UART_SCLK;
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cpu_clk = UART_SCLK;
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baud_rate_temp = cpu_clk/Ovsr/Divisor;
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baud_rate_temp = cpu_clk/Ovsr/Divisor;
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// DBG_8195A("baud_rate_temp %d\n", baud_rate_temp);
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if (baud_rate_temp > pHalRuartAdapter->BaudRate) {
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if (baud_rate_temp > pHalRuartAdapter->BaudRate) {
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err = baud_rate_temp - pHalRuartAdapter->BaudRate;
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err = baud_rate_temp - pHalRuartAdapter->BaudRate;
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} else {
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} else {
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@ -478,8 +480,9 @@ HalRuartSetBaudRateRtl8195a(
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UartIndex = pHalRuartAdapter->UartIndex;
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UartIndex = pHalRuartAdapter->UartIndex;
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DBG_UART_INFO("HalRuartSetBaudRateRtl8195a: BaudRate:%d Divisor:%d Ovsr:%d Ovsr_ADj:0x%x\n",
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DBG_UART_INFO("%sBaudRateRtl8195a: BaudRate:%d Divisor:%d Ovsr:%d Ovsr_ADj:0x%x\n",
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pHalRuartAdapter->BaudRate, Divisor, Ovsr, Ovsr_adj);
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"HalRuartSet", pHalRuartAdapter->BaudRate, Divisor, Ovsr, Ovsr_adj);
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DBG_UART_INFO("RealBaudRate: %d\n", RuartSpeedSetting.sclk/Divisor/Ovsr);
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Dll = Divisor & 0xFF;
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Dll = Divisor & 0xFF;
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Dlm = (Divisor & 0xFF00) >> 8;
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Dlm = (Divisor & 0xFF00) >> 8;
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