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add boot (startup RAM only!)

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This commit is contained in:
pvvx 2017-03-04 13:24:48 +03:00
parent 6278f73e47
commit bf4fb5d560
30 changed files with 905 additions and 1509 deletions
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BIN
RTL00_SDKV35a/component/common/api/at_cmd/atcmd_sys.zip
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Binary file not shown.

2
RTL00_SDKV35a/component/common/api/wifi/wifi_conf.c
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@ -32,6 +32,8 @@ extern int inic_stop(void);
#define printf(...)
#endif
#define sscanf _sscanf
#define SHOW_PRIVATE_OUT 1 // =0 - off, = 1 On
/******************************************************

4
RTL00_SDKV35a/component/common/application/xmodem/uart_fw_update.c
View file

@ -62,8 +62,8 @@ extern const u8 ROM_IMG1_VALID_PATTEN[];
extern HAL_RUART_ADAPTER *pxmodem_uart_adp;
#ifdef CONFIG_GPIO_EN
extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
//extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
//extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
#endif
extern BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode);

2
RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_com_reg.h
View file

@ -763,7 +763,7 @@
// BW_OPMODE bits (Offset 0x603, 8bit)
//----------------------------------------------------------------------------
#define BW_OPMODE_20MHZ BIT2
#define BW_OPMODE_5G BIT1
#define BW_OPMODE_5G BIT1
//----------------------------------------------------------------------------
// CAM Config Setting (offset 0x680, 1 byte)

2
RTL00_SDKV35a/component/common/network/lwip/lwip_v1.4.1/src/core/dhcp.c
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@ -550,7 +550,7 @@ dhcp_handle_ack(struct netif *netif)
dhcp->offered_t2_rebind = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T2);
} else {
/* calculate safe periods for rebinding */
dhcp->offered_t2_rebind = (u32_t)(dhcp->offered_t0_lease * 0.875);
dhcp->offered_t2_rebind = dhcp->offered_t0_lease/2 + dhcp->offered_t0_lease /4 + dhcp->offered_t0_lease/8; // (u32_t)(dhcp->offered_t0_lease * 0.875);
}
/* (y)our internet address */

8
RTL00_SDKV35a/component/os/freertos/freertos_v8.1.2/Source/portable/MemMang/heap_5.c
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@ -164,7 +164,9 @@ static size_t xMinimumEverFreeBytesRemaining = 0;
member of an BlockLink_t structure is set then the block belongs to the
application. When the bit is free the block is still part of the free heap
space. */
static size_t xBlockAllocatedBit = 0;
//static size_t xBlockAllocatedBit = 0;
/* Work out the position of the top bit in a size_t variable. */
#define xBlockAllocatedBit (( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ))
/* Realtek test code start */
//TODO: remove section when combine BD and BF
@ -175,7 +177,7 @@ SRAM_HEAP_SECTION
unsigned char ucHeap[configTOTAL_HEAP_SIZE];
//extern void * __sdram_bss_end__;
extern void * __ram_heap1_start__, __ram_heap1_end__, __ram_heap2_start__, __sdram_data_start__;
//extern void * __ram_heap1_start__, __ram_heap1_end__, __ram_heap2_start__, __sdram_data_start__;
extern HeapRegion_t xHeapRegions[];
@ -622,8 +624,6 @@ const HeapRegion_t *pxHeapRegion;
/* Check something was actually defined before it is accessed. */
configASSERT( xTotalHeapSize );
/* Work out the position of the top bit in a size_t variable. */
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
}
void* pvPortReAlloc( void *pv, size_t xWantedSize )

2
RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/rtl_stdlib.h
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@ -19,7 +19,7 @@
//
#define strlen(str) prvStrLen((const u8*)str)
#define strcmp(str1, str2) prvStrCmp((const u8*)str1, (const u8*)str2)
#define sscanf(src, format...) //TODO: Strtoul(src,0,16) / Strtoul(src,0,10)
#define sscanf(src, format...) //TODO: Strtoul(src,0,16) / Strtoul(src,0,10)
#define strtok(str, delim) prvStrTok(str, delim)
#define strcpy(dst, src) prvStrCpy((u8 *)dst, (const u8*)src)
#define atoi(str) prvAtoi(str)

12
RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/system_8195a.c
View file

@ -36,8 +36,10 @@
---------------------------------------------------------------------------*/
#include "platform_autoconf.h"
#include "basic_types.h"
#include "rtl8195a.h"
#include "rtl_bios_data.h"
/*----------------------------------------------------------------------------
Define clocks
@ -46,7 +48,7 @@
#define __XTAL ( 5000000UL) /* Oscillator frequency */
//#define __SYSTEM_CLOCK (5*__XTAL)
#define __SYSTEM_CLOCK (200000000UL/6*5) // PLATFORM_CLOCK //
//#define __SYSTEM_CLOCK (200000000UL/6*5) // PLATFORM_CLOCK in platform_autoconf.h ! //
//extern u32 HalGetCpuClk(VOID);
@ -61,8 +63,8 @@ const u32 SysCpkClkTbl[]= {
};
#endif
unsigned int rand_x = 12345;
//extern unsigned int rand_x = 12345;
/*
u32 Rand2(void)
{
static unsigned int y = 362436;
@ -77,11 +79,11 @@ u32 Rand2(void)
return rand_x + y + z;
}
*/
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
uint32_t SystemCoreClock = PLATFORM_CLOCK; // __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
u32

2
RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/system_8195a.h
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@ -68,7 +68,7 @@ extern void SystemInit (void);
*/
extern void SystemCoreClockUpdate (void);
extern u32 SystemGetCpuClk(void);
extern u32 Rand2(void);
extern _LONG_CALL_ u32 Rand2(void);
#ifdef __cplusplus
}

170
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/loader.c
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@ -1,170 +0,0 @@
/*
* loader.c
*
* Created on: 17 нояб. 2016 г.
* Author: PVV
*/
#include "rtl8195a.h"
#include "diag.h"
#include "hal_spi_flash.h"
#include "hal_api.h"
#include "hal_platform.h"
#include "diag.h"
#include "hal_diag.h"
#include "rtl8195a_uart.h"
#include "rtl8195a/rtl8195a_peri_on.h"
#include "hal_peri_on.h"
#include "wifi_conf.h"
//-------------------------------------------------------------------------
// Data declarations
extern u32 * NewVectorTable; // LD: NewVectorTable = 0x10000000;
extern START_FUNC __image2_entry_func__;
extern u8 __image2_validate_code__;
extern u8 __image1_bss_start__, __image1_bss_end__;
extern u8 __rom_bss_start__, __rom_bss_end__;
extern u8 __bss_start__, __bss_end__;
typedef struct __RAM_IMG2_VALID_PATTEN__ {
char rtkwin[7];
u8 x[13];
} _RAM_IMG2_VALID_PATTEN, *_PRAM_IMG2_VALID_PATTEN;
const uint8_t __attribute__((section(".image1.validate.rodata"))) RAM_IMG1_VALID_PATTEN[8] =
{ 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff };
PRAM_FUNCTION_START_TABLE __attribute__((section(".data.pRamStartFun"))) pRamStartFun =
(PRAM_FUNCTION_START_TABLE) 0x10000BC8;
RAM_START_FUNCTION __attribute__((section(".start.ram.data.a"))) gRamStartFun =
{ PreProcessForVendor + 1 };
RAM_START_FUNCTION __attribute__((section(".start.ram.data.b"))) gRamPatchWAKE =
{ RtlBootToSram + 1 };
RAM_START_FUNCTION __attribute__((section(".start.ram.data.c"))) gRamPatchFun0 =
{ RtlBootToSram + 1 };
RAM_START_FUNCTION __attribute__((section(".start.ram.data.d"))) gRamPatchFun1 =
{ RtlBootToSram + 1 };
RAM_START_FUNCTION __attribute__((section(".start.ram.data.e"))) gRamPatchFun2 =
{ RtlBootToSram + 1 };
RAM_START_FUNCTION __attribute__((section(".image2.ram.data"))) gImage2EntryFun0 =
{ InfraStart + 1 };
_RAM_IMG2_VALID_PATTEN __attribute__((section(".image2.validate.rodata"))) RAM_IMG2_VALID_PATTEN =
{ { IMG2_SIGN_TXT }, { 0xff, 0, 1, 1, 0, 0x95, 0x81, 1, 1, 0, 0, 0, 0 } }; // "RTKWin"
HAL_GPIO_ADAPTER __attribute__((section(".hal.ram.data"))) gBoot_Gpio_Adapter;
void sub_100037EC(void)
{
HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0, (HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xFFFFF) | 0xE00000);
HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0, HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) | 2);
}
void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(void) {
u8 efuse0xF8_data;
// memset((void *)0x10000300, 0 , 0x10000BC8-0x10000300); ???
HalPinCtrlRtl8195A(JTAG, 0, 1);
HalDelayUs(1000);
HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
&efuse0xF8_data, L25EOUTVOLTAGE);
if(efuse0xF8_data == CHIP_ID_8711AF) { // ??
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | 0x200000) ; 1<<21
sub_100037EC();
}
int flash_enable = HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN;
}
void sub_1000441A(void)
{
ConfigDebugErr = -1;
ConfigDebugWarn = 0;
ConfigDebugInfo = 0;
}
//----- InfraStart
void __attribute__((section(".infra.ram.start"))) InfraStart(void) {
NewVectorTable[2] = HalNMIHandler_Patch;
sub_100022F0();
memset((void *)0x10000300, 0 , 0x10000BC8-0x10000300);
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL, HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_VENDOR_REG_EN);
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL, HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_SLPCK_VENDOR_REG_EN);
HalPinCtrlRtl8195A(JTAG, 0, 1);
HAL_PERI_ON_WRITE32(REG_GPIO_SHTDN_CTRL, 0x7FF);
HAL_PERI_ON_WRITE32(REG_CPU_PERIPHERAL_CTRL, HAL_PERI_ON_READ32(REG_CPU_PERIPHERAL_CTRL) | BIT_SPI_FLSH_PIN_EN);
HAL_PERI_ON_WRITE32(REG_CPU_PERIPHERAL_CTRL, HAL_SYHAL_PERI_ON_READ32S_CTRL_READ32(REG_CPU_PERIPHERAL_CTRL) | BIT_LOG_UART_PIN_EN);
VectorTableInitRtl8195A(0x1FFFFFFC); // 0x1FFFFFFC StackP
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_FLASH_EN) ;
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL, HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_FLASH_EN);
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL, HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_SLPCK_FLASH_EN);
HalPinCtrlRtl8195A(SPI_FLASH, 0, 1);
sub_1000367C();
HAL_SYS_CTRL_WRITE32(REG_SYS_CLK_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) & 0x8F);
sub_1000441A();
HAL_UART_READ32(UART_REV_BUF_OFF);
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (~BIT_SOC_LOG_UART_EN));
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_LOG_UART_EN);
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL, HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_LOG_UART_EN);
LOG_UART_ADAPTER UartAdapter;
UartAdapter.BaudRate = UART_BAUD_RATE_38400;
UartAdapter.FIFOControl = 0xC1;
UartAdapter.IntEnReg = 0x00;
UartAdapter.Parity = UART_PARITY_DISABLE;
UartAdapter.Stop = UART_STOP_1BIT;
UartAdapter.DataLength = UART_DATA_LEN_8BIT;
HalLogUartInit(UartAdapter); // sub_10004434(38400, 193, 0, v14);
TIMER_ADAPTER tim_adapter;
tim_adapter.IrqHandle.IrqFun = &UartLogIrqHandle;
tim_adapter.IrqHandle.IrqNum = UART_LOG_IRQ;
tim_adapter.IrqHandle.Data = 0;
tim_adapter.IrqHandle.Priority = 5;
VectorIrqRegisterRtl8195A(&tim_adapter.IrqHandle);
UartAdapter.IntEnReg = 0x05;
HalLogUartInit(UartAdapter);
HAL_PERI_ON_WRITE32(REG_PON_ISO_CTRL, 3); // ? USB ?
HAL_PERI_ON_WRITE32(REG_OSC32K_CTRL, HAL_PERI_ON_READ32(REG_OSC32K_CTRL) | BIT_32K_POW_CKGEN_EN);
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_GTIMER_EN);
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL, HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_TIMER_EN);
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL, HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_SLPCK_TIMER_EN);
tim_adapter.TimerIrqPriority = 0;
tim_adapter.TimerLoadValueUs = 0;
tim_adapter.TimerMode = FREE_RUN_MODE;
tim_adapter.IrqDis = 1;
tim_adapter.TimerId = 1;
HalTimerInitRtl8195a((PTIMER_ADAPTER) &tim_adapter);
SpicInitRtl8195A(1, 1); // InitBaudRate 1, SpicBitMode 1
SpicFlashInitRtl8195A(1); // SpicBitMode 1
DBG_8195A("===== Enter Image 1.5 ====\nImg2 Sign: %s, InfaStart @ 0x%08x\n",
&__image2_validate_code__, __image2_entry_func__);
HAL_SYS_CTRL_WRITE32(REG_SYS_CLK_CTRL0,
HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL0) | BIT4);
if (HalCommonInit() != HAL_OK) DBG_8195A("Hal Common Init Failed.\n");
DBG_8195A("===== Enter Image 2 ====\n");
ShowRamBuildInfo(); // app_start.c: VOID ShowRamBuildInfo(VOID)
memset(&__bss_start__, 0, &__bss_end__ - &__bss_start__);
int clk = (HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL0)
>> BIT_SHIFT_PESOC_OCP_CPU_CK_SEL) & 1;
if (clk) {
SpicNVMCalLoadAll();
SpicReadIDRtl8195A();
}
SystemCoreClockUpdate();
SYSPlatformInit();
En32KCalibration();
InitSoCPM();
SDIO_Device_Off();
VectorTableInitForOSRtl8195A(&vPortSVCHandler, &xPortPendSVHandler,
&xPortSysTickHandler);
if (clk) SpicDisableRtl8195A();
_AppStart();
}

157
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_bios_data.c Normal file
View file

@ -0,0 +1,157 @@
/*
* rtl_bios_data.c
*
* Created on: 12/02/2017
* Author: pvvx
*
* This variables declared in ROM code!
* Variables use fixed addresses!
* (see *.ld script)
*/
#include "rtl_bios_data.h"
/* ROM + startup.c */
RAM_DEDECATED_VECTOR_TABLE_SECTION IRQ_FUN NewVectorTable[64]; // 10000000
RAM_USER_IRQ_FUN_TABLE_SECTION IRQ_FUN UserIrqFunTable[64]; // 10000100
RAM_USER_IRQ_DATA_TABLE_SECTION u32 UserIrqDataTable[64]; // 10000200
/* ROM + ... */
HAL_RAM_BSS_SECTION PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter; // 10000354
/* ROM + hal_ssi.h */
HAL_RAM_BSS_SECTION u32 SSI_DBG_CONFIG; // 10000350
/* ROM + hal_timer.h & .. */
HAL_RAM_BSS_SECTION u32 gTimerRecord; // 1000034C
HAL_RAM_BSS_SECTION u16 GPIOState[11]; // 10000334
HAL_RAM_BSS_SECTION HAL_TIMER_OP HalTimerOp; // 10000318
/* ROM + diag.h */
HAL_RAM_BSS_SECTION u32 ConfigDebugErr; // 10000314
HAL_RAM_BSS_SECTION u32 ConfigDebugInfo; // 10000310
HAL_RAM_BSS_SECTION u32 ConfigDebugWarn; // 1000030C
HAL_RAM_BSS_SECTION u32 CfgSysDebugErr; // 10000308
HAL_RAM_BSS_SECTION u32 CfgSysDebugInfo; // 10000304
HAL_RAM_BSS_SECTION u32 CfgSysDebugWarn; // 10000300
/* ROM + rtl8195a_timer.c */
SECTION_RAM_TIMER2TO7_VECTOR_TABLE IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM]; // 10000358 Timer2To7VectorTable[6] !
/* ROM + Rand() */
INFRA_RAM_BSS_SECTION u32 _rand_z4, _rand_z3, _rand_z2, _rand_z1, _rand_first; // 10000370..
/* ROM + RTL_CONSOL */
MON_RAM_BSS_SECTION u8 *ArgvArray[MAX_ARGV]; // 100006AC *ArgvArray[10] !
MON_RAM_BSS_SECTION u8 UartLogHistoryBuf[UART_LOG_HISTORY_LEN][UART_LOG_CMD_BUFLEN]; // 10000430 UartLogHistoryBuf[5][127] !
MON_RAM_BSS_SECTION volatile UART_LOG_CTL UartLogCtl; // 10000408
MON_RAM_BSS_SECTION UART_LOG_BUF UartLogBuf; // 10000388
MON_RAM_BSS_SECTION volatile UART_LOG_CTL *pUartLogCtl; // 10000384
/* ROM + LIB C */
LIBC_RAM_BSS_SECTION int __rtl_errno; // 10000bc4 __rtl_sread_v1_00(), __rtl_write_v1_00(), __rtl_lseek_v1_00(), __rtl_close_v1_00(), __rtl_sbrk_v1_00()..
LIBC_RAM_BSS_SECTION struct mallinfo __rtl_malloc_current_mallinfo; // 10000b9c __rom_mallocr_init_v1_00()
LIBC_RAM_BSS_SECTION u32 __rtl_malloc_max_total_mem; // 10000b98 __rom_mallocr_init_v1_00()
LIBC_RAM_BSS_SECTION u32 __rtl_malloc_max_sbrked_mem; // 10000b94 __rom_mallocr_init_v1_00()
LIBC_RAM_BSS_SECTION u8 * __rtl_malloc_sbrk_base; // 10000b90 __rom_mallocr_init_v1_00()
LIBC_RAM_BSS_SECTION u32 __rtl_malloc_top_pad; // 10000b8c __rom_mallocr_init_v1_00()
LIBC_RAM_BSS_SECTION u32 __rtl_malloc_trim_threshold; // 10000b88 __rom_mallocr_init_v1_00()
LIBC_RAM_BSS_SECTION struct malloc_chunk *__rtl_malloc_av_[258]; // 0x10000780 __rom_mallocr_init_v1_00(), _rtl_free_r_v1_00()..
LIBC_RAM_BSS_SECTION __attribute__((aligned(0x10))) struct _rom_libgloss_ram_map rom_libgloss_ram_map; // 10000760
// 10000BA0..10000BC0: 9 x dw __rom_mallocr_init_v1_00()
/* ROM: ROM_odm_FalseAlarmCounterStatistics() + .. */
#define _WLAN_RAM_MAP_SECTION __attribute__((__section__(".ram.rom.wlanmap")))
_WLAN_RAM_MAP_SECTION CFO_TRACKING DM_CfoTrack; // 10000738
_WLAN_RAM_MAP_SECTION ROM_INFO ROMInfo; // 10000720
_WLAN_RAM_MAP_SECTION __attribute__((aligned(0x10))) FALSE_ALARM_STATISTICS FalseAlmCnt; // 100006E0
WLAN_RAM_MAP_SECTION struct _rom_wlan_ram_map rom_wlan_ram_map; // 100006D4
#ifndef PRESENT_IMAGE1
/* IMAGE1 HEAD */
START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__;
/*
START_RAM_FUN_A_SECTION RAM_START_FUNCTION gRamStartFun; // 10000bc8 = { PreProcessForVendor + 1 };
START_RAM_FUN_B_SECTION RAM_START_FUNCTION gRamPatchWAKE; // 10000bcc = { RtlBootToSram + 1 };
START_RAM_FUN_C_SECTION RAM_START_FUNCTION gRamPatchFun0; // 10000bd0 = { RtlBootToSram + 1 };
START_RAM_FUN_D_SECTION RAM_START_FUNCTION gRamPatchFun1; // 10000bd4 = { RtlBootToSram + 1 };
START_RAM_FUN_E_SECTION RAM_START_FUNCTION gRamPatchFun2; // 10000bd8 = { RtlBootToSram + 1 };
*/
#endif
IMAGE1_VALID_PATTEN_SECTION uint8 RAM_IMG1_VALID_PATTEN[8] = IMG1_VALID_PATTEN_INIT(); // 10000bdc
//#ifdef NOT_USE_LIBROM_A
/* ROM + hal_sdr_controller.c */
//HAL_FLASH_DATA_SECTION
//SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // SpicInitParaAllClk[3][6] !
/* ROM + hal_sdr_controller.c */
HAL_CUT_B_RAM_DATA_SECTION DRAM_INFO SdrDramDev = DRAM_INFO_INIT(); // 10001c4c
HAL_CUT_B_RAM_DATA_SECTION DRAM_MODE_REG_INFO SdrDramModeReg = DRAM_MODE_REG_INFO_INIT(); // 10001c30
HAL_CUT_B_RAM_DATA_SECTION DRAM_TIMING_INFO SdrDramTiming = DRAM_TIMING_INFO_INIT(); // 10001bfc
HAL_CUT_B_RAM_DATA_SECTION DRAM_DEVICE_INFO SdrDramInfo = DRAM_DEVICE_INFO_INIT(); // 10001be8
HAL_CUT_B_RAM_DATA_SECTION u32 AvaWds[2][REC_NUM]; // 10000be8
/* ROM + hal_sdr_controller.c: Sdr_Rand2() */
HAL_CUT_B_RAM_DATA_SECTION u32 rand_x = 123456789; // 10000be4
#define RTL_REENT_INIT(var) \
{ 0, \
&(var).__sf[0], \
&(var).__sf[1], \
&(var).__sf[2], \
0, \
"", \
0, \
0x0437DC, \
0, \
_NULL, \
_NULL, \
0, \
_NULL, \
_NULL, \
0, \
_NULL, \
{ \
{ \
0, \
_NULL, \
"", \
{0, 0, 0, 0, 0, 0, 0, 0, 0}, \
0, \
1, \
{ \
{_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, \
{_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, \
_RAND48_ADD \
}, \
{0, {0}}, \
{0, {0}}, \
{0, {0}}, \
"", \
"", \
0, \
{0, {0}}, \
{0, {0}}, \
{0, {0}}, \
{0, {0}}, \
{0, {0}} \
} \
}, \
_REENT_INIT_ATEXIT \
_NULL, \
{_NULL, 0, _NULL} \
}
// ROM: _rtl_impure_ptr + impure_reent in lib_rom.a ".hal.ram.data"
__attribute__((section(".libc.reent"))) struct _reent impure_reent = RTL_REENT_INIT(impure_reent); // 10001c60
__attribute__((section(".libc.reent"))) struct _reent * _rtl_impure_ptr = { &impure_reent }; // 10001c68
/* ROM ? */
__attribute__((__section__(".rom.unc.data"))) u32 _rom_unc_data[9]; // 100020e8
/* ROM + hal_sdr_controller.c: Sdr_Rand2() */
__attribute__((__section__(".sdr.rand2.data"))) u32 _sdr_rnd2_c = 7654321, _sdr_rnd2_z = 521288629, _sdr_rnd2_y = 362436;
// 100020BC, 100020B8, 100020B4
HAL_GPIO_ADAPTER PINMUX_RAM_DATA_SECTION gBoot_Gpio_Adapter; // 100020C0 [300=0x12c]
// SPIC_INIT_PARA HAL_FLASH_DATA_SECTION SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90]
#ifndef PRESENT_IMAGE2
IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0; //= { InfraStart + 1 };
#endif
IMAGE2_VALID_PATTEN_SECTION _RAM_IMG2_VALID_PATTEN RAM_IMG2_VALID_PATTEN = RAM_IMG2_VALID_PATTEN_INIT();

128
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c Normal file
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@ -0,0 +1,128 @@
/*
* (SRAM) Debug BootLoader
* Created on: 12/02/2017
* Author: pvvx
*/
#include "platform_autoconf.h"
#include "rtl_bios_data.h"
#include "diag.h"
#include "rtl8195a/rtl8195a_sys_on.h"
//-------------------------------------------------------------------------
// Data declarations
//extern u32 STACK_TOP;
//extern volatile UART_LOG_CTL * pUartLogCtl;
#define DEFAULT_BAUDRATE UART_BAUD_RATE_38400
#define BOOT_RAM_TEXT_SECTION __attribute__((section(".ram.boot.text")))
//#define BOOT_RAM_RODATA_SECTION __attribute__((section(".ram.boot.rodata")))
//#define BOOT_RAM_DATA_SECTION __attribute__((section(".ram.boot.data")))
//#define BOOT_RAM_BSS_SECTION __attribute__((section(".ram.boot.bss")))
//-------------------------------------------------------------------------
// Function declarations
LOCAL void RtlBootToSram(void); // image1
LOCAL void EnterImage15(void); // image1
LOCAL void JtagOn(void); // image1
extern _LONG_CALL_ VOID HalCpuClkConfig(unsigned char CpuType);
extern _LONG_CALL_ VOID VectorTableInitRtl8195A(u32 StackP);
extern _LONG_CALL_ VOID HalInitPlatformLogUartV02(VOID);
extern _LONG_CALL_ VOID HalInitPlatformTimerV02(VOID);
//#pragma arm section code = ".ram.boot.text";
//#pragma arm section rodata = ".ram.boot.rodata", rwdata = ".ram.boot.data", zidata = ".ram.boot.bss";
typedef void (*START_FUNC)(void);
PRAM_FUNCTION_START_TABLE __attribute__((section(".data.pRamStartFun"))) pRamStartFun =
(PRAM_FUNCTION_START_TABLE) 0x10000BC8;
/* Start table: */
START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__ = {
RtlBootToSram + 1, // StartFun(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 )
RtlBootToSram + 1, // PatchWAKE(), Run if ( v40000210 & 0x20000000 )
RtlBootToSram + 1, //- PatchFun0(), Run if ( v40000210 & 0x10000000 )
RtlBootToSram + 1, //+ PatchFun1(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
EnterImage15 + 1}; // PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 )
/* Set Debug Flags */
LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() {
#if CONFIG_DEBUG_LOG > 2
CfgSysDebugWarn = -1;
CfgSysDebugInfo = -1;
CfgSysDebugErr = -1;
ConfigDebugWarn = -1;
ConfigDebugInfo = -1;
ConfigDebugErr = -1;
#elif CONFIG_DEBUG_LOG > 1
CfgSysDebugWarn = -1;
// CfgSysDebugInfo = 0;
CfgSysDebugErr = -1;
ConfigDebugWarn = -1;
// ConfigDebugInfo = 0;
ConfigDebugErr = -1;
#elif CONFIG_DEBUG_LOG > 0
// CfgSysDebugWarn = 0;
// CfgSysDebugInfo = 0;
CfgSysDebugErr = -1;
// ConfigDebugWarn = 0;
// ConfigDebugInfo = 0;
ConfigDebugErr = -1;
#else
// CfgSysDebugWarn = 0;
// CfgSysDebugInfo = 0;
// CfgSysDebugErr = 0;
// ConfigDebugWarn = 0;
// ConfigDebugInfo = 0;
// ConfigDebugErr = 0;
#endif
}
/* RTL Console ROM */
LOCAL void BOOT_RAM_TEXT_SECTION RtlConsolRam(void) {
// DiagPrintf("\r\nRTL Console ROM\r\n");
pUartLogCtl->pTmpLogBuf->UARTLogBuf[0] = '?';
pUartLogCtl->pTmpLogBuf->BufCount = 1;
pUartLogCtl->ExecuteCmd = 1;
RtlConsolTaskRom(pUartLogCtl);
}
/* JTAG On */
LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) {
ACTCK_VENDOR_CCTRL(ON);
SLPCK_VENDOR_CCTRL(ON);
HalPinCtrlRtl8195A(JTAG, 0, 1);
}
/* Enter Image 1.5 */
LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(void) {
SetDebugFlgs();
DBG_8195A("\rCPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
DBG_8195A("==!== Enter Image 1.5 ====\nImg2 Sign: %s, InfaStart @ 0x%08x\r\n",
&__image2_validate_code__, __image2_entry_func__);
if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) {
DBG_MISC_ERR("Invalid Image2 Signature!\n");
RtlConsolRam();
}
__image2_entry_func__();
}
/* RtlBootToSram */
LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToSram(void) {
JtagOn(); /* JTAG On */
_memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__);
__asm__ __volatile__ ("cpsid f\n");
HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) & ( ~BIT_SYS_SYSPLL_DIV5_3));
HalCpuClkConfig(2); // 41.666666 MHz
// HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) | BIT_SYS_SYSPLL_DIV5_3); // 50.000 MHz
VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC
HalInitPlatformLogUartV02();
HalInitPlatformTimerV02();
__asm__ __volatile__ ("cpsie f\n");
SpicInitRtl8195AV02(1, 0); // StartupSpicBaudRate InitBaudRate 1, SpicBitMode 1 StartupSpicBitMode
// HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & 0x1FFFFF); // Clear debug flags
EnterImage15();
}

788
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c
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@ -1,7 +1,7 @@
/*
* BootLoader
* startup.o sdk-ameba-rtl8710af-v3.5a_without_NDA_GCC_V1.0.0
* pvvx 2016
* StartUp SDK
* Created on: 02/03/2017
* Author: pvvx
*/
#include "rtl8195a.h"
@ -14,46 +14,17 @@
#include "rtl8195a_uart.h"
#include "rtl8195a/rtl8195a_peri_on.h"
#include "hal_peri_on.h"
#include "rtl_bios_data.h"
#include "wifi_conf.h"
#include "rtl_consol.h"
#ifndef USE_SRC_ONLY_BOOT
#define USE_SRC_ONLY_BOOT 0
#endif
#if USE_SRC_ONLY_BOOT
#define rtl_memset _memset
#define rtl_strcmp _strcmp
#define rtl_memcpy _memcpy
#endif
#define VREG32(addr) (*((volatile u32*)(addr)))
typedef void (*START_FUNC)(void);
#define DEFAULT_BAUDRATE UART_BAUD_RATE_38400
#define StartupSpicBitMode SpicDualBitMode // SpicOneBitMode
#define StartupSpicBaudRate 0
//#define INFRA_START_SECTION __attribute__((section(".infra.ram.start")))
//-------------------------------------------------------------------------
// Function declarations
void PreProcessForVendor(void); // image1
void RtlBootToSram(void); // image1
u32 StartupHalLogUartInit(u32 uart_irq); // image1
void StartupHalInitPlatformLogUart(void); // image1
int IsForceLoadDefaultImg2(void); // image1
void StartupHalSpicInit(int InitBaudRate); // image1
int _GetChipId(void); // image1
void RtlConsolRam(void); // image1
extern VOID UartLogIrqHandle(VOID * Data); // in ROM
extern int RtlConsolRom(int); // in ROM
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
extern VOID SpicUserReadRtl8195A(IN u32 Length, IN u32 addr, IN u8 * data,
IN u8 BitMode);
#if !USE_SRC_ONLY_BOOT
void InfraStart(void);
extern void HalWdgIntrHandle(void);
extern int wifi_off(void); // in wifi_conf.c
extern void xPortPendSVHandler(void);
extern void xPortSysTickHandler(void);
extern void vPortSVCHandler(void);
@ -62,587 +33,61 @@ void HalNMIHandler_Patch(void);
void SDIO_Device_Off(void);
void VectorTableOverrideRtl8195A(u32 StackP);
void SYSPlatformInit(void);
void HalHardFaultHandler_Patch_c(u32 HardDefaultArg);
void __HalReInitPlatformLogUart(void);
void _ReloadImg(void);
void _ReloadImg_user_define(void);
void _CPUResetHandler(void);
void _CPUReset(void);
void HalHardFaultHandler_user_define(u32 HardDefaultArg);
#endif
//-------------------------------------------------------------------------
// Data declarations
extern START_FUNC __image2_entry_func__;
extern u8 __image2_validate_code__;
extern u8 __image1_bss_start__, __image1_bss_end__;
extern u8 __rom_bss_start__, __rom_bss_end__;
//extern u32 STACK_TOP;
#define STACK_TOP 0x1FFFFFFC
#if !USE_SRC_ONLY_BOOT
extern u32 * NewVectorTable; // LD: NewVectorTable = 0x10000000;
extern u8 __bss_start__, __bss_end__;
#endif
//extern volatile UART_LOG_CTL * pUartLogCtl;
extern int UartLogCmdExecute(volatile u8 *);
/*
typedef struct __RAM_IMG2_VALID_PATTEN__ {
char rtkwin[7];
u8 x[13];
} _RAM_IMG2_VALID_PATTEN, *_PRAM_IMG2_VALID_PATTEN;
*/
const uint8_t IMAGE1_VALID_PATTEN_SECTION RAM_IMG1_VALID_PATTEN[8] =
{ 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff };
IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 = { InfraStart
+ 1 };
PRAM_FUNCTION_START_TABLE __attribute__((section(".data.pRamStartFun"))) pRamStartFun =
(PRAM_FUNCTION_START_TABLE) 0x10000BC8;
// HAL_GPIO_ADAPTER PINMUX_RAM_DATA_SECTION gBoot_Gpio_Adapter;
#include <reent.h>
struct _reent __attribute__((section(".libc.reent"))) impure_reent = _REENT_INIT(impure_reent);
//struct _reent * __attribute__((section(".libc.reent"))) _rtl_impure_ptr = { &impure_data };
//struct _reent * __attribute__((at(0x1098))) __attribute__((section(".libc.reent"))) _rtl_impure_ptr = { &impure_data };
struct _reent * __attribute__((at(0x10001c60))) __attribute__((section(".libc.reent"))) _rtl_impure_ptr = { &impure_reent };
/* ROM */
MON_RAM_BSS_SECTION
volatile UART_LOG_CTL *pUartLogCtl;
MON_RAM_BSS_SECTION
UART_LOG_BUF UartLogBuf;
MON_RAM_BSS_SECTION
volatile UART_LOG_CTL UartLogCtl;
MON_RAM_BSS_SECTION
u8 *ArgvArray[MAX_ARGV]; // *ArgvArray[10] !
MON_RAM_BSS_SECTION
u8 UartLogHistoryBuf[UART_LOG_HISTORY_LEN][UART_LOG_CMD_BUFLEN]; // UartLogHistoryBuf[5][127] !
RAM_START_FUNCTION START_RAM_FUN_A_SECTION gRamStartFun =
{ PreProcessForVendor + 1 };
RAM_START_FUNCTION START_RAM_FUN_B_SECTION gRamPatchWAKE =
{ RtlBootToSram + 1 };
RAM_START_FUNCTION START_RAM_FUN_C_SECTION gRamPatchFun0 =
{ RtlBootToSram + 1 };
RAM_START_FUNCTION START_RAM_FUN_D_SECTION gRamPatchFun1 =
{ RtlBootToSram + 1 };
RAM_START_FUNCTION START_RAM_FUN_E_SECTION gRamPatchFun2 =
{ RtlBootToSram + 1 };
#if !USE_SRC_ONLY_BOOT
RAM_START_FUNCTION IMAGE2_START_RAM_FUN_SECTION gImage2EntryFun0 =
{ InfraStart + 1 };
#else
RAM_START_FUNCTION IMAGE2_START_RAM_FUN_SECTION gImage2EntryFun0 =
{ 0x100 };
#endif // !USE_SRC_ONLY_BOOT
_RAM_IMG2_VALID_PATTEN IMAGE2_VALID_PATTEN_SECTION RAM_IMG2_VALID_PATTEN =
{ { IMG2_SIGN_TXT }, { 0xff, 0, 1, 1, 0, 0x95, 0x81, 1, 1, 0, 0, 0, 0 } }; // "RTKWin"
HAL_GPIO_ADAPTER PINMUX_RAM_DATA_SECTION gBoot_Gpio_Adapter;
#pragma arm section code = ".hal.ram.text"
#pragma arm section rodata = ".hal.ram.rodata", rwdata = ".hal.ram.data", zidata = ".hal.ram.bss"
#if !USE_SRC_ONLY_BOOT
//----- HalNMIHandler_Patch
void HalNMIHandler_Patch(void) {
DBG_8195A_HAL("%s:NMI Error!\n", __func__);
if ( HAL_READ32(VENDOR_REG_BASE, 0) < 0)
HalWdgIntrHandle(); // ROM: HalWdgIntrHandle = 0x3485;
}
#endif // !USE_SRC_ONLY_BOOT
void __attribute__((section(".hal.ram.text"))) SetDebugFlgs() {
#if CONFIG_DEBUG_LOG > 2
ConfigDebugErr = -1;
ConfigDebugWarn = -1;
ConfigDebugInfo = -1;
#elif CONFIG_DEBUG_LOG > 1
ConfigDebugErr = -1;
ConfigDebugWarn = -1;
ConfigDebugInfo = 0;
#elif CONFIG_DEBUG_LOG > 0
ConfigDebugErr = -1;
ConfigDebugWarn = 0;
ConfigDebugInfo = 0;
#else
ConfigDebugErr = 0;
ConfigDebugWarn = 0;
ConfigDebugInfo = 0;
#endif
}
void __attribute__((section(".hal.ram.text"))) InitSpic(void)
{
VREG32(0x40006000) = 0x01000300;
VREG32(0x40006004) = 0x1;
VREG32(0x400060E0) = 0x0B;
VREG32(0x400060E4) = 0x3B;
VREG32(0x400060E8) = 0x3B;
VREG32(0x400060EC) = 0x6B;
VREG32(0x400060F0) = 0xEB;
VREG32(0x400060F4) = 0x02;
VREG32(0x400060F8) = 0xA2;
VREG32(0x400060FC) = 0xA2;
VREG32(0x40006100) = 0x32;
VREG32(0x40006104) = 0x38;
VREG32(0x40006108) = 0x06;
VREG32(0x4000610C) = 0x05;
VREG32(0x40006110) = 0x51;
VREG32(0x40006114) = 0x01;
VREG32(0x40006118) = 0x03;
VREG32(0x4000611C) = 0x20030013;
VREG32(0x40006120) = 0x202;
VREG32(0x40006124) = 0x0E;
}
//----- StartupHalLogUartInit
u32 __attribute__((section(".hal.ram.text"))) StartupHalLogUartInit(u32 uart_irq) {
HAL_UART_WRITE32(UART_DLH_OFF, 0);
u32 SysClock = (HalGetCpuClk() >> 2);
u32 SampleRate = (16 * DEFAULT_BAUDRATE);
u32 Divisor = SysClock / SampleRate;
u32 Remaind = ((SysClock * 10) / SampleRate) - (Divisor * 10);
if (Remaind > 4) Divisor++;
// set DLAB bit to 1
// HAL_UART_WRITE32(UART_INTERRUPT_EN_REG_OFF, 0);
HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, RUART_LINE_CTL_REG_DLAB_ENABLE);
HAL_UART_WRITE32(UART_DLL_OFF, Divisor & 0xff);
HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, 3);
HAL_UART_WRITE32(UART_FIFO_CTL_REG_OFF, FIFO_CTL_DEFAULT_WITH_FIFO);
HAL_UART_WRITE32(UART_INTERRUPT_EN_REG_OFF, uart_irq);
if (uart_irq) {
// Enable Peripheral_IRQ Setting for Log_Uart
HAL_WRITE32(VENDOR_REG_BASE, PERIPHERAL_IRQ_EN, 0x1000000);
// Cortex-M3 SCB->AIRCR
HAL_WRITE32(0xE000ED00, 0x0C,
(HAL_READ32(0xE000ED00, 0x0C) & 0x0F8FF) | 0x5FA0300);
HAL_WRITE8(0xE000E100, 0x313, 0xE0); // HAL_WRITE8(0xE000E100, 0x313, 0xE0);
HAL_WRITE32(0xE000E100, 0, 0x80000); // NVIC enable external interrupt[?] ?
}
return 0;
}
//----- StartupHalInitPlatformLogUart
void __attribute__((section(".hal.ram.text"))) StartupHalInitPlatformLogUart(
void) {
HAL_UART_READ32(UART_REV_BUF_OFF);
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (~(BIT_SOC_LOG_UART_EN))); // 40000210 &= 0xFFFFEFFF; // ~(1<<12)
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_LOG_UART_EN); // 40000210 |= 0x1000u;
ACTCK_LOG_UART_CCTRL(ON); // 40000230 |= 0x1000u;
StartupHalLogUartInit(IER_ERBFI | IER_ELSI);
}
void __attribute__((section(".hal.ram.text"))) RtlConsolRam(void)
{
// __asm__ __volatile__ ("cpsid f\n");
// HalCpuClkConfig(0); // 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
// ConfigDebugErr = -1;
// VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC);
// HalInitPlatformLogUartV02();
// HalReInitPlatformLogUartV02();
// HalInitPlatformTimerV02();
__asm__ __volatile__ ("cpsie f\n");
DiagPrintf("\r\nRTL Console ROM: Start - press 'ESC' key, Help '?'\r\n");
while(!pUartLogCtl->ExecuteEsc);
pUartLogCtl->EscSTS = 0;
pUartLogCtl->BootRdy = 1;
DiagPrintf("\r<RTL>");
while(1) {
while(!pUartLogCtl->ExecuteCmd);
UartLogCmdExecute(pUartLogCtl);
DiagPrintf("\r<RTL>");
pUartLogCtl->ExecuteCmd = 0;
}
}
//----- RtlBootToSram
void __attribute__((section(".hal.ram.text"))) RtlBootToSram(void) {
TIMER_ADAPTER tim_adapter;
/* JTAG On */
ACTCK_VENDOR_CCTRL(ON);
SLPCK_VENDOR_CCTRL(ON);
HalPinCtrlRtl8195A(JTAG, 0, 1);
memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__);
/* Flash & LogUart On */
HAL_PERI_ON_WRITE32(REG_GPIO_SHTDN_CTRL, 0x7FF);
SPI_FLASH_PIN_FCTRL(ON);
HAL_PERI_ON_WRITE32(REG_CPU_PERIPHERAL_CTRL,
HAL_PERI_ON_READ32(REG_CPU_PERIPHERAL_CTRL) | BIT_SPI_FLSH_PIN_EN); // 400002C0 |= 0x1u;
HAL_PERI_ON_WRITE32(REG_CPU_PERIPHERAL_CTRL,
HAL_PERI_ON_READ32(REG_CPU_PERIPHERAL_CTRL) | BIT_LOG_UART_PIN_EN); // 400002C0 |= 0x100000u;
VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_FLASH_EN); // 40000210 |= 0x10u;
ACTCK_FLASH_CCTRL(ON);
SLPCK_FLASH_CCTRL(ON);
HalPinCtrlRtl8195A(SPI_FLASH, 0, 1);
SpicNVMCalLoadAll();
HAL_SYS_CTRL_WRITE32(REG_SYS_CLK_CTRL1,
HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) & 0x8F); // VREG32(0x40000014) &= 0x8F;
SetDebugFlgs();
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (~(BIT_SOC_LOG_UART_EN))); // 40000210 &= 0xFFFFEFFF; // ~(1<<12)
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_LOG_UART_EN); // 40000210 |= 0x1000u;
ACTCK_LOG_UART_CCTRL(ON);
// SLPCK_LOG_UART_CCTRL(ON);
tim_adapter.IrqHandle.IrqFun = &UartLogIrqHandle;
tim_adapter.IrqHandle.IrqNum = UART_LOG_IRQ;
tim_adapter.IrqHandle.Data = 0;
tim_adapter.IrqHandle.Priority = 5;
StartupHalLogUartInit(0);
VectorIrqRegisterRtl8195A(&tim_adapter.IrqHandle);
StartupHalLogUartInit(IER_ERBFI | IER_ELSI);
HAL_PERI_ON_WRITE32(REG_PON_ISO_CTRL, 3); // VREG32(0x40000204) = 3;
HAL_PERI_ON_WRITE32(REG_OSC32K_CTRL,
HAL_PERI_ON_READ32(REG_OSC32K_CTRL) | BIT_32K_POW_CKGEN_EN); // VREG32(0x40000270) |= 1u;
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_GTIMER_EN); // VREG32(0x40000210) |= 0x10000u;
ACTCK_TIMER_CCTRL(ON);
SLPCK_TIMER_CCTRL(ON);
tim_adapter.TimerIrqPriority = 0;
tim_adapter.TimerLoadValueUs = 0;
tim_adapter.TimerMode = FREE_RUN_MODE;
tim_adapter.IrqDis = 1;
tim_adapter.TimerId = 1;
HalTimerInitRtl8195a((PTIMER_ADAPTER) &tim_adapter);
SpicInitRtl8195A(1, StartupSpicBitMode); // StartupSpicBaudRate InitBaudRate 1, SpicBitMode 1 StartupSpicBitMode
SpicFlashInitRtl8195A(StartupSpicBitMode); // SpicBitMode 1 StartupSpicBitMode
DBG_8195A("==*== Enter Image 1.5 ====\nImg2 Sign: %s, InfaStart @ 0x%08x\n",
&__image2_validate_code__, __image2_entry_func__);
if (strcmp((const char * )&__image2_validate_code__, IMG2_SIGN_TXT)) {
DBG_MISC_ERR("Invalid Image2 Signature!\n");
RtlConsolRam();
}
// InitSpic();
__image2_entry_func__();
}
//----- SYSCpuClkConfig
void __attribute__((section(".hal.ram.text"))) SYSCpuClkConfig(int ChipID, int SysCpuClk) {
int flg = 0;
DBG_SPIF_INFO("SYSCpuClkConfig(0x%x)\n", SysCpuClk);
if(HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) {
SpicWaitWipRtl8195A(); //_SpicWaitWipDoneRefinedRtl8195A(); ???
flg = 1;
}
// if (ChipID == CHIP_ID_8710AF && (!SysCpuClk)) SysCpuClk = 1;
HalCpuClkConfig(SysCpuClk);
HalDelayUs(1000);
StartupHalInitPlatformLogUart();
if (flg) {
SpicOneBitCalibrationRtl8195A(SysCpuClk); // extern u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk);
/*
// Disable SPI_FLASH User Mode
HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0);
HAL_SPI_WRITE32(REG_SPIC_VALID_CMD,
(HAL_SPI_READ32(REG_SPIC_VALID_CMD)|(FLASH_VLD_DUAL_CMDS))); */
SpicCalibrationRtl8195A(StartupSpicBitMode, 0);
}
}
//----- IsForceLoadDefaultImg2
int __attribute__((section(".hal.ram.text"))) IsForceLoadDefaultImg2(void) {
u8 gpio_pin[4];
HAL_GPIO_PIN GPIO_Pin;
HAL_GPIO_PIN_STATE flg;
int result = 0;
*((u32 *) &gpio_pin) = HAL_READ32(SPI_FLASH_BASE, FLASH_SYSTEM_DATA_ADDR + 0x08); // config data + 8
_pHAL_Gpio_Adapter = (int) &gBoot_Gpio_Adapter;
for(int i = 0; i < 2; i++) {
u8 x = gpio_pin[i];
if (x != 0xff) {
GPIO_Pin.pin_name = HAL_GPIO_GetIPPinName_8195a(x & 0x7F);
if (x & 0x80) {
GPIO_Pin.pin_mode = DIN_PULL_LOW;
flg = GPIO_PIN_HIGH;
} else {
GPIO_Pin.pin_mode = DIN_PULL_HIGH;
flg = GPIO_PIN_LOW;
}
HAL_GPIO_Init_8195a(&GPIO_Pin);
result |= HAL_GPIO_ReadPin_8195a(&GPIO_Pin) == flg;
HAL_GPIO_DeInit_8195a(&GPIO_Pin);
}
}
_pHAL_Gpio_Adapter->IrqHandle.IrqFun = NULL;
return result;
}
//----- GetChipId
int __attribute__((section(".hal.ram.text"))) _GetChipId() {
u8 chip_id = CHIP_ID_8195AM;
if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
&chip_id, L25EOUTVOLTAGE) != 1)
DBG_MISC_INFO("Get Chip ID Failed\r");
return chip_id;
}
//----- StartupHalSpicInit
void __attribute__((section(".hal.ram.text"))) StartupHalSpicInit(
int InitBaudRate) {
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT4); // HAL_SYS_CTRL_READ32
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL,
HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_FLASH_EN | BIT_SOC_SLPCK_FLASH_EN);
HalPinCtrlRtl8195A(SPI_FLASH,
((HAL_SYS_CTRL_READ32(REG_SYS_SYSTEM_CFG1) & 0xF0000000)
== 0x30000000), 1);
SpicInitRtl8195A(InitBaudRate, StartupSpicBitMode);
}
void __attribute__((section(".hal.ram.text"))) flashcpy(u32 raddr, u32 faddr, s32 size) {
while(size > 0) {
HAL_WRITE32(0, raddr, HAL_READ32(SPI_FLASH_BASE, faddr));
raddr+=4;
faddr+=4;
size-=4;
}
}
//----- PreProcessForVendor
void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(void) {
START_FUNC entry_func;
u32 run_image;
u32 Image2Addr = *(u32 *)(0x1006FFFC);
u32 v16 = 0, v17;
#if 0
u8 efuse0xD3_data;
HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xD3,
&efuse0xD3_data, L25EOUTVOLTAGE);
if (efuse0xD3_data & 1)
#endif
HalPinCtrlRtl8195A(JTAG, 0, 1);
SetDebugFlgs();
int chip_id = _GetChipId();
int flash_enable = HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN; // v6 = ...
int spic_init = 0;
/// InitSpic();
if (flash_enable) {
entry_func = &__image2_entry_func__;
spic_init = 1;
} else {
entry_func = (START_FUNC) Image2Addr;
if (chip_id != CHIP_ID_8711AN) { // 0xFB
StartupHalSpicInit(StartupSpicBaudRate); // BaudRate 1
spic_init = 1;
}
}
DBG_8195A("BOOT from Flash: %s\n", (flash_enable) ? "YES" : "NO");
memset(&__image1_bss_start__, 0,
&__image1_bss_end__ - &__image1_bss_start__);
HalDelayUs(1000);
int sdr_enable = 0;
#ifdef CONFIG_SDR_EN
if (chip_id > CHIP_ID_8711AF || chip_id == CHIP_ID_8710AM) {
SdrCtrlInit();
sdr_enable = 1;
}
else {
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21));
}
#else
// SdrPowerOff();
SDR_PIN_FCTRL(OFF);
LDO25M_CTRL(OFF);
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21));
#endif
if (spic_init) SpicNVMCalLoadAll();
SYSCpuClkConfig(chip_id, 0);
StartupHalInitPlatformLogUart(); // double !?
__asm__ __volatile__ ("cpsie f\n");
DBG_8195A("===== Enter Image 1 ====\n");
if (spic_init) {
SpicReadIDRtl8195A();
SpicFlashInitRtl8195A(StartupSpicBitMode); // SpicBitMode 1
}
#ifdef CONFIG_SDR_EN
if (sdr_enable) SdrControllerInit();
#endif
if (flash_enable) {
u32 img1size = (*(u16 *) (SPI_FLASH_BASE + 0x18)) << 10; // size in 1024 bytes
if (img1size == 0 || img1size >= 0x3FFFC00)
img1size = *(u32 *) (SPI_FLASH_BASE + 0x10) + 32;
u32 * prdflash = (u32 *) (img1size + SPI_FLASH_BASE + 8);
u32 sign1 = *prdflash++;
u32 sign2 = *prdflash;
{
v16 = -1;
v17 = -1;
if (sign2 == IMG_SIGN2_RUN) {
if (sign1 == IMG_SIGN1_RUN) {
v16 = img1size;
v17 = -1;
} else if (sign1 == IMG_SIGN1_SWP) {
v17 = img1size;
v16 = -1;
}
}
u32 OTA_addr = *(u32 *) (SPI_FLASH_BASE + FLASH_SYSTEM_DATA_ADDR); // config sector data
if (OTA_addr != -1) {
u32 image2size = *(u32 *) (img1size + SPI_FLASH_BASE);
if (OTA_addr >= (img1size + image2size)
&& !(OTA_addr & 0xFFF)) {
prdflash = (u32 *) (OTA_addr + SPI_FLASH_BASE + 8);
sign1 = *prdflash++;
sign2 = *prdflash;
if (sign2 == IMG_SIGN2_RUN) {
if (sign1 == IMG_SIGN1_RUN) v16 = OTA_addr;
else if (sign1 == IMG_SIGN1_SWP) v17 = OTA_addr;
}
LABEL_41: if (IsForceLoadDefaultImg2()) {
if (v17 != -1) run_image = v17;
else {
run_image = v16;
if (run_image == -1) {
DiagPrintf("Fatal: no fw\n");
RtlConsolRam();
}
}
} else {
if (v16 != -1) run_image = v16;
else {
run_image = v17;
if (run_image == -1) {
DiagPrintf("Fatal: no fw\n");
RtlConsolRam();
}
}
}
u8 * pstr;
if (run_image == v17)
pstr = "load OLD fw %d\n";
else {
if (run_image != v16) {
LABEL_55: prdflash = run_image + SPI_FLASH_BASE;
u32 img_size = *prdflash++;
u32 Image2Addr = *prdflash;
DBG_8195A("Flash Image2: Addr 0x%x, Len %d, Load to SRAM 0x%x\n", run_image, img_size, Image2Addr); // debug!
flashcpy(Image2Addr, run_image+16, img_size);
// SpicUserReadFourByteRtl8195A(img_size, run_image + 16, Image2Addr, StartupSpicBitMode); // SpicDualBitMode
prdflash = run_image + img_size + SPI_FLASH_BASE + 16;
u32 sdram_image_size = *prdflash++; // +0x10
u32 sdram_load_addr = *prdflash; // +0x14
DBG_8195A("Image3 length: 0x%x, Image3 Addr: 0x%x\n",
sdram_image_size, sdram_load_addr);
if ((sdram_image_size - 1) <= 0xFFFFFFFD
&& *((u32 *)(sdram_load_addr)) == SDR_SDRAM_BASE) { // sdram_load_addr
if (!sdr_enable) {
DBG_MISC_ERR("FW/HW conflict. No DRAM on board.\n");
RtlConsolRam();
}
DBG_8195A("Image3 length: 0x%x, Image3 Addr: 0x%x\n",
sdram_image_size, sdram_load_addr);
// SpicUserReadRtl8195A(sdram_image_size, run_image + img_size + 32, SDR_SDRAM_BASE, StartupSpicBitMode);
} else DBG_8195A("No Image3\n");
entry_func = *(u32 *)Image2Addr;
DBG_8195A("Img2 Sign: %s, InfaStart @ 0x%08x \n",
(const char * )(Image2Addr + 4),
entry_func); // *(u32 *)Image2Addr);
if (strcmp((const char * )(Image2Addr + 4),
IMG2_SIGN_TXT)) {
DBG_MISC_ERR("Invalid Image2 Signature\n");
RtlConsolRam();
}
#if 0
DBG_8195A("CLK CPU: %d Hz\n", HalGetCpuClk());
RtlConsolRam();
#else
#endif
(void) (entry_func)();
return;
}
pstr = "load NEW fw %d\n";
} // if (run_image == v17) else
DiagPrintf(pstr, ((run_image - OTA_addr) <= 0));
goto LABEL_55;
}
DBG_MISC_ERR("OTA addr 0x%x INVALID\n", OTA_addr);
}
OTA_addr = -1;
goto LABEL_41;
}
} // if (flash_enable)
if (strcmp((const char * )(Image2Addr + 4), IMG2_SIGN_TXT)) {
DBG_MISC_ERR("Invalid Image2 Signature\n", 2 * ConfigDebugErr);
RtlConsolRam();
}
(void) (entry_func)();
}
#if !USE_SRC_ONLY_BOOT
//----- HalHardFaultHandler_Patch_c
void HalHardFaultHandler_Patch_c(u32 HardDefaultArg) {
u32 v1;
int v2;
int v3;
v1 = HardDefaultArg;
if ((VREG32(0xE000ED28) & 0x82)
&& (unsigned int) (VREG32(0xE000ED38) - 0x40080000) < 0x40000) {
DBG_8195A("\n.");
v2 = *(u32 *) (v1 + 24);
if ((*(u16 *) v2 & 0xF800) <= 0xE000) v3 = v2 + 2;
else v3 = v2 + 4;
*(u32 *) (v1 + 24) = v3;
} else {
HalHardFaultHandler_user_define(HardDefaultArg);
HalHardFaultHandler(v1); // ROM: HalHardFaultHandler = 0x911;
}
}
//----- VectorTableOverrideRtl8195A
void __attribute__((section(".infra.ram.start"))) VectorTableOverrideRtl8195A(u32 StackP) {
void INFRA_START_SECTION VectorTableOverrideRtl8195A(u32 StackP) {
NewVectorTable[2] = HalNMIHandler_Patch;
}
//----- SYSPlatformInit
void __attribute__((section(".infra.ram.start"))) SYSPlatformInit(void) {
void INFRA_START_SECTION SYSPlatformInit(void) {
HAL_SYS_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0,
(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0) & (~(BIT_MASK_SYS_EEROM_LDO_PAR_07_04 << BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04))) | BIT_SYS_EEROM_LDO_PAR_07_04(6)); // & 0xF0FFFFFF | 0x6000000
(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0)
& (~(BIT_MASK_SYS_EEROM_LDO_PAR_07_04 << BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04)))
| BIT_SYS_EEROM_LDO_PAR_07_04(6)); // & 0xF0FFFFFF | 0x6000000
HAL_SYS_CTRL_WRITE32(REG_SYS_XTAL_CTRL1,
(HAL_SYS_CTRL_READ32(REG_SYS_XTAL_CTRL1) & (~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1))) | BIT_SYS_XTAL_DRV_RF1(1)); // & 0xFFFFFFE7 | 8;
(HAL_SYS_CTRL_READ32(REG_SYS_XTAL_CTRL1)
& (~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1)))
| BIT_SYS_XTAL_DRV_RF1(1)); // & 0xFFFFFFE7 | 8;
}
//----- SDIO_Device_Off
void INFRA_START_SECTION SDIO_Device_Off(void) {
HAL_PERI_ON_WRITE32(REG_PESOC_HCI_CLK_CTRL0,
HAL_PERI_ON_READ32(REG_PESOC_HCI_CLK_CTRL0)
& (~BIT_SOC_ACTCK_SDIO_DEV_EN));
HAL_PERI_ON_WRITE32(REG_SOC_HCI_COM_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_HCI_COM_FUNC_EN)
& (~(BIT_SOC_HCI_SDIOD_ON_EN | BIT_SOC_HCI_SDIOD_OFF_EN)));
HAL_PERI_ON_WRITE32(REG_HCI_PINMUX_CTRL,
HAL_PERI_ON_READ32(REG_HCI_PINMUX_CTRL)
& (~(BIT_HCI_SDIOD_PIN_EN)));
}
//----- InfraStart
void __attribute__((section(".infra.ram.start"))) InfraStart(void) {
void INFRA_START_SECTION InfraStart(void) {
NewVectorTable[2] = HalNMIHandler_Patch;
HAL_SYS_CTRL_WRITE32(REG_SYS_CLK_CTRL0,
HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL0) | BIT4);
if (HalCommonInit() != HAL_OK) DBG_8195A("Hal Common Init Failed.\n");
DBG_8195A("===== Enter Image 2 ====\n");
if (HalCommonInit() != HAL_OK)
DBG_8195A("Hal Common Init Failed.\n");
DBG_8195A("==!== Enter Image 2 ====\n");
ShowRamBuildInfo(); // app_start.c: VOID ShowRamBuildInfo(VOID)
memset(&__bss_start__, 0, &__bss_end__ - &__bss_start__);
int clk = (HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL0)
@ -656,169 +101,10 @@ void __attribute__((section(".infra.ram.start"))) InfraStart(void) {
En32KCalibration();
InitSoCPM();
SDIO_Device_Off();
VectorTableInitForOSRtl8195A(&vPortSVCHandler, &xPortPendSVHandler, &xPortSysTickHandler);
if (clk) SpicDisableRtl8195A();
VectorTableInitForOSRtl8195A(&vPortSVCHandler, &xPortPendSVHandler,
&xPortSysTickHandler);
if (clk)
SpicDisableRtl8195A();
_AppStart();
}
//----- SDIO_Device_Off
void SDIO_Device_Off(void) {
HAL_PERI_ON_WRITE32(REG_PESOC_HCI_CLK_CTRL0,
HAL_PERI_ON_READ32(REG_PESOC_HCI_CLK_CTRL0) & (~BIT_SOC_ACTCK_SDIO_DEV_EN));
HAL_PERI_ON_WRITE32(REG_SOC_HCI_COM_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_HCI_COM_FUNC_EN) & (~(BIT_SOC_HCI_SDIOD_ON_EN | BIT_SOC_HCI_SDIOD_OFF_EN)));
HAL_PERI_ON_WRITE32(REG_HCI_PINMUX_CTRL,
HAL_PERI_ON_READ32(REG_HCI_PINMUX_CTRL) & (~(BIT_HCI_SDIOD_PIN_EN)));
}
//----- __HalReInitPlatformLogUart
void __HalReInitPlatformLogUart(void) {
LOG_UART_ADAPTER UartAdapter;
UartAdapter.BaudRate = DEFAULT_BAUDRATE;
HalLogUartInit(UartAdapter);
}
void _ReloadImg_user_define(void) {
}
//----- ReloadImg
void _ReloadImg(void) {
u32 img1size;
u32 img1addr;
unsigned int i;
u32 img2addr;
u32 img_addr1;
u32 img_addr2;
u32 ota_addr;
const char * pstr;
img1size = *(u32 *) (SPI_FLASH_BASE + 0x10);
img1addr = *(u32 *) (SPI_FLASH_BASE + 0x14);
DBG_8195A("Image1 length: 0x%x, Image Addr: 0x%x\n", img1size,
img1addr);
for (i = 32; i < img1size + 32; i += 4)
*(u32 *) (img1addr - 32 + i) = *(u32 *) (i + SPI_FLASH_BASE);
img2addr = *(u16 *) (SPI_FLASH_BASE + 0x16) << 10;
if (!(img2addr)) img2addr = img1size + 32;
u32 * prdflash = (u32 *) (img1size + SPI_FLASH_BASE + 8);
u32 sign1 = *prdflash++; // v4 = *(u32 *)(img2addr + SPI_FLASH_BASE + 8);
u32 sign2 = *prdflash; // v5 = *(u32 *)(img2addr + SPI_FLASH_BASE + 12);
if (sign1 == IMG_SIGN1_RUN) {
if (sign2 == IMG_SIGN2_RUN) {
img_addr1 = img2addr;
LABEL_11: img_addr2 = -1;
goto LABEL_16;
}
LABEL_14: img_addr1 = -1;
goto LABEL_11;
}
if (sign1 != IMG_SIGN1_SWP || sign2 != IMG_SIGN2_RUN) goto LABEL_14;
img_addr2 = img2addr;
img_addr1 = -1;
LABEL_16: ota_addr = *(u32 *) (SPI_FLASH_BASE + 0x9000);
if (ota_addr == -1) {
LABEL_21: ota_addr = -1;
goto LABEL_22;
}
if (ota_addr < (img2addr + *(u32 *) (img2addr + SPI_FLASH_BASE))
|| (ota_addr & 0xFFF)) {
DBG_MISC_ERR("OTA addr 0x%x INVALID\n");
goto LABEL_21;
}
prdflash = (u32 *) (ota_addr + SPI_FLASH_BASE + 8);
sign1 = *prdflash++; // v9 = *(u32 *)(ota_addr + SPI_FLASH_BASE + 8);
sign2 = *prdflash; // v11 = *(u32 *)(ota_addr + SPI_FLASH_BASE + 12);
if (sign1 == IMG_SIGN1_RUN) {
sign1 = IMG_SIGN2_RUN;
if (sign2 == IMG_SIGN2_RUN) {
img_addr1 = ota_addr;
goto LABEL_33;
}
goto LABEL_22;
}
if (sign1 != IMG_SIGN1_SWP || (sign1 = IMG_SIGN2_RUN, sign2 != IMG_SIGN2_RUN)) {
LABEL_22: if (img_addr1 == -1) {
if (img_addr2 == -1) {
DBG_MISC_ERR("Fatal:no fw\n", ota_addr,
2 * ConfigDebugErr);
RtlConsolRam();
}
img_addr1 = img_addr2;
LABEL_28: pstr = "load OLD fw %d\n";
if (ConfigDebugErr & _DBG_MISC_) {
LABEL_36: DiagPrintf(pstr,
((unsigned int) (img_addr1 - ota_addr) <= 0));
}
goto IMG2_LOAD_START;
}
goto LABEL_33;
}
if (img_addr1 == -1) {
img_addr1 = *(u32 *) (SPI_FLASH_BASE + 0x9000); // ota_addr
goto LABEL_28;
}
img_addr2 = *(u32 *) (SPI_FLASH_BASE + 0x9000);
LABEL_33: if (img_addr1 == img_addr2)
goto LABEL_28;
if (ConfigDebugErr & _DBG_MISC_) // DBG_8195A
{
pstr = "load NEW fw %d\n";
goto LABEL_36;
}
u32 v13;
IMG2_LOAD_START:
v13 = *(u32 *) (img_addr1 + SPI_FLASH_BASE + 4);
u32 v15 = *(u32 *) (img_addr1 + SPI_FLASH_BASE) + img_addr1;
for (i = img_addr1 + 16;; i += 4) {
if (i >= (unsigned int) (v15 + 16)) break;
*(u32 *) (v13 - 16 - img_addr1 + i) = *(u32 *) (i + SPI_FLASH_BASE);
}
u32 v16 = *(u32 *) (v15 + SPI_FLASH_BASE);
if ((unsigned int) (v16 - 1) <= 0xFFFFFFFD
&& *(u32 *) (v15 + SPI_FLASH_BASE + 0x14) == 0x30000000) {
DBG_8195A("Image3 length: 0x%x, Image3 Addr: 0x%x\n",
*(u32 *)(v15 + SPI_FLASH_BASE + 0x10));
for (i = v15 + 32; i < (v16 + v15 + 32); i += 4)
*(u32 *) (0x2FFFFFE0 - v15 + i) = *(u32 *) (i + SPI_FLASH_BASE);
} else
DBG_8195A("No Image3\n");
_ReloadImg_user_define();
}
//----- CPUResetHandler
void _CPUResetHandler(void) {
memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__);
ConfigDebugErr = -1;
HalCpuClkConfig(0);
VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT23);
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN);
HAL_PERI_ON_WRITE32(REG_SOC_PERI_BD_FUNC0_EN,
HAL_PERI_ON_READ32(REG_SOC_PERI_BD_FUNC0_EN) | BIT8 | BIT9);
HalPinCtrlRtl8195A(SPI_FLASH, 0, 1);
HalTimerOpInit_Patch(&HalTimerOp);
HalDelayUs(1000);
__HalReInitPlatformLogUart();
_ReloadImg();
InfraStart();
}
//----- CPUReset
void _CPUReset(void) // __noreturn
{
wifi_off();
pRamStartFun->RamPatchFun1 = _CPUResetHandler;
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT27);
HAL_WRITE32(0xE000ED00, 0x0C, 0x5FA0003); //
while (1);
}
void HalHardFaultHandler_user_define(u32 HardDefaultArg) {
}
#endif // !USE_SRC_ONLY_BOOT

9
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c
View file

@ -178,14 +178,16 @@ HalRuartGenBaudRateRtl8195a(
while ((min_err > pBaudSetting->max_err) && (div_res > 0)) {
uart_ovsr = pBaudSetting->Ovsr_max;
while(uart_ovsr >= pBaudSetting->Ovsr_min) {
divisor_temp = (uart_clock/baud_rate)/uart_ovsr;
// divisor_temp = (uart_clock/baud_rate)/uart_ovsr;
divisor_temp = div_u64(div_u64(uart_clock, baud_rate), uart_ovsr);
max_jitter_temp = 0;
if (divisor_temp > 0) {
max_jitter_temp = 100000/uart_ovsr;
if (max_jitter_temp >= pBaudSetting->jitter_lim) {
err_temp = 100;
} else {
err_temp = (uart_clock/divisor_temp)/((uart_ovsr/100)*100);
// err_temp = (uart_clock/divisor_temp)/((uart_ovsr/100)*100);
err_temp = div_u64(div_u64(uart_clock, divisor_temp), (uart_ovsr/100)*100);
if (err_temp > baud_rate) {
err_temp = (err_temp - baud_rate)*1000 / baud_rate;
} else {
@ -217,7 +219,8 @@ HalRuartGenBaudRateRtl8195a(
if (min_divisor == 0) {
min_divisor = 1;
}
uart_ovsr_target = (uart_clock/baud_rate)/min_divisor;
// uart_ovsr_target = (uart_clock/baud_rate)/min_divisor;
uart_ovsr_target = div_u64(div_u64(uart_clock,baud_rate), min_divisor);
ovsr_adj = 0;
adj_bits = 0;

35
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_spi_flash_ram.c
View file

@ -8,11 +8,9 @@
*/
#include "rtl8195a.h"
#include "hal_spi_flash.h"
#include "rtl8195a_spi_flash.h"
#pragma arm section code = ".hal.flash.text", rodata = ".hal.flash.rodata", rwdata = ".hal.flash.data", zidata = ".hal.flash.bss"
//#pragma arm section code = ".hal.flash.text", rodata = ".hal.flash.rodata", rwdata = ".hal.flash.data", zidata = ".hal.flash.bss"
//#define SPI_CTRL_BASE 0x1FFEF000
#define SPI_DLY_CTRL_ADDR 0x40000300 // [7:0]
@ -88,11 +86,11 @@ SECTION SPIC_INIT_PARA SpicInitParaAllClk[CPU_CLK_TYPE_NO] = {{0,0,0,0},
{0,0,0,0},
{0,0,0,0},};
#else
HAL_FLASH_DATA_SECTION
SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO];
extern HAL_FLASH_DATA_SECTION
SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // in rtl_bios_data.c
#endif
extern SPIC_INIT_PARA SpicInitCPUCLK[4];
//extern SPIC_INIT_PARA SpicInitCPUCLK[4];
/* Send Flash Instruction with Data Phase */
HAL_FLASH_TEXT_SECTION
@ -113,7 +111,7 @@ SpicTxCmdWithDataRtl8195A
HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0);
if (DataPhaseLen > 15) {
DBG_SPIF_WARN("SpicTxInstRtl8195A: Data Phase Leng too Big(%d)\n",DataPhaseLen);
DBG_SPIF_WARN("%s: Data Phase Leng too Big(%d)\n", __func__, DataPhaseLen);
DataPhaseLen = 15;
}
@ -1355,15 +1353,16 @@ SpicNVMCalLoad(u8 BitMode, u8 CpuClk)
SpicInitParaAllClk[BitMode][CpuClk].RdDummyCyle = pspci_para->RdDummyCyle;
SpicInitParaAllClk[BitMode][CpuClk].DelayLine = pspci_para->DelayLine;
SpicInitParaAllClk[BitMode][CpuClk].Valid = pspci_para->Valid;
DBG_SPIF_INFO("SpicNVMCalLoad: Calibration Loaded(BitMode %d, CPUClk %d): BaudRate=0x%x RdDummyCyle=0x%x DelayLine=0x%x\r\n",
BitMode, CpuClk,
DBG_SPIF_INFO("%s: Calibration Loaded(BitMode %d, CPUClk %d): BaudRate=0x%x RdDummyCyle=0x%x DelayLine=0x%x\r\n",
__func__, BitMode, CpuClk,
SpicInitParaAllClk[BitMode][CpuClk].BaudRate,
SpicInitParaAllClk[BitMode][CpuClk].RdDummyCyle,
SpicInitParaAllClk[BitMode][CpuClk].DelayLine);
}
else {
DBG_SPIF_WARN("SpicNVMCalLoad: Data in Flash(@ 0x%x = 0x%x 0x%x) is Invalid\r\n",
(FLASH_SPIC_PARA_BASE+flash_offset), spci_para, spci_para_inv);
DBG_SPIF_WARN("%s: Data in Flash(@ 0x%x = 0x%x 0x%x) is Invalid\r\n",
__func__,
(FLASH_SPIC_PARA_BASE+flash_offset), spci_para, spci_para_inv);
}
}
@ -1408,7 +1407,7 @@ SpicNVMCalStore(u8 BitMode, u8 CpuClk)
SPIC_INIT_PARA SpicInitPara;
#if CONFIG_DEBUG_LOG > 4
DBG_SPIF_INFO("SpicNVMCalStore==> BitMode=%d CpuClk=%d\r\n", BitMode, CpuClk);
DBG_SPIF_INFO("%s ==> BitMode=%d CpuClk=%d\r\n", __func__, BitMode, CpuClk);
#endif
/* each Calibration parameters use 8 bytes, first 4-bytes are the calibration data,
2nd 4-bytes are the validate data: ~(calibration data) */
@ -1436,7 +1435,8 @@ SpicNVMCalStore(u8 BitMode, u8 CpuClk)
SpicWaitWipDoneRefinedRtl8195A(SpicInitPara);
#if CONFIG_DEBUG_LOG > 4
DBG_SPIF_INFO("SpicNVMCalStore(BitMode %d, CPUClk %d): Calibration Stored: BaudRate=0x%x RdDummyCyle=0x%x DelayLine=0x%x\r\n",
DBG_SPIF_INFO("%s(BitMode %d, CPUClk %d): Calibration Stored: BaudRate=0x%x RdDummyCyle=0x%x DelayLine=0x%x\r\n",
__func__,
BitMode, CpuClk,
SpicInitParaAllClk[BitMode][CpuClk].BaudRate,
SpicInitParaAllClk[BitMode][CpuClk].RdDummyCyle,
@ -1444,18 +1444,21 @@ SpicNVMCalStore(u8 BitMode, u8 CpuClk)
#endif
// Read back to check
if (HAL_READ32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset)) != spci_para) {
DBG_SPIF_ERR("SpicNVMCalStore Err(Offset=0x%x), Wr=0x%x Rd=0x%x \r\n",
DBG_SPIF_ERR("%s: Err(Offset=0x%x), Wr=0x%x Rd=0x%x \r\n",
__func__,
flash_offset, spci_para, HAL_READ32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset)));
}
if (HAL_READ32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset+4)) != ~spci_para) {
DBG_SPIF_ERR("SpicNVMCalStore Err(Offset=0x%x), Wr=0x%x Rd=0x%x \r\n",
DBG_SPIF_ERR("%s: Err(Offset=0x%x), Wr=0x%x Rd=0x%x \r\n",
__func__,
flash_offset+4, ~spci_para, HAL_READ32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset+4)));
}
}
else {
// There is a parameter on the flash memory already
DBG_SPIF_ERR("SpicNVMCalStore: The flash memory(@0x%x = 0x%x) is not able to be write, Erase it first!\r\n",
DBG_SPIF_ERR("%s: The flash memory(@0x%x = 0x%x) is not able to be write, Erase it first!\r\n",
__func__,
(FLASH_SPIC_PARA_BASE+flash_offset), spci_para);
}
}

56
RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/export-rom_v04.txt
View file

@ -715,71 +715,19 @@ SECTIONS
/* RAM data used in ROM */
__ram_image_start__ = 0x10000000;
NewVectorTable = 0x10000000;
UserIrqFunTable = 0x10000100;
UserIrqDataTable = 0x10000200;
__rom_bss_start__ = 0x10000300;
CfgSysDebugWarn = 0x10000300;
CfgSysDebugInfo = 0x10000304;
CfgSysDebugErr = 0x10000308;
ConfigDebugWarn = 0x1000030c;
ConfigDebugInfo = 0x10000310;
ConfigDebugErr = 0x10000314;
HalTimerOp = 0x10000318;
GPIOState = 0x10000334; /* HalPinCtrlRtl8195A() */
gTimerRecord = 0x1000034c; /* HalGetTimerIdRtl8195a() */
SSI_DBG_CONFIG = 0x10000350; /* HalSsiPinmuxEnableRtl8195a() */
_pHAL_Gpio_Adapter = 0x10000354; /* GPIO_FuncOn_8195a() */
Timer2To7VectorTable = 0x10000358; /* HalTimerIrqUnRegisterRtl8195aV02() */
_rand_first = 0x10000370; /* Rand() */
_rand_z1 = 0x10000374; /* Rand() */
_rand_z2 = 0x10000378; /* Rand() */
_rand_z3 = 0x1000037C; /* Rand() */
_rand_z4 = 0x10000380; /* Rand() */
pUartLogCtl = 0x10000384; /* UartLogIrqHandle() */
UartLogBuf = 0x10000388; /* RtlConsolInit() */
UartLogCtl = 0x10000408; /* RtlConsolInit() */
UartLogHistoryBuf = 0x10000430; /* */
ArgvArray = 0x100006ac; /* GetArgv() */
rom_wlan_ram_map = 0x100006d4; /* os_zalloc(), WPS_realloc(),.. */
FalseAlmCnt = 0x100006e0; /* ROM_odm_FalseAlarmCounterStatistics() */
ROMInfo = 0x10000720; /* ROM_odm_GetDefaultCrytaltalCap(), ROM_odm_SetCrystalCap(), ROM_ODM_CfoTrackingReset(),.. */
DM_CfoTrack = 0x10000738; /* ROM_odm_CfoTrackingFlow() */
rom_libgloss_ram_map = 0x10000760; /* _rtl_fstat_v1_00(), _rtl_lseek_v1_00(),.. */
__rtl_malloc_av_ = 0x10000780; /* __rom_mallocr_init_v1_00(), _rtl_free_r_v1_00().. */
__rtl_malloc_trim_threshold = 0x10000b88; /* __rom_mallocr_init_v1_00() */
__rtl_malloc_top_pad = 0x10000b8c; /* __rom_mallocr_init_v1_00() */
__rtl_malloc_sbrk_base = 0x10000b90; /* __rom_mallocr_init_v1_00() */
__rtl_malloc_max_sbrked_mem = 0x10000b94; /* __rom_mallocr_init_v1_00() */
__rtl_malloc_max_total_mem = 0x10000b98; /* __rom_mallocr_init_v1_00() */
__rtl_malloc_current_mallinfo = 0x10000b9c; /* __rom_mallocr_init_v1_00() */
__rtl_errno = 0x10000bc4; /* __rtl_sread_v1_00(), __rtl_write_v1_00(), __rtl_lseek_v1_00(), __rtl_close_v1_00(), __rtl_sbrk_v1_00().. */
__ram_start_table_start__ = 0x10000bc8;
__rom_bss_end__ = 0x10000bc8;
/* BOOT-LOADER */
bootloader = 0x10000bc8; /* = gRamStartFun, HalResetVsr() */
gRamStartFun = 0x10000bc8; /* HalResetVsrV02(), HalResetVsr() */
gRamStartFun = 0x10000bc8; /* HalResetVsrV02(), HalResetVsr() */
gRamPatchWAKE = 0x10000bcc; /* HalResetVsrV02(), HalResetVsr() */
gRamPatchFun0 = 0x10000bd0; /* HalResetVsrV02(), HalResetVsr() */
gRamPatchFun1 = 0x10000bd4; /* HalResetVsrV02(), HalResetVsr() */
gRamPatchFun2 = 0x10000bd8; /* HalResetVsrV02(), HalResetVsr() */
__image1_validate_code__ = 0x10000bdc; /* 8 bytes HalResetVsrV02(), HalResetVsr() */
RAM_IMG1_VALID_PATTEN = 0x10000bdc;
rand_x = 0x10000be4; /* ChangeRandSeed_rom().. Sdr_Rand2_rom() */
AvaWds = 0x10000be8; /* SdrCalibration_rom() */
SdrDramInfo = 0x10001be8; /* SdrCalibration_rom() */
SdrDramTiming = 0x10001bfc; /* SdrCalibration_rom() */
SdrDramModeReg = 0x10001c30; /* SdrCalibration_rom() */
SdrDramDev = 0x10001c4c; /* SdrCalibration_rom() */
/* 0x10000be8: buf 0x1000+ bytes SdrCalibration_rom() */
_rtl_impure_ptr = 0x10001c60; /* struct _reent * _rtl_impure_ptr = { &impure_reent } (for standard library) */
impure_reent = 0x10001c68; /* struct _reent */
_rom_unc_data = 0x10002090; /* ? u32 _rom_unc_data[9] */
_sdr_rnd2_y = 0x100020b4; /* Sdr_Rand2_rom().. ChangeRandSeed_rom() */
_sdr_rnd2_z = 0x100020b8; /* Sdr_Rand2_rom().. ChangeRandSeed_rom() */
_sdr_rnd2_c = 0x100020bc; /* Sdr_Rand2_rom().. ChangeRandSeed_rom() */
__ram_image_end__ = 0x10002100;

390
RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img2.ld
View file

@ -1,13 +1,14 @@
ENTRY(Reset_Handler)
ENTRY(main)
INCLUDE "export-rom_v04.txt"
MEMORY
{
ROM_USED_RAM (rwx): ORIGIN = 0x10000bc8, LENGTH = 21560 /* end 0x10006000 */
ROM (rx) : ORIGIN = 0x000000, LENGTH = 1M /* end 0x00100000 */
ROM_USED_RAM (rwx): ORIGIN = 0x10000000, LENGTH = 0x2400 /* end 0x10002400 */
BOOT_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 21560 /* end 0x10006000 */
ROM_HEAP (rwx) : ORIGIN = 0x10002400, LENGTH = 3K /* end 0x10003000 */
RAM_HEAP1 (rwx) : ORIGIN = 0x10003000, LENGTH = 12K /* end 0x10006000 */
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 424K /* end 0x10070000 */
@ -17,211 +18,232 @@ MEMORY
}
EXTERN(RAM_IMG2_VALID_PATTEN)
EXTERN(main)
EXTERN(InfraStart)
EXTERN(gImage2EntryFun0)
SECTIONS
{
__rom_bss_start__ = 0x10000300;
__rom_bss_end__ = 0x10000bc8;
.bootloader :
{
KEEP(*(.loader.data*))
} > ROM_USED_RAM
/* 0x00000000: ROM */
.romheap :
{
__rom_heap_start__ = .;
end = __rom_heap_start__;
. = ALIGN(0x1000);
__rom_heap_end__ = .;
} > ROM_HEAP
.rom :
{
__rom_image_start__ = .;
KEEP(*(.rom));
__rom_image_end__ = .;
} > ROM
.ram_heap1 :
{
__ram_heap1_start__ = .;
/* *(.heap1*) */
} > RAM_HEAP1
OVERLAY 0x1FFF0000:
{
.valid
{
__ram_tcm_start__ = .;
*mem.o (.bss*)
*memp.o (.bss*)
__tcm_heap_start__ = .;
*(.tcm.heap)
}
.dummy
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.start.ram.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
/* 0x10000000: SRAM */
.rom_ram : /* use in rom */
{
__ram_image_start__ = .;
KEEP(*(.ram_dedecated_vector_table)) /* 0x10000000: NewVectorTable */
KEEP(*(.ram_user_define_irq_table)) /* 0x10000100: UserIrqFunTable */
KEEP(*(.ram_user_define_data_table)) /* 0x10000200: UserIrqDataTable */
__rom_bss_start__ = .;
KEEP(*(.hal.ram.bss)) /* 0x10000300: CfgSysDebugWarn .. _pHAL_Gpio_Adapter */
KEEP(*(.timer2_7_vector_table.data)) /* 0x10000358: Timer2To7VectorTable */
KEEP(*(.infra.ram.bss)) /* 0x10000370: first .. z4 */
KEEP(*(.mon.ram.bss)) /* 0x10000384: pUartLogCtl .. ArgvArray */
KEEP(*(.wlan_ram_map)) /* 0x100006d4: rom_wlan_ram_map, FalseAlmCnt, ROMInfo, DM_CfoTrack */
KEEP(*(.ram.rom.wlanmap)) /* align(8) */
KEEP(*(.libc.ram.bss)) /* 0x10000760: rom_libgloss_ram_map __rtl_malloc_av_ __rtl_errno */
__rom_bss_end__ = .;
} > ROM_USED_RAM
/* 0x10000bc8: bootloader */
.ram_image1.text . : /* use in rom & boot */
{
/* __ram_start_table_start__ = .; */
__ram_image1_text_start__ = .;
KEEP(*(SORT(.start.ram.data*)))
/* __image1_validate_code__ = .; */
KEEP(*(.image1.validate.rodata))
KEEP(*(.infra.ram.data*))
KEEP(*(.timer.ram.data*))
KEEP(*(.cutb.ram.data*))
KEEP(*(.cutc.ram.data*))
KEEP(*(.hal.ram.data*))
KEEP(*(.cutb.ram.data*))
KEEP(*(.cutc.ram.data*))
KEEP(*(.libc.reent))
KEEP(*(.rom.unc.data))
KEEP(*(.sdr.rand2.data))
__ram_image_end__ = .;
/* 0x100020c0: end */
/* boot & images data */
KEEP(*(.hal.ram.data))
KEEP(*(.hal.flash.data))
/* KEEP(*(.data)); ? */
build/obj/project/src/user/rtl_bios_data.o (.rodata*)
KEEP(*(.ram.boot.text))
build/obj/project/src/user/rtl_boot.o (.rodata*)
__image1_bss_start__ = .;
.ram_image1.bss$$Base = .;
__image1_bss_end__ = .;
.ram_image1.bss$$Limit = .;
__ram_image1_data_end__ = .;
*(.hal.ram.text*)
*(.infra.ram.text*)
}
} > TCM
__image1_bss_end__ = .;
__ram_image1_text_end__ = .;
} > BOOT_RAM
.soc_ps_monitor :
{
__tcm_heap_end__ = .;
} > TCM_TAB
.romheap :
{
__rom_heap_start__ = .;
end = __rom_heap_start__;
. = ALIGN(0x1000);
__rom_heap_end__ = .;
} > ROM_HEAP
.image2.start.table :
{
__ram_heap1_end__ = .;
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
.image2.start.table1$$Base = .;
KEEP(*(SORT(.image2.ram.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
KEEP(*(.custom.validate.rodata*))
} > BD_RAM
.ram_heap1 :
{
__ram_heap1_start__ = .;
/* *(.heap1*) */
} > RAM_HEAP1
.ram_image2.text :
{
*(.infra.ram.start*)
. = ALIGN(4);
KEEP(*(.init))
.tcm :
{
__ram_tcm_start__ = .;
__tcm_heap_start__ = .;
*(.tcm.heap)
} > TCM
/* init data */
. = ALIGN(4);
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
.soc_ps_monitor :
{
__tcm_heap_end__ = .;
} > TCM_TAB
. = ALIGN(4);
KEEP(*(.fini))
.image2.start.table :
{
__ram_heap1_end__ = .;
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
.image2.start.table1$$Base = .;
KEEP(*(SORT(.image2.ram.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
KEEP(*(.custom.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
*(.infra.ram.start*)
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
/* init data */
. = ALIGN(4);
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
*(.mon.ram.text*)
*(.hal.flash.text*)
*(.hal.sdrc.text*)
*(.hal.gpio.text*)
*(.fwu.text*)
*(.otg.rom.text*)
*(.text*)
*(.sdram.text*)
*(.p2p.text*)
*(.wps.text*)
*(.websocket.text*)
} > BD_RAM
. = ALIGN(4);
KEEP(*(.fini))
.ram_image2.rodata :
{
. = ALIGN(4);
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
*(.mon.ram.text*)
*(.hal.flash.text*)
*(.hal.sdrc.text*)
*(.hal.gpio.text*)
*(.fwu.text*)
*(.otg.rom.text*)
*(.text*)
*(.sdram.text*)
*(.p2p.text*)
*(.wps.text*)
*(.websocket.text*)
} > BD_RAM
.ram_image2.rodata :
{
*(.rodata*)
*(.fwu.rodata*)
*(.sdram.rodata*)
*(.p2p.rodata*)
*(.wps.rodata*)
*(.websocket.rodata*)
. = ALIGN(4);
xHeapRegions = .;
LONG(__ram_heap1_start__)
LONG(__ram_heap1_end__ - __ram_heap1_start__)
LONG(__ram_heap2_start__)
LONG(__ram_heap2_end__ - __ram_heap2_start__)
LONG(__sdram_heap_start__)
LONG(__sdram_heap_end__ - __sdram_heap_start__)
LONG(0)
LONG(0)
UartLogRamCmdTable = .;
KEEP(*(SORT(.mon.tab*)))
UartLogRamCmdTable_end = .;
LONG(0)
} > BD_RAM
PROVIDE(UartLogRamCmdTableSize = UartLogRamCmdTable_end - UartLogRamCmdTable);
*(.fwu.rodata*)
*(.sdram.rodata*)
*(.p2p.rodata*)
*(.wps.rodata*)
*(.websocket.rodata*)
. = ALIGN(4);
xHeapRegions = .;
LONG(__ram_heap1_start__)
LONG(__ram_heap1_end__ - __ram_heap1_start__)
LONG(__ram_heap2_start__)
LONG(__ram_heap2_end__ - __ram_heap2_start__)
LONG(__sdram_heap_start__)
LONG(__sdram_heap_end__ - __sdram_heap_start__)
LONG(0)
LONG(0)
UartLogRamCmdTable = .;
KEEP(*(SORT(.mon.tab*)))
UartLogRamCmdTable_end = .;
LONG(0)
} > BD_RAM
PROVIDE(UartLogRamCmdTableSize = UartLogRamCmdTable_end - UartLogRamCmdTable);
.ram.data :
{
__data_start__ = .;
*(.data*)
*(.p2p.data*)
*(.wps.data*)
*(.websocket.data*)
*(.sdram.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
} > BD_RAM
.ram.bss :
{
__bss_start__ = .;
.ram.bss$$Base = .;
*(.hal.flash.data*)
*(.hal.sdrc.data*)
*(.hal.gpio.data*)
*(.fwu.data*)
*(.bdsram.data*)
.ram.data :
{
__data_start__ = .;
*(.data*)
*(.p2p.data*)
*(.wps.data*)
*(.websocket.data*)
*(.sdram.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
} > BD_RAM
.ram.bss :
{
__bss_start__ = .;
.ram.bss$$Base = .;
*(.hal.flash.data*)
*(.hal.sdrc.data*)
*(.hal.gpio.data*)
*(.fwu.data*)
*(.bdsram.data*)
*(.bfsram.data*)
*(COMMON)
*(.bss*)
*(.sdram.bss*)
*(.p2p.bss*)
*(.wps.bss*)
*(.websocket.bss*)
*(.ssl_ram_map*)
__bss_end__ = .;
.ram.bss$$Limit = .;
} > BD_RAM
*(COMMON)
*(.bss*)
*(.sdram.bss*)
*(.p2p.bss*)
*(.wps.bss*)
*(.websocket.bss*)
*(.ssl_ram_map*)
__bss_end__ = .;
.ram.bss$$Limit = .;
} > BD_RAM
.ram_heap2 :
{
. = ALIGN(8);
__ram_heap2_start__ = .;
KEEP(*(.heap*)) /* ucHeap */
} > BD_RAM
__ram_heap2_end__ = 0x10070000;
.sdr_text :
{
__sdram_data_start__ = .;
} > SDRAM_RAM
.ram_heap2 :
{
. = ALIGN(8);
__ram_heap2_start__ = .;
*(.heap*) /* ucHeap */
} > BD_RAM
__ram_heap2_end__ = 0x10070000;
.sdr_text :
{
__sdram_data_start__ = .;
} > SDRAM_RAM
.sdr_rodata :
{
} > SDRAM_RAM
.sdr_rodata :
{
} > SDRAM_RAM
.sdr_data :
{
__sdram_data_end__ = .;
} > SDRAM_RAM
.sdr_data :
{
__sdram_data_end__ = .;
} > SDRAM_RAM
.sdr_bss :
{
__sdram_bss_start__ = .;
__sdram_bss_end__ = .;
. = ALIGN(8);
__sdram_heap_start__ = .;
} > SDRAM_RAM
__sdram_heap_end__ = 0x30200000;
.sdr_bss :
{
__sdram_bss_start__ = .;
__sdram_bss_end__ = .;
. = ALIGN(8);
__sdram_heap_start__ = .;
} > SDRAM_RAM
__sdram_heap_end__ = 0x30200000;
.boot.head :
{

5
RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/include/rtl_bios_data.h
View file

@ -12,6 +12,7 @@
#ifndef _RTL_BIOS_DATA_H_
#define _RTL_BIOS_DATA_H_
#include "platform_autoconf.h"
#include <stdarg.h>
#include <stddef.h>
#include <stdio.h>
@ -54,7 +55,7 @@ extern u32 ConfigDebugErr; // 10000314
/* ROM + hal_timer.h & .. */
extern HAL_TIMER_OP HalTimerOp; // 10000318
extern u16 GPIOState[11]; // 10000334 побитно 16 бит для каждого порта (A..K), бит=номер задействованного пина в порту на периферию.
extern u16 GPIOState[11]; // 10000334
extern u32 gTimerRecord; // 1000034C
/* ROM + hal_ssi.h */
extern u32 SSI_DBG_CONFIG; // 10000350
@ -167,7 +168,7 @@ extern RAM_START_FUNCTION gRamPatchWAKE; // 10000bcc = { RtlBootToSram + 1 };
extern RAM_START_FUNCTION gRamPatchFun0; // 10000bd0 = { RtlBootToSram + 1 };
extern RAM_START_FUNCTION gRamPatchFun1; // 10000bd4 = { RtlBootToSram + 1 };
extern RAM_START_FUNCTION gRamPatchFun2; // 10000bd8 = { RtlBootToSram + 1 };
extern uint8 RAM_IMG1_VALID_PATTEN[8]; // 10000bdc = { 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff };
//extern uint8 RAM_IMG1_VALID_PATTEN[8]; // 10000bdc = { 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff };
/* ROM + hal_sdr_controller.c */
extern u32 rand_x; // 10000be4: ChangeRandSeed_rom(), Sdr_Rand2_rom()

43
flasher.mk
View file

@ -55,8 +55,10 @@ FLASHER_SPEED = 500
endif
endif
# COMPILED_BOOT if defined -> extract image1, =1 boot head in elf, =2 boot head ?
#COMPILED_BOOT=1
# COMPILED_BOOT if defined -> extract image1, boot head in elf
COMPILED_BOOT=1
# COMPILED_BOOT_BIN if !defined -> use source startup boot
#COMPILED_BOOT_BIN=1
# PADDINGSIZE defined -> image2 OTA
PADDINGSIZE =44k
@ -64,6 +66,8 @@ NMAPFILE = $(OBJ_DIR)/$(TARGET).nmap
#FLASHER_PATH ?= flasher/
RAM_IMAGE?= $(BIN_DIR)/ram.bin
RAM1_IMAGE ?= $(BIN_DIR)/ram_1.bin
RAM1P_IMAGE ?= $(BIN_DIR)/ram_1.p.bin
@ -71,8 +75,8 @@ RAM2_IMAGE = $(BIN_DIR)/ram_2.bin
RAM2P_IMAGE = $(BIN_DIR)/ram_2.p.bin
RAM2NS_IMAGE = $(BIN_DIR)/ram_2.ns.bin
RAM3_IMAGE = $(BIN_DIR)/ram_3.bin
RAM3P_IMAGE = $(BIN_DIR)/ram_3.p.bin
RAM3_IMAGE = $(BIN_DIR)/sdram.bin
RAM3P_IMAGE = $(BIN_DIR)/sdram.p.bin
FLASH_IMAGE = $(BIN_DIR)/ram_all.bin
OTA_IMAGE = $(BIN_DIR)/ota.bin
@ -139,20 +143,19 @@ $(NMAPFILE): $(ELFFILE)
@$(NM) $< | sort > $@
# @echo "==========================================================="
$(FLASH_IMAGE): $(RAM1P_IMAGE) $(RAM2P_IMAGE) $(RAM3_IMAGE)
$(FLASH_IMAGE): $(RAM1P_IMAGE) $(RAM2P_IMAGE) $(RAM3P_IMAGE)
@echo "==========================================================="
@echo "Make Flash image ($(FLASH_IMAGE))"
# @echo "==========================================================="
@mkdir -p $(BIN_DIR)
@rm -f $(FLASH_IMAGE)
@if [ -s $(RAM3_IMAGE) ]; then $(PICK) 0x$(RAM3_START_ADDR) 0x$(RAM3_END_ADDR) $(RAM3_IMAGE) $(RAM3P_IMAGE) body+reset_offset; fi
@cat $(RAM1P_IMAGE) > $(FLASH_IMAGE)
# @chmod 777 $(FLASH_IMAGE)
ifdef PADDINGSIZE
@$(PADDING) $(PADDINGSIZE) 0xFF $(FLASH_IMAGE)
endif
@cat $(RAM2P_IMAGE) >> $(FLASH_IMAGE)
@if [ -s $(RAM3_IMAGE) ]; then cat $(RAM3P_IMAGE) >> $(FLASH_IMAGE); fi
@cat $(RAM3P_IMAGE) >> $(FLASH_IMAGE)
# @echo "Image ($(FLASH_IMAGE)) size $(shell printf '%d\n' $$(( $$(stat --printf="%s" $(FLASH_IMAGE)) )) ) bytes"
# @echo "==========================================================="
# @rm $(BIN_DIR)/ram_*.p.bin
@ -161,9 +164,8 @@ $(OTA_IMAGE): $(RAM2NS_IMAGE) $(RAM3_IMAGE)
@echo "==========================================================="
@echo "Make OTA image ($(OTA_IMAGE))"
@rm -f $(OTA_IMAGE)
@if [ -s $(RAM3_IMAGE) ]; then $(PICK) 0x$(RAM3_START_ADDR) 0x$(RAM3_END_ADDR) $(RAM3_IMAGE) $(RAM3P_IMAGE) body+reset_offset; fi
@cat $(RAM2NS_IMAGE) > $(OTA_IMAGE)
@if [ -s $(RAM3_IMAGE) ]; then cat $(RAM3P_IMAGE) >> $(OTA_IMAGE); fi
@cat $(RAM3P_IMAGE) >> $(OTA_IMAGE)
# @chmod 777 $(OTA_IMAGE)
@$(CHCKSUM) $(OTA_IMAGE) || true
# @echo "==========================================================="
@ -175,7 +177,7 @@ $(RAM1P_IMAGE): $(ELFFILE) $(NMAPFILE)
ifdef COMPILED_BOOT
@mkdir -p $(BIN_DIR)
@rm -f $(RAM1_IMAGE) $(RAM1P_IMAGE)
ifeq ($(COMPILED_BOOT),1)
ifdef COMPILED_BOOT_BIN
@$(eval RAM1_START_ADDR := $(shell grep _binary_build_bin_ram_1_r_bin_start $(NMAPFILE) | awk '{print $$1}'))
@$(eval RAM1_END_ADDR := $(shell grep _binary_build_bin_ram_1_r_bin_end $(NMAPFILE) | awk '{print $$1}'))
else
@ -185,13 +187,13 @@ endif
$(if $(RAM1_START_ADDR),,$(error "Not found __ram_image1_text_start__!"))
$(if $(RAM1_END_ADDR),,$(error "Not found __ram_image1_text_end__!"))
ifeq ($(RAM1_START_ADDR),$(RAM1_END_ADDR))
ifneq ($(COMPILED_BOOT),1)
$(OBJCOPY) -j .ram.start.table -j .ram_image1.text -Obinary $(ELFFILE) $(RAM1_IMAGE)
$(PICK) 0x$(RAM1_START_ADDR) 0x$(RAM1_END_ADDR) $(RAM1_IMAGE) $(RAM1P_IMAGE) body+reset_offset
else
ifdef COMPILED_BOOT_BIN
$(OBJCOPY) --change-section-address .boot.head=0x10000ba8 -j .boot.head -j .bootloader -Obinary $(ELFFILE) $(RAM1P_IMAGE)
else
$(OBJCOPY) -j .rom_ram -Obinary $(ELFFILE) $(RAM_IMAGE)
$(OBJCOPY) -j .ram.start.table -j .ram_image1.text -Obinary $(ELFFILE) $(RAM1_IMAGE)
$(PICK) 0x$(RAM1_START_ADDR) 0x$(RAM1_END_ADDR) $(RAM1_IMAGE) $(RAM1P_IMAGE) head+reset_offset 0x0B000
endif
$(warning "Flasher: Use external $(RAM1_IMAGE)?")
else
$(error "BOOT-image size = 0")
# $(error Flasher: COMPILE_BOOT = No)
@ -236,13 +238,14 @@ $(RAM3_IMAGE): $(ELFFILE) $(NMAPFILE)
@$(eval RAM3_END_ADDR = $(shell grep __sdram_data_ $(NMAPFILE) | grep _end__ | awk '{print $$1}'))
$(if $(RAM3_START_ADDR),,$(error "Not found __sdram_data_start__!"))
$(if $(RAM3_END_ADDR),,$(error "Not found __sdram_data_end__!"))
ifneq ($(RAM3_START_ADDR),$(RAM3_END_ADDR))
#ifneq ($(RAM3_START_ADDR),$(RAM3_END_ADDR))
@echo $(RAM3_START_ADDR) $(RAM3_END_ADDR)
@$(OBJCOPY) -j .image3 -j .sdr_text -j .sdr_rodata -j .sdr_data -Obinary $(ELFFILE) $(RAM3_IMAGE)
else
@rm -f $(RAM3_IMAGE) $(RAM3P_IMAGE)
@echo "SDRAM not used (size = 0)"
endif
$(PICK) 0x$(RAM3_START_ADDR) 0x$(RAM3_END_ADDR) $(RAM3_IMAGE) $(RAM3P_IMAGE) body+reset_offset
#else
# @rm -f $(RAM3_IMAGE) $(RAM3P_IMAGE)
# @echo "SDRAM not used (size = 0)"
#endif
$(ELFFILE):
$(error Falsher: file $@ not found)

2
flasher/RTL_RunRAM.JLinkScript
View file

@ -1,6 +1,6 @@
h
r
loadbin build/bin/ram_1.r.bin 0x10000bc8
loadbin build/bin/ram_1.bin 0x10000bc8
loadbin build/bin/ram_2.bin 0x10006000
r
w4 0x40000210,0x20200113

4
paths.mk
View file

@ -1,12 +1,12 @@
#---------------------------
# User defined
#---------------------------
SDK_PATH = RTL00_SDKV35a/
SDK_PATH = ../RTL00_SDKV35a/
#GCC_PATH = d:/MCU/GNU_Tools_ARM_Embedded/5.2_2015q4/bin/# + or set in PATH
#OPENOCD_PATH = d:/MCU/OpenOCD/bin/# + or set in PATH
TOOLS_PATH ?= $(SDK_PATH)component/soc/realtek/8195a/misc/iar_utility/common/tools/
FLASHER_PATH ?= flasher/
JLINK_PATH ?= D:/MCU/SEGGER/JLink_V612f/
JLINK_PATH ?= D:/MCU/SEGGER/JLink_V610a/
#---------------------------
# Default
#---------------------------

88
project/inc/lwipopts.h
View file

@ -26,7 +26,27 @@
#include <platform/platform_stdlib.h>
#include "platform_opts.h"
#define WIFI_LOGO_CERTIFICATION_CONFIG 0 //for ping 10k test buffer setting
/**
* LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first
* local TCP/UDP pcb (default==0). This can prevent creating predictable port
* numbers after booting a device.
*/
#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 1
#define WIFI_LOGO_CERTIFICATION_CONFIG 1 //for ping 10k test buffer setting
/**
* MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library
* instead of the lwip internal allocator. Can save code size if you
* already use it.
*/
#define MEM_LIBC_MALLOC 1
/**
* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator.
* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution
* speed and usage from interrupts!
*/
#define MEMP_MEM_MALLOC 1
/**
* SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
@ -124,34 +144,33 @@ a lot of data that needs to be copied, this should be set high. */
#define TCP_SND_QUEUELEN (4* TCP_SND_BUF/TCP_MSS)
/* TCP receive window. */
#define TCP_WND (2*TCP_MSS)
#define TCP_WND (4*TCP_MSS) // (2*TCP_MSS)
/* ---------- ICMP options ---------- */
#define LWIP_ICMP 1
#define LWIP_ICMP 1
/* ---------- ARP options ----------- */
#define LWIP_ARP 1
#define LWIP_ARP 1
/* ---------- DHCP options ---------- */
/* Define LWIP_DHCP to 1 if you want DHCP configuration of
interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
turning this on does currently not work. */
#define LWIP_DHCP 1
#define LWIP_DHCP 1
/* ---------- UDP options ---------- */
#define LWIP_UDP 1
#define UDP_TTL 255
#define LWIP_UDP 1
#define UDP_TTL 255
/* ---------- DNS options ---------- */
#define LWIP_DNS 1
#define LWIP_DNS 1
/* ---------- UPNP options --------- */
#define LWIP_UPNP 0
/* Support Multicast */
#define LWIP_IGMP 1
#define LWIP_RAND() rand()
#define LWIP_IGMP 1
#define LWIP_RAND() Rand()
/* Support TCP Keepalive */
#define LWIP_TCP_KEEPALIVE 1
@ -209,8 +228,8 @@ a lot of data that needs to be copied, this should be set high. */
#endif
/* ---------- Statistics options ---------- */
#define LWIP_STATS 0
#define LWIP_PROVIDE_ERRNO 1
#define LWIP_STATS 0
#define LWIP_PROVIDE_ERRNO 1
/*
@ -275,7 +294,7 @@ The STM32F2x7 allows computing and verifying the IP, UDP, TCP and ICMP checksums
/**
* LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
*/
#define LWIP_SOCKET 1
#define LWIP_SOCKET 1
/*
-----------------------------------
@ -285,20 +304,59 @@ The STM32F2x7 allows computing and verifying the IP, UDP, TCP and ICMP checksums
#define LWIP_DEBUG 0
/*
---------------------------------
---------- OS options ----------
---------------------------------
*/
/**
* TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread.
* The stack size value itself is platform-dependent, but is passed to
* sys_thread_new() when the thread is created.
*/
#define TCPIP_THREAD_STACKSIZE 1000
/**
* TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages
* The queue size value itself is platform-dependent, but is passed to
* sys_mbox_new() when tcpip_init is called.
*/
#define TCPIP_MBOX_SIZE 6
/**
* DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
* NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
* to sys_mbox_new() when the recvmbox is created.
*/
#define DEFAULT_UDP_RECVMBOX_SIZE 6
/**
* DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
* NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
* to sys_mbox_new() when the recvmbox is created.
*/
#define DEFAULT_TCP_RECVMBOX_SIZE 6
/**
* DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
* NETCONN_RAW. The queue size value itself is platform-dependent, but is passed
* to sys_mbox_new() when the recvmbox is created.
*/
#define DEFAULT_RAW_RECVMBOX_SIZE 6
/**
* DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
* The queue size value itself is platform-dependent, but is passed to
* sys_mbox_new() when the acceptmbox is created.
*/
#define DEFAULT_ACCEPTMBOX_SIZE 6
/**
* DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread.
* The stack size value itself is platform-dependent, but is passed to
* sys_thread_new() when the thread is created.
*/
#define DEFAULT_THREAD_STACKSIZE 500
/**
* TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread.
* The priority value itself is platform-dependent, but is passed to
* sys_thread_new() when the thread is created.
*/
#define TCPIP_THREAD_PRIO (configMAX_PRIORITIES - 2)
/** LWIP_TIMEVAL_PRIVATE: if you want to use the struct timeval provided

6
project/inc/platform_autoconf.h
View file

@ -5,6 +5,10 @@
#define RTL8710AF
//#define RTL8711AM
/* Image1 on project */
#define PRESENT_IMAGE1
/* Image2 on project */
#define PRESENT_IMAGE2
/*
* Target Platform Selection
*/
@ -24,7 +28,7 @@
#define RTL8195A 1
/* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz,
6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */
#define CONFIG_CPU_CLK 0
#define CONFIG_CPU_CLK 1
//166.6MHZ - RUN/IDLE/SLP ~63/21/6.4 mA
//83.3MHZ - RUN/IDLE/SLP ~55/15/6.4 mA
//41.6MHZ - RUN/IDLE ~51/11 mA

2
project/src/driver/console_api.c
View file

@ -6,7 +6,7 @@
*/
//======================================================
#define LOGUART_STACK_SIZE 400 // USE_MIN_STACK_SIZE modify from 512 to 128
#define CONSOLE_PRIORITY 1
#define CONSOLE_PRIORITY 0
//======================================================
#include "rtl8195a.h"
#include "rtl_bios_data.h"

17
project/src/driver/i2s_freertos.c
View file

@ -29,25 +29,28 @@ speed.
#include "queue.h"
#include "user/playerconfig.h"
#include "osdep_api.h"
#include "i2s_api.h"
#include "driver/i2s_freertos.h"
#define USE_RTL_I2S_API 0 // speed
PI2S_OBJS pi2s[MAX_I2S_OBJS]; // I2S0, I2S1
xSemaphoreHandle I2sTxSema;
// i2s interrupt callback
static void i2s_test_tx_complete(void *data, char *pbuf)
{
#if I2S_DEBUG_LEVEL > 1
i2s_t *i2s_obj = (i2s_t *)data;
int idx = i2s_obj->InitDat.I2SIdx;
#if I2S_DEBUG_LEVEL > 1
int reg = HAL_I2S_READ32(idx, REG_I2S_TX_PAGE0_OWN);
reg |= HAL_I2S_READ32(idx, REG_I2S_TX_PAGE1_OWN);
reg |= HAL_I2S_READ32(idx, REG_I2S_TX_PAGE2_OWN);
reg |= HAL_I2S_READ32(idx, REG_I2S_TX_PAGE3_OWN);
if(!(reg & BIT_PAGE_I2S_OWN_BIT)) pi2s[idx]->underrunCnt++;
#endif
if(!idx) xSemaphoreGive(I2sTxSema);
}
void i2sClose(int mask) {
@ -68,7 +71,10 @@ void i2sClose(int mask) {
}
vPortFree(pi2s[i]);
pi2s[i] = NULL;
if(i==0) HalPinCtrlRtl8195A(JTAG, 0, 1);
if(i==0) {
vSemaphoreDelete(I2sTxSema);
HalPinCtrlRtl8195A(JTAG, 0, 1);
}
DBG_8195A("I2S%d: Closed.\n", i);
}
}
@ -121,6 +127,8 @@ int i2sInit(int mask, int bufsize, int word_len) { // word_len = WL_16b or WL_24
if(i == 0) {
HalPinCtrlRtl8195A(JTAG, 0, 0);
i2s_init(pi2s_obj, I2S0_SCLK_PIN, I2S0_WS_PIN, I2S0_SD_PIN);
// Create a Semaphone
RtlInitSema(&I2sTxSema, 1);
}
else i2s_init(pi2s_obj, I2S1_SCLK_PIN, I2S1_WS_PIN, I2S1_SD_PIN);
i2s_set_param(pi2s_obj, pi2s_obj->channel_num, pi2s_obj->sampling_rate, pi2s_obj->word_length);
@ -185,11 +193,12 @@ u32 i2sPushPWMSamples(u32 sample) {
while(pi2s_cur->currDMABuff == NULL){
#if USE_RTL_I2S_API
pi2s_cur->currDMABuff = i2s_get_tx_page(&pi2s_cur->i2s_obj);
if(pi2s_cur->currDMABuff == NULL) vTaskDelay(I2S_DMA_PAGE_WAIT_MS_MIN);
if(pi2s_cur->currDMABuff == NULL) RtlDownSema(&I2sTxSema);
#else
u8 page_idx = HalI2SGetTxPage((VOID*)I2SAdapter->pInitDat);
if(page_idx < I2S_DMA_PAGE_NUM) pi2s_cur->currDMABuff = ((u32 *)I2SAdapter->TxPageList[page_idx]);
else vTaskDelay(I2S_DMA_PAGE_WAIT_MS_MIN);
else xSemaphoreTake(I2sTxSema, portMAX_DELAY);
// RtlDownSema(&I2sTxSema);
#endif
pi2s_cur->currDMABuffPos = 0;
}

15
project/src/user/atcmd_user.c
View file

@ -126,7 +126,7 @@ void fATWS(int argc, char *argv[]){
void fATST(void){
printf("\nCLK CPU\t\t%d Hz\nRAM heap\t%d bytes\nTCM heap\t%d bytes\n",
HalGetCpuClk(), xPortGetFreeHeapSize(), tcm_heap_freeSpace());
#if CONFIG_DEBUG_LOG > 1
#if 0 //CONFIG_DEBUG_LOG > 1
dump_mem_block_list();
tcm_heap_dump();
#endif;
@ -139,6 +139,19 @@ void fATST(void){
}
vPortFree(cBuffer);
#endif
#if defined(configUSE_TRACE_FACILITY) && (configUSE_TRACE_FACILITY == 1) && (configUSE_STATS_FORMATTING_FUNCTIONS == 1)
{
char * pcWriteBuffer = malloc(1024);
if(pcWriteBuffer) {
vTaskList((char*)pcWriteBuffer);
printf("\nTask List:\n");
printf("==============================\n");
printf("Name\t Status Priority HighWaterMark TaskNumber\n%s\n", pcWriteBuffer);
free(pcWriteBuffer);
}
}
#endif
}
void fATWC(int argc, char *argv[]){

8
project/src/user/main.c
View file

@ -36,11 +36,9 @@
#define DEBUG_MAIN_LEVEL 1
//Priorities of the reader and the decoder thread. Higher = higher prio. (ESP8266!)
//#define PRIO_READER (configMAX_PRIORITIES - 2) // (tskIDLE_PRIORITY + PRIORITIE_OFFSET)
//#define PRIO_MAD (PRIO_READER - 1) // PRIO_READER + n; (TCPIP_THREAD_PRIO = (configMAX_PRIORITIES - 2))
#define PRIO_MAD (tskIDLE_PRIORITY + 1 + PRIORITIE_OFFSET)
#define PRIO_READER (PRIO_MAD + 7) // max 11 ?
//Priorities of the reader and the decoder thread. Higher = higher prio.
#define PRIO_MAD (tskIDLE_PRIORITY + 3 + PRIORITIE_OFFSET)
#define PRIO_READER (PRIO_MAD + 1)
#define mMIN(a, b) ((a < b)? a : b)

184
readme.txt
View file

@ -1,140 +1,66 @@
MP3 stereo player V0004
MP3 stereo player V0005
PWM Out GC_2 and PE_2
RTL00 module (RTL8710AF)
Console:
# help
WLAN AT COMMAND SET:
>?
CONSOLE COMMAND SET:
==============================
Set MP3 server
# ATWS=URL,PATH,PORT
Sample: ATWS=icecast.omroep.nl/3fm-sb-mp3,80
ATWS=meuk.spritesserver.nl/Ii.Romanzeandante.mp3,80
ATWS=?, ATWS=close, ATWS=save, ATWS=read
Connect to an AES AP
# ATW0=SSID
# ATW1=PASSPHRASE
# ATWC
DisConnect AP
# ATWD
ATPN=<SSID>[,<PASSPHRASE>[,WEPKEY]]: WIFI Connect to AP
ATWS=<URL,PORT>: MP3 Connect to URL
ATWS=<c>[lose]: Close MP3
ATWS=<r>[ead]: Read MP3 URL
ATWS=<s>[ave]: Save MP3 URL
ATWS=<?>: URL Info
ATWD: WIFI Disconnect
ATST: Memory info
ATLW: Lwip Info
ATSB=<ADDRES(hex)>[,COUNT(dec)]: Dump byte register
ATSD=<ADDRES(hex)>[,COUNT(dec)]: Dump dword register
ATSW=<ADDRES(hex)>,<DATA(hex)>: Set register
ATDS=[TIME(ms)]: Deep sleep
ATON: Open connections
ATOF: Close connections
?: This Help
==============================
>atst
CLK CPU 83333333 Hz
RAM heap 22808 bytes
TCM heap 27928 bytes
# ATST
CLK CPU 166666666 Hz
RAM heap 16824 bytes
RAM free 5912 bytes
TCM heap 408 bytes
TCM ps_monitor 764 bytes
RAM Heap Memory List:
[0]=0x0x10052278, 0
[1]=0x0x10003010, 1984
[2]=0x0x100597a8, 272
[3]=0x0x1006aea0, 14568
TCM Free List:
prev 10052468, chunk 1fff5454, size 408
CPU total run time is 1995102
CPU total run time is 3980699
TaskName DeltaRunTime percentage
log_servi 0 <1%
tskmad 330 33%
IDLE 660 66%
Tmr Svc 0 <1%
TCP_IP 0 <1%
cmd_threa 0 <1%
rtw_check 0 <1%
log_uart 0 <1%
rtw_littl 0 <1%
rtw_recv_ 0 <1%
tskreader 0 <1%
rtw_inter 0 <1%
rtw_TDMA_ 0 <1%
rtw_xmit_ 0 <1%
loguart 3126 <1%
IDLE 809857 20%
Tmr Svc 322 <1%
TCP_IP 22486 <1%
rtw_xmit_ 3 <1%
cmd_threa 3380 <1%
rtw_check 0 <1%
rtw_littl 11151 <1%
rtw_inter 8980 <1%
rtw_recv_ 33723 <1%
tskmad 2988434 75%
tskreader 20133 <1%
rtw_TDMA_ 0 <1%
[MEM] After do cmd, available heap 16824+408
Task List:
==============================
Name Status Priority HighWaterMark TaskNumber
loguart R 4 218 2
IDLE R 0 36 3
Tmr Svc B 5 438 4
TCP_IP B 9 637 5
rtw_check B 5 219 11
tskreader B 8 130 54
rtw_TDMA_ B 7 219 12
rtw_littl B 10 439 10
rtw_inter B 6 209 8
rtw_recv_ B 5 891 6
tskmad B 7 106 55
rtw_xmit_ B 5 183 7
cmd_threa B 6 221 9
sdk-ameba-rtl8710af-v3.5a_without_NDA_GCC_V1.0.0.zip: readme.txt
###########################################################################################
###########################################################################################
####################RTL8710_GCC_VERSION_V1.0.0#############################################
###########################################################################################
GCC SDK RTL8710 basic version (including the window platform cygwin installation and Ubuntu platform Linux Installation routines),
including cross compilation of the installation, compile, link, run, debug, and so on.
SDK implementation of the function:
1, WiFi connection settings (including AP mode and STA mode).
2, peripheral resource control (including GPIO, SPI, UART, IIC, etc.).
3, the user uses the sample method.
SDK directory is as follows, please first read the document:
UM0096 Realtek Ameba-1 build environment setup - gcc.pdf
├── component
│   ├── common
│   │   ├── api
│   │   ├── application
│   │   ├── drivers
│   │   ├── example
│   │   ├── file_system
│   │   ├── mbed
│   │   ├── network
│   │   ├── test
│   │   └── utilities
│   ├── os
│   │   ├── freertos
│   │   └── os_dep
│   └── soc
│   └── realtek
├── doc
│   ├── AN0004 Realtek low power wi-fi mp user guide.pdf
│   ├── AN0011 Realtek wlan simple configuration.pdf
│   ├── AN0012 Realtek secure socket layer(ssl).pdf
│   ├── AN0025 Realtek at command.pdf
│   ├── AN0033 Realtek Ameba-1 over the air firmware update.pdf
│   ├── AN0038 Realtek googlenest user guide.pdf
│   ├── AN0043 Realtek mdns user guide.pdf
│   ├── AN0045 Realtek Ameba-1 power modes.pdf
│   ├── AN0046 Realtek Ameba uart adapter.pdf
│   ├── AN0049 Realtek Ameba WiGadget iot demo kit application note.pdf
│   ├── AN0075 Realtek Ameba-1 at command v2.0.pdf
│   ├── UM0006 Realtek wificonf application programming interface.pdf
│   ├── UM0014 Realtek web server user guide.pdf
│   ├── UM0023 Realtek Ameba-1 build environment setup - iar.pdf
│   ├── UM0027 Realtek Ameba-1 crypto engine.pdf
│   ├── UM0034 Realtek Ameba-1 memory layout.pdf
│   ├── UM0039 Realtek Ameba-1 SDK quick start.pdf
│   └── UM0096 Realtek Ameba-1 build environment setup - gcc.pdf
├── project
│   └── realtek_ameba1_va0_example
│   ├── example_sources
│   ├── GCC-RELEASE
│   ├── inc
│   └── src
├── release_note.txt
└── tools
├── arm-none-eabi-gcc
│   ├── 4.8.3-2014q1
│   ├── 4.8.3-2014q1.tar.gz
│   └── gcc-arm-none-eabi-4_8-2014q1-20140314-linux.tar.bz2
├── autopatch
│   └── auto_patch.bat
├── DownloadServer
│   ├── DownloadServer.exe
│   ├── readme.txt
│   └── start.bat
├── file_check_sum
│   └── file_checksum.c
├── iperf.exe
├── serial_to_usb
│   └── mbedWinSerial_16466.zip
├── simple_config_wizard
│   ├── Android
│   └── iOS
├── simple_config_wizard_3.4b
│   ├── Android
│   └── iOS
├── uart_adapter
│   └── app
└── wigadget
├── Android
└── iOS
sdk-v3.5a+

10
sdkbuild.mk
View file

@ -48,15 +48,15 @@ application: build_info $(SRC_O) $(DRAM_O)
@echo "Make BootLoader (ram_1.p.bin, ram_1.r.bin)"
# @echo "==========================================================="
@mkdir -p $(BIN_DIR) $(OBJ_DIR)
@cp $(patsubst sdk/%,$(SDK_PATH)%,$(BOOTS))/ram_1.r.bin $(BIN_DIR)/ram_1.r.bin
@cp $(patsubst sdk/%,$(SDK_PATH)%,$(BOOTS))/ram_1.p.bin $(BIN_DIR)/ram_1.p.bin
## @cp $(patsubst sdk/%,$(SDK_PATH)%,$(BOOTS))/ram_1.r.bin $(BIN_DIR)/ram_1.r.bin
## @cp $(patsubst sdk/%,$(SDK_PATH)%,$(BOOTS))/ram_1.p.bin $(BIN_DIR)/ram_1.p.bin
# @chmod 777 $(OBJ_DIR)/ram_1.r.bin
$(OBJCOPY) --rename-section .data=.loader.data,contents,alloc,load,readonly,data -I binary -O elf32-littlearm -B arm $(BIN_DIR)/ram_1.r.bin $(OBJ_DIR)/ram_1.r.o
## $(OBJCOPY) --rename-section .data=.loader.data,contents,alloc,load,readonly,data -I binary -O elf32-littlearm -B arm $(BIN_DIR)/ram_1.r.bin $(OBJ_DIR)/ram_1.r.o
@echo "==========================================================="
@echo "Link ($(TARGET))"
# @echo "==========================================================="
@$(file > $(OBJ_DIR)/obj_list.lst,$(OBJ_LIST))
@$(LD) $(LFLAGS) -o $(ELFFILE) @$(OBJ_DIR)/obj_list.lst $(OBJ_DIR)/ram_1.r.o $(LIBFLAGS) -T$(LDFILE)
## @$(LD) $(LFLAGS) -o $(ELFFILE) $(OBJ_LIST) $(OBJ_DIR)/ram_1.r.o $(LIBFLAGS) -T$(LDFILE)
@$(LD) $(LFLAGS) -o $(ELFFILE) $(OBJ_LIST) $(LIBFLAGS) -T$(LDFILE)
@$(OBJDUMP) -d $(ELFFILE) > $(OBJ_DIR)/$(TARGET).asm
.PHONY: prerequirement

263
sdkset.mk
View file

@ -4,15 +4,17 @@ CFLAGS = -DM3 -DCONFIG_PLATFORM_8195A -DGCC_ARMCM3 -DARDUINO_SDK -DF_CPU=1666666
CFLAGS += -mcpu=cortex-m3 -mthumb -g2 -Os -std=gnu99
CFLAGS += -fno-common -fmessage-length=0 -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-short-enums -fsigned-char
CFLAGS += -w -Wno-pointer-sign
LFLAGS = -mcpu=cortex-m3 -mthumb -g -Os --specs=nano.specs -nostartfiles
LFLAGS += -Wl,--gc-sections -Wl,--cref -Wl,--entry=Reset_Handler -Wl,--no-enum-size-warning -Wl,--no-wchar-size-warning
LFLAGS = -mcpu=cortex-m3 -mthumb -g -Os -nostartfiles -nostdlib
#--specs=nano.specs
LFLAGS += -Wl,--gc-sections -Wl,--cref -Wl,--entry=Reset_Handler -Wl,--no-enum-size-warning -Wl,--no-wchar-size-warning -Wl,-nostdlib
# LIBS
# -------------------------------------------------------------------
LIBS =
all: LIBS +=_platform_new _wlan _p2p _wps _rtlstd _websocket _sdcard _xmodem _mdns m c nosys gcc
mp: LIBS +=_platform_new _wlan_mp _p2p _wps _rtlstd _websocket _sdcard _xmodem _mdns m c nosys gcc
PATHLIBS = sdk/component/soc/realtek/8195a/misc/bsp/lib/common/GCC
all: LIBS +=_platform_new _wlan
# _mdns m c nosys gcc _wps _p2p _websocket _sdcard _xmodem
mp: LIBS +=_platform_new _wlan_mp
PATHLIBS = sdk/component/soc/realtek/8195a/misc/bsp/lib/common/gcc
LDFILE = rlx8195A-symbol-v04-img2.ld
BOOTS = sdk/component/soc/realtek/8195a/misc/bsp/image
@ -51,7 +53,7 @@ INCLUDES += sdk/component/soc/realtek/8195a/cmsis
INCLUDES += sdk/component/soc/realtek/8195a/cmsis/device
INCLUDES += sdk/component/soc/realtek/8195a/fwlib
INCLUDES += sdk/component/soc/realtek/8195a/fwlib/rtl8195a
INCLUDES += sdk/component/soc/realtek/8195a/misc/rtl_std_lib
INCLUDES += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/
INCLUDES += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/include
INCLUDES += sdk/component/common/drivers
INCLUDES += sdk/component/common/drivers/wlan/realtek/include
@ -63,7 +65,6 @@ INCLUDES += sdk/component/soc/realtek/8195a/fwlib/ram_lib/wlan/realtek/wlan_ram_
INCLUDES += sdk/component/common/network/ssl/polarssl-1.3.8/include
INCLUDES += sdk/component/common/network/ssl/ssl_ram_map/rom
INCLUDES += sdk/component/common/utilities
INCLUDES += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/include
INCLUDES += sdk/component/common/application/apple/WACServer/External/Curve25519
INCLUDES += sdk/component/common/application/apple/WACServer/External/GladmanAES
INCLUDES += sdk/component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include
@ -80,27 +81,22 @@ INCLUDES += sdk/component/common/application/xmodem
# -------------------------------------------------------------------
SRC_C =
DRAM_C =
#std_lib
SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_libc.c
SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_libgloss_retarget.c
SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/rtl_eabi_cast_ram.c
SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/rtl_math_ram.c
#cmsis
SRC_C += sdk/component/soc/realtek/8195a/cmsis/device/system_8195a.c
#console
#SRC_C += sdk/component/common/api/at_cmd/atcmd_ethernet.c
#SRC_C += sdk/component/common/api/at_cmd/atcmd_lwip.c
#SRC_C += sdk/component/common/api/at_cmd/atcmd_sys.c
#SRC_C += sdk/component/common/api/at_cmd/atcmd_wifi.c
#SRC_C += sdk/component/common/api/at_cmd/log_service.c
SRC_C += sdk/component/soc/realtek/8195a/misc/driver/low_level_io.c
DRAM_C += sdk/component/common/api/at_cmd/atcmd_ethernet.c
DRAM_C += sdk/component/common/api/at_cmd/atcmd_lwip.c
DRAM_C += sdk/component/common/api/at_cmd/atcmd_sys.c
DRAM_C += sdk/component/common/api/at_cmd/atcmd_wifi.c
SRC_C += sdk/component/common/api/at_cmd/log_service.c
#SRC_C += sdk/component/soc/realtek/8195a/misc/driver/low_level_io.c
#SRC_C += sdk/component/soc/realtek/8195a/misc/driver/rtl_consol.c
#network - api
SRC_C += sdk/component/common/api/wifi/rtw_wpa_supplicant/wpa_supplicant/wifi_eap_config.c
SRC_C += sdk/component/common/api/wifi/rtw_wpa_supplicant/wpa_supplicant/wifi_p2p_config.c
SRC_C += sdk/component/common/api/wifi/rtw_wpa_supplicant/wpa_supplicant/wifi_wps_config.c
#SRC_C += sdk/component/common/api/wifi/rtw_wpa_supplicant/wpa_supplicant/wifi_p2p_config.c
#SRC_C += sdk/component/common/api/wifi/rtw_wpa_supplicant/wpa_supplicant/wifi_wps_config.c
SRC_C += sdk/component/common/api/wifi/wifi_conf.c
SRC_C += sdk/component/common/api/wifi/wifi_ind.c
SRC_C += sdk/component/common/api/wifi/wifi_promisc.c
@ -109,12 +105,12 @@ SRC_C += sdk/component/common/api/wifi/wifi_util.c
SRC_C += sdk/component/common/api/lwip_netconf.c
#network - app
SRC_C += sdk/component/common/utilities/ssl_client.c
SRC_C += sdk/component/common/utilities/ssl_client_ext.c
#SRC_C += sdk/component/common/utilities/ssl_client.c
#SRC_C += sdk/component/common/utilities/ssl_client_ext.c
SRC_C += sdk/component/common/utilities/tcptest.c
SRC_C += sdk/component/common/utilities/uart_ymodem.c
SRC_C += sdk/component/common/utilities/update.c
SRC_C += sdk/component/common/application/uart_adapter/uart_adapter.c
#SRC_C += sdk/component/common/application/uart_adapter/uart_adapter.c
SRC_C += sdk/component/common/api/network/src/wlan_network.c
SRC_C += sdk/component/common/api/wifi_interactive_mode.c
SRC_C += sdk/component/common/api/network/src/ping_test.c
@ -158,10 +154,9 @@ SRC_C += sdk/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c
SRC_C += sdk/component/common/network/lwip/lwip_v1.4.1/port/realtek/freertos/sys_arch.c
SRC_C += sdk/component/common/network/dhcp/dhcps.c
SRC_C += sdk/component/common/network/sntp/sntp.c
SRC_C += sdk/component/common/network/netbios/netbios.c
#network - mdns
SRC_C += sdk/component/common/network/mDNS/mDNSPlatform.c
#SRC_C += sdk/component/common/network/mDNS/mDNSPlatform.c
#os - freertos
SRC_C += sdk/component/os/freertos/freertos_v8.1.2/Source/portable/MemMang/heap_5.c
@ -186,29 +181,29 @@ SRC_C += sdk/component/os/os_dep/tcm_heap.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/analogin_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/dma_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/efuse_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/ethernet_api.c
#SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/ethernet_api.c
#SRC_C += sdk/component/common/drivers/ethernet_mii/ethernet_mii.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/flash_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/gpio_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/gpio_irq_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/i2c_api.c
#SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/i2c_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/i2s_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/log_uart_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/nfc_api.c
#SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/log_uart_api.c
#SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/nfc_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/pinmap.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/pinmap_common.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/port_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/pwmout_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/rtc_api.c
#SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/port_api.c
#SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/pwmout_api.c
#SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/rtc_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/serial_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/sleep.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/spdio_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/spi_api.c
#SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/spdio_api.c
#SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/spi_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/sys_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/timer_api.c
#SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/timer_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/us_ticker.c
SRC_C += sdk/component/common/mbed/common/us_ticker_api.c
SRC_C += sdk/component/common/mbed/common/wait_api.c
#SRC_C += sdk/component/common/mbed/common/wait_api.c
SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/wdt_api.c
#peripheral - hal
@ -216,14 +211,14 @@ SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_32k.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_adc.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_gdma.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_gpio.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_i2c.c
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_i2c.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_i2s.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_mii.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_nfc.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_pcm.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_pwm.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_ssi.c
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_mii.c
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_nfc.c
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_pcm.c
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_pwm.c
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_ssi.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_timer.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_uart.c
@ -234,12 +229,12 @@ SRC_C += sdk/component/os/freertos/freertos_pmu.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_adc.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gpio.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_i2c.c
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_i2c.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_i2s.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_mii.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_nfc.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pwm.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_mii.c
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_nfc.c
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pwm.c
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_timer.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c
@ -247,85 +242,85 @@ SRC_C += sdk/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c
#SRC_C += sdk/component/common/drivers/wlan/realtek/src/core/option/rtw_opt_skbuf.c
#SDRAM
DRAM_C += sdk/component/common/api/platform/stdlib_patch.c
#DRAM_C += sdk/component/common/api/platform/stdlib_patch.c
#SDRAM - polarssl
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/aes.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/aesni.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/arc4.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/asn1parse.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/asn1write.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/base64.c
SRC_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/bignum.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/blowfish.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/camellia.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ccm.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/certs.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/cipher.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/cipher_wrap.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ctr_drbg.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/debug.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/des.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/dhm.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ecp.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ecp_curves.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ecdh.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ecdsa.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/entropy.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/entropy_poll.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/error.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/gcm.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/havege.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/hmac_drbg.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/md.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/md_wrap.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/md2.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/md4.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/md5.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/memory_buffer_alloc.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/net.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/oid.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/padlock.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pbkdf2.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pem.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pkcs5.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pkcs11.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pkcs12.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pk.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pk_wrap.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pkparse.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pkwrite.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/platform.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ripemd160.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/rsa.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/sha1.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/sha256.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/sha512.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ssl_cache.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ssl_ciphersuites.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ssl_cli.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ssl_srv.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ssl_tls.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/threading.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/timing.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/version.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/version_features.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/x509.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/x509_crt.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/x509_crl.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/x509_csr.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/x509_create.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/x509write_crt.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/x509write_csr.c
DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/xtea.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/aes.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/aesni.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/arc4.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/asn1parse.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/asn1write.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/base64.c
#SRC_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/bignum.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/blowfish.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/camellia.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ccm.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/certs.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/cipher.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/cipher_wrap.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ctr_drbg.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/debug.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/des.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/dhm.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ecp.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ecp_curves.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ecdh.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ecdsa.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/entropy.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/entropy_poll.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/error.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/gcm.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/havege.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/hmac_drbg.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/md.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/md_wrap.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/md2.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/md4.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/md5.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/memory_buffer_alloc.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/net.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/oid.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/padlock.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pbkdf2.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pem.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pkcs5.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pkcs11.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pkcs12.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pk.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pk_wrap.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pkparse.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/pkwrite.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/platform.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ripemd160.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/rsa.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/sha1.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/sha256.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/sha512.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ssl_cache.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ssl_ciphersuites.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ssl_cli.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ssl_srv.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/ssl_tls.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/threading.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/timing.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/version.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/version_features.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/x509.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/x509_crt.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/x509_crl.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/x509_csr.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/x509_create.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/x509write_crt.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/x509write_csr.c
#DRAM_C += sdk/component/common/network/ssl/polarssl-1.3.8/library/xtea.c
#SDRAM - ssl_ram_map
DRAM_C += sdk/component/common/network/ssl/ssl_ram_map/rom/rom_ssl_ram_map.c
DRAM_C += sdk/component/common/network/ssl/ssl_ram_map/ssl_ram_map.c
#SDRAM - wigadget
DRAM_C += sdk/component/common/application/wigadget/cloud_link.c
DRAM_C += sdk/component/common/application/wigadget/shtc1.c
DRAM_C += sdk/component/common/application/wigadget/wigadget.c
#DRAM_C += sdk/component/common/application/wigadget/cloud_link.c
#DRAM_C += sdk/component/common/application/wigadget/shtc1.c
#DRAM_C += sdk/component/common/application/wigadget/wigadget.c
#utilities
SRC_C += sdk/component/common/utilities/cJSON.c
@ -359,23 +354,32 @@ ADD_SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_efuse.c
ADD_SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_log_uart.c
ADD_SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_pinmux.c
ADD_SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_misc.c
ADD_SRC_C += sdk/component/soc/realtek/8195a/fwlib/ram_lib/startup.c
ADD_SRC_C += sdk/component/common/drivers/sdio/realtek/sdio_host/src/sd.c
ADD_SRC_C += sdk/component/common/drivers/sdio/realtek/sdio_host/src/sdio_host.c
ADD_SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_sdio_host.c
#ADD_SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_spi_flash_ram.c
# COMPONENTS
ADD_SRC_C += sdk/component/soc/realtek/8195a/fwlib/ram_lib/startup.c
ADD_SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/flash_eep.c
ADD_SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_libc.c
ADD_SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_pvvx_libc.c
ADD_SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_libgloss_retarget.c
ADD_SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/rtl_eabi_cast_ram.c
ADD_SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/rtl_math_ram.c
ADD_SRC_C += component/soc/realtek/8195a/fwlib/ram_lib/rtl_bios_data.c
ADD_SRC_C += component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c
# -------------------------------------------------------------------
# SAMPLES
# -------------------------------------------------------------------
ADD_SRC_C += sdk/component/common/example/cJSON/cJSON_example.c
ADD_SRC_C += sdk/component/common/example/googlenest/example_google.c
ADD_SRC_C += sdk/component/common/example/mdns/example_mdns.c
ADD_SRC_C += sdk/component/common/example/socket_select/example_socket_select.c
#ADD_SRC_C += sdk/component/common/example/cJSON/cJSON_example.c
#ADD_SRC_C += sdk/component/common/example/googlenest/example_google.c
#ADD_SRC_C += sdk/component/common/example/mdns/example_mdns.c
#ADD_SRC_C += sdk/component/common/example/socket_select/example_socket_select.c
ADD_SRC_C += sdk/component/common/example/uart_atcmd/example_uart_atcmd.c
ADD_SRC_C += sdk/component/common/example/wlan_fast_connect/example_wlan_fast_connect.c
ADD_SRC_C += sdk/component/common/example/xml/example_xml.c
#ADD_SRC_C += sdk/component/common/example/xml/example_xml.c
ADD_SRC_C += sdk/component/common/example/example_entry.c
#ADD_SRC_C += sdk/component/common/drivers/sdio/realtek/sdio_host/src/sd.c
#ADD_SRC_C += sdk/component/common/drivers/sdio/realtek/sdio_host/src/sdio_host.c
#ADD_SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_sdio_host.c
#ADD_SRC_C += sdk/component/common/file_system/fatfs/disk_if/src/sdcard.c
#=============================================
# PROGECT
#=============================================
@ -401,7 +405,6 @@ ADD_SRC_C += project/src/mad/stream.c
#driver
ADD_SRC_C += project/src/driver/i2s_freertos.c
#ADD_SRC_C += project/src/driver/wifi_api.c
ADD_SRC_C += project/src/driver/console_api.c
#include