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fix clk cpu

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pvvx 2017-03-10 01:40:25 +03:00
parent affec14b99
commit b976c62423
7 changed files with 4 additions and 4 deletions
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6
RTL00_SDKV35a/component/common/mbed/common/wait_api.c
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@ -94,14 +94,14 @@ void wait_us(int us) { // До 2.147483648 секунды!
uint32_t start; uint32_t start;
#ifdef WAIT_US_USE_CYCCNT #ifdef WAIT_US_USE_CYCCNT
if(us < 1) return; if(us < 1) return;
if (us < 255) { // G-timer resolution is ~31 us (1/32K), use DWT->CYCCNT... if (us < 327) { // G-timer resolution is ~31 us (1/32K), use DWT->CYCCNT...
if(!(DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk)) { // уже включен? if(!(DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk)) { // уже включен?
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; // открыть доступ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; // открыть доступ
DWT->CYCCNT = 0; // обнулить и запустить DWT->CYCCNT = 0; // обнулить и запустить
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; // запустить счет DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; // запустить счет
} }
start = DWT->CYCCNT + us * ( PLATFORM_CLOCK / 1000000 ); start = DWT->CYCCNT + us * (PLATFORM_CLOCK / 1000000ul);
while ( ( ( int32_t )DWT->CYCCNT - start) < 0 ); while ((int32_t)(start - DWT->CYCCNT) > 0);
} }
else else
#endif #endif

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build/bin/ota.bin
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build/bin/ram_2.bin
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build/bin/ram_2.ns.bin
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build/bin/ram_2.p.bin
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build/bin/ram_all.bin
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2
project/inc/platform_autoconf.h
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@ -246,6 +246,6 @@
#if CPU__CLK_DIV5_3 #if CPU__CLK_DIV5_3
#define PLATFORM_CLOCK (200000000ul>>CPU_CLOCK_SEL_VALUE) #define PLATFORM_CLOCK (200000000ul>>CPU_CLOCK_SEL_VALUE)
#else #else
#define PLATFORM_CLOCK (((200000000ul*5ul)/3ul)>>CPU_CLOCK_SEL_VALUE) #define PLATFORM_CLOCK (((200000000ul*5ul)/6ul)>>CPU_CLOCK_SEL_VALUE)
#endif #endif