diff --git a/RTL00_SDKV35a/component/common/mbed/targets/hal/rtl8195a/i2c_api.c b/RTL00_SDKV35a/component/common/mbed/targets/hal/rtl8195a/i2c_api.c index ae6b31c..6d1ed3e 100644 --- a/RTL00_SDKV35a/component/common/mbed/targets/hal/rtl8195a/i2c_api.c +++ b/RTL00_SDKV35a/component/common/mbed/targets/hal/rtl8195a/i2c_api.c @@ -88,7 +88,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { i2c_sel = (uint32_t)pinmap_merge(i2c_sda, i2c_scl); i2c_idx = RTL_GET_PERI_IDX(i2c_sel); if (unlikely(i2c_idx == NC)) { - DBG_8195A("%s: Cannot find matched UART\n", __FUNCTION__); + DBG_8195A("%s: Cannot find matched port i2c\n", __FUNCTION__); return; } @@ -184,7 +184,6 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { pSalI2CMngtAdpt->InnerTimeOut = pSalI2CHND->TimeOut; - /* Deinit I2C first */ //i2c_reset(obj); @@ -200,8 +199,6 @@ void i2c_frequency(i2c_t *obj, int hz) { uint16_t i2c_default_clk = (uint16_t) pSalI2CHND->I2CClk; uint16_t i2c_user_clk = (uint16_t) (hz/1000); - - if (i2c_default_clk != i2c_user_clk) { /* Deinit I2C first */ diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_i2c.h b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_i2c.h index 5e70828..5659f77 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_i2c.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_i2c.h @@ -17,9 +17,9 @@ // I2C SAL User Configuration Flags // I2C SAL operation types -#define I2C_POLL_OP_TYPE 1 -#define I2C_INTR_OP_TYPE 1 -#define I2C_DMA_OP_TYPE 1 +#define I2C_POLL_OP_TYPE 1 //1 +#define I2C_INTR_OP_TYPE 1 //1 +#define I2C_DMA_OP_TYPE 1 //1 // I2C supports user register address #define I2C_USER_REG_ADDR 1 //I2C User specific register address by using diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h index 293635f..bf6190f 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h @@ -739,49 +739,49 @@ #define BIT_GET_IC_COMP_TYPE(x) (((x) >> BIT_SHIFT_IC_COMP_TYPE) & BIT_MASK_IC_COMP_TYPE) //======================== Register Address Definition ======================== -#define REG_DW_I2C_IC_CON 0x0000 -#define REG_DW_I2C_IC_TAR 0x0004 -#define REG_DW_I2C_IC_SAR 0x0008 -#define REG_DW_I2C_IC_HS_MADDR 0x000C -#define REG_DW_I2C_IC_DATA_CMD 0x0010 -#define REG_DW_I2C_IC_SS_SCL_HCNT 0x0014 -#define REG_DW_I2C_IC_SS_SCL_LCNT 0x0018 -#define REG_DW_I2C_IC_FS_SCL_HCNT 0x001C -#define REG_DW_I2C_IC_FS_SCL_LCNT 0x0020 -#define REG_DW_I2C_IC_HS_SCL_HCNT 0x0024 -#define REG_DW_I2C_IC_HS_SCL_LCNT 0x0028 -#define REG_DW_I2C_IC_INTR_STAT 0x002C -#define REG_DW_I2C_IC_INTR_MASK 0x0030 -#define REG_DW_I2C_IC_RAW_INTR_STAT 0x0034 -#define REG_DW_I2C_IC_RX_TL 0x0038 -#define REG_DW_I2C_IC_TX_TL 0x003C -#define REG_DW_I2C_IC_CLR_INTR 0x0040 -#define REG_DW_I2C_IC_CLR_RX_UNDER 0x0044 -#define REG_DW_I2C_IC_CLR_RX_OVER 0x0048 -#define REG_DW_I2C_IC_CLR_TX_OVER 0x004C -#define REG_DW_I2C_IC_CLR_RD_REQ 0x0050 -#define REG_DW_I2C_IC_CLR_TX_ABRT 0x0054 -#define REG_DW_I2C_IC_CLR_RX_DONE 0x0058 -#define REG_DW_I2C_IC_CLR_ACTIVITY 0x005C -#define REG_DW_I2C_IC_CLR_STOP_DET 0x0060 -#define REG_DW_I2C_IC_CLR_START_DET 0x0064 -#define REG_DW_I2C_IC_CLR_GEN_CALL 0x0068 -#define REG_DW_I2C_IC_ENABLE 0x006C -#define REG_DW_I2C_IC_STATUS 0x0070 -#define REG_DW_I2C_IC_TXFLR 0x0074 -#define REG_DW_I2C_IC_RXFLR 0x0078 -#define REG_DW_I2C_IC_SDA_HOLD 0x007C -#define REG_DW_I2C_IC_TX_ABRT_SOURCE 0x0080 -#define REG_DW_I2C_IC_SLV_DATA_NACK_ONLY 0x0084 -#define REG_DW_I2C_IC_DMA_CR 0x0088 -#define REG_DW_I2C_IC_DMA_TDLR 0x008C -#define REG_DW_I2C_IC_DMA_RDLR 0x0090 -#define REG_DW_I2C_IC_SDA_SETUP 0x0094 -#define REG_DW_I2C_IC_ACK_GENERAL_CALL 0x0098 -#define REG_DW_I2C_IC_ENABLE_STATUS 0x009C -#define REG_DW_I2C_IC_COMP_PARAM_1 0x00F4 -#define REG_DW_I2C_IC_COMP_VERSION 0x00F8 -#define REG_DW_I2C_IC_COMP_TYPE 0x00FC +#define REG_DW_I2C_IC_CON 0x0000 // Control Register +#define REG_DW_I2C_IC_TAR 0x0004 // Master Target Address +#define REG_DW_I2C_IC_SAR 0x0008 // Slave Address +#define REG_DW_I2C_IC_HS_MADDR 0x000C // High Speed Master ID +#define REG_DW_I2C_IC_DATA_CMD 0x0010 // Data Buffer and Command +#define REG_DW_I2C_IC_SS_SCL_HCNT 0x0014 // Standard Speed Clock SCL High Count +#define REG_DW_I2C_IC_SS_SCL_LCNT 0x0018 // Standard Speed Clock SCL Low Count +#define REG_DW_I2C_IC_FS_SCL_HCNT 0x001C // Fast Speed Clock SCL High Count +#define REG_DW_I2C_IC_FS_SCL_LCNT 0x0020 // Fast Speed I2C Clock SCL Low Count +#define REG_DW_I2C_IC_HS_SCL_HCNT 0x0024 // High Speed I2C Clock SCL High Count +#define REG_DW_I2C_IC_HS_SCL_LCNT 0x0028 // High Speed I2C Clock SCL Low Count +#define REG_DW_I2C_IC_INTR_STAT 0x002C // Interrupt Status +#define REG_DW_I2C_IC_INTR_MASK 0x0030 // Interrupt Mask +#define REG_DW_I2C_IC_RAW_INTR_STAT 0x0034 // Raw Interrupt Status +#define REG_DW_I2C_IC_RX_TL 0x0038 // Receive FIFO Threshold Level +#define REG_DW_I2C_IC_TX_TL 0x003C // Transmit FIFO Threshold Level +#define REG_DW_I2C_IC_CLR_INTR 0x0040 // Clear Combined and Individual Interrupt +#define REG_DW_I2C_IC_CLR_RX_UNDER 0x0044 // Clear RX_UNDER Interrupt +#define REG_DW_I2C_IC_CLR_RX_OVER 0x0048 // Clear RX_OVER Interrupt +#define REG_DW_I2C_IC_CLR_TX_OVER 0x004C // Clear TX_OVER Interrupt +#define REG_DW_I2C_IC_CLR_RD_REQ 0x0050 // Clear RD_REQ Interrupt +#define REG_DW_I2C_IC_CLR_TX_ABRT 0x0054 // Clear TX_ABRT Interrupt +#define REG_DW_I2C_IC_CLR_RX_DONE 0x0058 // Clear RX_DONE Interrupt +#define REG_DW_I2C_IC_CLR_ACTIVITY 0x005C // Clear ACTIVITY Interrupt +#define REG_DW_I2C_IC_CLR_STOP_DET 0x0060 // Clear STOP_DET Interrupt +#define REG_DW_I2C_IC_CLR_START_DET 0x0064 // Clear START_DET Interrupt +#define REG_DW_I2C_IC_CLR_GEN_CALL 0x0068 // Clear GEN_CALL Interrupt +#define REG_DW_I2C_IC_ENABLE 0x006C // Enable +#define REG_DW_I2C_IC_STATUS 0x0070 // Status +#define REG_DW_I2C_IC_TXFLR 0x0074 // Transmit FIFO Level +#define REG_DW_I2C_IC_RXFLR 0x0078 // Receive FIFO Level +#define REG_DW_I2C_IC_SDA_HOLD 0x007C // SDA Hold +#define REG_DW_I2C_IC_TX_ABRT_SOURCE 0x0080 // Transmit Abort Source +#define REG_DW_I2C_IC_SLV_DATA_NACK_ONLY 0x0084 // +#define REG_DW_I2C_IC_DMA_CR 0x0088 // +#define REG_DW_I2C_IC_DMA_TDLR 0x008C // DMA Transmit Data Level Register +#define REG_DW_I2C_IC_DMA_RDLR 0x0090 // I2C Receive Data Level Register +#define REG_DW_I2C_IC_SDA_SETUP 0x0094 // SDA Setup +#define REG_DW_I2C_IC_ACK_GENERAL_CALL 0x0098 // General Call Ack +#define REG_DW_I2C_IC_ENABLE_STATUS 0x009C // Enable Status +#define REG_DW_I2C_IC_COMP_PARAM_1 0x00F4 // Configuration Parameters +#define REG_DW_I2C_IC_COMP_VERSION 0x00F8 // Component Version +#define REG_DW_I2C_IC_COMP_TYPE 0x00FC // Component Type //====================================================== // I2C related enumeration diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/export-rom_v04.txt b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/export-rom_v04.txt index d9fd885..6d0a421 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/export-rom_v04.txt +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/export-rom_v04.txt @@ -240,6 +240,7 @@ SECTIONS RtkI2CDeInit = 0xbe4d; RtkI2CSendUserAddr = 0xbee5; RtkI2CSend = 0xc07d; + _RtkI2CReceive = 0x0c6dd; RtkI2CLoadDefault = 0xce51; RtkSalI2COpInit = 0xcf21; HalI2SWrite32 = 0xcf65;