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https://github.com/drasko/open-ameba.git
synced 2024-11-21 13:34:17 +00:00
update
This commit is contained in:
parent
ea5f1c1b46
commit
96cac1005b
12 changed files with 71 additions and 87 deletions
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@ -374,7 +374,7 @@ void _LwIP_Init(void)
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tcpip_init( NULL, NULL );
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chk_ap_netif_num(); // Исполняется после _wifi_on()
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for(int idx = 0; idx < NET_IF_NUM; idx++) {
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for(idx = 0; idx < NET_IF_NUM; idx++) {
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xnetif[idx].name[0] = 'r';
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xnetif[idx].name[1] = '0' + idx;
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}
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@ -728,7 +728,7 @@ void fATWT(int argc, char *argv[]) {
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#define ReadTSF_Lo32() (*((volatile unsigned int *)(WIFI_REG_BASE + REG_TSFTR)))
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#define ReadTSF_Hi32() (*((volatile unsigned int *)(WIFI_REG_BASE + REG_TSFTR1)))
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uint64_t get_tsf(void)
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LOCAL uint64_t get_tsf(void)
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{
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return *((uint64_t *)(WIFI_REG_BASE + REG_TSFTR));
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}
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@ -207,9 +207,10 @@ struct spic_table_flash_type spic_table_flash = {
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BIT_FLASE_SIZE(0x0F), // REG_SPIC_FLASE_SIZE 0x40006124 0x0E ?
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BIT_CS_H_WR_DUM_LEN(2)| BIT_AUTO_ADDR__LENGTH(3) | BIT_RD_DUMMY_LENGTH(0x0), // REG_SPIC_AUTO_LENGTH 0x4000611C 0x20030001 ?
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{
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BIT_WR_BLOCKING, // REG_SPIC_VALID_CMD 0x40006120 0x200 SpicOneBitMode
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BIT_WR_BLOCKING | BIT_RD_DUAL_I, // REG_SPIC_VALID_CMD 0x40006120 0x200 SpicOneBitMode
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BIT_WR_BLOCKING | BIT_RD_QUAD_O, // REG_SPIC_VALID_CMD 0x40006120 0x200 SpicOneBitMode
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BIT_WR_BLOCKING, // REG_SPIC_VALID_CMD 0x40006120 0x200 SpicOneBitMode
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BIT_WR_BLOCKING | BIT_RD_DUAL_I, // REG_SPIC_VALID_CMD 0x40006120 0x202 SpicDualBitMode
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BIT_WR_BLOCKING | BIT_RD_DUAL_I, // REG_SPIC_VALID_CMD 0x40006120 0x202 SpicDualBitMode
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// BIT_WR_BLOCKING | BIT_RD_QUAD_O, // REG_SPIC_VALID_CMD 0x40006120 0x208 SpicQuadBitMode MXIC not QIO
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},
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0xC2, 0x20 // MX25L8006/MX25L1606
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};
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@ -274,7 +275,7 @@ LOCAL int BOOT_RAM_TEXT_SECTION InitSpic(uint8 SpicBitMode) {
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for(x = 0; x < SpicMaxMode; x++) {
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*(uint32 *)&SpicInitParaAllClk[SpicOneBitMode][x].BaudRate = ptr[0];
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*(uint32 *)&SpicInitParaAllClk[SpicDualBitMode][x].BaudRate = ptr[CPU_CLK_TYPE_NO];
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*(uint32 *)&SpicInitParaAllClk[SpicQuadBitMode][x].BaudRate = ptr[CPU_CLK_TYPE_NO];
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*(uint32 *)&SpicInitParaAllClk[SpicQuadBitMode][x].BaudRate = ptr[CPU_CLK_TYPE_NO]; // MXIC not QIO
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ptr++;
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}
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ACTCK_FLASH_CCTRL(1);
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@ -2655,65 +2655,65 @@
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1003bcc4 T ODM_TXPowerTrackingCallback_ThermalMeter
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1003c0d0 T ODM_ResetIQKResult
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1003c118 T ODM_GetRightChnlPlaceforIQK
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1003c170 t __CmdDumpWord_veneer
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1003c180 t __rtw_get_sec_ie_veneer
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1003c190 t __rtw_set_fixed_ie_veneer
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1003c1a0 t __Strtoul_veneer
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1003c1b0 t __rtw_set_supported_rate_veneer
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1003c1c0 t __rtw_set_ie_veneer
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1003c1d0 t __AES_UnWRAP_veneer
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1003c1e0 t __rtw_get_wps_attr_content_veneer
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1003c1f0 t __AES_WRAP_veneer
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1003c200 t __rt_arc4_init_veneer
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1003c210 t __phy_CalculateBitShift_veneer
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1003c220 t __aes_80211_decrypt_veneer
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1003c230 t ___vsscanf_veneer
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1003c240 t __rtw_get_rateset_len_veneer
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1003c250 t __prvStrCmp_veneer
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1003c260 t __HalI2SClrAllIntrRtl8195a_veneer
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1003c270 t __rtw_get_wps_ie_veneer
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1003c280 t __rtw_get_wpa2_ie_veneer
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1003c290 t __wep_80211_decrypt_veneer
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1003c2a0 t __PHY_SetBBReg_8195A_veneer
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1003c2b0 t __ROM_odm_QueryRxPwrPercentage_veneer
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1003c2c0 t __HalI2SRead32_veneer
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1003c2d0 t __wep_80211_encrypt_veneer
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1003c2e0 t __rtw_get_bit_value_from_ieee_value_veneer
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1003c2f0 t __rtw_check_network_type_veneer
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1003c300 t __ROM_odm_FalseAlarmCounterStatistics_veneer
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1003c310 t __rt_arc4_crypt_veneer
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1003c320 t __CmdWriteWord_veneer
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1003c330 t __rt_md5_hmac_veneer
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1003c340 t __PHY_QueryBBReg_8195A_veneer
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1003c350 t __rom_psk_CalcGTK_veneer
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1003c360 t __tkip_80211_encrypt_veneer
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1003c370 t __rom_psk_CalcPTK_veneer
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1003c380 t __rtw_secgetmic_veneer
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1003c390 t __rtw_parse_wpa_ie_veneer
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1003c3a0 t __rtw_seccalctkipmic_veneer
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1003c3b0 t __rtw_secmicsetkey_veneer
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1003c3c0 t __tkip_80211_decrypt_veneer
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1003c3d0 t __StrUpr_veneer
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1003c3e0 t __ROM_odm_CfoTrackingFlow_veneer
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1003c3f0 t __aes_80211_encrypt_veneer
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1003c400 t __rt_hmac_sha1_veneer
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1003c410 t __ROM_odm_SetCrystalCap_veneer
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1003c420 t __HalDelayUs_veneer
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1003c430 t __rtw_get_ie_veneer
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1003c440 t __HalI2SIntrCtrlRtl8195a_veneer
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1003c450 t __SpicWaitBusyDoneRtl8195A_veneer
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1003c460 t __HalI2SWrite32_veneer
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1003c470 t __ROM_odm_EVMdbToPercentage_veneer
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1003c480 t __HalCpuClkConfig_veneer
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1003c490 t __rtw_secmicappend_veneer
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1003c4a0 t __rtw_parse_wpa2_ie_veneer
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1003c4b0 t __ROM_ODM_CfoTrackingReset_veneer
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1003c4c0 t __ROM_odm_GetDefaultCrytaltalCap_veneer
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1003c4d0 t __rtw_get_wpa_ie_veneer
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1003c4e0 t __rom_psk_PasswordHash_veneer
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1003c4f0 t __rtw_ieee802_11_parse_elems_veneer
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1003c500 t __key_2char2num_veneer
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1003c510 t __Rand_veneer
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1003c170 t __rtw_get_ie_veneer
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1003c180 t __rtw_get_wpa_ie_veneer
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1003c190 t __HalI2SRead32_veneer
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1003c1a0 t __aes_80211_decrypt_veneer
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1003c1b0 t __rom_psk_PasswordHash_veneer
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1003c1c0 t __ROM_odm_SetCrystalCap_veneer
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1003c1d0 t __rtw_set_supported_rate_veneer
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1003c1e0 t __rtw_ieee802_11_parse_elems_veneer
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1003c1f0 t __SpicWaitBusyDoneRtl8195A_veneer
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1003c200 t __ROM_ODM_CfoTrackingReset_veneer
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1003c210 t ___vsscanf_veneer
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1003c220 t __rtw_parse_wpa_ie_veneer
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1003c230 t __AES_WRAP_veneer
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1003c240 t __rtw_get_wpa2_ie_veneer
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1003c250 t __rtw_secmicappend_veneer
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1003c260 t __rtw_check_network_type_veneer
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1003c270 t __wep_80211_decrypt_veneer
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1003c280 t __rom_psk_CalcGTK_veneer
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1003c290 t __rtw_set_ie_veneer
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1003c2a0 t __CmdWriteWord_veneer
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1003c2b0 t __ROM_odm_CfoTrackingFlow_veneer
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1003c2c0 t __ROM_odm_EVMdbToPercentage_veneer
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1003c2d0 t __phy_CalculateBitShift_veneer
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1003c2e0 t __rtw_get_wps_attr_content_veneer
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1003c2f0 t __rtw_seccalctkipmic_veneer
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1003c300 t __rt_arc4_init_veneer
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1003c310 t __rtw_get_bit_value_from_ieee_value_veneer
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1003c320 t __tkip_80211_decrypt_veneer
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1003c330 t __ROM_odm_FalseAlarmCounterStatistics_veneer
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1003c340 t __HalCpuClkConfig_veneer
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1003c350 t __rt_md5_hmac_veneer
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1003c360 t __rtw_secgetmic_veneer
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1003c370 t __StrUpr_veneer
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1003c380 t __ROM_odm_QueryRxPwrPercentage_veneer
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1003c390 t __HalDelayUs_veneer
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1003c3a0 t __wep_80211_encrypt_veneer
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1003c3b0 t __tkip_80211_encrypt_veneer
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1003c3c0 t __rtw_get_sec_ie_veneer
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1003c3d0 t __ROM_odm_GetDefaultCrytaltalCap_veneer
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1003c3e0 t __rom_psk_CalcPTK_veneer
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1003c3f0 t __rtw_get_rateset_len_veneer
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1003c400 t __PHY_SetBBReg_8195A_veneer
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1003c410 t __HalI2SClrAllIntrRtl8195a_veneer
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1003c420 t __rtw_get_wps_ie_veneer
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1003c430 t __rt_hmac_sha1_veneer
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1003c440 t __CmdDumpWord_veneer
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1003c450 t __rtw_secmicsetkey_veneer
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1003c460 t __rt_arc4_crypt_veneer
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1003c470 t __HalI2SWrite32_veneer
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1003c480 t __AES_UnWRAP_veneer
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1003c490 t __rtw_parse_wpa2_ie_veneer
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1003c4a0 t __aes_80211_encrypt_veneer
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1003c4b0 t __key_2char2num_veneer
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1003c4c0 t __Strtoul_veneer
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1003c4d0 t __prvStrCmp_veneer
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1003c4e0 t __Rand_veneer
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1003c4f0 t __PHY_QueryBBReg_8195A_veneer
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1003c500 t __HalI2SIntrCtrlRtl8195a_veneer
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1003c510 t __rtw_set_fixed_ie_veneer
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1003c9f5 d __func__.21276
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1003ca01 d __FUNCTION__.14658
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1003cf5c d bitrate_table
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14
flasher.mk
14
flasher.mk
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@ -66,7 +66,7 @@ NMAPFILE = $(OBJ_DIR)/$(TARGET).nmap
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#FLASHER_PATH ?= flasher/
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RAM_IMAGE?= $(BIN_DIR)/ram.bin
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#RAM_IMAGE?= $(BIN_DIR)/ram.bin
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RAM1_IMAGE ?= $(BIN_DIR)/ram_1.bin
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RAM1P_IMAGE ?= $(BIN_DIR)/ram_1.p.bin
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@ -91,18 +91,12 @@ TST_IMAGE = $(BIN_DIR)/ram_2.bin
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LD_ADDRESS = 0x1000B000
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ST_ADDRESS = 0x10006068
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.PHONY: copybin1 genbin1 genbin23 flashburn reset test readfullflash
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.NOTPARALLEL: all mp copybin1 genbin1 genbin23 flashburn reset test readfullflash _endgenbin
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.PHONY: genbin1 genbin23 flashburn reset test readfullflash
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.NOTPARALLEL: all mp genbin1 genbin23 flashburn reset test readfullflash _endgenbin
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all: $(ELFFILE) $(OTA_IMAGE) $(FLASH_IMAGE) _endgenbin
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mp: $(ELFFILE) $(OTA_IMAGE) $(FLASH_IMAGE) _endgenbin
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copybin1:
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# cp $(patsubst sdk/%,$(SDK_PATH)%,$(BOOTS))/ram_1.r.bin $(BIN_DIR)/ram_1.r.bin
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cp $(patsubst sdk/%,$(SDK_PATH)%,$(BOOTS))/ram_1.p.bin $(BIN_DIR)/ram_1.p.bin
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# @chmod 777 $(OBJ_DIR)/ram_1.r.bin
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# @$(OBJCOPY) --rename-section .data=.loader.data,contents,alloc,load,readonly,data -I binary -O elf32-littlearm -B arm $(BIN_DIR)/ram_1.r.bin $(OBJ_DIR)/ram_1.r.o
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genbin1: $(ELFFILE) $(RAM1P_IMAGE)
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genbin23: $(ELFFILE) $(OTA_IMAGE) $(FLASH_IMAGE) _endgenbin
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@ -191,7 +185,7 @@ ifeq ($(RAM1_START_ADDR),$(RAM1_END_ADDR))
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ifdef COMPILED_BOOT_BIN
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$(OBJCOPY) --change-section-address .boot.head=0x10000ba8 -j .boot.head -j .bootloader -Obinary $(ELFFILE) $(RAM1P_IMAGE)
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else
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$(OBJCOPY) -j .rom_ram -Obinary $(ELFFILE) $(RAM_IMAGE)
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# $(OBJCOPY) -j .rom_ram -Obinary $(ELFFILE) $(RAM_IMAGE)
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$(OBJCOPY) -j .ram.start.table -j .ram_image1.text -Obinary $(ELFFILE) $(RAM1R_IMAGE)
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$(PICK) 0x$(RAM1_START_ADDR) 0x$(RAM1_END_ADDR) $(RAM1R_IMAGE) $(RAM1P_IMAGE) head+reset_offset 0x0B000
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endif
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@ -7,7 +7,6 @@ set $rtl8710_flasher_auto_erase = 1
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set $rtl8710_flasher_auto_verify = 1
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set $rtl8710_flasher_firmware_ptr = 0x10001000
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set $rtl8710_flasher_buffer = 0x10008000
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#262144
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set $rtl8710_flasher_buffer_size = 421888
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set $rtl8710_flasher_sector_size = 4096
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set $rtl8710_flasher_auto_erase_sector = 0xFFFFFFFF
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12
sdkbuild.mk
12
sdkbuild.mk
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@ -45,18 +45,10 @@ build_info:
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.PHONY: application
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application: build_info $(SRC_O) $(DRAM_O) $(BOOT_O)
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@echo "==========================================================="
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@echo "Make BootLoader (ram_1.p.bin, ram_1.r.bin)"
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# @echo "==========================================================="
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@mkdir -p $(BIN_DIR) $(OBJ_DIR)
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## @cp $(patsubst sdk/%,$(SDK_PATH)%,$(BOOTS))/ram_1.r.bin $(BIN_DIR)/ram_1.r.bin
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## @cp $(patsubst sdk/%,$(SDK_PATH)%,$(BOOTS))/ram_1.p.bin $(BIN_DIR)/ram_1.p.bin
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# @chmod 777 $(OBJ_DIR)/ram_1.r.bin
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## $(OBJCOPY) --rename-section .data=.loader.data,contents,alloc,load,readonly,data -I binary -O elf32-littlearm -B arm $(BIN_DIR)/ram_1.r.bin $(OBJ_DIR)/ram_1.r.o
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@echo "==========================================================="
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@echo "Link ($(TARGET))"
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# @echo "==========================================================="
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## @$(LD) $(LFLAGS) -o $(ELFFILE) $(OBJ_LIST) $(OBJ_DIR)/ram_1.r.o $(LIBFLAGS) -T$(LDFILE)
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@mkdir -p $(BIN_DIR) $(OBJ_DIR)
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@$(LD) $(LFLAGS) -o $(ELFFILE) $(OBJ_LIST) $(LIBFLAGS) -T$(LDFILE)
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@$(OBJDUMP) -d $(ELFFILE) > $(OBJ_DIR)/$(TARGET).asm
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#.PHONY: clean
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clean:
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rm -rf $(OBJ_DIR) $(BIN_DIR) $(OBJ_DIR)/$(SDK_PATH)
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# @rm -f $(patsubst %.c,%.d,$(SRC_C_LIST))
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# @rm -f $(patsubst %.c,%.o,$(SRC_C_LIST))
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