From 95b8017e9525a183d9cf7769a11c96d86e8ca5d3 Mon Sep 17 00:00:00 2001 From: pvvx Date: Mon, 3 Apr 2017 10:32:32 +0300 Subject: [PATCH] update --- Makefile | 42 +- RTL00_SDKV35a/component/common/api/wifi_api.c | 295 +- RTL00_SDKV35a/component/common/api/wifi_api.h | 27 +- .../common/network/netbios/netbios.c | 2 +- .../soc/realtek/8195a/fwlib/bitband_io.h | 208 +- build/bin/ota.bin | Bin 299952 -> 299964 bytes build/bin/ram_2.bin | Bin 299916 -> 299928 bytes build/bin/ram_2.ns.bin | Bin 299932 -> 299944 bytes build/bin/ram_2.p.bin | Bin 299932 -> 299944 bytes build/bin/ram_all.bin | Bin 345004 -> 345016 bytes build/obj/build.nmap | 4574 ++++++++--------- flasher.mk | 99 +- flasher/gdb_wrfile.jlink | 156 + flasher/gdb_wrflash.jlink | 6 +- jlinkarm.py | 113 + project/inc/rtl8195a/rtl_libc.h | 162 + project/src/user/main.c | 15 +- project/src/user/wifi_console.c | 294 ++ runram.py | 53 + sdkset.mk | 1 + 20 files changed, 3315 insertions(+), 2732 deletions(-) create mode 100644 flasher/gdb_wrfile.jlink create mode 100644 jlinkarm.py create mode 100644 project/inc/rtl8195a/rtl_libc.h create mode 100644 project/src/user/wifi_console.c create mode 100644 runram.py diff --git a/Makefile b/Makefile index 54c7506..3444c2c 100644 --- a/Makefile +++ b/Makefile @@ -7,6 +7,9 @@ ram_all: @$(MAKE) -f sdkbuild.mk @$(MAKE) -f flasher.mk genbin1 genbin23 +webfs: + @$(MAKE) -f webfs.mk webpages.espfs + .PHONY: ram_all_mp ram_all_mp: @$(MAKE) -f sdkbuild.mk mp @@ -15,33 +18,32 @@ ram_all_mp: .PHONY: clean clean_all clean: @$(MAKE) -f sdkbuild.mk clean + @$(MAKE) -f webfs.mk clean clean_all: @$(MAKE) -f sdkbuild.mk clean_all + @$(MAKE) -f webfs.mk clean -.PHONY: debug ramdebug -debug: - @$(MAKE) -f application.mk debug - -ramdebug: - @$(MAKE) -f application.mk ramdebug - -.PHONY: flash_OTA flashburn runram reset test readfullflash - -flash_OTA: - JLinkGDB_OTA.bat - +.PHONY: flashburn runram reset test readfullflash flashwebfs flashburn: - JLinkGDB-WrFlash.bat - #@$(MAKE) -f flasher.mk flashburn + #JLinkGDB-WrFlash.bat + @$(MAKE) -f flasher.mk flashburn + +flash_OTA: + @$(MAKE) -f flasher.mk flash_OTA + +flashwebfs: + @$(MAKE) -f webfs.mk webpages.espfs + @$(MAKE) -f flasher.mk flashwebfs + #JLinkGDB-WrWebFs.bat runram: - JLink-RunRAM.bat - #@$(MAKE) --f flasher.mk runram + #JLink-RunRAM.bat + @$(MAKE) --f flasher.mk runram reset: - JLink-Reset.bat - #@make -f flasher.mk reset + #JLink-Reset.bat + @$(MAKE) -f flasher.mk reset test: JLink-RTL00ConsoleROM.bat @@ -54,6 +56,4 @@ readfullflash: .PHONY: prerequirement prerequirement: @$(file >DEPENDENCY_LIST.txt,$(DEPENDENCY_LIST)) - -#TARGETTYPE := APP -#TARGETNAME := build\obj\build.axf + \ No newline at end of file diff --git a/RTL00_SDKV35a/component/common/api/wifi_api.c b/RTL00_SDKV35a/component/common/api/wifi_api.c index a194b6a..133cf16 100644 --- a/RTL00_SDKV35a/component/common/api/wifi_api.c +++ b/RTL00_SDKV35a/component/common/api/wifi_api.c @@ -88,11 +88,11 @@ typedef struct _feep_element { } FEEP_ELEMENT, *PFEEP_ELEMENT; FEEP_ELEMENT feep_tab[] = { - { FEEP_ID_WIFI_AP_CFG, sizeof(wifi_ap_cfg), &wifi_ap_cfg }, // Bit0 - { FEEP_ID_WIFI_ST_CFG, sizeof(wifi_st_cfg), &wifi_st_cfg }, // Bit1 - { FEEP_ID_AP_DHCP_CFG, sizeof(wifi_ap_dhcp), &wifi_ap_dhcp }, // Bit2 - { FEEP_ID_ST_DHCP_CFG, sizeof(wifi_st_dhcp), &wifi_st_dhcp }, // Bit3 - { FEEP_ID_WIFI_CFG, sizeof(wifi_cfg), &wifi_cfg }, // Bit4 + { FEEP_ID_WIFI_AP_CFG, sizeof(wifi_ap_cfg), &wifi_ap_cfg }, // Bit0 BID_WIFI_AP_CFG + { FEEP_ID_WIFI_ST_CFG, sizeof(wifi_st_cfg), &wifi_st_cfg }, // Bit1 BID_WIFI_ST_CFG + { FEEP_ID_AP_DHCP_CFG, sizeof(wifi_ap_dhcp), &wifi_ap_dhcp }, // Bit2 BID_AP_DHCP_CFG + { FEEP_ID_ST_DHCP_CFG, sizeof(wifi_st_dhcp), &wifi_st_dhcp }, // Bit3 BID_ST_DHCP_CFG + { FEEP_ID_WIFI_CFG, sizeof(wifi_cfg), &wifi_cfg }, // Bit4 BID_WIFI_CFG // { FEEP_ID_LWIP_CFG, sizeof(lwip_conn_info), &lwip_conn_info }, // Bit5 { 0, 0, NULL } }; @@ -144,11 +144,6 @@ _WEAK void connect_close(void) info_printf("\%s: Time at start %d ms.\n", __func__, xTaskGetTickCount()); } -_WEAK void user_start(void) -{ - info_printf("\%s: Time at start %d ms.\n", __func__, xTaskGetTickCount()); -} - int wlan_init_done_callback(void) { info_printf("WiFi Init after %d ms\n", xTaskGetTickCount()); return 0; @@ -479,9 +474,9 @@ error_end: return ret; } -void wifi_init_thrd(void) { +void wifi_init(void) { debug_printf("\nLoad Config\n"); - read_wifi_cfg(DEF_LOAD_CFG); + read_wifi_cfg(wifi_cfg.load_flg); // DEF_LOAD_CFG // Call back from wlan driver after wlan init done p_wlan_init_done_callback = wlan_init_done_callback; // Call back from application layer after wifi_connection success @@ -493,12 +488,7 @@ void wifi_init_thrd(void) { wifi_manager_init(); #endif wifi_run(wifi_cfg.mode); - user_start(); } - /* Initilaize the console stack */ - console_init(); - /* Kill init thread after all init tasks done */ - vTaskDelete(NULL); } rtw_security_t translate_rtw_security(u8 security_type) @@ -563,274 +553,3 @@ void show_wifi_cfg(void) { printf("\tSave flags: %p\n", wifi_cfg.save_flg); } -//========================================================== -//--- CONSOLE -------------------------- -#include "section_config.h" -#include "hal_diag.h" - -// ATPN=[,password[,encryption[,auto reconnect[,reconnect pause]]]: WIFI Connect to AP -void fATPN(int argc, char *argv[]){ - if(argc > 1) { - if(argv[1][0] == '?') { - show_wifi_st_cfg(); - } - else { - strncpy(wifi_st_cfg.ssid, argv[1], NDIS_802_11_LENGTH_SSID); - if(argc > 2) { - strncpy(wifi_st_cfg.password, argv[2], NDIS_802_11_LENGTH_SSID); - int i = strlen(wifi_st_cfg.password); - if(i > 7) { - wifi_st_cfg.security_type = RTW_SECURITY_WPA2_AES_PSK; - } - else if(!i) { - wifi_st_cfg.security_type = RTW_SECURITY_OPEN; - } - else { - printf("password len < 8!\n"); - wifi_st_cfg.security_type = RTW_SECURITY_OPEN; - } - } - else { - wifi_st_cfg.password[0] = 0; - wifi_st_cfg.security_type = RTW_SECURITY_OPEN; - } - if(argc > 3) { - wifi_st_cfg.security_type = translate_rtw_security(atoi(argv[3])); - } - if(argc > 4) { - wifi_st_cfg.autoreconnect = atoi(argv[3]); - } - else wifi_st_cfg.autoreconnect = 0; - if(argc > 5) { - wifi_st_cfg.reconnect_pause = atoi(argv[3]); - } - else wifi_st_cfg.reconnect_pause = 5; - show_wifi_st_cfg(); - wifi_run(wifi_run_mode | RTW_MODE_STA); - } - } -} - -// ATPA=[,password[,encryption[,channel[,hidden[,max connections]]]]]: Start WIFI AP -void fATPA(int argc, char *argv[]){ - if(argc > 1) { - if(argv[1][0] == '?') { - show_wifi_ap_cfg(); - } - else { - strncpy(wifi_ap_cfg.ssid, argv[1], NDIS_802_11_LENGTH_SSID); - if(argc > 2) { - strncpy(wifi_ap_cfg.password, argv[2], NDIS_802_11_LENGTH_SSID); - int i = strlen(wifi_ap_cfg.password); - if(i > 7) { - wifi_ap_cfg.security_type = RTW_SECURITY_WPA2_AES_PSK; - } - else if(i == 0) { - wifi_ap_cfg.security_type = RTW_SECURITY_OPEN; - } - else { - printf("password len < 8!\n"); - wifi_ap_cfg.security_type = RTW_SECURITY_OPEN; - } - } - else { - wifi_ap_cfg.password[0] = 0; - wifi_ap_cfg.security_type = RTW_SECURITY_OPEN; - } - if(argc > 3) { - wifi_ap_cfg.security_type = translate_rtw_security(atoi(argv[3])); - } - if(argc > 4) { - wifi_ap_cfg.channel = atoi(argv[4]); - } - else wifi_ap_cfg.channel = 1; - if(argc > 5) { - wifi_ap_cfg.ssid_hidden = atoi(argv[5]); - } - else wifi_ap_cfg.ssid_hidden = 0; - - if(argc > 6) { - wifi_ap_cfg.max_sta = atoi(argv[6]); - } - else wifi_ap_cfg.max_sta = 3; - - show_wifi_ap_cfg(); - wifi_run(wifi_run_mode | RTW_MODE_AP); - } - } -} - -// WIFI Connect, Disconnect -void fATWR(int argc, char *argv[]){ - rtw_mode_t mode = RTW_MODE_NONE; - if(argc > 1) mode = atoi(argv[1]); - wifi_run(mode); -} - -// Close connections -void fATOF(int argc, char *argv[]){ - connect_close(); -} - -// Open connections -void fATON(int argc, char *argv[]){ - connect_start(); -} - -void fATWI(int argc, char *argv[]) { - rtw_wifi_setting_t Setting; - if((wifi_run_mode & RTW_MODE_AP) - && wifi_get_setting(wlan_ap_name, &Setting) == 0) { - wifi_show_setting(wlan_ap_name, &Setting); -// show_wifi_ap_ip(); - printf("\tIP: " IPSTR "\n", IP2STR(&xnetif[WLAN_AP_NETIF_NUM].ip_addr)); - } - if((wifi_run_mode & RTW_MODE_STA) - && wifi_get_setting(wlan_st_name, &Setting) == 0) { - wifi_show_setting(wlan_st_name, &Setting); -// show_wifi_st_ip(); - printf("\tIP: " IPSTR "\n", IP2STR(&xnetif[WLAN_ST_NETIF_NUM].ip_addr)); - } - printf("\nWIFI config:\n"); - printf(&str_rom_57ch3Dch0A[25]); // "================================\n" - show_wifi_cfg(); - printf("\nWIFI AP config:\n"); - printf(&str_rom_57ch3Dch0A[25]); // "================================\n" - show_wifi_ap_cfg(); - printf("\nWIFI ST config:\n"); - printf(&str_rom_57ch3Dch0A[25]); // "================================\n" - show_wifi_st_cfg(); - printf("\n"); - if(argc > 2 - && (argv[1][0] == 's' - || argv[1][0] == 'S')) { - int i = atoi(argv[2]); - printf("Save configs(%d)..\n", i); - write_wifi_cfg(atoi(argv[2])); - } -} - -void fATWT(int argc, char *argv[]) { - if(argc > 1) { - int txpwr = atoi(argv[1]); - debug_printf("set tx power (%d)...\n", txpwr); - if(rltk_set_tx_power_percentage(txpwr) != RTW_SUCCESS) { - error_printf("Error set tx power (%d)!", wifi_cfg.tx_pwr); - } - } - printf("TX power = %d\n", rtw_power_percentage_idx); -} - -//-- Test tsf (64-bits counts, 1 us step) --- - -#include "hal_com_reg.h" - -#define ReadTSF_Lo32() (*((volatile unsigned int *)(WIFI_REG_BASE + REG_TSFTR))) -#define ReadTSF_Hi32() (*((volatile unsigned int *)(WIFI_REG_BASE + REG_TSFTR1))) - -LOCAL uint64_t get_tsf(void) -{ - return *((uint64_t *)(WIFI_REG_BASE + REG_TSFTR)); -} - -void fATSF(int argc, char *argv[]) -{ - uint64_t tsf = get_tsf(); - printf("\nTSF: %08x%08x\n", (uint32_t)(tsf>>32), (uint32_t)(tsf)); -} - -/* -------- WiFi Scan ------------------------------- */ -unsigned char *tab_txt_rtw_secyrity[] = { - "OPEN ", - "WEP ", - "WPA TKIP", - "WPA AES", - "WPA2 AES", - "WPA2 TKIP", - "WPA2 Mixed", - "WPA/WPA2 AES", - "Unknown" -}; -unsigned int *tab_code_rtw_secyrity[] = { - RTW_SECURITY_OPEN, - RTW_SECURITY_WEP_PSK, - RTW_SECURITY_WPA_TKIP_PSK, - RTW_SECURITY_WPA_AES_PSK, - RTW_SECURITY_WPA2_AES_PSK, - RTW_SECURITY_WPA2_TKIP_PSK, - RTW_SECURITY_WPA2_MIXED_PSK, - RTW_SECURITY_WPA_WPA2_MIXED, - RTW_SECURITY_UNKNOWN -}; - -volatile uint8_t scan_end; - -/* -------- WiFi Scan ------------------------------- */ -static rtw_result_t _scan_result_handler( rtw_scan_handler_result_t* malloced_scan_result ) -{ - if (malloced_scan_result->scan_complete != RTW_TRUE) { - rtw_scan_result_t* record = &malloced_scan_result->ap_details; - record->SSID.val[record->SSID.len] = 0; /* Ensure the SSID is null terminated */ - if(scan_end == 1) { - printf("\nScan networks:\n\n"); - printf("N\tType\tMAC\t\t\tSignal\tCh\tWPS\tSecyrity\tSSID\n\n"); - }; - printf("%d\t", scan_end++); - printf("%s\t", (record->bss_type == RTW_BSS_TYPE_ADHOC)? "Adhoc": "Infra"); - printf(MAC_FMT, MAC_ARG(record->BSSID.octet)); - printf("\t%d\t", record->signal_strength); - printf("%d\t", record->channel); - printf("%d\t", record->wps_type); - int i = 0; - for(; record->security != tab_code_rtw_secyrity[i] && tab_code_rtw_secyrity[i] != RTW_SECURITY_UNKNOWN; i++); - printf("%s \t", tab_txt_rtw_secyrity[i]); - printf("%s\n", record->SSID.val); - } else { - scan_end = 0; - printf("\n"); - } - return RTW_SUCCESS; -} -/* -------- WiFi Scan ------------------------------- */ -#define scan_channels 14 -void fATSN(int argc, char *argv[]) -{ - int i; - u8 *channel_list = (u8*)pvPortMalloc(scan_channels*2); - if(channel_list) { - scan_end = 1; - u8 * pscan_config = &channel_list[scan_channels]; - //parse command channel list - for(i = 1; i <= scan_channels; i++){ - *(channel_list + i - 1) = i; - *(pscan_config + i - 1) = PSCAN_ENABLE; - }; - if(wifi_set_pscan_chan(channel_list, pscan_config, scan_channels) < 0){ - printf("ERROR: wifi set partial scan channel fail\n"); - } else if(wifi_scan_networks(_scan_result_handler, NULL ) != RTW_SUCCESS){ - printf("ERROR: wifi scan failed\n"); - } else { - i = 300; - while(i-- && scan_end) { - vTaskDelay(10); - }; - }; - vPortFree(channel_list); - } else { - printf("ERROR: Can't malloc memory for channel list\n"); - }; -} - -MON_RAM_TAB_SECTION COMMAND_TABLE console_cmd_wifi_api[] = { - {"ATPN", 1, fATPN, "=[,password[,encryption[,auto-reconnect[,reconnect pause]]]: WIFI Connect to AP"}, - {"ATPA", 1, fATPA, "=[,password[,encryption[,channel[,hidden[,max connections]]]]]: Start WIFI AP"}, - {"ATWR", 0, fATWR, ": WIFI Connect, Disconnect"}, - {"ATON", 0, fATON, ": Open connections"}, - {"ATOF", 0, fATOF, ": Close connections"}, - {"ATWI", 0, fATWI, ": WiFi Info"}, -#if CONFIG_DEBUG_LOG > 3 - {"ATWT", 1, fATWT, "=: WiFi tx power: 0 - 100%, 1 - 75%, 2 - 50%, 3 - 25%, 4 - 12.5%"}, - {"ATSF", 0, fATSF, ": Test TSF value"}, -#endif - {"ATSN", 0, fATSN, ": Scan networks"} -}; diff --git a/RTL00_SDKV35a/component/common/api/wifi_api.h b/RTL00_SDKV35a/component/common/api/wifi_api.h index 7513c5c..a3c7e9e 100644 --- a/RTL00_SDKV35a/component/common/api/wifi_api.h +++ b/RTL00_SDKV35a/component/common/api/wifi_api.h @@ -7,11 +7,13 @@ #ifndef _WIFI_API_H_ #define _WIFI_API_H_ +#include "wifi_constants.h" +#include "wifi_conf.h" -#define ip4_addr1(ipaddr) (((u8_t*)(ipaddr))[0]) -#define ip4_addr2(ipaddr) (((u8_t*)(ipaddr))[1]) -#define ip4_addr3(ipaddr) (((u8_t*)(ipaddr))[2]) -#define ip4_addr4(ipaddr) (((u8_t*)(ipaddr))[3]) +#define ip4_addr1(ipaddr) (((uint8_t*)(ipaddr))[0]) +#define ip4_addr2(ipaddr) (((uint8_t*)(ipaddr))[1]) +#define ip4_addr3(ipaddr) (((uint8_t*)(ipaddr))[2]) +#define ip4_addr4(ipaddr) (((uint8_t*)(ipaddr))[3]) #define IPSTR "%d.%d.%d.%d" @@ -97,6 +99,19 @@ typedef struct _dhcp_config { unsigned char mode; // =0 dhcp off, =1 - dhcp on, =2 Static ip, =3 - auto } DHCP_CONFIG, *PDHCP_CONFIG; + +extern WIFI_CONFIG wifi_cfg; +extern SOFTAP_CONFIG wifi_ap_cfg; +extern DHCP_CONFIG wifi_ap_dhcp; +extern STATION_CONFIG wifi_st_cfg; +extern DHCP_CONFIG wifi_st_dhcp; +extern rtw_mode_t wifi_run_mode; +extern char wlan_st_name[]; +extern char wlan_ap_name[]; +extern char wlan_st_netifn; +extern char wlan_ap_netifn; + + void show_wifi_ap_ip(void); void show_wifi_st_ip(void); void show_wifi_cfg(void); @@ -105,6 +120,8 @@ void show_wifi_ap_cfg(void); uint32 read_wifi_cfg(uint32 flg); uint32 write_wifi_cfg(uint32 flg); int wifi_run(rtw_mode_t mode); -void wifi_init_thrd(void); +void wifi_init(void); + +void _LwIP_Init(void); #endif // _WIFI_API_H_ diff --git a/RTL00_SDKV35a/component/common/network/netbios/netbios.c b/RTL00_SDKV35a/component/common/network/netbios/netbios.c index bd85587..cb0db96 100644 --- a/RTL00_SDKV35a/component/common/network/netbios/netbios.c +++ b/RTL00_SDKV35a/component/common/network/netbios/netbios.c @@ -374,8 +374,8 @@ void NETBIOS_CODE_ATTR netbios_init(void) { for(int i = 0; i < NET_IF_NUM; i++) { os_printf("%d: '%s' ", i, netbios_name[i]); } + os_printf("\n"); #endif - pcb = udp_new(); if (pcb != NULL) { /* we have to be allowed to send broadcast packets! */ diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/bitband_io.h b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/bitband_io.h index 120899d..3fb4c60 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/bitband_io.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/bitband_io.h @@ -12,27 +12,27 @@ /* * in hal_platform.h -#define GPIO_REG_BASE 0x40001000 +#define BITBAND_REG_BASE 0x40001000 */ /* * in rtl8195a_gpio.h * -#define GPIO_PORTA_DR 0x00 // data register -#define GPIO_PORTA_DDR 0x04 // data direction -#define GPIO_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software +#define BITBAND_PORTA_DR 0x00 // data register +#define BITBAND_PORTA_DDR 0x04 // data direction +#define BITBAND_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software -#define GPIO_PORTB_DR 0x0c // data register -#define GPIO_PORTB_DDR 0x10 // data direction -#define GPIO_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software +#define BITBAND_PORTB_DR 0x0c // data register +#define BITBAND_PORTB_DDR 0x10 // data direction +#define BITBAND_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software -#define GPIO_PORTC_DR 0x18 // data register -#define GPIO_PORTC_DDR 0x1c // data direction -#define GPIO_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software +#define BITBAND_PORTC_DR 0x18 // data register +#define BITBAND_PORTC_DDR 0x1c // data direction +#define BITBAND_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software -#define GPIO_EXT_PORTA 0x50 // GPIO IN read or OUT read back -#define GPIO_EXT_PORTB 0x54 // GPIO IN read or OUT read back -#define GPIO_EXT_PORTC 0x58 // GPIO IN read or OUT read back +#define BITBAND_EXT_PORTA 0x50 // GPIO IN read or OUT read back +#define BITBAND_EXT_PORTB 0x54 // GPIO IN read or OUT read back +#define BITBAND_EXT_PORTC 0x58 // GPIO IN read or OUT read back */ #define BITBAND_PERI_REF 0x40000000 @@ -41,106 +41,106 @@ #define ucBITBAND_PERI(a,b) *((volatile unsigned char *)BITBAND_PERI(a,b)) #define uiBITBAND_PERI(a,b) *((volatile unsigned int *)BITBAND_PERI(a,b)) -#define GPIO_A0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,0) //Port = 0, bit = 0, A0 -#define GPIO_A1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,1) //Port = 0, bit = 1, A1 -#define GPIO_A2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,0) //Port = 1, bit = 0, A2 -#define GPIO_A3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,1) //Port = 1, bit = 1, A3 -#define GPIO_A4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,2) //Port = 1, bit = 2, A4 -#define GPIO_A5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,3) //Port = 1, bit = 3, A5 -#define GPIO_A6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,4) //Port = 1, bit = 4, A6 -#define GPIO_A7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,5) //Port = 1, bit = 5, A7 +#define BITBAND_A0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,0) //Port = 0, bit = 0, A0 +#define BITBAND_A1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,1) //Port = 0, bit = 1, A1 +#define BITBAND_A2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,0) //Port = 1, bit = 0, A2 +#define BITBAND_A3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,1) //Port = 1, bit = 1, A3 +#define BITBAND_A4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,2) //Port = 1, bit = 2, A4 +#define BITBAND_A5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,3) //Port = 1, bit = 3, A5 +#define BITBAND_A6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,4) //Port = 1, bit = 4, A6 +#define BITBAND_A7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,5) //Port = 1, bit = 5, A7 -#define GPIO_B0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,6) //Port = 1, bit = 6, B0 -#define GPIO_B1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,7) //Port = 1, bit = 7, B1 -#define GPIO_B2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,8) //Port = 1, bit = 8, B2 -#define GPIO_B3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,2) //Port = 0, bit = 2, B3 -#define GPIO_B4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,3) //Port = 0, bit = 3, B4 -#define GPIO_B5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,9) //Port = 1, bit = 9, B5 -#define GPIO_B6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,4) //Port = 0, bit = 4, B6 -#define GPIO_B7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,5) //Port = 0, bit = 5, B7 +#define BITBAND_B0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,6) //Port = 1, bit = 6, B0 +#define BITBAND_B1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,7) //Port = 1, bit = 7, B1 +#define BITBAND_B2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,8) //Port = 1, bit = 8, B2 +#define BITBAND_B3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,2) //Port = 0, bit = 2, B3 +#define BITBAND_B4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,3) //Port = 0, bit = 3, B4 +#define BITBAND_B5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,9) //Port = 1, bit = 9, B5 +#define BITBAND_B6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,4) //Port = 0, bit = 4, B6 +#define BITBAND_B7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,5) //Port = 0, bit = 5, B7 -#define GPIO_C0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,10) //Port = 1, bit = 10, C0 -#define GPIO_C1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,6) //Port = 0, bit = 6, C1 -#define GPIO_C2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,11) //Port = 1, bit = 11, C2 -#define GPIO_C3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,7) //Port = 0, bit = 7, C3 -#define GPIO_C4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,8) //Port = 0, bit = 8, C4 -#define GPIO_C5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,9) //Port = 0, bit = 9, C5 -#define GPIO_C6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,10) //Port = 0, bit = 10, C6 -#define GPIO_C7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,11) //Port = 0, bit = 11, C7 -#define GPIO_C8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,12) //Port = 0, bit = 12, C8 -#define GPIO_C9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,13) //Port = 0, bit = 13, C9 +#define BITBAND_C0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,10) //Port = 1, bit = 10, C0 +#define BITBAND_C1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,6) //Port = 0, bit = 6, C1 +#define BITBAND_C2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,11) //Port = 1, bit = 11, C2 +#define BITBAND_C3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,7) //Port = 0, bit = 7, C3 +#define BITBAND_C4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,8) //Port = 0, bit = 8, C4 +#define BITBAND_C5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,9) //Port = 0, bit = 9, C5 +#define BITBAND_C6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,10) //Port = 0, bit = 10, C6 +#define BITBAND_C7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,11) //Port = 0, bit = 11, C7 +#define BITBAND_C8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,12) //Port = 0, bit = 12, C8 +#define BITBAND_C9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,13) //Port = 0, bit = 13, C9 -#define GPIO_D0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,12) //Port = 1, bit = 12, D0 -#define GPIO_D1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,14) //Port = 0, bit = 14, D1 -#define GPIO_D2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,13) //Port = 1, bit = 13, D2 -#define GPIO_D3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,15) //Port = 0, bit = 15, D3 -#define GPIO_D4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,16) //Port = 0, bit = 16, D4 -#define GPIO_D5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,17) //Port = 0, bit = 17, D5 -#define GPIO_D6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,18) //Port = 0, bit = 18, D6 -#define GPIO_D7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,19) //Port = 0, bit = 19, D7 -#define GPIO_D8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,14) //Port = 1, bit = 14, D8 -#define GPIO_D9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,20) //Port = 0, bit = 20, D9 +#define BITBAND_D0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,12) //Port = 1, bit = 12, D0 +#define BITBAND_D1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,14) //Port = 0, bit = 14, D1 +#define BITBAND_D2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,13) //Port = 1, bit = 13, D2 +#define BITBAND_D3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,15) //Port = 0, bit = 15, D3 +#define BITBAND_D4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,16) //Port = 0, bit = 16, D4 +#define BITBAND_D5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,17) //Port = 0, bit = 17, D5 +#define BITBAND_D6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,18) //Port = 0, bit = 18, D6 +#define BITBAND_D7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,19) //Port = 0, bit = 19, D7 +#define BITBAND_D8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,14) //Port = 1, bit = 14, D8 +#define BITBAND_D9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,20) //Port = 0, bit = 20, D9 -#define GPIO_E0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,15) //Port = 2, bit = 15, E0 -#define GPIO_E1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,21) //Port = 0, bit = 21, E1 -#define GPIO_E2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,22) //Port = 0, bit = 22, E2 -#define GPIO_E3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,23) //Port = 0, bit = 23, E3 -#define GPIO_E4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,16) //Port = 1, bit = 16, E4 -#define GPIO_E5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,24) //Port = 0, bit = 24, E5 -#define GPIO_E6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,25) //Port = 0, bit = 25, E6 -#define GPIO_E7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,26) //Port = 0, bit = 26, E7 -#define GPIO_E8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,27) //Port = 0, bit = 27, E8 -#define GPIO_E9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,17) //Port = 1, bit = 17, E9 -#define GPIO_E10 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,18) //Port = 1, bit = 17, E10 +#define BITBAND_E0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,15) //Port = 2, bit = 15, E0 +#define BITBAND_E1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,21) //Port = 0, bit = 21, E1 +#define BITBAND_E2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,22) //Port = 0, bit = 22, E2 +#define BITBAND_E3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,23) //Port = 0, bit = 23, E3 +#define BITBAND_E4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,16) //Port = 1, bit = 16, E4 +#define BITBAND_E5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,24) //Port = 0, bit = 24, E5 +#define BITBAND_E6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,25) //Port = 0, bit = 25, E6 +#define BITBAND_E7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,26) //Port = 0, bit = 26, E7 +#define BITBAND_E8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,27) //Port = 0, bit = 27, E8 +#define BITBAND_E9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,17) //Port = 1, bit = 17, E9 +#define BITBAND_E10 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,18) //Port = 1, bit = 17, E10 -#define GPIO_F0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,19) //Port = 1, bit = 19, F0 -#define GPIO_F1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,20) //Port = 1, bit = 20, F1 -#define GPIO_F2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,21) //Port = 1, bit = 21, F2 -#define GPIO_F3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,22) //Port = 1, bit = 22, F3 -#define GPIO_F4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,23) //Port = 1, bit = 23, F4 -#define GPIO_F5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,24) //Port = 1, bit = 24, F5 +#define BITBAND_F0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,19) //Port = 1, bit = 19, F0 +#define BITBAND_F1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,20) //Port = 1, bit = 20, F1 +#define BITBAND_F2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,21) //Port = 1, bit = 21, F2 +#define BITBAND_F3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,22) //Port = 1, bit = 22, F3 +#define BITBAND_F4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,23) //Port = 1, bit = 23, F4 +#define BITBAND_F5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,24) //Port = 1, bit = 24, F5 -#define GPIO_G0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,25) //Port = 1, bit = 25, G0 -#define GPIO_G1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,26) //Port = 1, bit = 26, G1 -#define GPIO_G2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,27) //Port = 1, bit = 27, G2 -#define GPIO_G3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,28) //Port = 0, bit = 28, G3 -#define GPIO_G4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,28) //Port = 1, bit = 28, G4 -#define GPIO_G5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,29) //Port = 1, bit = 29, G5 -#define GPIO_G6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,30) //Port = 1, bit = 30, G6 -#define GPIO_G7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,31) //Port = 1, bit = 31, G7 +#define BITBAND_G0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,25) //Port = 1, bit = 25, G0 +#define BITBAND_G1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,26) //Port = 1, bit = 26, G1 +#define BITBAND_G2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,27) //Port = 1, bit = 27, G2 +#define BITBAND_G3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,28) //Port = 0, bit = 28, G3 +#define BITBAND_G4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,28) //Port = 1, bit = 28, G4 +#define BITBAND_G5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,29) //Port = 1, bit = 29, G5 +#define BITBAND_G6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,30) //Port = 1, bit = 30, G6 +#define BITBAND_G7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,31) //Port = 1, bit = 31, G7 -#define GPIO_H0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,0) //Port = 2, bit = 0, H0 -#define GPIO_H1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,29) //Port = 0, bit = 29, H1 -#define GPIO_H2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,1) //Port = 2, bit = 1, H2 -#define GPIO_H3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,30) //Port = 0, bit = 30, H3 -#define GPIO_H4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,2) //Port = 2, bit = 2, H4 -#define GPIO_H5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,31) //Port = 0, bit = 31, H5 -#define GPIO_H6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,3) //Port = 2, bit = 3, H6 -#define GPIO_H7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,4) //Port = 2, bit = 4, H7 +#define BITBAND_H0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,0) //Port = 2, bit = 0, H0 +#define BITBAND_H1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,29) //Port = 0, bit = 29, H1 +#define BITBAND_H2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,1) //Port = 2, bit = 1, H2 +#define BITBAND_H3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,30) //Port = 0, bit = 30, H3 +#define BITBAND_H4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,2) //Port = 2, bit = 2, H4 +#define BITBAND_H5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,31) //Port = 0, bit = 31, H5 +#define BITBAND_H6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,3) //Port = 2, bit = 3, H6 +#define BITBAND_H7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,4) //Port = 2, bit = 4, H7 -#define GPIO_I0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,5) //Port = 2, bit = 5, I0 -#define GPIO_I1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,6) //Port = 2, bit = 6, I1 -#define GPIO_I2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,7) //Port = 2, bit = 7, I2 -#define GPIO_I3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,8) //Port = 2, bit = 8, I3 -#define GPIO_I4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,9) //Port = 2, bit = 9, I4 -#define GPIO_I5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,10) //Port = 2, bit = 10, I5 -#define GPIO_I6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,11) //Port = 2, bit = 11, I6 -#define GPIO_I7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,12) //Port = 2, bit = 12, I7 +#define BITBAND_I0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,5) //Port = 2, bit = 5, I0 +#define BITBAND_I1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,6) //Port = 2, bit = 6, I1 +#define BITBAND_I2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,7) //Port = 2, bit = 7, I2 +#define BITBAND_I3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,8) //Port = 2, bit = 8, I3 +#define BITBAND_I4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,9) //Port = 2, bit = 9, I4 +#define BITBAND_I5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,10) //Port = 2, bit = 10, I5 +#define BITBAND_I6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,11) //Port = 2, bit = 11, I6 +#define BITBAND_I7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,12) //Port = 2, bit = 12, I7 -#define GPIO_J0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,13) //Port = 2, bit = 13, J0 -#define GPIO_J1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,14) //Port = 2, bit = 14, J1 -#define GPIO_J2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,15) //Port = 2, bit = 15, J2 -#define GPIO_J3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,16) //Port = 2, bit = 16, J3 -#define GPIO_J4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,17) //Port = 2, bit = 17, J4 -#define GPIO_J5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,18) //Port = 2, bit = 18, J5 -#define GPIO_J6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,19) //Port = 2, bit = 19, J6 +#define BITBAND_J0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,13) //Port = 2, bit = 13, J0 +#define BITBAND_J1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,14) //Port = 2, bit = 14, J1 +#define BITBAND_J2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,15) //Port = 2, bit = 15, J2 +#define BITBAND_J3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,16) //Port = 2, bit = 16, J3 +#define BITBAND_J4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,17) //Port = 2, bit = 17, J4 +#define BITBAND_J5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,18) //Port = 2, bit = 18, J5 +#define BITBAND_J6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,19) //Port = 2, bit = 19, J6 -#define GPIO_K0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,20) //Port = 2, bit = 20, K0 -#define GPIO_K1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,21) //Port = 2, bit = 21, K1 -#define GPIO_K2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,22) //Port = 2, bit = 22, K2 -#define GPIO_K3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,23) //Port = 2, bit = 23, K3 -#define GPIO_K4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,24) //Port = 2, bit = 24, K4 -#define GPIO_K5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,25) //Port = 2, bit = 25, K5 -#define GPIO_K6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,26) //Port = 2, bit = 26, K6 +#define BITBAND_K0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,20) //Port = 2, bit = 20, K0 +#define BITBAND_K1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,21) //Port = 2, bit = 21, K1 +#define BITBAND_K2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,22) //Port = 2, bit = 22, K2 +#define BITBAND_K3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,23) //Port = 2, bit = 23, K3 +#define BITBAND_K4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,24) //Port = 2, bit = 24, K4 +#define BITBAND_K5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,25) //Port = 2, bit = 25, K5 +#define BITBAND_K6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,26) //Port = 2, bit = 26, K6 #endif // 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z#BVp`C+O1wKlRUstUy7gIk1Jp%NvLkWH=dLiH%JMjz9s{{T? z{PpPT0l(@78@O8SPjLM_wF?{84U%CHq{A>63u!P5QYPdYI@|c4mf%z+ZP1hHosMlc69Kpp(*oc^~i96CT`IhRIZ9&CW)P!BN`+?s|(umiq? p_UB0+1N*?Zz<>C8oz*(n50&797cO!G8|Fb-fNz}{JzeRM{{_$(FLASHER_PATH)flash_file.jlink + @echo SetFirwareSize build/bin/ram_all.bin>>$(FLASHER_PATH)flash_file.jlink + @echo end>>$(FLASHER_PATH)flash_file.jlink + @echo define call2>>$(FLASHER_PATH)flash_file.jlink + @echo FlasherWrite build/bin/ram_all.bin 0 '$$'Image1Size>>$(FLASHER_PATH)flash_file.jlink + @echo end>>$(FLASHER_PATH)flash_file.jlink + @echo define call3>>$(FLASHER_PATH)flash_file.jlink + @echo FlasherWrite build/bin/ram_all.bin '$$'Image2Addr '$$'Image2Size>>$(FLASHER_PATH)flash_file.jlink + @echo end>>$(FLASHER_PATH)flash_file.jlink + @start $(JLINK_PATH)$(JLINK_GDBSRV) -device Cortex-M3 -if SWD -ir -endian little -speed 1000 + @$(GDB) -x $(FLASHER_PATH)gdb_wrflash.jlink + @taskkill /F /IM $(JLINK_GDBSRV) + +flashwebfs: + @echo set '$$'ImageSize = $(shell printf '0x%X\n' $$(stat --printf="%s" $(BIN_DIR)/webpages.espfs))>$(FLASHER_PATH)file_info.jlink + @echo set '$$'ImageAddr = 0x0D0000>>$(FLASHER_PATH)file_info.jlink + @echo define call1>>$(FLASHER_PATH)file_info.jlink + @echo FlasherWrite $(BIN_DIR)/webpages.espfs '$$'ImageAddr '$$'ImageSize>>$(FLASHER_PATH)file_info.jlink + @echo end>>$(FLASHER_PATH)file_info.jlink + @start $(JLINK_PATH)$(JLINK_GDBSRV) -device Cortex-M3 -if SWD -ir -endian little -speed 1000 + @$(GDB) -x $(FLASHER_PATH)gdb_wrfile.jlink + @taskkill /F /IM $(JLINK_GDBSRV) + +flash_OTA: + @start $(JLINK_PATH)$(JLINK_GDBSRV) -device Cortex-M3 -if SWD -ir -endian little -speed 1000 + @$(GDB) -x $(FLASHER_PATH)gdb_ota.jlink + @taskkill /F /IM $(JLINK_GDBSRV) + +else + +flashburn: + @$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \ + -c "rtl8710_flash_auto_erase 1" -c "rtl8710_flash_auto_verify 1" \ + -c "rtl8710_flash_write $(RAM1P_IMAGE) 0" \ + -c "rtl8710_flash_write $(RAM2P_IMAGE) 0xb000" \ + -c "rtl8710_reboot" -c "reset run" -c shutdown + +flashimage2p: + @$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \ + -c "rtl8710_flash_auto_erase 1" -c "rtl8710_flash_auto_verify 1" \ + -c "rtl8710_flash_write $(RAM2P_IMAGE) 0xb000" \ + -c "rtl8710_reboot" -c "reset run" -c shutdown + +flashwebfs: + @$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \ + -c "rtl8710_flash_auto_erase 1" -c "rtl8710_flash_auto_verify 1" \ + -c "rtl8710_flash_write $(BIN_DIR)/webpages.espfs 0xd0000" \ + -c "rtl8710_reboot" -c "reset run" -c shutdown + + +reset: +# @$(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed $(FLASHER_SPEED) flasher/RTLreset.JLinkScript + @$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \ + -c "rtl8710_reboot" -c shutdown + +runram: +# @start $(JLINK_PATH)$(JLINK_GDB) -device Cortex-M3 -if SWD -ir -endian little -speed $(FLASHER_SPEED) +# @$(GDB) -x flasher/gdb_run_ram.jlink +# @taskkill.exe -F -IM $(JLINK_GDB) + @$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \ + -c "load_image $(RAM1R_IMAGE) 0x10000bc8 bin" \ + -c "load_image $(RAM2_IMAGE) 0x10006000 bin" \ + -c "mww 0x40000210 0x20200113" \ + -c "reset run" -c shutdown + +endif $(NMAPFILE): $(ELFFILE) @echo "===========================================================" diff --git a/flasher/gdb_wrfile.jlink b/flasher/gdb_wrfile.jlink new file mode 100644 index 0000000..361dc73 --- /dev/null +++ b/flasher/gdb_wrfile.jlink @@ -0,0 +1,156 @@ +############### +# FlasherInit # +############### +define FlasherInit +set $rtl8710_flasher_capacity = 0 +set $rtl8710_flasher_auto_erase = 1 +set $rtl8710_flasher_auto_verify = 1 +set $rtl8710_flasher_firmware_ptr = 0x10001000 +set $rtl8710_flasher_buffer = 0x10008000 +set $rtl8710_flasher_buffer_size = 421888 +set $rtl8710_flasher_sector_size = 4096 +set $rtl8710_flasher_auto_erase_sector = 0xFFFFFFFF +end +############### +# FlasherWait # +############### +define FlasherWait +set $fresult = {int}($rtl8710_flasher_buffer) +while ($fresult != 0) +set $fresult = {int}($rtl8710_flasher_buffer) +end +end +############### +# FlasherLoad # +############### +define FlasherLoad +if $rtl8710_flasher_capacity == 0 + printf "initializing RTL8710 flasher\n" + restore $arg0 binary $rtl8710_flasher_firmware_ptr 0 968 + monitor reset + set $pc = $rtl8710_flasher_firmware_ptr + set $sp = 0x1ffffffc + set {int}($rtl8710_flasher_buffer + 0x08) = 0 + set {int}($rtl8710_flasher_buffer + 0x00) = 1 + #continue + monitor go + FlasherWait + set $id = {int}($rtl8710_flasher_buffer + 0x0C) + if ($id == 0x1420c2) + set $rtl8710_flasher_capacity = 1 << (($id >> 16) & 0x0ff) + printf "Flash ID = 0x%08x : MX25L8006E (%d kbytes)\n", $id, $rtl8710_flasher_capacity>>10 + else + set $rtl8710_flasher_capacity = 1024*1024) + error "Flash ID = 0x%08x : ?\n", $id + end + printf "RTL8710 flasher initialized\n" +else +printf "reinitializing RTL8710 flasher\n" +end +end +################## +# FlasherWrBlock # +################## +define FlasherWrBlock +#printf "FlashWrBlock 0x%08x, 0x%08x\n", $arg0, $arg1 +set {int}($rtl8710_flasher_buffer + 0x04) = 4 +set {int}($rtl8710_flasher_buffer + 0x08) = 0 +set {int}($rtl8710_flasher_buffer + 0x10) = $arg0 +set {int}($rtl8710_flasher_buffer + 0x14) = $arg1 +set {int}($rtl8710_flasher_buffer + 0x00) = 1 +FlasherWait +set $status = {int}($rtl8710_flasher_buffer + 0x08) +if $status > 0 + error "write error, offset 0x%08x", $arg0 +end +end +################## +# FlasherVrBlock # +################## +define FlasherVrBlock +#printf "FlashVrBlock 0x%08x, 0x%08x\n", $arg0, $arg1 +set {int}($rtl8710_flasher_buffer + 0x04) = 5 +set {int}($rtl8710_flasher_buffer + 0x08) = 0 +set {int}($rtl8710_flasher_buffer + 0x10) = $arg0 +set {int}($rtl8710_flasher_buffer + 0x14) = $arg1 +set {int}($rtl8710_flasher_buffer + 0x00) = 1 +FlasherWait +set $status = {int}($rtl8710_flasher_buffer + 0x08) +if $status > 0 + set $status = {int}($rtl8710_flasher_buffer + 0x0C) + set $status = {int}($status + $arg0) + error "verify error, offset 0x%08x", $status +end +end +################# +# FlashSecErase # +################# +define FlashSecErase +#printf "FlashSecErase 0x%08x, 0x%08x\n", $rtl8710_flasher_buffer, $arg0 +set {int}($rtl8710_flasher_buffer + 0x04) = 2 +set {int}($rtl8710_flasher_buffer + 0x08) = 0 +set {int}($rtl8710_flasher_buffer + 0x10) = $arg0 +set {int}($rtl8710_flasher_buffer + 0x00) = 1 +FlasherWait +end +################ +# FlasherWrite # +################ +define FlasherWrite +set $sector = 0 +set $offset = 0 +set $size = $arg2 +while $offset < $size + set $len = $size - $offset + if $len > $rtl8710_flasher_buffer_size + set $len = $rtl8710_flasher_buffer_size + end + set $flash_offset = $arg1 + $offset + printf "write offset 0x%08x\n", $flash_offset + set $parms1 = $rtl8710_flasher_buffer + 0x20 - $offset + set $parms2 = $offset + set $parms3 = $offset + $len + restore $arg0 binary $parms1 $parms2 $parms3 + if $rtl8710_flasher_auto_erase != 0 + set $count_i = $flash_offset + while $count_i < ($flash_offset + $len) + set $sector = $count_i/$rtl8710_flasher_sector_size + if $rtl8710_flasher_auto_erase_sector != $sector + set $parms1 = $sector * $rtl8710_flasher_sector_size + printf "erase sector %d at 0x%08x\n", $sector, $parms1 + FlashSecErase $parms1 + set $rtl8710_flasher_auto_erase_sector = $sector + end + set $count_i = $count_i + 1 + end + end + FlasherWrBlock $flash_offset $len + printf "wrote %d bytes at 0x%08x\n", $len, $flash_offset + if $rtl8710_flasher_auto_verify != 0 + printf "verify offset 0x%08x len %d\n", $flash_offset, $len + FlasherVrBlock $flash_offset $len + end + set $offset = $offset + $rtl8710_flasher_buffer_size +end +end +######################################### +source -v flasher/gdb_flasher.jlink +source -v flasher/file_info.jlink +InitJlink +SystemInit +SetClk83MHz +SPI_Init +FlasherInit +FlasherLoad flasher/rtl8710_flasher.bin +if $ImageSize != 0 +set $ImageEnd = $ImageSize + $ImageAddr + 0x4000 +if $rtl8710_flasher_capacity >= $ImageEnd + printf "Write Image size %d to Flash addr 0x%08x:\n", $ImageSize, $ImageAddr + call1 +else + printf "Error: Image size is too big!\n" +end +else + printf "Error: Image size is zero!\n" +end +quit diff --git a/flasher/gdb_wrflash.jlink b/flasher/gdb_wrflash.jlink index c07f501..6d37642 100644 --- a/flasher/gdb_wrflash.jlink +++ b/flasher/gdb_wrflash.jlink @@ -106,9 +106,9 @@ while $offset < $size end set $flash_offset = $arg1 + $offset printf "write offset 0x%08x\n", $flash_offset - set $parms1 = $rtl8710_flasher_buffer + 0x20 - $offset - $arg1 - set $parms2 = $offset + $arg1 - set $parms3 = $offset + $len + $arg1 + set $parms1 = $rtl8710_flasher_buffer + 0x20 - $flash_offset + set $parms2 = $flash_offset + set $parms3 = $flash_offset + $len restore $arg0 binary $parms1 $parms2 $parms3 if $rtl8710_flasher_auto_erase != 0 set $count_i = $flash_offset diff --git a/jlinkarm.py b/jlinkarm.py new file mode 100644 index 0000000..b856da1 --- /dev/null +++ b/jlinkarm.py @@ -0,0 +1,113 @@ +import ctypes + +_jl = None + +def loadJLinkARMdll(lib_str): + global _jl + _jl = ctypes.cdll.LoadLibrary(lib_str) + if _jl: + return _jl + else: + raise RuntimeError('JLink ARM dynamic library is not loaded') + +def _jlink(): + if _jl: + return _jl + else: + raise RuntimeError('JLink ARM dynamic library is not loaded') + +def open(): + r = _jlink().JLINKARM_Open() + if r != 0: raise RuntimeError('Adapter is not found') + +def exec_command(cmd, a, b): + r = _jlink().JLINKARM_ExecCommand(cmd, a, b) + #if r != 0: raise RuntimeError('Unable to execute command') + +def tif_select(n): + if not isinstance(n, ctypes.c_ulong): + n = ctypes.c_ulong(n) + r = _jlink().JLINKARM_TIF_Select(n) + if r != 0: raise RuntimeError('Unable to select TIF') + +def set_speed(speed): + if not isinstance(speed, ctypes.c_ulong): + speed = ctypes.c_ulong(speed) + r = _jlink().JLINKARM_SetSpeed(speed) + #if r != 0: raise RuntimeError('Unable to set speed') + +def reset(): + r = _jlink().JLINKARM_Reset() + if r != 0: raise RuntimeError('fail') + +def is_connected(): + if _jlink().JLINKARM_IsConnected() != 0: return True + else: return False + +def go(): + r = _jlink().JLINKARM_Go() + #if r != 0: raise RuntimeError('fail') + +def write_u32(r, val): + if not isinstance(val, ctypes.c_ulong): + val = ctypes.c_ulong(val) + r = _jlink().JLINKARM_WriteU32(r, val) + if r != 0: raise RuntimeError('fail') + +def read_reg(r): + return _jlink().JLINKARM_ReadReg(r) + +def write_reg(r, val): + if not isinstance(val, ctypes.c_ulong): + val = ctypes.c_ulong(val) + ret = _jlink().JLINKARM_WriteReg(r, val) + #if ret != 0: raise RuntimeError('fail') + +def get_speed(): + return _jlink().JLINKARM_GetSpeed() + +def write_mem(startaddress, buf): + _jlink().JLINKARM_WriteMem.argtypes = [ctypes.c_int, ctypes.c_int, ctypes.c_char_p] + _jlink().JLINKARM_WriteMem.restype = ctypes.c_int + print "writemem addr %s size %s" % (hex(startaddress), hex(len(buf))) + r = _jlink().JLINKARM_WriteMem(startaddress, len(buf), buf) + #if r != 0: raise RuntimeError('fail') + +def read_mem_U32(startaddress, count): + buftype=ctypes.c_uint32 * int(count) + buf=buftype() + r=_jlink().JLINKARM_ReadMemU32(startaddress, count, buf, 0) + #if r != 0: raise RuntimeError('fail') + return buf + +def close(): + r = _jlink().JLINKARM_Close() + #if r != 0: raise RuntimeError('fail') + +def clear_TCK(): + r = _jlink().JLINKARM_ClrTCK() +def set_TCK(): + r = _jlink().JLINKARM_SetTCK() + +def clear_TMS(): + r = _jlink().JLINKARM_ClrTMS() +def set_TMS(): + r = _jlink().JLINKARM_SetTMS() + +def clear_TDI(): + r = _jlink().JLINKARM_ClrTDI() +def set_TDI(): + r = _jlink().JLINKARM_SetTDI() + +def clear_TRST(): + r = _jlink().JLINKARM_ClrTRST() +def set_TRST(): + r = _jlink().JLINKARM_SetTRST() + +def clear_RESET(): + r = _jlink().JLINKARM_ClrRESET() +def set_RESET(): + r = _jlink().JLINKARM_SetRESET() + +def halt(): + r = _jlink().JLINKARM_Halt() diff --git a/project/inc/rtl8195a/rtl_libc.h b/project/inc/rtl8195a/rtl_libc.h new file mode 100644 index 0000000..0af1874 --- /dev/null +++ b/project/inc/rtl8195a/rtl_libc.h @@ -0,0 +1,162 @@ +/* +* ROM calls +*/ + +#ifndef _INC_RTL_LIBC_ +#define _INC_RTL_LIBC_ + +//#undef malloc +#define malloc(size) pvPortMalloc(size) +//#undef free +#define free(pbuf) vPortFree(pbuf) + +#define calloc(nelements, elementSize) calloc_freertos(nelements, elementSize) + +#define snprintf rtl_snprintf +#define sprintf rtl_sprintf +#define printf rtl_printf +#define vprintf rtl_vprintf +#define vsnprintf rtl_vsnprintf +#define vfprintf rtl_vfprintf +#define memchr rtl_memchr +#define memcmp rtl_memcmp +#define memcpy rtl_memcpy +#define memmove rtl_memmove +#define memset rtl_memset +#define strcat rtl_strcat +#define strchr rtl_strchr +#define strcmp rtl_strcmp +#define strcpy rtl_strcpy +#define strlen rtl_strlen +#define strncat rtl_strncat +#define strncmp rtl_strncmp +#define strncpy rtl_strncpy +#define strstr rtl_strstr +#define strsep rtl_strsep +#define strtok rtl_strtok + +#define dtoi rtl_dtoi +#define dtoui rtl_dtoui +#define i2f rtl_i2f +#define i2d rtl_i2d +#define ui2f rtl_ui2f +#define ui2d rtl_ui2d +#define itoa rtl_itoa +#define ltoa rtl_ltoa +#define utoa rtl_utoa +#define ultoa rtl_ultoa +#define ftol rtl_ftol +#define ftod rtl_ftod +#define dtof rtl_dtof +#define fadd rtl_fadd +#define fsub rtl_fsub +#define fmul rtl_fmul +#define fdiv rtl_fdiv +#define dadd rtl_dadd +#define dsub rtl_dsub +#define dmul rtl_dmul +#define ddiv rtl_ddiv +#define dcmpeq rtl_dcmpeq +#define dcmplt rtl_dcmplt +#define dcmple rtl_dcmple +#define dcmpgt rtl_dcmpgt +#define fcmplt rtl_fcmplt +#define fcmpgt rtl_fcmpgt + +#define fabsf rtl_fabsf +#define fabs rtl_fabs +#define cos_f32 rtl_cos_f32 +#define sin_f32 rtl_sin_f32 + + +#if 0 +extern void *calloc_freertos(size_t nelements, size_t elementSize); +// ram_libc.c +extern int rtl_snprintf(char *str, size_t size, const char *fmt, ...); +extern int rtl_sprintf(char *str, const char *fmt, ...); +extern int rtl_printf(const char *fmt, ...); +extern int rtl_vprintf(const char *fmt, void *param); +extern int rtl_vsnprintf(char *str, size_t size, const char *fmt, void *param); +extern int rtl_vfprintf(FILE *fp, const char *fmt0, va_list ap); +extern int rtl_memchr(const void *src_void, int c, size_t length); +extern int rtl_memcmp(const void *m1, const void *m2, size_t n); +extern int rtl_memcpy(void *dst0, const void *src0, size_t len0); +extern int rtl_memmove(void *dst_void, const void *src_void, size_t length); +extern int rtl_memset(void *m, int c, size_t n); +extern char * rtl_strcat(char *s1, const char *s2); +extern char * rtl_strchr(const char *s1, int i); +extern int rtl_strcmp(const char *s1, const char *s2); +extern char * rtl_strcpy(char *dst0, const char *src0); +extern int rtl_strlen(const char *str); +extern char * rtl_strncat(char *s1, const char *s2, size_t n); +extern int rtl_strncmp(const char *s1, const char *s2, size_t n); +extern char * rtl_strncpy(char *dst0, const char *src0, size_t count); +extern char * rtl_strstr(const char *searchee, const char *lookfor); +extern char * rtl_strsep(char **source_ptr, const char *delim); +extern char * rtl_strtok(char *s, const char *delim); + +//rtl_eabi_cast_ram.c +extern int rtl_dtoi(double d); +extern int rtl_dtoui(double d); +extern float rtl_i2f(int val); +extern int rtl_i2d(int val); +extern float rtl_ui2f(unsigned int val); +extern int rtl_ui2d(unsigned int val); +extern char *rtl_itoa(int value, char *string, int radix); +extern char *rtl_ltoa(int value, char *string, int radix); +extern char *rtl_utoa(unsigned int value, char *string, int radix); +extern char *rtl_ultoa(unsigned int value, char *string, int radix); +extern int rtl_ftol(float f); +extern int rtl_ftod(float f); +extern float rtl_dtof(double d); +extern float rtl_fadd(float a, float b); +extern float rtl_fsub(float a, float b); +extern float rtl_fmul(float a, float b); +extern float rtl_fdiv(float a, float b); +extern int rtl_dadd(double a, double b); +extern int rtl_dsub(double a, double b); +extern int rtl_dmul(double a, double b); +extern int rtl_ddiv(double a, double b); +extern int rtl_dcmpeq(double a, double b); +extern int rtl_dcmplt(double a, double b); +extern int rtl_dcmple(double a, double b); +extern int rtl_dcmpgt(double a, double b); +extern int rtl_fcmplt(float a, float b); +extern int rtl_fcmpgt(float a, float b); + +// rtl_math_ram.c +extern float rtl_fabsf(float a); +extern int rtl_fabs(double a); +extern float rtl_cos_f32(float a); +extern float rtl_sin_f32(float a); + +// ram_pvvx_libc.c +extern int snprintf(char *str, size_t size, const char *fmt, ...); +extern int sprintf(char *str, const char *fmt, ...); +extern int printf(const char *fmt, ...); +extern int vprintf(const char *fmt, void *param); +extern int vsnprintf(char *str, size_t size, const char *fmt, void *param); +extern int vfprintf(FILE *fp, const char *fmt0, va_list ap); +extern int memchr(const void *src_void, int c, size_t length); +extern int memcmp(const void *m1, const void *m2, size_t n); +extern int memcpy(void *dst0, const void *src0, size_t len0); +extern int memmove(void *dst_void, const void *src_void, size_t length); +extern int memset(void *m, int c, size_t n); +extern char * strcat(char *s1, const char *s2); +extern char * strchr(const char *s1, int i); +extern int strcmp(const char *s1, const char *s2); +extern char * strcpy(char *dst0, const char *src0); +extern int strlen(const char *str); +extern char * strncat(char *s1, const char *s2, size_t n); +extern int strncmp(const char *s1, const char *s2, size_t n); +extern char * strncpy(char *dst0, const char *src0, size_t count); +extern char * strstr(const char *searchee, const char *lookfor); +extern char * strsep(char **source_ptr, const char *delim); +extern char * strtok(char *s, const char *delim); +extern int sscanf(const char *buf, const char *fmt, ...); +extern char toupper(char ch); +extern int _stricmp (const char *s1, const char *s2); +extern unsigned long long __aeabi_llsr(unsigned long long val, unsigned int shift); +#endif + +#endif // _INC_RTL_LIBC_ \ No newline at end of file diff --git a/project/src/user/main.c b/project/src/user/main.c index cee3de4..31195c3 100644 --- a/project/src/user/main.c +++ b/project/src/user/main.c @@ -508,6 +508,19 @@ void ShowMemInfo(void) HalGetCpuClk(), xPortGetFreeHeapSize(), tcm_heap_freeSpace()); } + +void user_init_thrd(void) { + + wifi_init(); + + /* Initilaize the console stack */ + console_init(); + + /* Kill init thread after all init tasks done */ + vTaskDelete(NULL); +} + + /** * @brief Main program. * @param None @@ -544,7 +557,7 @@ void main(void) mp3_cfg_read(); /* wlan & user_start intialization */ - xTaskCreate(wifi_init_thrd, "wc_start", 1024, NULL, tskIDLE_PRIORITY + 0 + PRIORITIE_OFFSET, NULL); + xTaskCreate(user_init_thrd, "user_init", 1024, NULL, tskIDLE_PRIORITY + 0 + PRIORITIE_OFFSET, NULL); /*Enable Schedule, Start Kernel*/ #if defined(CONFIG_KERNEL) && !TASK_SCHEDULER_DISABLED diff --git a/project/src/user/wifi_console.c b/project/src/user/wifi_console.c new file mode 100644 index 0000000..cc11f23 --- /dev/null +++ b/project/src/user/wifi_console.c @@ -0,0 +1,294 @@ +/* + * wifi_console.c + * + * Created on: 03/04/2017 + * Author: pvvx + */ + +#include +#include "FreeRTOS.h" +#include "diag.h" +#include "wifi_api.h" +#include "rtl8195a/rtl_libc.h" +#include "hal_platform.h" + +#include "section_config.h" +#include "hal_diag.h" +#include "lwip/netif.h" + + +extern struct netif xnetif[NET_IF_NUM]; + +//========================================================== +//--- CONSOLE -------------------------- + +// ATPN=[,password[,encryption[,auto reconnect[,reconnect pause]]]: WIFI Connect to AP +void fATPN(int argc, char *argv[]){ + if(argc > 1) { + if(argv[1][0] == '?') { + show_wifi_st_cfg(); + } + else { + strncpy(wifi_st_cfg.ssid, argv[1], NDIS_802_11_LENGTH_SSID); + if(argc > 2) { + strncpy(wifi_st_cfg.password, argv[2], NDIS_802_11_LENGTH_SSID); + int i = strlen(wifi_st_cfg.password); + if(i > 7) { + wifi_st_cfg.security_type = RTW_SECURITY_WPA2_AES_PSK; + } + else if(!i) { + wifi_st_cfg.security_type = RTW_SECURITY_OPEN; + } + else { + printf("password len < 8!\n"); + wifi_st_cfg.security_type = RTW_SECURITY_OPEN; + } + } + else { + wifi_st_cfg.password[0] = 0; + wifi_st_cfg.security_type = RTW_SECURITY_OPEN; + } + if(argc > 3) { + wifi_st_cfg.security_type = translate_rtw_security(atoi(argv[3])); + } + if(argc > 4) { + wifi_st_cfg.autoreconnect = atoi(argv[3]); + } + else wifi_st_cfg.autoreconnect = 0; + if(argc > 5) { + wifi_st_cfg.reconnect_pause = atoi(argv[3]); + } + else wifi_st_cfg.reconnect_pause = 5; + show_wifi_st_cfg(); + wifi_run(wifi_run_mode | RTW_MODE_STA); + } + } +} + +// ATPA=[,password[,encryption[,channel[,hidden[,max connections]]]]]: Start WIFI AP +void fATPA(int argc, char *argv[]){ + if(argc > 1) { + if(argv[1][0] == '?') { + show_wifi_ap_cfg(); + } + else { + strncpy(wifi_ap_cfg.ssid, argv[1], NDIS_802_11_LENGTH_SSID); + if(argc > 2) { + strncpy(wifi_ap_cfg.password, argv[2], NDIS_802_11_LENGTH_SSID); + int i = strlen(wifi_ap_cfg.password); + if(i > 7) { + wifi_ap_cfg.security_type = RTW_SECURITY_WPA2_AES_PSK; + } + else if(i == 0) { + wifi_ap_cfg.security_type = RTW_SECURITY_OPEN; + } + else { + printf("password len < 8!\n"); + wifi_ap_cfg.security_type = RTW_SECURITY_OPEN; + } + } + else { + wifi_ap_cfg.password[0] = 0; + wifi_ap_cfg.security_type = RTW_SECURITY_OPEN; + } + if(argc > 3) { + wifi_ap_cfg.security_type = translate_rtw_security(atoi(argv[3])); + } + if(argc > 4) { + wifi_ap_cfg.channel = atoi(argv[4]); + } + else wifi_ap_cfg.channel = 1; + if(argc > 5) { + wifi_ap_cfg.ssid_hidden = atoi(argv[5]); + } + else wifi_ap_cfg.ssid_hidden = 0; + + if(argc > 6) { + wifi_ap_cfg.max_sta = atoi(argv[6]); + } + else wifi_ap_cfg.max_sta = 3; + + show_wifi_ap_cfg(); + wifi_run(wifi_run_mode | RTW_MODE_AP); + } + } +} + +// WIFI Connect, Disconnect +void fATWR(int argc, char *argv[]){ + rtw_mode_t mode = RTW_MODE_NONE; + if(argc > 1) mode = atoi(argv[1]); + wifi_run(mode); +} + +// Close connections +void fATOF(int argc, char *argv[]){ + connect_close(); +} + +// Open connections +void fATON(int argc, char *argv[]){ + connect_start(); +} + +void fATWI(int argc, char *argv[]) { + rtw_wifi_setting_t Setting; + if((wifi_run_mode & RTW_MODE_AP) + && wifi_get_setting(wlan_ap_name, &Setting) == 0) { + wifi_show_setting(wlan_ap_name, &Setting); +// show_wifi_ap_ip(); + printf("\tIP: " IPSTR "\n", IP2STR(&xnetif[WLAN_AP_NETIF_NUM].ip_addr)); + } + if((wifi_run_mode & RTW_MODE_STA) + && wifi_get_setting(wlan_st_name, &Setting) == 0) { + wifi_show_setting(wlan_st_name, &Setting); +// show_wifi_st_ip(); + printf("\tIP: " IPSTR "\n", IP2STR(&xnetif[WLAN_ST_NETIF_NUM].ip_addr)); + } + printf("\nWIFI config:\n"); + printf(&str_rom_57ch3Dch0A[25]); // "================================\n" + show_wifi_cfg(); + printf("\nWIFI AP config:\n"); + printf(&str_rom_57ch3Dch0A[25]); // "================================\n" + show_wifi_ap_cfg(); + printf("\nWIFI ST config:\n"); + printf(&str_rom_57ch3Dch0A[25]); // "================================\n" + show_wifi_st_cfg(); + printf("\n"); + if(argc > 1 + && (argv[1][0] == 's' + || argv[1][0] == 'S')) { + int i = atoi(argv[2]); + printf("Save configs(%d)..\n", i); + write_wifi_cfg(atoi(argv[2])); + } +} + +extern uint8_t rtw_power_percentage_idx; + +void fATWT(int argc, char *argv[]) { + if(argc > 1) { + int txpwr = atoi(argv[1]); + debug_printf("set tx power (%d)...\n", txpwr); + if(rltk_set_tx_power_percentage(txpwr) != RTW_SUCCESS) { + error_printf("Error set tx power (%d)!", wifi_cfg.tx_pwr); + } + } + printf("TX power = %d\n", rtw_power_percentage_idx); +} + +//-- Test tsf (64-bits counts, 1 us step) --- + +#include "hal_com_reg.h" + +#define ReadTSF_Lo32() (*((volatile unsigned int *)(WIFI_REG_BASE + REG_TSFTR))) +#define ReadTSF_Hi32() (*((volatile unsigned int *)(WIFI_REG_BASE + REG_TSFTR1))) + +LOCAL uint64_t get_tsf(void) +{ + return *((uint64_t *)(WIFI_REG_BASE + REG_TSFTR)); +} + +void fATSF(int argc, char *argv[]) +{ + uint64_t tsf = get_tsf(); + printf("\nTSF: %08x%08x\n", (uint32_t)(tsf>>32), (uint32_t)(tsf)); +} + +/* -------- WiFi Scan ------------------------------- */ +unsigned char *tab_txt_rtw_secyrity[] = { + "OPEN ", + "WEP ", + "WPA TKIP", + "WPA AES", + "WPA2 AES", + "WPA2 TKIP", + "WPA2 Mixed", + "WPA/WPA2 AES", + "Unknown" +}; +unsigned int *tab_code_rtw_secyrity[] = { + RTW_SECURITY_OPEN, + RTW_SECURITY_WEP_PSK, + RTW_SECURITY_WPA_TKIP_PSK, + RTW_SECURITY_WPA_AES_PSK, + RTW_SECURITY_WPA2_AES_PSK, + RTW_SECURITY_WPA2_TKIP_PSK, + RTW_SECURITY_WPA2_MIXED_PSK, + RTW_SECURITY_WPA_WPA2_MIXED, + RTW_SECURITY_UNKNOWN +}; + +volatile uint8_t scan_end; + +/* -------- WiFi Scan ------------------------------- */ +static rtw_result_t _scan_result_handler( rtw_scan_handler_result_t* malloced_scan_result ) +{ + if (malloced_scan_result->scan_complete != RTW_TRUE) { + rtw_scan_result_t* record = &malloced_scan_result->ap_details; + record->SSID.val[record->SSID.len] = 0; /* Ensure the SSID is null terminated */ + if(scan_end == 1) { + printf("\nScan networks:\n\n"); + printf("N\tType\tMAC\t\t\tSignal\tCh\tWPS\tSecyrity\tSSID\n\n"); + }; + printf("%d\t", scan_end++); + printf("%s\t", (record->bss_type == RTW_BSS_TYPE_ADHOC)? "Adhoc": "Infra"); + printf(MAC_FMT, MAC_ARG(record->BSSID.octet)); + printf("\t%d\t", record->signal_strength); + printf("%d\t", record->channel); + printf("%d\t", record->wps_type); + int i = 0; + for(; record->security != tab_code_rtw_secyrity[i] && tab_code_rtw_secyrity[i] != RTW_SECURITY_UNKNOWN; i++); + printf("%s \t", tab_txt_rtw_secyrity[i]); + printf("%s\n", record->SSID.val); + } else { + scan_end = 0; + printf("\n"); + } + return RTW_SUCCESS; +} +/* -------- WiFi Scan ------------------------------- */ +#define scan_channels 14 +void fATSN(int argc, char *argv[]) +{ + int i; + u8 *channel_list = (u8*)pvPortMalloc(scan_channels*2); + if(channel_list) { + scan_end = 1; + u8 * pscan_config = &channel_list[scan_channels]; + //parse command channel list + for(i = 1; i <= scan_channels; i++){ + *(channel_list + i - 1) = i; + *(pscan_config + i - 1) = PSCAN_ENABLE; + }; + if(wifi_set_pscan_chan(channel_list, pscan_config, scan_channels) < 0){ + printf("ERROR: wifi set partial scan channel fail\n"); + } else if(wifi_scan_networks(_scan_result_handler, NULL ) != RTW_SUCCESS){ + printf("ERROR: wifi scan failed\n"); + } else { + i = 300; + while(i-- && scan_end) { + vTaskDelay(10); + }; + }; + vPortFree(channel_list); + } else { + printf("ERROR: Can't malloc memory for channel list\n"); + }; +} + +MON_RAM_TAB_SECTION COMMAND_TABLE console_cmd_wifi_api[] = { + {"ATPN", 1, fATPN, "=[,password[,encryption[,auto-reconnect[,reconnect pause]]]: WIFI Connect to AP"}, + {"ATPA", 1, fATPA, "=[,password[,encryption[,channel[,hidden[,max connections]]]]]: Start WIFI AP"}, + {"ATWR", 0, fATWR, ": WIFI Connect, Disconnect"}, + {"ATON", 0, fATON, ": Open connections"}, + {"ATOF", 0, fATOF, ": Close connections"}, + {"ATWI", 0, fATWI, "=[s]: WiFi Info, s - save"}, +#if CONFIG_DEBUG_LOG > 3 + {"ATWT", 1, fATWT, "=: WiFi tx power: 0 - 100%, 1 - 75%, 2 - 50%, 3 - 25%, 4 - 12.5%"}, + {"ATSF", 0, fATSF, ": Test TSF value"}, +#endif + {"ATSN", 0, fATSN, ": Scan networks"} +}; + + diff --git a/runram.py b/runram.py new file mode 100644 index 0000000..c4c3cb3 --- /dev/null +++ b/runram.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +# -*- coding: cp1251 -*- +import jlinkarm as jl +import os, sys, time, struct + +dllfilename = 'D:/MCU/SEGGER/JLink_V612i/JLinkARM.dll' + +if __name__ == '__main__': + if len(sys.argv) >= 2: + if sys.argv[1] == '-h': + print 'Usage: ldram.py ram_all.bin' + exit(0) + imgfilename = 'build/bin/ram_all.bin' + + if len(sys.argv) > 1: + if sys.argv[1]: + imgfilename = sys.argv[1] + try: + ff = open(imgfilename, "rb") + except: + print "Error file open " + imgfilename + exit(1) + jl.loadJLinkARMdll(dllfilename) + jl.open() + if jl.is_connected == 0: + raise RuntimeError('Jlink not connected') + jl.exec_command('device Cortex-M3', 0, 0) + jl.exec_command('endian little', 0, 0) + jl.tif_select(1) + jl.set_speed(1000) + jl.clear_RESET() + jl.clear_TRST() + time.sleep(0.01) + jl.set_RESET() + jl.set_TRST() + jl.reset() + jl.halt() + jl.set_speed(3500) + bin = ff.read() + get_dword = lambda address: struct.unpack('