diff --git a/Makefile b/Makefile index 54c7506..3444c2c 100644 --- a/Makefile +++ b/Makefile @@ -7,6 +7,9 @@ ram_all: @$(MAKE) -f sdkbuild.mk @$(MAKE) -f flasher.mk genbin1 genbin23 +webfs: + @$(MAKE) -f webfs.mk webpages.espfs + .PHONY: ram_all_mp ram_all_mp: @$(MAKE) -f sdkbuild.mk mp @@ -15,33 +18,32 @@ ram_all_mp: .PHONY: clean clean_all clean: @$(MAKE) -f sdkbuild.mk clean + @$(MAKE) -f webfs.mk clean clean_all: @$(MAKE) -f sdkbuild.mk clean_all + @$(MAKE) -f webfs.mk clean -.PHONY: debug ramdebug -debug: - @$(MAKE) -f application.mk debug - -ramdebug: - @$(MAKE) -f application.mk ramdebug - -.PHONY: flash_OTA flashburn runram reset test readfullflash - -flash_OTA: - JLinkGDB_OTA.bat - +.PHONY: flashburn runram reset test readfullflash flashwebfs flashburn: - JLinkGDB-WrFlash.bat - #@$(MAKE) -f flasher.mk flashburn + #JLinkGDB-WrFlash.bat + @$(MAKE) -f flasher.mk flashburn + +flash_OTA: + @$(MAKE) -f flasher.mk flash_OTA + +flashwebfs: + @$(MAKE) -f webfs.mk webpages.espfs + @$(MAKE) -f flasher.mk flashwebfs + #JLinkGDB-WrWebFs.bat runram: - JLink-RunRAM.bat - #@$(MAKE) --f flasher.mk runram + #JLink-RunRAM.bat + @$(MAKE) --f flasher.mk runram reset: - JLink-Reset.bat - #@make -f flasher.mk reset + #JLink-Reset.bat + @$(MAKE) -f flasher.mk reset test: JLink-RTL00ConsoleROM.bat @@ -54,6 +56,4 @@ readfullflash: .PHONY: prerequirement prerequirement: @$(file >DEPENDENCY_LIST.txt,$(DEPENDENCY_LIST)) - -#TARGETTYPE := APP -#TARGETNAME := build\obj\build.axf + \ No newline at end of file diff --git a/RTL00_SDKV35a/component/common/api/wifi_api.c b/RTL00_SDKV35a/component/common/api/wifi_api.c index a194b6a..133cf16 100644 --- a/RTL00_SDKV35a/component/common/api/wifi_api.c +++ b/RTL00_SDKV35a/component/common/api/wifi_api.c @@ -88,11 +88,11 @@ typedef struct _feep_element { } FEEP_ELEMENT, *PFEEP_ELEMENT; FEEP_ELEMENT feep_tab[] = { - { FEEP_ID_WIFI_AP_CFG, sizeof(wifi_ap_cfg), &wifi_ap_cfg }, // Bit0 - { FEEP_ID_WIFI_ST_CFG, sizeof(wifi_st_cfg), &wifi_st_cfg }, // Bit1 - { FEEP_ID_AP_DHCP_CFG, sizeof(wifi_ap_dhcp), &wifi_ap_dhcp }, // Bit2 - { FEEP_ID_ST_DHCP_CFG, sizeof(wifi_st_dhcp), &wifi_st_dhcp }, // Bit3 - { FEEP_ID_WIFI_CFG, sizeof(wifi_cfg), &wifi_cfg }, // Bit4 + { FEEP_ID_WIFI_AP_CFG, sizeof(wifi_ap_cfg), &wifi_ap_cfg }, // Bit0 BID_WIFI_AP_CFG + { FEEP_ID_WIFI_ST_CFG, sizeof(wifi_st_cfg), &wifi_st_cfg }, // Bit1 BID_WIFI_ST_CFG + { FEEP_ID_AP_DHCP_CFG, sizeof(wifi_ap_dhcp), &wifi_ap_dhcp }, // Bit2 BID_AP_DHCP_CFG + { FEEP_ID_ST_DHCP_CFG, sizeof(wifi_st_dhcp), &wifi_st_dhcp }, // Bit3 BID_ST_DHCP_CFG + { FEEP_ID_WIFI_CFG, sizeof(wifi_cfg), &wifi_cfg }, // Bit4 BID_WIFI_CFG // { FEEP_ID_LWIP_CFG, sizeof(lwip_conn_info), &lwip_conn_info }, // Bit5 { 0, 0, NULL } }; @@ -144,11 +144,6 @@ _WEAK void connect_close(void) info_printf("\%s: Time at start %d ms.\n", __func__, xTaskGetTickCount()); } -_WEAK void user_start(void) -{ - info_printf("\%s: Time at start %d ms.\n", __func__, xTaskGetTickCount()); -} - int wlan_init_done_callback(void) { info_printf("WiFi Init after %d ms\n", xTaskGetTickCount()); return 0; @@ -479,9 +474,9 @@ error_end: return ret; } -void wifi_init_thrd(void) { +void wifi_init(void) { debug_printf("\nLoad Config\n"); - read_wifi_cfg(DEF_LOAD_CFG); + read_wifi_cfg(wifi_cfg.load_flg); // DEF_LOAD_CFG // Call back from wlan driver after wlan init done p_wlan_init_done_callback = wlan_init_done_callback; // Call back from application layer after wifi_connection success @@ -493,12 +488,7 @@ void wifi_init_thrd(void) { wifi_manager_init(); #endif wifi_run(wifi_cfg.mode); - user_start(); } - /* Initilaize the console stack */ - console_init(); - /* Kill init thread after all init tasks done */ - vTaskDelete(NULL); } rtw_security_t translate_rtw_security(u8 security_type) @@ -563,274 +553,3 @@ void show_wifi_cfg(void) { printf("\tSave flags: %p\n", wifi_cfg.save_flg); } -//========================================================== -//--- CONSOLE -------------------------- -#include "section_config.h" -#include "hal_diag.h" - -// ATPN=[,password[,encryption[,auto reconnect[,reconnect pause]]]: WIFI Connect to AP -void fATPN(int argc, char *argv[]){ - if(argc > 1) { - if(argv[1][0] == '?') { - show_wifi_st_cfg(); - } - else { - strncpy(wifi_st_cfg.ssid, argv[1], NDIS_802_11_LENGTH_SSID); - if(argc > 2) { - strncpy(wifi_st_cfg.password, argv[2], NDIS_802_11_LENGTH_SSID); - int i = strlen(wifi_st_cfg.password); - if(i > 7) { - wifi_st_cfg.security_type = RTW_SECURITY_WPA2_AES_PSK; - } - else if(!i) { - wifi_st_cfg.security_type = RTW_SECURITY_OPEN; - } - else { - printf("password len < 8!\n"); - wifi_st_cfg.security_type = RTW_SECURITY_OPEN; - } - } - else { - wifi_st_cfg.password[0] = 0; - wifi_st_cfg.security_type = RTW_SECURITY_OPEN; - } - if(argc > 3) { - wifi_st_cfg.security_type = translate_rtw_security(atoi(argv[3])); - } - if(argc > 4) { - wifi_st_cfg.autoreconnect = atoi(argv[3]); - } - else wifi_st_cfg.autoreconnect = 0; - if(argc > 5) { - wifi_st_cfg.reconnect_pause = atoi(argv[3]); - } - else wifi_st_cfg.reconnect_pause = 5; - show_wifi_st_cfg(); - wifi_run(wifi_run_mode | RTW_MODE_STA); - } - } -} - -// ATPA=[,password[,encryption[,channel[,hidden[,max connections]]]]]: Start WIFI AP -void fATPA(int argc, char *argv[]){ - if(argc > 1) { - if(argv[1][0] == '?') { - show_wifi_ap_cfg(); - } - else { - strncpy(wifi_ap_cfg.ssid, argv[1], NDIS_802_11_LENGTH_SSID); - if(argc > 2) { - strncpy(wifi_ap_cfg.password, argv[2], NDIS_802_11_LENGTH_SSID); - int i = strlen(wifi_ap_cfg.password); - if(i > 7) { - wifi_ap_cfg.security_type = RTW_SECURITY_WPA2_AES_PSK; - } - else if(i == 0) { - wifi_ap_cfg.security_type = RTW_SECURITY_OPEN; - } - else { - printf("password len < 8!\n"); - wifi_ap_cfg.security_type = RTW_SECURITY_OPEN; - } - } - else { - wifi_ap_cfg.password[0] = 0; - wifi_ap_cfg.security_type = RTW_SECURITY_OPEN; - } - if(argc > 3) { - wifi_ap_cfg.security_type = translate_rtw_security(atoi(argv[3])); - } - if(argc > 4) { - wifi_ap_cfg.channel = atoi(argv[4]); - } - else wifi_ap_cfg.channel = 1; - if(argc > 5) { - wifi_ap_cfg.ssid_hidden = atoi(argv[5]); - } - else wifi_ap_cfg.ssid_hidden = 0; - - if(argc > 6) { - wifi_ap_cfg.max_sta = atoi(argv[6]); - } - else wifi_ap_cfg.max_sta = 3; - - show_wifi_ap_cfg(); - wifi_run(wifi_run_mode | RTW_MODE_AP); - } - } -} - -// WIFI Connect, Disconnect -void fATWR(int argc, char *argv[]){ - rtw_mode_t mode = RTW_MODE_NONE; - if(argc > 1) mode = atoi(argv[1]); - wifi_run(mode); -} - -// Close connections -void fATOF(int argc, char *argv[]){ - connect_close(); -} - -// Open connections -void fATON(int argc, char *argv[]){ - connect_start(); -} - -void fATWI(int argc, char *argv[]) { - rtw_wifi_setting_t Setting; - if((wifi_run_mode & RTW_MODE_AP) - && wifi_get_setting(wlan_ap_name, &Setting) == 0) { - wifi_show_setting(wlan_ap_name, &Setting); -// show_wifi_ap_ip(); - printf("\tIP: " IPSTR "\n", IP2STR(&xnetif[WLAN_AP_NETIF_NUM].ip_addr)); - } - if((wifi_run_mode & RTW_MODE_STA) - && wifi_get_setting(wlan_st_name, &Setting) == 0) { - wifi_show_setting(wlan_st_name, &Setting); -// show_wifi_st_ip(); - printf("\tIP: " IPSTR "\n", IP2STR(&xnetif[WLAN_ST_NETIF_NUM].ip_addr)); - } - printf("\nWIFI config:\n"); - printf(&str_rom_57ch3Dch0A[25]); // "================================\n" - show_wifi_cfg(); - printf("\nWIFI AP config:\n"); - printf(&str_rom_57ch3Dch0A[25]); // "================================\n" - show_wifi_ap_cfg(); - printf("\nWIFI ST config:\n"); - printf(&str_rom_57ch3Dch0A[25]); // "================================\n" - show_wifi_st_cfg(); - printf("\n"); - if(argc > 2 - && (argv[1][0] == 's' - || argv[1][0] == 'S')) { - int i = atoi(argv[2]); - printf("Save configs(%d)..\n", i); - write_wifi_cfg(atoi(argv[2])); - } -} - -void fATWT(int argc, char *argv[]) { - if(argc > 1) { - int txpwr = atoi(argv[1]); - debug_printf("set tx power (%d)...\n", txpwr); - if(rltk_set_tx_power_percentage(txpwr) != RTW_SUCCESS) { - error_printf("Error set tx power (%d)!", wifi_cfg.tx_pwr); - } - } - printf("TX power = %d\n", rtw_power_percentage_idx); -} - -//-- Test tsf (64-bits counts, 1 us step) --- - -#include "hal_com_reg.h" - -#define ReadTSF_Lo32() (*((volatile unsigned int *)(WIFI_REG_BASE + REG_TSFTR))) -#define ReadTSF_Hi32() (*((volatile unsigned int *)(WIFI_REG_BASE + REG_TSFTR1))) - -LOCAL uint64_t get_tsf(void) -{ - return *((uint64_t *)(WIFI_REG_BASE + REG_TSFTR)); -} - -void fATSF(int argc, char *argv[]) -{ - uint64_t tsf = get_tsf(); - printf("\nTSF: %08x%08x\n", (uint32_t)(tsf>>32), (uint32_t)(tsf)); -} - -/* -------- WiFi Scan ------------------------------- */ -unsigned char *tab_txt_rtw_secyrity[] = { - "OPEN ", - "WEP ", - "WPA TKIP", - "WPA AES", - "WPA2 AES", - "WPA2 TKIP", - "WPA2 Mixed", - "WPA/WPA2 AES", - "Unknown" -}; -unsigned int *tab_code_rtw_secyrity[] = { - RTW_SECURITY_OPEN, - RTW_SECURITY_WEP_PSK, - RTW_SECURITY_WPA_TKIP_PSK, - RTW_SECURITY_WPA_AES_PSK, - RTW_SECURITY_WPA2_AES_PSK, - RTW_SECURITY_WPA2_TKIP_PSK, - RTW_SECURITY_WPA2_MIXED_PSK, - RTW_SECURITY_WPA_WPA2_MIXED, - RTW_SECURITY_UNKNOWN -}; - -volatile uint8_t scan_end; - -/* -------- WiFi Scan ------------------------------- */ -static rtw_result_t _scan_result_handler( rtw_scan_handler_result_t* malloced_scan_result ) -{ - if (malloced_scan_result->scan_complete != RTW_TRUE) { - rtw_scan_result_t* record = &malloced_scan_result->ap_details; - record->SSID.val[record->SSID.len] = 0; /* Ensure the SSID is null terminated */ - if(scan_end == 1) { - printf("\nScan networks:\n\n"); - printf("N\tType\tMAC\t\t\tSignal\tCh\tWPS\tSecyrity\tSSID\n\n"); - }; - printf("%d\t", scan_end++); - printf("%s\t", (record->bss_type == RTW_BSS_TYPE_ADHOC)? "Adhoc": "Infra"); - printf(MAC_FMT, MAC_ARG(record->BSSID.octet)); - printf("\t%d\t", record->signal_strength); - printf("%d\t", record->channel); - printf("%d\t", record->wps_type); - int i = 0; - for(; record->security != tab_code_rtw_secyrity[i] && tab_code_rtw_secyrity[i] != RTW_SECURITY_UNKNOWN; i++); - printf("%s \t", tab_txt_rtw_secyrity[i]); - printf("%s\n", record->SSID.val); - } else { - scan_end = 0; - printf("\n"); - } - return RTW_SUCCESS; -} -/* -------- WiFi Scan ------------------------------- */ -#define scan_channels 14 -void fATSN(int argc, char *argv[]) -{ - int i; - u8 *channel_list = (u8*)pvPortMalloc(scan_channels*2); - if(channel_list) { - scan_end = 1; - u8 * pscan_config = &channel_list[scan_channels]; - //parse command channel list - for(i = 1; i <= scan_channels; i++){ - *(channel_list + i - 1) = i; - *(pscan_config + i - 1) = PSCAN_ENABLE; - }; - if(wifi_set_pscan_chan(channel_list, pscan_config, scan_channels) < 0){ - printf("ERROR: wifi set partial scan channel fail\n"); - } else if(wifi_scan_networks(_scan_result_handler, NULL ) != RTW_SUCCESS){ - printf("ERROR: wifi scan failed\n"); - } else { - i = 300; - while(i-- && scan_end) { - vTaskDelay(10); - }; - }; - vPortFree(channel_list); - } else { - printf("ERROR: Can't malloc memory for channel list\n"); - }; -} - -MON_RAM_TAB_SECTION COMMAND_TABLE console_cmd_wifi_api[] = { - {"ATPN", 1, fATPN, "=[,password[,encryption[,auto-reconnect[,reconnect pause]]]: WIFI Connect to AP"}, - {"ATPA", 1, fATPA, "=[,password[,encryption[,channel[,hidden[,max connections]]]]]: Start WIFI AP"}, - {"ATWR", 0, fATWR, ": WIFI Connect, Disconnect"}, - {"ATON", 0, fATON, ": Open connections"}, - {"ATOF", 0, fATOF, ": Close connections"}, - {"ATWI", 0, fATWI, ": WiFi Info"}, -#if CONFIG_DEBUG_LOG > 3 - {"ATWT", 1, fATWT, "=: WiFi tx power: 0 - 100%, 1 - 75%, 2 - 50%, 3 - 25%, 4 - 12.5%"}, - {"ATSF", 0, fATSF, ": Test TSF value"}, -#endif - {"ATSN", 0, fATSN, ": Scan networks"} -}; diff --git a/RTL00_SDKV35a/component/common/api/wifi_api.h b/RTL00_SDKV35a/component/common/api/wifi_api.h index 7513c5c..a3c7e9e 100644 --- a/RTL00_SDKV35a/component/common/api/wifi_api.h +++ b/RTL00_SDKV35a/component/common/api/wifi_api.h @@ -7,11 +7,13 @@ #ifndef _WIFI_API_H_ #define _WIFI_API_H_ +#include "wifi_constants.h" +#include "wifi_conf.h" -#define ip4_addr1(ipaddr) (((u8_t*)(ipaddr))[0]) -#define ip4_addr2(ipaddr) (((u8_t*)(ipaddr))[1]) -#define ip4_addr3(ipaddr) (((u8_t*)(ipaddr))[2]) -#define ip4_addr4(ipaddr) (((u8_t*)(ipaddr))[3]) +#define ip4_addr1(ipaddr) (((uint8_t*)(ipaddr))[0]) +#define ip4_addr2(ipaddr) (((uint8_t*)(ipaddr))[1]) +#define ip4_addr3(ipaddr) (((uint8_t*)(ipaddr))[2]) +#define ip4_addr4(ipaddr) (((uint8_t*)(ipaddr))[3]) #define IPSTR "%d.%d.%d.%d" @@ -97,6 +99,19 @@ typedef struct _dhcp_config { unsigned char mode; // =0 dhcp off, =1 - dhcp on, =2 Static ip, =3 - auto } DHCP_CONFIG, *PDHCP_CONFIG; + +extern WIFI_CONFIG wifi_cfg; +extern SOFTAP_CONFIG wifi_ap_cfg; +extern DHCP_CONFIG wifi_ap_dhcp; +extern STATION_CONFIG wifi_st_cfg; +extern DHCP_CONFIG wifi_st_dhcp; +extern rtw_mode_t wifi_run_mode; +extern char wlan_st_name[]; +extern char wlan_ap_name[]; +extern char wlan_st_netifn; +extern char wlan_ap_netifn; + + void show_wifi_ap_ip(void); void show_wifi_st_ip(void); void show_wifi_cfg(void); @@ -105,6 +120,8 @@ void show_wifi_ap_cfg(void); uint32 read_wifi_cfg(uint32 flg); uint32 write_wifi_cfg(uint32 flg); int wifi_run(rtw_mode_t mode); -void wifi_init_thrd(void); +void wifi_init(void); + +void _LwIP_Init(void); #endif // _WIFI_API_H_ diff --git a/RTL00_SDKV35a/component/common/network/netbios/netbios.c b/RTL00_SDKV35a/component/common/network/netbios/netbios.c index bd85587..cb0db96 100644 --- a/RTL00_SDKV35a/component/common/network/netbios/netbios.c +++ b/RTL00_SDKV35a/component/common/network/netbios/netbios.c @@ -374,8 +374,8 @@ void NETBIOS_CODE_ATTR netbios_init(void) { for(int i = 0; i < NET_IF_NUM; i++) { os_printf("%d: '%s' ", i, netbios_name[i]); } + os_printf("\n"); #endif - pcb = udp_new(); if (pcb != NULL) { /* we have to be allowed to send broadcast packets! */ diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/bitband_io.h b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/bitband_io.h index 120899d..3fb4c60 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/bitband_io.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/bitband_io.h @@ -12,27 +12,27 @@ /* * in hal_platform.h -#define GPIO_REG_BASE 0x40001000 +#define BITBAND_REG_BASE 0x40001000 */ /* * in rtl8195a_gpio.h * -#define GPIO_PORTA_DR 0x00 // data register -#define GPIO_PORTA_DDR 0x04 // data direction -#define GPIO_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software +#define BITBAND_PORTA_DR 0x00 // data register +#define BITBAND_PORTA_DDR 0x04 // data direction +#define BITBAND_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software -#define GPIO_PORTB_DR 0x0c // data register -#define GPIO_PORTB_DDR 0x10 // data direction -#define GPIO_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software +#define BITBAND_PORTB_DR 0x0c // data register +#define BITBAND_PORTB_DDR 0x10 // data direction +#define BITBAND_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software -#define GPIO_PORTC_DR 0x18 // data register -#define GPIO_PORTC_DDR 0x1c // data direction -#define GPIO_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software +#define BITBAND_PORTC_DR 0x18 // data register +#define BITBAND_PORTC_DDR 0x1c // data direction +#define BITBAND_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software -#define GPIO_EXT_PORTA 0x50 // GPIO IN read or OUT read back -#define GPIO_EXT_PORTB 0x54 // GPIO IN read or OUT read back -#define GPIO_EXT_PORTC 0x58 // GPIO IN read or OUT read back +#define BITBAND_EXT_PORTA 0x50 // GPIO IN read or OUT read back +#define BITBAND_EXT_PORTB 0x54 // GPIO IN read or OUT read back +#define BITBAND_EXT_PORTC 0x58 // GPIO IN read or OUT read back */ #define BITBAND_PERI_REF 0x40000000 @@ -41,106 +41,106 @@ #define ucBITBAND_PERI(a,b) *((volatile unsigned char *)BITBAND_PERI(a,b)) #define uiBITBAND_PERI(a,b) *((volatile unsigned int *)BITBAND_PERI(a,b)) -#define GPIO_A0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,0) //Port = 0, bit = 0, A0 -#define GPIO_A1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,1) //Port = 0, bit = 1, A1 -#define GPIO_A2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,0) //Port = 1, bit = 0, A2 -#define GPIO_A3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,1) //Port = 1, bit = 1, A3 -#define GPIO_A4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,2) //Port = 1, bit = 2, A4 -#define GPIO_A5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,3) //Port = 1, bit = 3, A5 -#define GPIO_A6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,4) //Port = 1, bit = 4, A6 -#define GPIO_A7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,5) //Port = 1, bit = 5, A7 +#define BITBAND_A0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,0) //Port = 0, bit = 0, A0 +#define BITBAND_A1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,1) //Port = 0, bit = 1, A1 +#define BITBAND_A2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,0) //Port = 1, bit = 0, A2 +#define BITBAND_A3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,1) //Port = 1, bit = 1, A3 +#define BITBAND_A4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,2) //Port = 1, bit = 2, A4 +#define BITBAND_A5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,3) //Port = 1, bit = 3, A5 +#define BITBAND_A6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,4) //Port = 1, bit = 4, A6 +#define BITBAND_A7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,5) //Port = 1, bit = 5, A7 -#define GPIO_B0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,6) //Port = 1, bit = 6, B0 -#define GPIO_B1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,7) //Port = 1, bit = 7, B1 -#define GPIO_B2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,8) //Port = 1, bit = 8, B2 -#define GPIO_B3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,2) //Port = 0, bit = 2, B3 -#define GPIO_B4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,3) //Port = 0, bit = 3, B4 -#define GPIO_B5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,9) //Port = 1, bit = 9, B5 -#define GPIO_B6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,4) //Port = 0, bit = 4, B6 -#define GPIO_B7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,5) //Port = 0, bit = 5, B7 +#define BITBAND_B0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,6) //Port = 1, bit = 6, B0 +#define BITBAND_B1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,7) //Port = 1, bit = 7, B1 +#define BITBAND_B2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,8) //Port = 1, bit = 8, B2 +#define BITBAND_B3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,2) //Port = 0, bit = 2, B3 +#define BITBAND_B4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,3) //Port = 0, bit = 3, B4 +#define BITBAND_B5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,9) //Port = 1, bit = 9, B5 +#define BITBAND_B6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,4) //Port = 0, bit = 4, B6 +#define BITBAND_B7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,5) //Port = 0, bit = 5, B7 -#define GPIO_C0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,10) //Port = 1, bit = 10, C0 -#define GPIO_C1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,6) //Port = 0, bit = 6, C1 -#define GPIO_C2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,11) //Port = 1, bit = 11, C2 -#define GPIO_C3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,7) //Port = 0, bit = 7, C3 -#define GPIO_C4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,8) //Port = 0, bit = 8, C4 -#define GPIO_C5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,9) //Port = 0, bit = 9, C5 -#define GPIO_C6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,10) //Port = 0, bit = 10, C6 -#define GPIO_C7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,11) //Port = 0, bit = 11, C7 -#define GPIO_C8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,12) //Port = 0, bit = 12, C8 -#define GPIO_C9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,13) //Port = 0, bit = 13, C9 +#define BITBAND_C0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,10) //Port = 1, bit = 10, C0 +#define BITBAND_C1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,6) //Port = 0, bit = 6, C1 +#define BITBAND_C2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,11) //Port = 1, bit = 11, C2 +#define BITBAND_C3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,7) //Port = 0, bit = 7, C3 +#define BITBAND_C4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,8) //Port = 0, bit = 8, C4 +#define BITBAND_C5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,9) //Port = 0, bit = 9, C5 +#define BITBAND_C6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,10) //Port = 0, bit = 10, C6 +#define BITBAND_C7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,11) //Port = 0, bit = 11, C7 +#define BITBAND_C8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,12) //Port = 0, bit = 12, C8 +#define BITBAND_C9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,13) //Port = 0, bit = 13, C9 -#define GPIO_D0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,12) //Port = 1, bit = 12, D0 -#define GPIO_D1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,14) //Port = 0, bit = 14, D1 -#define GPIO_D2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,13) //Port = 1, bit = 13, D2 -#define GPIO_D3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,15) //Port = 0, bit = 15, D3 -#define GPIO_D4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,16) //Port = 0, bit = 16, D4 -#define GPIO_D5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,17) //Port = 0, bit = 17, D5 -#define GPIO_D6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,18) //Port = 0, bit = 18, D6 -#define GPIO_D7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,19) //Port = 0, bit = 19, D7 -#define GPIO_D8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,14) //Port = 1, bit = 14, D8 -#define GPIO_D9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,20) //Port = 0, bit = 20, D9 +#define BITBAND_D0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,12) //Port = 1, bit = 12, D0 +#define BITBAND_D1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,14) //Port = 0, bit = 14, D1 +#define BITBAND_D2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,13) //Port = 1, bit = 13, D2 +#define BITBAND_D3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,15) //Port = 0, bit = 15, D3 +#define BITBAND_D4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,16) //Port = 0, bit = 16, D4 +#define BITBAND_D5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,17) //Port = 0, bit = 17, D5 +#define BITBAND_D6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,18) //Port = 0, bit = 18, D6 +#define BITBAND_D7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,19) //Port = 0, bit = 19, D7 +#define BITBAND_D8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,14) //Port = 1, bit = 14, D8 +#define BITBAND_D9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,20) //Port = 0, bit = 20, D9 -#define GPIO_E0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,15) //Port = 2, bit = 15, E0 -#define GPIO_E1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,21) //Port = 0, bit = 21, E1 -#define GPIO_E2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,22) //Port = 0, bit = 22, E2 -#define GPIO_E3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,23) //Port = 0, bit = 23, E3 -#define GPIO_E4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,16) //Port = 1, bit = 16, E4 -#define GPIO_E5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,24) //Port = 0, bit = 24, E5 -#define GPIO_E6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,25) //Port = 0, bit = 25, E6 -#define GPIO_E7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,26) //Port = 0, bit = 26, E7 -#define GPIO_E8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,27) //Port = 0, bit = 27, E8 -#define GPIO_E9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,17) //Port = 1, bit = 17, E9 -#define GPIO_E10 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,18) //Port = 1, bit = 17, E10 +#define BITBAND_E0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,15) //Port = 2, bit = 15, E0 +#define BITBAND_E1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,21) //Port = 0, bit = 21, E1 +#define BITBAND_E2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,22) //Port = 0, bit = 22, E2 +#define BITBAND_E3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,23) //Port = 0, bit = 23, E3 +#define BITBAND_E4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,16) //Port = 1, bit = 16, E4 +#define BITBAND_E5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,24) //Port = 0, bit = 24, E5 +#define BITBAND_E6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,25) //Port = 0, bit = 25, E6 +#define BITBAND_E7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,26) //Port = 0, bit = 26, E7 +#define BITBAND_E8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,27) //Port = 0, bit = 27, E8 +#define BITBAND_E9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,17) //Port = 1, bit = 17, E9 +#define BITBAND_E10 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,18) //Port = 1, bit = 17, E10 -#define GPIO_F0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,19) //Port = 1, bit = 19, F0 -#define GPIO_F1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,20) //Port = 1, bit = 20, F1 -#define GPIO_F2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,21) //Port = 1, bit = 21, F2 -#define GPIO_F3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,22) //Port = 1, bit = 22, F3 -#define GPIO_F4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,23) //Port = 1, bit = 23, F4 -#define GPIO_F5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,24) //Port = 1, bit = 24, F5 +#define BITBAND_F0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,19) //Port = 1, bit = 19, F0 +#define BITBAND_F1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,20) //Port = 1, bit = 20, F1 +#define BITBAND_F2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,21) //Port = 1, bit = 21, F2 +#define BITBAND_F3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,22) //Port = 1, bit = 22, F3 +#define BITBAND_F4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,23) //Port = 1, bit = 23, F4 +#define BITBAND_F5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,24) //Port = 1, bit = 24, F5 -#define GPIO_G0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,25) //Port = 1, bit = 25, G0 -#define GPIO_G1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,26) //Port = 1, bit = 26, G1 -#define GPIO_G2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,27) //Port = 1, bit = 27, G2 -#define GPIO_G3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,28) //Port = 0, bit = 28, G3 -#define GPIO_G4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,28) //Port = 1, bit = 28, G4 -#define GPIO_G5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,29) //Port = 1, bit = 29, G5 -#define GPIO_G6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,30) //Port = 1, bit = 30, G6 -#define GPIO_G7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,31) //Port = 1, bit = 31, G7 +#define BITBAND_G0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,25) //Port = 1, bit = 25, G0 +#define BITBAND_G1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,26) //Port = 1, bit = 26, G1 +#define BITBAND_G2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,27) //Port = 1, bit = 27, G2 +#define BITBAND_G3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,28) //Port = 0, bit = 28, G3 +#define BITBAND_G4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,28) //Port = 1, bit = 28, G4 +#define BITBAND_G5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,29) //Port = 1, bit = 29, G5 +#define BITBAND_G6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,30) //Port = 1, bit = 30, G6 +#define BITBAND_G7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,31) //Port = 1, bit = 31, G7 -#define GPIO_H0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,0) //Port = 2, bit = 0, H0 -#define GPIO_H1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,29) //Port = 0, bit = 29, H1 -#define GPIO_H2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,1) //Port = 2, bit = 1, H2 -#define GPIO_H3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,30) //Port = 0, bit = 30, H3 -#define GPIO_H4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,2) //Port = 2, bit = 2, H4 -#define GPIO_H5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,31) //Port = 0, bit = 31, H5 -#define GPIO_H6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,3) //Port = 2, bit = 3, H6 -#define GPIO_H7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,4) //Port = 2, bit = 4, H7 +#define BITBAND_H0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,0) //Port = 2, bit = 0, H0 +#define BITBAND_H1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,29) //Port = 0, bit = 29, H1 +#define BITBAND_H2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,1) //Port = 2, bit = 1, H2 +#define BITBAND_H3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,30) //Port = 0, bit = 30, H3 +#define BITBAND_H4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,2) //Port = 2, bit = 2, H4 +#define BITBAND_H5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,31) //Port = 0, bit = 31, H5 +#define BITBAND_H6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,3) //Port = 2, bit = 3, H6 +#define BITBAND_H7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,4) //Port = 2, bit = 4, H7 -#define GPIO_I0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,5) //Port = 2, bit = 5, I0 -#define GPIO_I1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,6) //Port = 2, bit = 6, I1 -#define GPIO_I2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,7) //Port = 2, bit = 7, I2 -#define GPIO_I3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,8) //Port = 2, bit = 8, I3 -#define GPIO_I4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,9) //Port = 2, bit = 9, I4 -#define GPIO_I5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,10) //Port = 2, bit = 10, I5 -#define GPIO_I6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,11) //Port = 2, bit = 11, I6 -#define GPIO_I7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,12) //Port = 2, bit = 12, I7 +#define BITBAND_I0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,5) //Port = 2, bit = 5, I0 +#define BITBAND_I1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,6) //Port = 2, bit = 6, I1 +#define BITBAND_I2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,7) //Port = 2, bit = 7, I2 +#define BITBAND_I3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,8) //Port = 2, bit = 8, I3 +#define BITBAND_I4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,9) //Port = 2, bit = 9, I4 +#define BITBAND_I5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,10) //Port = 2, bit = 10, I5 +#define BITBAND_I6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,11) //Port = 2, bit = 11, I6 +#define BITBAND_I7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,12) //Port = 2, bit = 12, I7 -#define GPIO_J0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,13) //Port = 2, bit = 13, J0 -#define GPIO_J1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,14) //Port = 2, bit = 14, J1 -#define GPIO_J2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,15) //Port = 2, bit = 15, J2 -#define GPIO_J3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,16) //Port = 2, bit = 16, J3 -#define GPIO_J4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,17) //Port = 2, bit = 17, J4 -#define GPIO_J5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,18) //Port = 2, bit = 18, J5 -#define GPIO_J6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,19) //Port = 2, bit = 19, J6 +#define BITBAND_J0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,13) //Port = 2, bit = 13, J0 +#define BITBAND_J1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,14) //Port = 2, bit = 14, J1 +#define BITBAND_J2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,15) //Port = 2, bit = 15, J2 +#define BITBAND_J3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,16) //Port = 2, bit = 16, J3 +#define BITBAND_J4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,17) //Port = 2, bit = 17, J4 +#define BITBAND_J5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,18) //Port = 2, bit = 18, J5 +#define BITBAND_J6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,19) //Port = 2, bit = 19, J6 -#define GPIO_K0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,20) //Port = 2, bit = 20, K0 -#define GPIO_K1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,21) //Port = 2, bit = 21, K1 -#define GPIO_K2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,22) //Port = 2, bit = 22, K2 -#define GPIO_K3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,23) //Port = 2, bit = 23, K3 -#define GPIO_K4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,24) //Port = 2, bit = 24, K4 -#define GPIO_K5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,25) //Port = 2, bit = 25, K5 -#define GPIO_K6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,26) //Port = 2, bit = 26, K6 +#define BITBAND_K0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,20) //Port = 2, bit = 20, K0 +#define BITBAND_K1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,21) //Port = 2, bit = 21, K1 +#define BITBAND_K2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,22) //Port = 2, bit = 22, K2 +#define BITBAND_K3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,23) //Port = 2, bit = 23, K3 +#define BITBAND_K4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,24) //Port = 2, bit = 24, K4 +#define BITBAND_K5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,25) //Port = 2, bit = 25, K5 +#define BITBAND_K6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,26) //Port = 2, bit = 26, K6 #endif // _BITBAND_IO_H_ diff --git a/build/bin/ota.bin b/build/bin/ota.bin index 1a988de..27212c4 100644 Binary files a/build/bin/ota.bin and b/build/bin/ota.bin differ diff --git a/build/bin/ram_2.bin b/build/bin/ram_2.bin index dcae708..2f2341f 100644 Binary files a/build/bin/ram_2.bin and b/build/bin/ram_2.bin differ diff --git a/build/bin/ram_2.ns.bin b/build/bin/ram_2.ns.bin index 0db9858..1844214 100644 Binary files a/build/bin/ram_2.ns.bin and b/build/bin/ram_2.ns.bin differ diff --git a/build/bin/ram_2.p.bin b/build/bin/ram_2.p.bin index 3a9973e..7305577 100644 Binary files a/build/bin/ram_2.p.bin and b/build/bin/ram_2.p.bin differ diff --git a/build/bin/ram_all.bin b/build/bin/ram_all.bin index 7e37e2c..3ac4d32 100644 Binary files a/build/bin/ram_all.bin and b/build/bin/ram_all.bin differ diff --git a/build/obj/build.nmap b/build/obj/build.nmap index fbbb3ff..3c9cee8 100644 --- a/build/obj/build.nmap +++ b/build/obj/build.nmap @@ -908,2293 +908,2293 @@ 10008948 T sscanf 10008962 T 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HalI2SInitRtl8195a_Patch -1001b57e T HalI2SSetRateRtl8195a -1001b5c4 T HalI2SSetWordLenRtl8195a -1001b5ec T HalI2SSetChNumRtl8195a -1001b614 T HalI2SSetPageNumRtl8195a -1001b63c T HalI2SSetPageSizeRtl8195a -1001b666 T HalI2SSetDMABufRtl8195a -1001b6d0 T HalI2SGetTxPageRtl8195a -1001b6f0 T HalI2SPageSendRtl8195a -1001b73c T HalI2SClearAllOwnBitRtl8195a -1001b770 T HalI2SDMACtrlRtl8195a -1001b774 T HalTimerIrq2To7Handle_Patch -1001b7c8 T HalTimerIrqRegisterRtl8195a_Patch -1001b844 T HalTimerIrqUnRegisterRtl8195a_Patch -1001b8bc T HalTimerDeInitRtl8195a_Patch -1001b8f0 T HalTimerReadCountRtl8195a_Patch -1001b908 T HalTimerReLoadRtl8195a_Patch -1001b93c T HalTimerInitRtl8195a_Patch -1001ba10 T HalTimerIrqEnRtl8195a -1001ba24 T HalTimerEnRtl8195a_Patch -1001ba38 T HalTimerDisRtl8195a_Patch -1001ba4c t rtw_ht_operation_update -1001bafe t associated_clients_update.part.11 -1001bb3a T chk_sta_is_alive -1001bb78 T add_RATid -1001bc80 T update_sta_info_apmode -1001bd38 T update_beacon -1001bff8 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T xmitframe_addmic -10029342 T xmitframe_swencrypt -1002936e T rtw_make_wlanhdr -1002954e T rtw_txframes_pending -1002958a T rtw_txframes_sta_ac_pending -100295c0 T rtw_txframes_update_attrib_vcs_info -10029660 T rtw_put_snap -100296a4 T rtw_update_protection -100296ea T rtw_count_tx_stats -1002973a T rtw_free_xmitbuf_ext -1002977c T rtw_alloc_xmitframe -100297d4 T rtw_free_xmitframe -10029826 T rtw_free_xmitframe_queue -10029864 T rtw_get_sta_pending -100298a4 T rtw_xmit_classifier -1002990a T rtw_xmitframe_enqueue -10029918 T rtw_alloc_hwxmits -10029972 T rtw_free_hwxmits -10029988 T _rtw_free_xmit_priv -10029a54 T rtw_init_hwxmits -10029a6c T _rtw_init_xmit_priv -10029c24 T rtw_get_ff_hwaddr -10029c38 T xmitframe_enqueue_for_sleeping_sta -10029df8 t dequeue_xmitframes_to_sleeping_queue -10029e4e T stop_sta_xmit -10029f36 T wakeup_sta_to_xmit -1002a14c T xmit_delivery_enabled_frames -1002a268 T rtw_xmit_tasklet -1002a2c0 T rtw_xmit_mgnt -1002a2c4 T rtw_xmit -1002a5ee T rtw_sctx_done_err -1002a5fa T rtw_alloc_xmitbuf -1002a654 T rtw_free_xmitbuf -1002a6c6 T rtw_alloc_xmitbuf_ext -1002a74c T rtw_sctx_done -1002a752 t rtl8195a_free_rx_ring -1002a760 t bus_write32 -1002a7bc t bus_write16 -1002a818 t bus_write8 -1002a874 t bus_read32 -1002a8ce t bus_read16 -1002a92a t bus_read8 -1002a986 t rtl8195a_free_tx_ring -1002aa14 T rtl8195a_init_desc_ring -1002ab54 T rtl8195a_free_desc_ring -1002ab70 T rtl8195a_reset_desc_ring -1002ac06 T InitLxDmaRtl8195a -1002ad68 T rtl8195a_check_txdesc_closed -1002ade0 t rtl8195a_tx_isr -1002aec4 T InterruptRecognized8195a -1002af54 T InitInterrupt8195a -1002af74 T EnableDMA8195a -1002af9c T EnableInterrupt8195a -1002afdc T DisableDMA8195a -1002afe8 T DisableInterrupt8195a -1002b000 T UpdateInterruptMask8195a -1002b062 T CheckRxTgRtl8195a -1002b09c T rtl8192ee_check_rxdesc_remain -1002b0cc T rtl8195a_recv_tasklet -1002b3e0 T rtl8195a_tx_int_handler -1002b40c T InterruptHandle8195a -1002b680 T rtl8195a_xmit_tasklet -1002b6a8 T lxbus_set_intf_ops -1002b6e8 t GetTxBufDesc -1002b732 t UpdateFirstTxbdtoXmitBuf.isra.3 -1002b764 t check_nic_enough_desc.isra.4 -1002b7b4 T rtl8195ab_init_xmit_priv -1002b7c2 T rtl8195ab_free_xmit_priv -1002b7ca T GetDmaTxbdIdx -1002b7e6 T rtl8195a_enqueue_xmitbuf -1002b80a T rtl8195a_dequeue_xmitbuf -1002b82e T SetTxbdForLxDMARtl8195ab -1002b8ae T UpdateTxbdHostIndex -1002b8ec T rtw_dump_xframe -1002babe T check_tx_desc_resource -1002baf8 T rtw_dequeue_xframe -1002bb8c T rtw_xmitframe_coalesce -1002be40 T rtl8195ab_xmitframe_resume -1002bf36 T rtl8195ab_mgnt_xmit -1002bf72 T rtl8195ab_hal_xmit -1002c080 t Hal_GetEfuseDefinition -1002c0b0 t ResumeTxBeacon -1002c0f4 T UpdateHalRAMask8195A -1002c28c T HalLittleWifiMCUThreadRtl8195a -1002c2e0 T HalCheckInReqStateThreadRtl8195a -1002c32c T HalTDMAChangeStateThreadRtl8195a -1002c378 t rtl8195a_read_chip_version -1002c3ec t Hal_EfuseWordEnableDataWrite -1002c630 t Hal_EfusePowerSwitch -1002c644 t rtl8195a_free_hal_data -1002c65e t StopTxBeacon -1002c6a8 T SetHalODMVar8195A -1002c760 T rtl8195a_start_thread -1002c7c8 T rtl8195a_stop_thread -1002c7ec t Hal_ReadEFuse -1002c95c T GetHalODMVar8195A -1002c970 t rtw_flash_map_update.part.12 -1002ca10 t rtw_flash_map_erase -1002ca54 t Hal_EfusePgPacketWrite -1002ccd0 t Hal_EfuseGetCurrentSize -1002cdb0 t rtw_flash_map_write -1002cf7e T rtl8195a_InitBeaconParameters -1002cfee T _InitBurstPktLen_8195AB -1002cff8 T rtl8195a_set_hal_ops -1002d0d8 T rtl8195a_init_default_value -1002d0da T rtl8195a_InitLLTTable -1002d124 T Hal_GetChnlGroup8195A -1002d160 T rtw_config_map_read -1002d24c T rtw_config_map_write -1002d2f8 T Hal_InitPGData -1002d356 T Hal_EfuseParseIDCode -1002d36e T Hal_ReadPowerValueFromPROM_8195A -1002d40c T Hal_EfuseParseTxPowerInfo_8195A -1002d4a4 T Hal_EfuseParseEEPROMVer_8195A -1002d4ba T Hal_EfuseParsePackageType_8195A -1002d524 T Hal_EfuseParseChnlPlan_8195A -1002d554 T Hal_EfuseParseCustomerID_8195A -1002d56a T Hal_EfuseParseXtal_8195A -1002d582 T Hal_EfuseParseThermalMeter_8195A -1002d5aa T Hal_ReadRFGainOffset -1002d5fa T BWMapping_8195A -1002d61a T SCMapping_8195A -1002d642 T rtl8195a_update_txdesc -1002d912 T rtl8195a_fill_fake_txdesc -1002d9d0 T SetHwReg8195A -1002e690 T GetHwReg8195A -1002e724 T SetHalDefVar8195A -1002e804 T GetHalDefVar8195A -1002e828 T PHY_QueryBBReg_8195A_Safe -1002e854 T PHY_SetBBReg_8195A_Safe -1002e880 t phy_RFSerialRead_8195A -1002e934 T PHY_QueryRFReg_8195A -1002e94c T PHY_SetRFReg_8195A -1002e9a4 T PHY_MACConfig8195A -1002e9be T PHY_BBConfig8195A -1002eace T PHY_RFConfig8195A -1002ead2 T PHY_SetTxPowerIndex_8195A -1002ebdc T phy_TxPwrAdjInPercentage -1002ec1c T PHY_GetTxPowerIndex_8195A -1002ed0c T PHY_SetTxPowerLevel8195A -1002ed12 T phy_SpurCalibration_8195A -1002efca T phy_SetRegBW_8195A -1002f008 T phy_PostSetBwMode8195A -1002f164 T phy_SwChnl8195A -1002f20c T phy_SwChnlAndSetBwMode8195A -1002f25c T PHY_HandleSwChnlAndSetBW8195A -1002f30c T PHY_SetBWMode8195A -1002f32e T PHY_SwChnl8195A -1002f348 T PHY_SetSwChnlBWMode8195A -1002f366 t HalTimerEnable -1002f378 T InitTDMATimer -1002f3a0 T ChangeStateByTDMA -1002f3b0 T GetMinRateInRRSR -1002f3e4 T CheckInReqState -1002f3f4 T InitCheckStateTimer -1002f424 T InitGTimer1ms -1002f470 T DeInitGTimer1ms -1002f4b8 T ChangeTransmiteRate -1002f4f4 T PowerBitSetting -1002f570 T ChkandChangePS -1002f5d4 T IssueRsvdPagePacketSetting -1002f648 T IssuePSPoll -1002f674 T WaitTxStateMachineOk -1002f6c8 T IssueNullData -1002f758 T PsCloseRF -1002f78c T PsOpenRF -1002f7bc T ChkTxQueueIsEmpty -1002f7d4 T InitPS -1002f844 T ConfigListenBeaconPeriod -1002f868 T PS_S2_Condition_Match -1002f89c T PS_S4_Condition_Match -1002f918 T PS_32K_Condition_Match -1002f954 T PS_S2ToS3ToS0State -1002f9bc T PS_S2ToS0State -1002f9d8 T PS_S3ToS2orS0State -1002fa08 T PS_S0ToS1ToS2State -1002fa64 T PS_S1ToS0orS2State -1002fa94 T PS_S2ToS4State -1002fae0 T PS_S0ToS6State -1002fb00 T PS_S6ToS0State -1002fb18 T CheckTSFIsStable -1002fb68 T WaitHWStateReady -1002fb78 T SysClkDown -1002fbe8 T SysClkUp -1002fc34 T ResetPSParm -1002fca8 T PS_S4ToS2State -1002fccc T SleepTo32K -1002fd2c T Change_PS_State -1002fed8 T Legacy_PS_Setting -1002ff4c T PSModeSetting -1002fff0 T ChangePSStateByRPWM -10030034 T ChangeTDMAState -10030154 T TDMAChangeStateTask -1003017e T EnterPS -100301a0 T SetSmartPSTimer -100301dc T GTimer7Handle -10030238 T SmartPS2InitTimerAndToGetRxPkt -10030274 T PS_OnBeacon -10030324 T PSBcnEarlyProcess -100303e0 T PSMtiBcnEarlyProcess -1003048c T PSRxBcnProcess -100305dc T TxPktInPSOn -1003061a T PsBcnToProcess -100306d4 T GTimer6Handle -10030720 T RPWMProcess -1003075c T PSSetMode -100307d4 T SpeRPT -100308f4 T ISR_BcnEarly -10030960 T ISR_MtiBcnEarly -10030994 T ISR_RxBcn -100309b0 T ISR_RxBCMD1 -100309e0 T ISR_RxBCMD0 -10030a34 T ISR_RxUCMD1 -10030a72 T ISR_RxUCMD0 -10030aae T ISR_TxPktIn -10030ac0 T ISR_TXCCX -10030ac4 T H2CHDL_SetPwrMode -10030bec T CheckInReqStateTask -10030c32 T HalGetNullTxRpt -10030c50 T ISR_TBTT -10030cc8 T H2CHDL_BcnIgnoreEDCCA -10030cd8 T PMUInitial -10030d28 T PMUTask -10030e34 T PHY_RF6052SetBandwidth8195A -10030e78 T PHY_RF6052_Config8195A -10030f30 t process_rssi -10030f66 T rtl8195a_query_rx_desc_status -10031016 T rtl8195a_query_rx_phy_status -1003116e T hal_com_get_channel_plan -100311a2 T HAL_IsLegalChannel -100311c0 T MRateToHwRate -100311d4 T HwRateToMRate -100311e8 T HalSetBrateCfg -10031294 T Hal_MappingOutPipe -100312b0 T hal_init_macaddr -100312dc T hw_var_port_switch -10031564 T SetHwReg -1003156e T GetHwReg -10031570 T switch_power_saving_mode -100315b4 T rtw_bb_rf_gain_offset -100315fc T PHY_GetRateValuesOfTxPowerByRate -10031794 T PHY_StoreTxPowerByRateNew -10031830 T PHY_InitTxPowerByRate -10031848 T PHY_StoreTxPowerByRate -10031860 T PHY_GetTxPowerIndexBase -10031900 T PHY_GetTxPowerTrackingOffset -1003192c T PHY_GetRateIndexOfTxPowerByRate -10031940 T PHY_GetTxPowerByRate -100319a0 T phy_StoreTxPowerByRateBase -100319ec T PHY_SetTxPowerByRate -10031a28 T phy_ConvertTxPowerByRateInDbmToRelativeValues -10031b28 T PHY_TxPowerByRateConfiguration -10031b3a T PHY_SetTxPowerIndexByRateArray -10031b78 T PHY_SetTxPowerIndexByRateSection -10031bdc T PHY_SetTxPowerLevelByPath -10031c12 T phy_GetWorldWideLimit -10031c3e T PHY_GetTxPowerLimit -10031d68 T PHY_ConvertTxPowerLimitToPowerIndex -10031eb8 T PHY_InitTxPowerLimit -10031f00 T PHY_SetTxPowerLimit -10031f7c T PHY_GetTxPowerIndex -10031f8c T rtw_hal_chip_configure -10031fa2 T rtw_hal_read_chip_info -10031fb8 T rtw_hal_read_chip_version -10031fce T rtw_hal_def_value_init -10031fe4 T rtw_hal_free_data -10031ffa T rtw_hal_dm_init -10032010 T rtw_hal_dm_deinit -10032026 T rtw_hal_init -10032050 T rtw_hal_deinit -1003206a T rtw_hal_set_hwreg -10032078 T rtw_hal_get_hwreg -10032086 T rtw_hal_set_def_var -10032098 T rtw_hal_get_def_var -100320aa T rtw_hal_set_odm_var -100320b8 T rtw_hal_get_odm_var -100320c6 T rtw_hal_enable_interrupt -100320e8 T rtw_hal_disable_interrupt -1003210a T rtw_hal_inirp_init -1003211c T rtw_hal_inirp_deinit -1003212e T rtw_hal_irp_reset -1003213c T rtw_hal_xmit -1003214e T rtw_hal_mgnt_xmit -10032160 T rtw_hal_init_xmit_priv -10032172 T rtw_hal_free_xmit_priv -10032180 T rtw_hal_update_ra_mask -100321ae T rtw_hal_add_ra_tid -100321bc T rtw_hal_clone_data -100321ca T rtw_hal_start_thread -100321d8 T rtw_hal_stop_thread -100321e6 T rtw_hal_read_bbreg -1003221a T rtw_hal_write_bbreg -10032246 T rtw_hal_read_rfreg -10032258 T rtw_hal_write_rfreg -1003226c T rtw_hal_interrupt_handler -1003227e T rtw_hal_set_bwmode -1003228c T rtw_hal_set_chan -1003229a T rtw_hal_set_chnl_bw -100322b0 T rtw_hal_dm_watchdog -100322c6 T rtw_hal_macid_sleep -100322e6 T rtw_hal_macid_wakeup -10032306 T decide_chip_type_by_device_id -1003230c t rtw_net_get_stats -1003235c t netdev_if2_close -1003237c t netdev_close -100323d8 t rtw_if1_deinit -10032472 T rtw_os_indicate_connect -10032476 T rtw_os_indicate_scan_done -1003247a T rtw_reset_securitypriv -1003256e T rtw_os_indicate_disconnect -100325b8 T rtw_init_netdev -10032708 T rtw_drv_if2_init -10032910 T rtw_drv_if2_stop -10032966 T rtw_drv_if2_free -100329b4 T _netdev_open -10032ad0 T _netdev_if2_open -10032b8c T netdev_if2_open -10032bb4 T netdev_open -10032bdc T rtw_drv_probe -10032d5c T rtw_dev_remove -10032da0 T rtw_drv_entry -10032dcc T rtw_drv_halt -10032dfc t rtw_wx_set_autoreconnect -10032e2a t rtw_wx_get_autoreconnect -10032e38 t rtw_forwarding_set -10032e5a t rtw_set_ch_deauth -10032e7c t get_priv_size -10032e90 t rtw_wx_del_custome_ie -10032edc t rtw_wx_set_pscan_freq -10032f5e t rtw_wx_update_custome_ie -10032fd0 t rtw_set_tos_value -10032ff0 t rtw_get_tx_power -10033134 t rtw_wx_set_custome_ie -100331e0 t rtw_pm_get -10033224 t rtw_pm_set -100332d8 t rtw_wx_read32 -10033384 t rtw_wx_write32 -100333e8 t rtw_wx_set_freq.isra.10 -10033490 T rtw_ex_set -10033550 T wireless_send_event -1003355a T indicate_wx_custom_event -100335b6 T indicate_wx_scan_result_present -100335de T indicate_wx_scan_complete_event -10033608 T rtw_indicate_sta_assoc -10033658 T rtw_indicate_sta_disassoc -100336b0 T rtw_indicate_wx_assoc_event -100336e2 T rtw_indicate_wx_disassoc_event -10033712 T rtw_set_wpa_ie -10033828 T strtopsk -10033894 T rtw_wx_get_passphrase -100338e0 T rtw_wx_set_ap_essid -100339d0 T mac_reg_dump -10033a7c T bb_reg_dump -10033ad8 T rf_reg_dump -10033b50 t rtw_dbg_port -100341b8 T rtw_set_sta_num -100341d4 T rtw_ex_get_drv_ability -10034294 T rtw_ex_get -1003452c T rtw_ioctl -100354b8 T rtw_os_recv_resource_init -100354bc T rtw_os_recv_resource_alloc -100354c6 T rtw_os_recv_resource_free -100354c8 T rtw_tkip_countermeasure -10035568 T rtw_handle_tkip_mic_err -10035610 T rtw_recv_indicatepkt -10035860 T skb_fail_inc -1003587c T skb_fail_get_and_rst -10035898 T init_skb_pool -100358f0 T init_skb_data_pool -10035948 T alloc_skb -10035a48 T kfree_skb -10035ab0 T kfree_skb_chk_key -10035ab4 T skb_put -10035ae8 T skb_reserve -10035af6 T dev_alloc_skb -10035b12 T skb_end_pointer -10035b16 T skb_set_tail_pointer -10035b1e T skb_pull -10035b36 T skb_copy -10035b5e T rtw_remainder_len -10035b6a T _rtw_open_pktfile -10035b7c T _rtw_pktfile_read -10035baa T rtw_set_tx_chksum_offload -10035bac T rtw_os_xmit_resource_alloc -10035bb6 T rtw_os_xmit_resource_free -10035bb8 T rtw_os_pkt_complete -10035bc0 T rtw_os_xmit_complete -10035bd2 T rtw_os_xmit_schedule -10035c0e T rtw_xmit_entry -10035c5a T rtw_alloc_etherdev_with_old_priv -10035c70 T rtw_alloc_etherdev -10035c9c T rtw_free_netdev -10035cbc T timer_wrapper -10035d10 T alloc_etherdev -10035d6c T free_netdev -10035d86 T dev_alloc_name -10035d90 T init_timer_wrapper -10035db0 T deinit_timer_wrapper -10035dfc T init_timer -10035eb4 T mod_timer -10035f94 T cancel_timer_ex -10035fdc T del_timer_sync -10036040 T rtw_init_timer -10036048 T rtw_set_timer -1003604c T rtw_cancel_timer -10036056 T rtw_del_timer -1003605c T rltk_get_idx_bydev -1003606c T rltk_wlan_init -100360f4 T rltk_wlan_deinit -100361b8 T rltk_wlan_start -100361ec T rltk_wlan_check_isup -100361fc T rltk_wlan_tx_inc -10036210 T rltk_wlan_tx_dec -10036224 T rltk_wlan_get_recv_skb -10036234 T rltk_wlan_alloc_skb -10036274 T rltk_wlan_send_skb -100362a8 T rltk_netif_rx -10036354 T rltk_set_sta_num -10036358 T rltk_set_tx_power_percentage -1003638c T rltk_wlan_control -10036420 T rltk_wlan_running -10036438 T rltk_wlan_handshake_done -1003646c T rltk_wlan_is_connected_to_ap -100364b0 T Efuse_PowerSwitch -100364bc T Efuse_GetCurrentSize -100364c8 T Efuse_CalculateWordCnts -100364ec T EFUSE_GetEfuseDefinition -10036500 T efuse_OneByteRead -10036534 T efuse_OneByteWrite -10036568 T Efuse_PgPacketWrite -1003657c T efuse_WordEnableDataRead -100365ae T Efuse_WordEnableDataWrite -100365c2 T efuse_GetCurrentSize -100365ea T rtw_efuse_map_read -1003664c T rtw_efuse_map_write -100367cc T rtw_macaddr_cfg -10036890 T rtw_get_cipher_info -1003690a T rtw_get_bcn_info -100369da T rtw_init_default_value -10036a48 T rtw_cancel_all_timer -10036ab2 T rtw_free_drv_sw -10036b28 T rtw_reset_drv_sw -10036b84 T rtw_init_drv_sw -10036c0c T rtw_start_drv_threads -10036cc8 T rtw_stop_drv_threads -10036cfc T rtw_read8 -10036d0a T rtw_read16 -10036d18 T rtw_read32 -10036d26 T rtw_write8 -10036d34 T rtw_write16 -10036d42 T rtw_write32 -10036d50 T rtw_do_join -10036df4 T rtw_set_802_11_bssid -10036f78 T rtw_set_802_11_ssid -10037080 T rtw_set_802_11_infrastructure_mode -10037122 T rtw_set_802_11_bssid_list_scan -10037172 T rtw_set_802_11_authentication_mode -10037194 T rtw_set_802_11_add_wep -100371f4 T ODM_InitRAInfo -10037294 T InitialRateUpdate -10037394 T RateUp_search_RateMask -100373c6 T RateDown_search_RateMask -10037418 T StartRateByRSSI -10037442 T RateUpRAM8195A -100374d6 T RateDownTrying -10037514 T TryDone -100375ac T RateDownStepRAM8195A -1003764c T RateDecisionRAM8195A -10037730 T ArfrRefresh -10037938 T H2CHDL_Set_MACID_Config -100379fc T PHY_DM_RA_SetRSSI_8195A -10037a2a t CheckPositive.isra.0 -10037b0c T ODM_ReadAndConfig_MP_8195A_AGC_TAB -10037b84 T ODM_ReadAndConfig_MP_8195A_PHY_REG -10037bfc T ODM_GetVersion_MP_8195A_PHY_REG -10037c00 T ODM_ReadAndConfig_MP_8195A_PHY_REG_PG -10037c34 T odm_ConfigRFReg_8195A -10037c6c T odm_ConfigRF_RadioA_8195A -10037c7c T odm_ConfigMAC_8195A -10037c80 T odm_ConfigBB_AGC_8195A -10037c90 T odm_ConfigBB_PHY_REG_PG_8195A -10037cbe T odm_ConfigBB_PHY_8195A -10037d06 T odm_ConfigBB_TXPWR_LMT_8195A -10037d2c T ODM_CmnInfoInit -10037e20 T ODM_CmnInfoHook -10037ec4 T ODM_CmnInfoPtrArrayHook -10037ed4 T ODM_CmnInfoUpdate -10037fa4 T odm_CommonInfoSelfInit -10038018 T ODM_DMInit -10038066 T odm_CommonInfoSelfUpdate -100380b8 T ODM_DMWatchdog -10038124 T PhyDM_Get_Structure -10038148 T Phydm_CheckAdaptivity -10038176 T Phydm_NHMCounterStatisticsInit -100381ec T Phydm_SetEDCCAThreshold -10038224 T Phydm_MACEDCCAState -10038262 T Phydm_AdaptivityInit -10038340 T Phydm_Adaptivity -10038460 T ODM_CfoTrackingInit -1003848a T ODM_CfoTracking -100384aa T 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+1004dc28 d rtw_private_handler +1004dc6c V max_local_skb_num +1004dc70 V max_skb_buf_num +1004dc74 D rom_e_rtw_msgp_str_ +1004de50 D ARFB_table +1004de8f D TRYING_NECESSARY_idx +1004dea3 D DROPING_NECESSARY +1004deb7 D PER_RATE_UP +1004decb D PER_RATE_DOWN +1004dee0 V Array_MP_8195A_PHY_REG_PG +1004df70 D Array_MP_8195A_AGC_TAB +1004e180 D Array_MP_8195A_PHY_REG +1004e7f8 D rtl8195A_card_disable_flow +1004e898 D rtl8195A_card_enable_flow +1004e938 D Array_MP_8195A_MAC_REG +1004ec40 D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_TFBGA96_8195A +1004ec60 D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_TFBGA96_8195A +1004ec80 D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_QFN48_8195A +1004ec9e D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_QFN56_8195A +1004ecbc D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_QFN48_8195A +1004ecda D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN56_8195A +1004ecf8 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_TFBGA96_8195A +1004ed18 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_QFN56_8195A +1004ed36 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_QFN48_8195A +1004ed54 D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_QFN56_8195A +1004ed74 D Array_MP_8195A_RadioA +1004f33c D gDeltaSwingTableXtal_MP_P_TxXtalTrack_8195A +1004f35a D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_TFBGA96_8195A +1004f37a D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN48_8195A +1004f398 D .ram.bss$$Base +1004f398 D __bss_start__ +1004f398 D __data_end__ +1004f398 D __ram_image2_text_end__ +1004f398 d skbdata_list +1004f3a0 V skb_data_pool +100527a0 d ucIdleTaskHeap +100528b8 D HalI2SOpSAL +100528f4 D SYSAdapte +100528f8 D PwrAdapter +10052b84 D libc_has_init +10052b88 d rheap_end +10052b8c d event_init.21292 +10052b90 D wlan_st_netifn +10052b94 D wifi_run_mode +10052b98 d sampCntAdd +10052b9c d sampCnt +10052ba0 D mp3_serv +10052c22 D tskreader_enable +10052c24 D readBuf +10052c28 D tskmad_enable +10052c2c d bufUnderrunCt +10052c30 d oldRate +10052c34 d sampDelCnt +10052c35 D scan_end +10052c38 D pbuf_fifo +10052c3c D pi2s +10052c44 D I2sTxSema +10052c48 D eap_method +10052c49 D eap_phase +10052c4c d param.21256 +10052c64 D rtw_join_status +10052c68 D wifi_mode +10052c6c d scan_result_handler_ptr +10052c90 d join_user_data +10052c94 d event_callback_list +10052e14 D paff_array +10052e8c D lwip_init_done +10052e90 D xnetif +10052f10 d s_aliases.7444 +10052f14 d s_hostent.7443 +10052f28 d s_hostent_addr.7445 +10052f2c D h_errno +10052f30 d s_phostent_addr.7446 +10052f38 d select_cb_list +10052f3c d sockets +10052ffc d select_cb_ctr +10053000 d mbox +10053004 d tcpip_init_done_arg +10053008 d tcpip_init_done +1005300c d allsystems +10053010 d allrouters +10053014 d igmp_group_list +10053018 D current_header +1005301c d ip_id +10053020 D current_iphdr_src +10053024 D current_iphdr_dest +10053028 D current_netif +1005302c d str.6809 +1005303c d reassdatagrams +10053040 d ip_reass_pbufcount +10053042 D dhcp_rx_options_given +1005304c d xid.7759 +10053050 D dhcp_rx_options_val +10053078 d dns_seqno +1005307c d dns_table +100534dc d dns_servers +100534e4 d dns_payload_buffer +100536e8 d dns_pcb +100536ec d dns_payload +100536f0 d tcpip_tcp_timer_active +100536f4 d next_timeout +100536f8 D netif_list +100536fc D netif_default +10053700 d netif_num +10053701 D pbuf_free_ooseq_pending +10053704 d raw_pcbs +10053708 D tcp_active_pcbs_changed +1005370c D tcp_ticks +10053710 d tcp_timer +10053714 D tcp_listen_pcbs +10053718 D tcp_active_pcbs +1005371c d tcp_timer_ctr +10053720 D tcp_tw_pcbs +10053724 D tcp_tmp_pcb +10053728 D tcp_bound_pcbs +1005372c d seqno +10053730 d tcplen +10053734 d ackno +10053738 d flags +10053739 d recv_flags +1005373c d tcphdr +10053740 d recv_data +10053744 d inseg +10053758 D tcp_input_pcb +1005375c D udp_pcbs +10053760 d etharp_cached_entry +10053764 d arp_table +1005382c D lwip_tickless_used +10053830 d s_timeoutlist +10053860 d s_nextthread +10053864 d dhcps_ip_table_semaphore +10053868 d dhcps_send_broadcast_address +1005386c D dhcps_ip4addr_pool_end +1005386d d dhcp_client_ethernet_address +10053880 d dhcps_subnet_broadcast +10053884 d bound_client_ethernet_address +10053894 d ip_table +100538b4 d dhcps_pcb +100538b8 d dhcp_message_total_options_lenth +100538bc d dhcps_local_address +100538c0 d dhcps_netif +100538c4 d client_request_ip +100538c8 d dhcps_allocated_client_address +100538cc d dhcps_local_mask +100538d0 d dhcps_local_gateway +100538d4 d dhcps_network_id +100538d8 D dhcps_ip4addr_pool_start +100538dc d dhcp_message_repository +100538e0 D ext_upper +100538e4 d xFreeBytesRemaining +100538e8 d ext_free +100538ec D ext_lower +100538f0 d pxEnd +100538f4 d xStart +100538fc d xMinimumEverFreeBytesRemaining +10053900 d ulTimerCountsForOneTick +10053904 d ulStoppedTimerCompensation +10053908 d xMaximumPossibleSuppressedTicks +1005390c d xPendingReadyList +10053920 d uxTopReadyPriority +10053924 d uxTasksDeleted +10053928 d xTickCount +1005392c d pxReadyTasksLists +10053a08 d pxOverflowDelayedTaskList +10053a0c d xTasksWaitingTermination +10053a20 d pxDelayedTaskList +10053a24 d xSchedulerRunning +10053a28 d ulTaskSwitchedInTime +10053a2c D pxCurrentTCB +10053a30 d uxPendedTicks +10053a34 d xSuspendedTaskList +10053a48 d uxCurrentNumberOfTasks +10053a4c d ulDeltaTotalRunTime +10053a50 d xDelayedTaskList2 +10053a64 d xDelayedTaskList1 +10053a78 d uxTaskNumber +10053a7c d xYieldPending +10053a80 d uxSchedulerSuspended +10053a84 d xNumOfOverflows +10053a88 d pxCurrentTimerList +10053a8c d xActiveTimerList1 +10053aa0 d xActiveTimerList2 +10053ab4 d xLastTime.5284 +10053ab8 d xTimerQueue +10053abc d pxOverflowTimerList +10053ac0 d xTimerTaskHandle +10053ac4 d device_mutex +10053ad0 d mutex_init +10053ad4 d uxSavedInterruptStatus +10053ad8 D min_free_heap_size +10053adc d g_heap_inited +10053ae0 d tcm_lock +10053ae4 D g_tcm_heap +10053ae8 D flashobj +10053af4 D fspic_isinit +10053af8 D WDGAdapter +10053b34 d last_acquire_wakelock_time +10053bb4 D post_sleep_callback +10053c34 D pre_sleep_callback +10053cb4 D reserve_pll +10053cb8 d sys_sleep_time +10053cbc d hold_wakelock_time +10053d3c D missing_tick +10053d40 D Timer2To7HandlerData +10053d58 D auto_reconnect_running +10053d5c D p_wlan_autoreconnect_hdl +10053d60 D mac_monitor_callback +10053d64 D mf_list_head +10053d68 d pscan_retry_cnt.21430 +10053d6c D promisc_callback_all +10053d70 D promisc_sema +10053d74 D promisc_callback +10053d78 D psk_essid +10053dc0 D psk_passphrase +10053e42 D psk_passphrase64 +10053e83 D wpa_global_PSK +10053ed3 d RFC1042_OUI +10053ed8 d rx_ring_pool +10055fb8 d stop_report_count.20629 +10055fb9 D bCheckStateTIMER +10055fbc d WifiMcuCmdBitMap.20974 +10055fc0 D p_wlan_init_done_callback +10055fc4 D rtw_power_percentage_idx +10055fc8 D p_wlan_uart_adapter_callback +10055fcc D rtw_adaptivity_en +10055fd0 D p_wlan_mgmt_filter +10055fd4 D rtw_initmac +10055fd8 D rtw_adaptivity_th_l2h_ini +10055fdc d drvpriv +10055ff0 D skbbuf_used_num +10055ff4 V skb_pool +100561ac D skbdata_used_num +100561b0 d wrapper_skbbuf_list +100561b8 D max_skbdata_used_num +100561bc D max_skbbuf_used_num +100561c0 d skb_fail_count +100561c4 D timer_table +100561cc D rltk_wlan_info +100561fc d timer_used_num +10056200 D max_timer_used_num +10056204 D Noisy_State +10056208 D pExportWlanIrqSemaphore +1005620c D gDeltaSwingTableXtal_MP_N_TxXtalTrack_8195A +1005622a D .ram.bss$$Limit +1005622a D __bss_end__ +10056230 B __ram_heap2_start__ 10070000 A __ram_heap2_end__ 1fff0000 D __ram_tcm_start__ 1fff0000 D __tcm_heap_start__ diff --git a/flasher.mk b/flasher.mk index 31daea2..f0ac29f 100644 --- a/flasher.mk +++ b/flasher.mk @@ -88,11 +88,9 @@ mp: FLASH_IMAGE = $(BIN_DIR)/ram_all_mp.bin mp: OTA_IMAGE = $(BIN_DIR)/ota_mp.bin TST_IMAGE = $(BIN_DIR)/ram_2.bin -LD_ADDRESS = 0x1000B000 -ST_ADDRESS = 0x10006068 -.PHONY: genbin1 genbin23 flashburn reset test readfullflash -.NOTPARALLEL: all mp genbin1 genbin23 flashburn reset test readfullflash _endgenbin +.PHONY: genbin1 genbin23 flashburn reset test readfullflash flashwebfs flash_OTA +.NOTPARALLEL: all mp genbin1 genbin23 flashburn reset test readfullflash _endgenbin flashwebfs flash_OTA all: $(ELFFILE) $(OTA_IMAGE) $(FLASH_IMAGE) _endgenbin mp: $(ELFFILE) $(OTA_IMAGE) $(FLASH_IMAGE) _endgenbin @@ -101,35 +99,92 @@ genbin1: $(ELFFILE) $(RAM1P_IMAGE) genbin23: $(ELFFILE) $(OTA_IMAGE) $(FLASH_IMAGE) _endgenbin + _endgenbin: @echo "-----------------------------------------------------------" @echo "Image ($(OTA_IMAGE)) size $(shell printf '%d\n' $$(( $$(stat --printf="%s" $(OTA_IMAGE)) )) ) bytes" @echo "Image ($(FLASH_IMAGE)) size $(shell printf '%d\n' $$(( $$(stat --printf="%s" $(FLASH_IMAGE)) )) ) bytes" @echo "===========================================================" -flashburn: - @$(OPENOCD) -f interface/$(FLASHER).cfg -c "adapter_khz $(FLASHER_SPEED)" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "reset halt" -c "rtl8710_flash_auto_erase 1" -c "rtl8710_flash_auto_verify 1" -c "rtl8710_flash_write $(FLASH_IMAGE) 0" -c "rtl8710_reboot" -c "reset run" -c shutdown -# @$(JLINK_PATH)$(JLINK_GDB) - +ifeq ($(FLASHER_TYPE), Jlink) + reset: - @$(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed $(FLASHER_SPEED) flasher/RTLreset.JLinkScript -# @$(OPENOCD) -f interface/$(FLASHER).cfg -c "adapter_khz $(FLASHER_SPEED)" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "reset halt" -c "rtl8710_reboot" -c shutdown + @start $(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed 1000 $(FLASHER_PATH)RTL_Reset.JLinkScript runram: - @start $(JLINK_PATH)$(JLINK_GDB) -device Cortex-M3 -if SWD -ir -endian little -speed $(FLASHER_SPEED) - @$(GDB) -x flasher/gdb_run_ram.jlink - @taskkill.exe -F -IM $(JLINK_GDB) + @start $(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed 1000 $(FLASHER_PATH)RTL_RunRAM.JLinkScript -test: - @$(OPENOCD) -f interface/$(FLASHER).cfg -c "adapter_khz $(FLASHER_SPEED)" -f $(FLASHER_PATH)rtl8710.ocd -f $(FLASHER_PATH)cortex.ocd -c "init" -c "reset halt" -c "load_image $(TST_IMAGE) $(LD_ADDRESS) bin" -c "cortex_bootstrap $(ST_ADDRESS)" -c "shutdown" - readfullflash: - @rm -f $(BIN_DIR)/fullflash.bin - @start $(JLINK_PATH)$(JLINK_GDB) -device Cortex-M3 -if SWD -ir -endian little -speed $(FLASHER_SPEED) - @$(GDB) -x flasher/gdb_rdflash.jlink - @taskkill.exe -F -IM $(JLINK_GDB) -# @$(OPENOCD) -f interface/$(FLASHER).cfg -c "adapter_khz $(FLASHER_SPEED)" -f $(FLASHER_PATH)rtl8710.ocd -f $(FLASHER_PATH)cortex.ocd -c "init" -c "reset halt" -c "rtl8710_flash_read_id" -c "rtl8710_flash_read $(BIN_DIR)/fullflash.bin 0 1048576" -c "reset run" -c "shutdown" - if [ -s $(BIN_DIR)/fullflash.bin ]; then echo FullFlash = $(BIN_DIR)/fullflash.bin; fi + @start $(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed 1000 $(FLASHER_PATH)RTL_FFlash.JLinkScript + + +flashburn: + @echo define call1>$(FLASHER_PATH)flash_file.jlink + @echo SetFirwareSize build/bin/ram_all.bin>>$(FLASHER_PATH)flash_file.jlink + @echo end>>$(FLASHER_PATH)flash_file.jlink + @echo define call2>>$(FLASHER_PATH)flash_file.jlink + @echo FlasherWrite build/bin/ram_all.bin 0 '$$'Image1Size>>$(FLASHER_PATH)flash_file.jlink + @echo end>>$(FLASHER_PATH)flash_file.jlink + @echo define call3>>$(FLASHER_PATH)flash_file.jlink + @echo FlasherWrite build/bin/ram_all.bin '$$'Image2Addr '$$'Image2Size>>$(FLASHER_PATH)flash_file.jlink + @echo end>>$(FLASHER_PATH)flash_file.jlink + @start $(JLINK_PATH)$(JLINK_GDBSRV) -device Cortex-M3 -if SWD -ir -endian little -speed 1000 + @$(GDB) -x $(FLASHER_PATH)gdb_wrflash.jlink + @taskkill /F /IM $(JLINK_GDBSRV) + +flashwebfs: + @echo set '$$'ImageSize = $(shell printf '0x%X\n' $$(stat --printf="%s" $(BIN_DIR)/webpages.espfs))>$(FLASHER_PATH)file_info.jlink + @echo set '$$'ImageAddr = 0x0D0000>>$(FLASHER_PATH)file_info.jlink + @echo define call1>>$(FLASHER_PATH)file_info.jlink + @echo FlasherWrite $(BIN_DIR)/webpages.espfs '$$'ImageAddr '$$'ImageSize>>$(FLASHER_PATH)file_info.jlink + @echo end>>$(FLASHER_PATH)file_info.jlink + @start $(JLINK_PATH)$(JLINK_GDBSRV) -device Cortex-M3 -if SWD -ir -endian little -speed 1000 + @$(GDB) -x $(FLASHER_PATH)gdb_wrfile.jlink + @taskkill /F /IM $(JLINK_GDBSRV) + +flash_OTA: + @start $(JLINK_PATH)$(JLINK_GDBSRV) -device Cortex-M3 -if SWD -ir -endian little -speed 1000 + @$(GDB) -x $(FLASHER_PATH)gdb_ota.jlink + @taskkill /F /IM $(JLINK_GDBSRV) + +else + +flashburn: + @$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \ + -c "rtl8710_flash_auto_erase 1" -c "rtl8710_flash_auto_verify 1" \ + -c "rtl8710_flash_write $(RAM1P_IMAGE) 0" \ + -c "rtl8710_flash_write $(RAM2P_IMAGE) 0xb000" \ + -c "rtl8710_reboot" -c "reset run" -c shutdown + +flashimage2p: + @$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \ + -c "rtl8710_flash_auto_erase 1" -c "rtl8710_flash_auto_verify 1" \ + -c "rtl8710_flash_write $(RAM2P_IMAGE) 0xb000" \ + -c "rtl8710_reboot" -c "reset run" -c shutdown + +flashwebfs: + @$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \ + -c "rtl8710_flash_auto_erase 1" -c "rtl8710_flash_auto_verify 1" \ + -c "rtl8710_flash_write $(BIN_DIR)/webpages.espfs 0xd0000" \ + -c "rtl8710_reboot" -c "reset run" -c shutdown + + +reset: +# @$(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed $(FLASHER_SPEED) flasher/RTLreset.JLinkScript + @$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \ + -c "rtl8710_reboot" -c shutdown + +runram: +# @start $(JLINK_PATH)$(JLINK_GDB) -device Cortex-M3 -if SWD -ir -endian little -speed $(FLASHER_SPEED) +# @$(GDB) -x flasher/gdb_run_ram.jlink +# @taskkill.exe -F -IM $(JLINK_GDB) + @$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \ + -c "load_image $(RAM1R_IMAGE) 0x10000bc8 bin" \ + -c "load_image $(RAM2_IMAGE) 0x10006000 bin" \ + -c "mww 0x40000210 0x20200113" \ + -c "reset run" -c shutdown + +endif $(NMAPFILE): $(ELFFILE) @echo "===========================================================" diff --git a/flasher/gdb_wrfile.jlink b/flasher/gdb_wrfile.jlink new file mode 100644 index 0000000..361dc73 --- /dev/null +++ b/flasher/gdb_wrfile.jlink @@ -0,0 +1,156 @@ +############### +# FlasherInit # +############### +define FlasherInit +set $rtl8710_flasher_capacity = 0 +set $rtl8710_flasher_auto_erase = 1 +set $rtl8710_flasher_auto_verify = 1 +set $rtl8710_flasher_firmware_ptr = 0x10001000 +set $rtl8710_flasher_buffer = 0x10008000 +set $rtl8710_flasher_buffer_size = 421888 +set $rtl8710_flasher_sector_size = 4096 +set $rtl8710_flasher_auto_erase_sector = 0xFFFFFFFF +end +############### +# FlasherWait # +############### +define FlasherWait +set $fresult = {int}($rtl8710_flasher_buffer) +while ($fresult != 0) +set $fresult = {int}($rtl8710_flasher_buffer) +end +end +############### +# FlasherLoad # +############### +define FlasherLoad +if $rtl8710_flasher_capacity == 0 + printf "initializing RTL8710 flasher\n" + restore $arg0 binary $rtl8710_flasher_firmware_ptr 0 968 + monitor reset + set $pc = $rtl8710_flasher_firmware_ptr + set $sp = 0x1ffffffc + set {int}($rtl8710_flasher_buffer + 0x08) = 0 + set {int}($rtl8710_flasher_buffer + 0x00) = 1 + #continue + monitor go + FlasherWait + set $id = {int}($rtl8710_flasher_buffer + 0x0C) + if ($id == 0x1420c2) + set $rtl8710_flasher_capacity = 1 << (($id >> 16) & 0x0ff) + printf "Flash ID = 0x%08x : MX25L8006E (%d kbytes)\n", $id, $rtl8710_flasher_capacity>>10 + else + set $rtl8710_flasher_capacity = 1024*1024) + error "Flash ID = 0x%08x : ?\n", $id + end + printf "RTL8710 flasher initialized\n" +else +printf "reinitializing RTL8710 flasher\n" +end +end +################## +# FlasherWrBlock # +################## +define FlasherWrBlock +#printf "FlashWrBlock 0x%08x, 0x%08x\n", $arg0, $arg1 +set {int}($rtl8710_flasher_buffer + 0x04) = 4 +set {int}($rtl8710_flasher_buffer + 0x08) = 0 +set {int}($rtl8710_flasher_buffer + 0x10) = $arg0 +set {int}($rtl8710_flasher_buffer + 0x14) = $arg1 +set {int}($rtl8710_flasher_buffer + 0x00) = 1 +FlasherWait +set $status = {int}($rtl8710_flasher_buffer + 0x08) +if $status > 0 + error "write error, offset 0x%08x", $arg0 +end +end +################## +# FlasherVrBlock # +################## +define FlasherVrBlock +#printf "FlashVrBlock 0x%08x, 0x%08x\n", $arg0, $arg1 +set {int}($rtl8710_flasher_buffer + 0x04) = 5 +set {int}($rtl8710_flasher_buffer + 0x08) = 0 +set {int}($rtl8710_flasher_buffer + 0x10) = $arg0 +set {int}($rtl8710_flasher_buffer + 0x14) = $arg1 +set {int}($rtl8710_flasher_buffer + 0x00) = 1 +FlasherWait +set $status = {int}($rtl8710_flasher_buffer + 0x08) +if $status > 0 + set $status = {int}($rtl8710_flasher_buffer + 0x0C) + set $status = {int}($status + $arg0) + error "verify error, offset 0x%08x", $status +end +end +################# +# FlashSecErase # +################# +define FlashSecErase +#printf "FlashSecErase 0x%08x, 0x%08x\n", $rtl8710_flasher_buffer, $arg0 +set {int}($rtl8710_flasher_buffer + 0x04) = 2 +set {int}($rtl8710_flasher_buffer + 0x08) = 0 +set {int}($rtl8710_flasher_buffer + 0x10) = $arg0 +set {int}($rtl8710_flasher_buffer + 0x00) = 1 +FlasherWait +end +################ +# FlasherWrite # +################ +define FlasherWrite +set $sector = 0 +set $offset = 0 +set $size = $arg2 +while $offset < $size + set $len = $size - $offset + if $len > $rtl8710_flasher_buffer_size + set $len = $rtl8710_flasher_buffer_size + end + set $flash_offset = $arg1 + $offset + printf "write offset 0x%08x\n", $flash_offset + set $parms1 = $rtl8710_flasher_buffer + 0x20 - $offset + set $parms2 = $offset + set $parms3 = $offset + $len + restore $arg0 binary $parms1 $parms2 $parms3 + if $rtl8710_flasher_auto_erase != 0 + set $count_i = $flash_offset + while $count_i < ($flash_offset + $len) + set $sector = $count_i/$rtl8710_flasher_sector_size + if $rtl8710_flasher_auto_erase_sector != $sector + set $parms1 = $sector * $rtl8710_flasher_sector_size + printf "erase sector %d at 0x%08x\n", $sector, $parms1 + FlashSecErase $parms1 + set $rtl8710_flasher_auto_erase_sector = $sector + end + set $count_i = $count_i + 1 + end + end + FlasherWrBlock $flash_offset $len + printf "wrote %d bytes at 0x%08x\n", $len, $flash_offset + if $rtl8710_flasher_auto_verify != 0 + printf "verify offset 0x%08x len %d\n", $flash_offset, $len + FlasherVrBlock $flash_offset $len + end + set $offset = $offset + $rtl8710_flasher_buffer_size +end +end +######################################### +source -v flasher/gdb_flasher.jlink +source -v flasher/file_info.jlink +InitJlink +SystemInit +SetClk83MHz +SPI_Init +FlasherInit +FlasherLoad flasher/rtl8710_flasher.bin +if $ImageSize != 0 +set $ImageEnd = $ImageSize + $ImageAddr + 0x4000 +if $rtl8710_flasher_capacity >= $ImageEnd + printf "Write Image size %d to Flash addr 0x%08x:\n", $ImageSize, $ImageAddr + call1 +else + printf "Error: Image size is too big!\n" +end +else + printf "Error: Image size is zero!\n" +end +quit diff --git a/flasher/gdb_wrflash.jlink b/flasher/gdb_wrflash.jlink index c07f501..6d37642 100644 --- a/flasher/gdb_wrflash.jlink +++ b/flasher/gdb_wrflash.jlink @@ -106,9 +106,9 @@ while $offset < $size end set $flash_offset = $arg1 + $offset printf "write offset 0x%08x\n", $flash_offset - set $parms1 = $rtl8710_flasher_buffer + 0x20 - $offset - $arg1 - set $parms2 = $offset + $arg1 - set $parms3 = $offset + $len + $arg1 + set $parms1 = $rtl8710_flasher_buffer + 0x20 - $flash_offset + set $parms2 = $flash_offset + set $parms3 = $flash_offset + $len restore $arg0 binary $parms1 $parms2 $parms3 if $rtl8710_flasher_auto_erase != 0 set $count_i = $flash_offset diff --git a/jlinkarm.py b/jlinkarm.py new file mode 100644 index 0000000..b856da1 --- /dev/null +++ b/jlinkarm.py @@ -0,0 +1,113 @@ +import ctypes + +_jl = None + +def loadJLinkARMdll(lib_str): + global _jl + _jl = ctypes.cdll.LoadLibrary(lib_str) + if _jl: + return _jl + else: + raise RuntimeError('JLink ARM dynamic library is not loaded') + +def _jlink(): + if _jl: + return _jl + else: + raise RuntimeError('JLink ARM dynamic library is not loaded') + +def open(): + r = _jlink().JLINKARM_Open() + if r != 0: raise RuntimeError('Adapter is not found') + +def exec_command(cmd, a, b): + r = _jlink().JLINKARM_ExecCommand(cmd, a, b) + #if r != 0: raise RuntimeError('Unable to execute command') + +def tif_select(n): + if not isinstance(n, ctypes.c_ulong): + n = ctypes.c_ulong(n) + r = _jlink().JLINKARM_TIF_Select(n) + if r != 0: raise RuntimeError('Unable to select TIF') + +def set_speed(speed): + if not isinstance(speed, ctypes.c_ulong): + speed = ctypes.c_ulong(speed) + r = _jlink().JLINKARM_SetSpeed(speed) + #if r != 0: raise RuntimeError('Unable to set speed') + +def reset(): + r = _jlink().JLINKARM_Reset() + if r != 0: raise RuntimeError('fail') + +def is_connected(): + if _jlink().JLINKARM_IsConnected() != 0: return True + else: return False + +def go(): + r = _jlink().JLINKARM_Go() + #if r != 0: raise RuntimeError('fail') + +def write_u32(r, val): + if not isinstance(val, ctypes.c_ulong): + val = ctypes.c_ulong(val) + r = _jlink().JLINKARM_WriteU32(r, val) + if r != 0: raise RuntimeError('fail') + +def read_reg(r): + return _jlink().JLINKARM_ReadReg(r) + +def write_reg(r, val): + if not isinstance(val, ctypes.c_ulong): + val = ctypes.c_ulong(val) + ret = _jlink().JLINKARM_WriteReg(r, val) + #if ret != 0: raise RuntimeError('fail') + +def get_speed(): + return _jlink().JLINKARM_GetSpeed() + +def write_mem(startaddress, buf): + _jlink().JLINKARM_WriteMem.argtypes = [ctypes.c_int, ctypes.c_int, ctypes.c_char_p] + _jlink().JLINKARM_WriteMem.restype = ctypes.c_int + print "writemem addr %s size %s" % (hex(startaddress), hex(len(buf))) + r = _jlink().JLINKARM_WriteMem(startaddress, len(buf), buf) + #if r != 0: raise RuntimeError('fail') + +def read_mem_U32(startaddress, count): + buftype=ctypes.c_uint32 * int(count) + buf=buftype() + r=_jlink().JLINKARM_ReadMemU32(startaddress, count, buf, 0) + #if r != 0: raise RuntimeError('fail') + return buf + +def close(): + r = _jlink().JLINKARM_Close() + #if r != 0: raise RuntimeError('fail') + +def clear_TCK(): + r = _jlink().JLINKARM_ClrTCK() +def set_TCK(): + r = _jlink().JLINKARM_SetTCK() + +def clear_TMS(): + r = _jlink().JLINKARM_ClrTMS() +def set_TMS(): + r = _jlink().JLINKARM_SetTMS() + +def clear_TDI(): + r = _jlink().JLINKARM_ClrTDI() +def set_TDI(): + r = _jlink().JLINKARM_SetTDI() + +def clear_TRST(): + r = _jlink().JLINKARM_ClrTRST() +def set_TRST(): + r = _jlink().JLINKARM_SetTRST() + +def clear_RESET(): + r = _jlink().JLINKARM_ClrRESET() +def set_RESET(): + r = _jlink().JLINKARM_SetRESET() + +def halt(): + r = _jlink().JLINKARM_Halt() diff --git a/project/inc/rtl8195a/rtl_libc.h b/project/inc/rtl8195a/rtl_libc.h new file mode 100644 index 0000000..0af1874 --- /dev/null +++ b/project/inc/rtl8195a/rtl_libc.h @@ -0,0 +1,162 @@ +/* +* ROM calls +*/ + +#ifndef _INC_RTL_LIBC_ +#define _INC_RTL_LIBC_ + +//#undef malloc +#define malloc(size) pvPortMalloc(size) +//#undef free +#define free(pbuf) vPortFree(pbuf) + +#define calloc(nelements, elementSize) calloc_freertos(nelements, elementSize) + +#define snprintf rtl_snprintf +#define sprintf rtl_sprintf +#define printf rtl_printf +#define vprintf rtl_vprintf +#define vsnprintf rtl_vsnprintf +#define vfprintf rtl_vfprintf +#define memchr rtl_memchr +#define memcmp rtl_memcmp +#define memcpy rtl_memcpy +#define memmove rtl_memmove +#define memset rtl_memset +#define strcat rtl_strcat +#define strchr rtl_strchr +#define strcmp rtl_strcmp +#define strcpy rtl_strcpy +#define strlen rtl_strlen +#define strncat rtl_strncat +#define strncmp rtl_strncmp +#define strncpy rtl_strncpy +#define strstr rtl_strstr +#define strsep rtl_strsep +#define strtok rtl_strtok + +#define dtoi rtl_dtoi +#define dtoui rtl_dtoui +#define i2f rtl_i2f +#define i2d rtl_i2d +#define ui2f rtl_ui2f +#define ui2d rtl_ui2d +#define itoa rtl_itoa +#define ltoa rtl_ltoa +#define utoa rtl_utoa +#define ultoa rtl_ultoa +#define ftol rtl_ftol +#define ftod rtl_ftod +#define dtof rtl_dtof +#define fadd rtl_fadd +#define fsub rtl_fsub +#define fmul rtl_fmul +#define fdiv rtl_fdiv +#define dadd rtl_dadd +#define dsub rtl_dsub +#define dmul rtl_dmul +#define ddiv rtl_ddiv +#define dcmpeq rtl_dcmpeq +#define dcmplt rtl_dcmplt +#define dcmple rtl_dcmple +#define dcmpgt rtl_dcmpgt +#define fcmplt rtl_fcmplt +#define fcmpgt rtl_fcmpgt + +#define fabsf rtl_fabsf +#define fabs rtl_fabs +#define cos_f32 rtl_cos_f32 +#define sin_f32 rtl_sin_f32 + + +#if 0 +extern void *calloc_freertos(size_t nelements, size_t elementSize); +// ram_libc.c +extern int rtl_snprintf(char *str, size_t size, const char *fmt, ...); +extern int rtl_sprintf(char *str, const char *fmt, ...); +extern int rtl_printf(const char *fmt, ...); +extern int rtl_vprintf(const char *fmt, void *param); +extern int rtl_vsnprintf(char *str, size_t size, const char *fmt, void *param); +extern int rtl_vfprintf(FILE *fp, const char *fmt0, va_list ap); +extern int rtl_memchr(const void *src_void, int c, size_t length); +extern int rtl_memcmp(const void *m1, const void *m2, size_t n); +extern int rtl_memcpy(void *dst0, const void *src0, size_t len0); +extern int rtl_memmove(void *dst_void, const void *src_void, size_t length); +extern int rtl_memset(void *m, int c, size_t n); +extern char * rtl_strcat(char *s1, const char *s2); +extern char * rtl_strchr(const char *s1, int i); +extern int rtl_strcmp(const char *s1, const char *s2); +extern char * rtl_strcpy(char *dst0, const char *src0); +extern int rtl_strlen(const char *str); +extern char * rtl_strncat(char *s1, const char *s2, size_t n); +extern int rtl_strncmp(const char *s1, const char *s2, size_t n); +extern char * rtl_strncpy(char *dst0, const char *src0, size_t count); +extern char * rtl_strstr(const char *searchee, const char *lookfor); +extern char * rtl_strsep(char **source_ptr, const char *delim); +extern char * rtl_strtok(char *s, const char *delim); + +//rtl_eabi_cast_ram.c +extern int rtl_dtoi(double d); +extern int rtl_dtoui(double d); +extern float rtl_i2f(int val); +extern int rtl_i2d(int val); +extern float rtl_ui2f(unsigned int val); +extern int rtl_ui2d(unsigned int val); +extern char *rtl_itoa(int value, char *string, int radix); +extern char *rtl_ltoa(int value, char *string, int radix); +extern char *rtl_utoa(unsigned int value, char *string, int radix); +extern char *rtl_ultoa(unsigned int value, char *string, int radix); +extern int rtl_ftol(float f); +extern int rtl_ftod(float f); +extern float rtl_dtof(double d); +extern float rtl_fadd(float a, float b); +extern float rtl_fsub(float a, float b); +extern float rtl_fmul(float a, float b); +extern float rtl_fdiv(float a, float b); +extern int rtl_dadd(double a, double b); +extern int rtl_dsub(double a, double b); +extern int rtl_dmul(double a, double b); +extern int rtl_ddiv(double a, double b); +extern int rtl_dcmpeq(double a, double b); +extern int rtl_dcmplt(double a, double b); +extern int rtl_dcmple(double a, double b); +extern int rtl_dcmpgt(double a, double b); +extern int rtl_fcmplt(float a, float b); +extern int rtl_fcmpgt(float a, float b); + +// rtl_math_ram.c +extern float rtl_fabsf(float a); +extern int rtl_fabs(double a); +extern float rtl_cos_f32(float a); +extern float rtl_sin_f32(float a); + +// ram_pvvx_libc.c +extern int snprintf(char *str, size_t size, const char *fmt, ...); +extern int sprintf(char *str, const char *fmt, ...); +extern int printf(const char *fmt, ...); +extern int vprintf(const char *fmt, void *param); +extern int vsnprintf(char *str, size_t size, const char *fmt, void *param); +extern int vfprintf(FILE *fp, const char *fmt0, va_list ap); +extern int memchr(const void *src_void, int c, size_t length); +extern int memcmp(const void *m1, const void *m2, size_t n); +extern int memcpy(void *dst0, const void *src0, size_t len0); +extern int memmove(void *dst_void, const void *src_void, size_t length); +extern int memset(void *m, int c, size_t n); +extern char * strcat(char *s1, const char *s2); +extern char * strchr(const char *s1, int i); +extern int strcmp(const char *s1, const char *s2); +extern char * strcpy(char *dst0, const char *src0); +extern int strlen(const char *str); +extern char * strncat(char *s1, const char *s2, size_t n); +extern int strncmp(const char *s1, const char *s2, size_t n); +extern char * strncpy(char *dst0, const char *src0, size_t count); +extern char * strstr(const char *searchee, const char *lookfor); +extern char * strsep(char **source_ptr, const char *delim); +extern char * strtok(char *s, const char *delim); +extern int sscanf(const char *buf, const char *fmt, ...); +extern char toupper(char ch); +extern int _stricmp (const char *s1, const char *s2); +extern unsigned long long __aeabi_llsr(unsigned long long val, unsigned int shift); +#endif + +#endif // _INC_RTL_LIBC_ \ No newline at end of file diff --git a/project/src/user/main.c b/project/src/user/main.c index cee3de4..31195c3 100644 --- a/project/src/user/main.c +++ b/project/src/user/main.c @@ -508,6 +508,19 @@ void ShowMemInfo(void) HalGetCpuClk(), xPortGetFreeHeapSize(), tcm_heap_freeSpace()); } + +void user_init_thrd(void) { + + wifi_init(); + + /* Initilaize the console stack */ + console_init(); + + /* Kill init thread after all init tasks done */ + vTaskDelete(NULL); +} + + /** * @brief Main program. * @param None @@ -544,7 +557,7 @@ void main(void) mp3_cfg_read(); /* wlan & user_start intialization */ - xTaskCreate(wifi_init_thrd, "wc_start", 1024, NULL, tskIDLE_PRIORITY + 0 + PRIORITIE_OFFSET, NULL); + xTaskCreate(user_init_thrd, "user_init", 1024, NULL, tskIDLE_PRIORITY + 0 + PRIORITIE_OFFSET, NULL); /*Enable Schedule, Start Kernel*/ #if defined(CONFIG_KERNEL) && !TASK_SCHEDULER_DISABLED diff --git a/project/src/user/wifi_console.c b/project/src/user/wifi_console.c new file mode 100644 index 0000000..cc11f23 --- /dev/null +++ b/project/src/user/wifi_console.c @@ -0,0 +1,294 @@ +/* + * wifi_console.c + * + * Created on: 03/04/2017 + * Author: pvvx + */ + +#include +#include "FreeRTOS.h" +#include "diag.h" +#include "wifi_api.h" +#include "rtl8195a/rtl_libc.h" +#include "hal_platform.h" + +#include "section_config.h" +#include "hal_diag.h" +#include "lwip/netif.h" + + +extern struct netif xnetif[NET_IF_NUM]; + +//========================================================== +//--- CONSOLE -------------------------- + +// ATPN=[,password[,encryption[,auto reconnect[,reconnect pause]]]: WIFI Connect to AP +void fATPN(int argc, char *argv[]){ + if(argc > 1) { + if(argv[1][0] == '?') { + show_wifi_st_cfg(); + } + else { + strncpy(wifi_st_cfg.ssid, argv[1], NDIS_802_11_LENGTH_SSID); + if(argc > 2) { + strncpy(wifi_st_cfg.password, argv[2], NDIS_802_11_LENGTH_SSID); + int i = strlen(wifi_st_cfg.password); + if(i > 7) { + wifi_st_cfg.security_type = RTW_SECURITY_WPA2_AES_PSK; + } + else if(!i) { + wifi_st_cfg.security_type = RTW_SECURITY_OPEN; + } + else { + printf("password len < 8!\n"); + wifi_st_cfg.security_type = RTW_SECURITY_OPEN; + } + } + else { + wifi_st_cfg.password[0] = 0; + wifi_st_cfg.security_type = RTW_SECURITY_OPEN; + } + if(argc > 3) { + wifi_st_cfg.security_type = translate_rtw_security(atoi(argv[3])); + } + if(argc > 4) { + wifi_st_cfg.autoreconnect = atoi(argv[3]); + } + else wifi_st_cfg.autoreconnect = 0; + if(argc > 5) { + wifi_st_cfg.reconnect_pause = atoi(argv[3]); + } + else wifi_st_cfg.reconnect_pause = 5; + show_wifi_st_cfg(); + wifi_run(wifi_run_mode | RTW_MODE_STA); + } + } +} + +// ATPA=[,password[,encryption[,channel[,hidden[,max connections]]]]]: Start WIFI AP +void fATPA(int argc, char *argv[]){ + if(argc > 1) { + if(argv[1][0] == '?') { + show_wifi_ap_cfg(); + } + else { + strncpy(wifi_ap_cfg.ssid, argv[1], NDIS_802_11_LENGTH_SSID); + if(argc > 2) { + strncpy(wifi_ap_cfg.password, argv[2], NDIS_802_11_LENGTH_SSID); + int i = strlen(wifi_ap_cfg.password); + if(i > 7) { + wifi_ap_cfg.security_type = RTW_SECURITY_WPA2_AES_PSK; + } + else if(i == 0) { + wifi_ap_cfg.security_type = RTW_SECURITY_OPEN; + } + else { + printf("password len < 8!\n"); + wifi_ap_cfg.security_type = RTW_SECURITY_OPEN; + } + } + else { + wifi_ap_cfg.password[0] = 0; + wifi_ap_cfg.security_type = RTW_SECURITY_OPEN; + } + if(argc > 3) { + wifi_ap_cfg.security_type = translate_rtw_security(atoi(argv[3])); + } + if(argc > 4) { + wifi_ap_cfg.channel = atoi(argv[4]); + } + else wifi_ap_cfg.channel = 1; + if(argc > 5) { + wifi_ap_cfg.ssid_hidden = atoi(argv[5]); + } + else wifi_ap_cfg.ssid_hidden = 0; + + if(argc > 6) { + wifi_ap_cfg.max_sta = atoi(argv[6]); + } + else wifi_ap_cfg.max_sta = 3; + + show_wifi_ap_cfg(); + wifi_run(wifi_run_mode | RTW_MODE_AP); + } + } +} + +// WIFI Connect, Disconnect +void fATWR(int argc, char *argv[]){ + rtw_mode_t mode = RTW_MODE_NONE; + if(argc > 1) mode = atoi(argv[1]); + wifi_run(mode); +} + +// Close connections +void fATOF(int argc, char *argv[]){ + connect_close(); +} + +// Open connections +void fATON(int argc, char *argv[]){ + connect_start(); +} + +void fATWI(int argc, char *argv[]) { + rtw_wifi_setting_t Setting; + if((wifi_run_mode & RTW_MODE_AP) + && wifi_get_setting(wlan_ap_name, &Setting) == 0) { + wifi_show_setting(wlan_ap_name, &Setting); +// show_wifi_ap_ip(); + printf("\tIP: " IPSTR "\n", IP2STR(&xnetif[WLAN_AP_NETIF_NUM].ip_addr)); + } + if((wifi_run_mode & RTW_MODE_STA) + && wifi_get_setting(wlan_st_name, &Setting) == 0) { + wifi_show_setting(wlan_st_name, &Setting); +// show_wifi_st_ip(); + printf("\tIP: " IPSTR "\n", IP2STR(&xnetif[WLAN_ST_NETIF_NUM].ip_addr)); + } + printf("\nWIFI config:\n"); + printf(&str_rom_57ch3Dch0A[25]); // "================================\n" + show_wifi_cfg(); + printf("\nWIFI AP config:\n"); + printf(&str_rom_57ch3Dch0A[25]); // "================================\n" + show_wifi_ap_cfg(); + printf("\nWIFI ST config:\n"); + printf(&str_rom_57ch3Dch0A[25]); // "================================\n" + show_wifi_st_cfg(); + printf("\n"); + if(argc > 1 + && (argv[1][0] == 's' + || argv[1][0] == 'S')) { + int i = atoi(argv[2]); + printf("Save configs(%d)..\n", i); + write_wifi_cfg(atoi(argv[2])); + } +} + +extern uint8_t rtw_power_percentage_idx; + +void fATWT(int argc, char *argv[]) { + if(argc > 1) { + int txpwr = atoi(argv[1]); + debug_printf("set tx power (%d)...\n", txpwr); + if(rltk_set_tx_power_percentage(txpwr) != RTW_SUCCESS) { + error_printf("Error set tx power (%d)!", wifi_cfg.tx_pwr); + } + } + printf("TX power = %d\n", rtw_power_percentage_idx); +} + +//-- Test tsf (64-bits counts, 1 us step) --- + +#include "hal_com_reg.h" + +#define ReadTSF_Lo32() (*((volatile unsigned int *)(WIFI_REG_BASE + REG_TSFTR))) +#define ReadTSF_Hi32() (*((volatile unsigned int *)(WIFI_REG_BASE + REG_TSFTR1))) + +LOCAL uint64_t get_tsf(void) +{ + return *((uint64_t *)(WIFI_REG_BASE + REG_TSFTR)); +} + +void fATSF(int argc, char *argv[]) +{ + uint64_t tsf = get_tsf(); + printf("\nTSF: %08x%08x\n", (uint32_t)(tsf>>32), (uint32_t)(tsf)); +} + +/* -------- WiFi Scan ------------------------------- */ +unsigned char *tab_txt_rtw_secyrity[] = { + "OPEN ", + "WEP ", + "WPA TKIP", + "WPA AES", + "WPA2 AES", + "WPA2 TKIP", + "WPA2 Mixed", + "WPA/WPA2 AES", + "Unknown" +}; +unsigned int *tab_code_rtw_secyrity[] = { + RTW_SECURITY_OPEN, + RTW_SECURITY_WEP_PSK, + RTW_SECURITY_WPA_TKIP_PSK, + RTW_SECURITY_WPA_AES_PSK, + RTW_SECURITY_WPA2_AES_PSK, + RTW_SECURITY_WPA2_TKIP_PSK, + RTW_SECURITY_WPA2_MIXED_PSK, + RTW_SECURITY_WPA_WPA2_MIXED, + RTW_SECURITY_UNKNOWN +}; + +volatile uint8_t scan_end; + +/* -------- WiFi Scan ------------------------------- */ +static rtw_result_t _scan_result_handler( rtw_scan_handler_result_t* malloced_scan_result ) +{ + if (malloced_scan_result->scan_complete != RTW_TRUE) { + rtw_scan_result_t* record = &malloced_scan_result->ap_details; + record->SSID.val[record->SSID.len] = 0; /* Ensure the SSID is null terminated */ + if(scan_end == 1) { + printf("\nScan networks:\n\n"); + printf("N\tType\tMAC\t\t\tSignal\tCh\tWPS\tSecyrity\tSSID\n\n"); + }; + printf("%d\t", scan_end++); + printf("%s\t", (record->bss_type == RTW_BSS_TYPE_ADHOC)? "Adhoc": "Infra"); + printf(MAC_FMT, MAC_ARG(record->BSSID.octet)); + printf("\t%d\t", record->signal_strength); + printf("%d\t", record->channel); + printf("%d\t", record->wps_type); + int i = 0; + for(; record->security != tab_code_rtw_secyrity[i] && tab_code_rtw_secyrity[i] != RTW_SECURITY_UNKNOWN; i++); + printf("%s \t", tab_txt_rtw_secyrity[i]); + printf("%s\n", record->SSID.val); + } else { + scan_end = 0; + printf("\n"); + } + return RTW_SUCCESS; +} +/* -------- WiFi Scan ------------------------------- */ +#define scan_channels 14 +void fATSN(int argc, char *argv[]) +{ + int i; + u8 *channel_list = (u8*)pvPortMalloc(scan_channels*2); + if(channel_list) { + scan_end = 1; + u8 * pscan_config = &channel_list[scan_channels]; + //parse command channel list + for(i = 1; i <= scan_channels; i++){ + *(channel_list + i - 1) = i; + *(pscan_config + i - 1) = PSCAN_ENABLE; + }; + if(wifi_set_pscan_chan(channel_list, pscan_config, scan_channels) < 0){ + printf("ERROR: wifi set partial scan channel fail\n"); + } else if(wifi_scan_networks(_scan_result_handler, NULL ) != RTW_SUCCESS){ + printf("ERROR: wifi scan failed\n"); + } else { + i = 300; + while(i-- && scan_end) { + vTaskDelay(10); + }; + }; + vPortFree(channel_list); + } else { + printf("ERROR: Can't malloc memory for channel list\n"); + }; +} + +MON_RAM_TAB_SECTION COMMAND_TABLE console_cmd_wifi_api[] = { + {"ATPN", 1, fATPN, "=[,password[,encryption[,auto-reconnect[,reconnect pause]]]: WIFI Connect to AP"}, + {"ATPA", 1, fATPA, "=[,password[,encryption[,channel[,hidden[,max connections]]]]]: Start WIFI AP"}, + {"ATWR", 0, fATWR, ": WIFI Connect, Disconnect"}, + {"ATON", 0, fATON, ": Open connections"}, + {"ATOF", 0, fATOF, ": Close connections"}, + {"ATWI", 0, fATWI, "=[s]: WiFi Info, s - save"}, +#if CONFIG_DEBUG_LOG > 3 + {"ATWT", 1, fATWT, "=: WiFi tx power: 0 - 100%, 1 - 75%, 2 - 50%, 3 - 25%, 4 - 12.5%"}, + {"ATSF", 0, fATSF, ": Test TSF value"}, +#endif + {"ATSN", 0, fATSN, ": Scan networks"} +}; + + diff --git a/runram.py b/runram.py new file mode 100644 index 0000000..c4c3cb3 --- /dev/null +++ b/runram.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +# -*- coding: cp1251 -*- +import jlinkarm as jl +import os, sys, time, struct + +dllfilename = 'D:/MCU/SEGGER/JLink_V612i/JLinkARM.dll' + +if __name__ == '__main__': + if len(sys.argv) >= 2: + if sys.argv[1] == '-h': + print 'Usage: ldram.py ram_all.bin' + exit(0) + imgfilename = 'build/bin/ram_all.bin' + + if len(sys.argv) > 1: + if sys.argv[1]: + imgfilename = sys.argv[1] + try: + ff = open(imgfilename, "rb") + except: + print "Error file open " + imgfilename + exit(1) + jl.loadJLinkARMdll(dllfilename) + jl.open() + if jl.is_connected == 0: + raise RuntimeError('Jlink not connected') + jl.exec_command('device Cortex-M3', 0, 0) + jl.exec_command('endian little', 0, 0) + jl.tif_select(1) + jl.set_speed(1000) + jl.clear_RESET() + jl.clear_TRST() + time.sleep(0.01) + jl.set_RESET() + jl.set_TRST() + jl.reset() + jl.halt() + jl.set_speed(3500) + bin = ff.read() + get_dword = lambda address: struct.unpack('