From 82853f3eed2e7d72d9d770b3566a0abb71b7b5b9 Mon Sep 17 00:00:00 2001 From: pvvx Date: Sun, 25 Dec 2016 13:07:26 +0300 Subject: [PATCH] add flashloader --- .../iar_utility/common/dram/EM6A6165TS_7G.mac | 41 + .../misc/iar_utility/common/dram/common.mac | 4 + .../misc/iar_utility/common/dram/readme.txt | 4 + .../flashloader/EWARM_bcut/FlashLoader.ewd | 1352 +++++++++++++++++ .../flashloader/EWARM_bcut/FlashLoader.ewp | 982 ++++++++++++ .../flashloader/EWARM_bcut/FlashLoader.eww | 10 + .../flashloader/EWARM_bcut/flash_MX25L8008.c | 376 +++++ .../EWARM_bcut/framework2/flash_config.h | 22 + .../EWARM_bcut/framework2/flash_loader.c | 145 ++ .../EWARM_bcut/framework2/flash_loader.h | 78 + .../EWARM_bcut/framework2/flash_loader_asm.s | 197 +++ .../framework2/flash_loader_extra.h | 27 + .../EWARM_bcut/mx25l8008_flashloader_mp.icf | 59 + .../EWARM_bcut/platform_autoconf.h.1 | 210 +++ .../flashloader/EWARM_bcut/preload.mp.mac | 64 + .../EWARM_bcut/rtl8195a/hal_misc.c | 359 +++++ .../common/flashloader/FlashRTL8195aMP.board | 24 + .../common/flashloader/FlashRTL8195aMP.flash | 10 + .../common/flashloader/FlashRTL8195aMP.mac | 72 + .../common/flashloader/FlashRTL8195aMP.out | Bin 0 -> 99428 bytes .../flashloader/FlashRTL8195aMP_img1.board | 17 + .../flashloader/FlashRTL8195aMP_img1_v0.board | 17 + .../flashloader/FlashRTL8195aMP_img2.board | 26 + .../common/flashloader/FlashRTL8195aQA.board | 30 + .../common/flashloader/FlashRTL8195aQA.flash | 10 + .../common/flashloader/FlashRTL8195aQA.mac | 60 + .../common/flashloader/FlashRTL8195aQA.out | Bin 0 -> 151784 bytes 27 files changed, 4196 insertions(+) create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/dram/EM6A6165TS_7G.mac create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/dram/common.mac create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/dram/readme.txt create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/FlashLoader.ewd create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/FlashLoader.ewp create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/FlashLoader.eww create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/flash_MX25L8008.c create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_config.h create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader.c create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader.h create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader_asm.s create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader_extra.h create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/mx25l8008_flashloader_mp.icf create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/platform_autoconf.h.1 create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/preload.mp.mac create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/rtl8195a/hal_misc.c create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP.board create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP.flash create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP.mac create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP.out create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP_img1.board create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP_img1_v0.board create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP_img2.board create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aQA.board create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aQA.flash create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aQA.mac create mode 100644 RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aQA.out diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/dram/EM6A6165TS_7G.mac b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/dram/EM6A6165TS_7G.mac new file mode 100644 index 0000000..64aea1e --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/dram/EM6A6165TS_7G.mac @@ -0,0 +1,41 @@ +__load_dram_param(){ + //DRAM_INFO + DeviceType = 8; //DRAM_SDR + Page = 0; //DRAM_COLADDR_8B + Bank=0; //DRAM_BANK_2 + DqWidth=0; //DRAM_DQ_1 + + //DRAM_MODE_REG_INFO + BstLen=0; //BST_LEN_4 + BstType=0; //SENQUENTIAL + Mode0Cas=3; + Mode0Wr=0; + Mode1DllEnN=0; + Mode1AllLat=0; + Mode2Cwl=0; + + //DRAM_TIMING_INFO + DramTimingTref = 64000; + DramRowNum = 8192; + //SDR 100MHZ==>10000, 50MHZ==>20000, 25MHZ==>40000, 12.5MHZ==>80000 + Tck = 80000; //SDR 12.5MHZ + + TrfcPs=60000; + TrefiPs=((DramTimingTref*1000)/DramRowNum)*1000; + WrMaxTck=2; + TrcdPs=15000; + TrpPs=15000; + TrasPs=42000; + TrrdTck=2; + TwrPs=Tck*2; + TwtrTck=0; + TmrdTck=2; + TrtpTck=0; + TccdTck=1; + TrcPs=60000; + + //DRAM_DEVICE_INFO + DdrPeriodPs=Tck; + DfiRate=0; //DFI_RATIO_1 + +} \ No newline at end of file diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/dram/common.mac b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/dram/common.mac new file mode 100644 index 0000000..d79771c --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/dram/common.mac @@ -0,0 +1,4 @@ + +__load_dram_common(){ + __registerMacroFile("$PROJ_DIR$\\..\\..\\..\\component\\soc\\realtek\\8195a\\misc\\iar_utility\\common\\dram\\EM6A6165TS_7G.mac"); +} \ No newline at end of file diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/dram/readme.txt b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/dram/readme.txt new file mode 100644 index 0000000..2fa0238 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/dram/readme.txt @@ -0,0 +1,4 @@ +To Change DRAM setting + +1. Create and Fill content like EM6A6165TS_7G.mac +2. Change load file in common.mac \ No newline at end of file diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/FlashLoader.ewd b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/FlashLoader.ewd new file mode 100644 index 0000000..a159e05 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/FlashLoader.ewd @@ -0,0 +1,1352 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + IJET_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/FlashLoader.ewp b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/FlashLoader.ewp new file mode 100644 index 0000000..3051ef7 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/FlashLoader.ewp @@ -0,0 +1,982 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Framework + + $PROJ_DIR$\framework2\flash_loader.c + + + $PROJ_DIR$\framework2\flash_loader_asm.s + + + + rtl8195a + + $PROJ_DIR$\rtl8195a\hal_misc.c + + + $PROJ_DIR$\..\..\..\..\..\fwlib\ram_lib\hal_spi_flash_ram.c + + + + $PROJ_DIR$\flash_MX25L8008.c + + + + diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/FlashLoader.eww b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/FlashLoader.eww new file mode 100644 index 0000000..306dcc2 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/FlashLoader.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\FlashLoader.ewp + + + + + diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/flash_MX25L8008.c b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/flash_MX25L8008.c new file mode 100644 index 0000000..5c6e947 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/flash_MX25L8008.c @@ -0,0 +1,376 @@ +/******************************************************************************* +* +* Project: Realtek Ameba flash loader project +* +* Description: Memory-specific routines for Flash Loader. +* +* Copyright by Diolan Ltd. All rights reserved. +* +*******************************************************************************/ +#include +#include +#include "flash_loader.h" +#include "flash_loader_extra.h" + +#include "rtl8195a.h" +//#include "rtl8195a/hal_misc.h" +//#include "rtl8195a/hal_spi_flash.h" +//#include "rtl8195a/core_cm3.h" + +extern VOID +HalReInitPlatformLogUart( + VOID +); + +extern VOID +SpicLoadInitParaFromClockRtl8195A +( + IN u8 CpuClkMode, + IN u8 BaudRate, + IN PSPIC_INIT_PARA pSpicInitPara +); + +extern VOID +SpicWaitBusyDoneRtl8195A(); + +extern VOID +SpicWaitWipDoneRtl8195A +( + IN SPIC_INIT_PARA SpicInitPara +); + +extern VOID +SpicTxCmdRtl8195A +( + IN u8 cmd, + IN SPIC_INIT_PARA SpicInitPara +); + +extern u8 +SpicGetFlashStatusRtl8195A +( + IN SPIC_INIT_PARA SpicInitPara +); + +__no_init unsigned int flash_loc; +__no_init unsigned int erase_loc; +__no_init unsigned int is_cascade; +__no_init unsigned int is_head; +__no_init unsigned int is_dbgmsg; +__no_init unsigned int is_erasecal; +__no_init unsigned int img2_addr; + +int rest_count; +int first_write; +SPIC_INIT_PARA SpicInitPara; + +#define PATTERN_1 0x96969999 +#define PATTERN_2 0xFC66CC3F +#define PATTERN_3 0x03CC33C0 +#define PATTERN_4 0x6231DCE5 + + +#define DBGPRINT(fmt, arg...) do{ if( is_dbgmsg ) DiagPrintf(fmt, ##arg);}while(0) + +//unsigned int fw_head[4] = {PATTERN_1, PATTERN_2, PATTERN_3, PATTERN_4}; +unsigned int seg_head[4] = {0,0,0,0}; + +extern SPIC_INIT_PARA SpicInitCPUCLK[4]; + +void dump_flash_header(void) +{ + uint32_t data; + data = HAL_READ32(SPI_FLASH_BASE, 0); + DBGPRINT("\n\r 0: %x", data); + data = HAL_READ32(SPI_FLASH_BASE, 4); + DBGPRINT("\n\r 4: %x", data); + data = HAL_READ32(SPI_FLASH_BASE, 8); + DBGPRINT("\n\r 8: %x", data); + data = HAL_READ32(SPI_FLASH_BASE, 12); + DBGPRINT("\n\r 12: %x", data); +} + +const char* find_option(char* option, int withValue, int argc, char const* argv[]) +{ + int i; + for (i = 0; i < argc; i++) { + if (strcmp(option, argv[i]) == 0){ + if (withValue) { + if (i + 1 < argc) { + // The next argument is the value. + return argv[i + 1]; + } + else { + // The option was found but there is no value to return. + return 0; + } + } + else + { + // Return the flag argument itself just to get a non-zero pointer. + return argv[i]; + } + } + } + return 0; +} + +static VOID +FlashDownloadHalInitialROMCodeGlobalVar(VOID) +{ + // to initial ROM code using global variable + ConfigDebugErr = _DBG_MISC_; + ConfigDebugInfo= 0x0; + ConfigDebugWarn= 0x0; +} + +static VOID +FlashDownloadHalCleanROMCodeGlobalVar(VOID) +{ + ConfigDebugErr = 0x0; + ConfigDebugInfo= 0x0; + ConfigDebugWarn= 0x0; +} + +// Please clean this Array +extern SPIC_INIT_PARA SpicInitParaAllClk[3][CPU_CLK_TYPE_NO]; + +u8 FlashType; +uint32_t FlashInit(void *base_of_flash, uint32_t image_size, uint32_t link_address, uint32_t flags, int argc, char const *argv[]) +{ + u8 CpuClk; + u8 Value8, InitBaudRate; + + char *addr; + + SPIC_INIT_PARA InitCPUCLK[4] = { + {0x1,0x1,0x5E,0}, //default cpu 41, baud 1 + {0x1,0x1,0x0,0}, //cpu 20.8 , baud 1 + {0x1,0x2,0x23,0}, //cpu 83.3, baud 1 + {0x1,0x5,0x5,0}, + }; + memcpy(SpicInitCPUCLK, InitCPUCLK, sizeof(InitCPUCLK)); + memset(SpicInitParaAllClk, 0, sizeof(SPIC_INIT_PARA)*3*CPU_CLK_TYPE_NO); + + SpicInitPara.BaudRate = 0; + SpicInitPara.DelayLine = 0; + SpicInitPara.RdDummyCyle = 0; + SpicInitPara.Rsvd = 0; + + if(find_option( "--erase_cal", 0, argc, argv )) + is_erasecal = 1; + else + is_erasecal = 0; + + if(find_option( "--cascade", 0, argc, argv )) + is_cascade = 1; + else + is_cascade = 0; + + if(find_option( "--head", 0, argc, argv )) + is_head = 1; + else + is_head = 0; + + if(find_option( "--dbgmsg", 0, argc, argv )) + is_dbgmsg = 1; + else + is_dbgmsg = 0; + + if( (addr = (char*)find_option( "--img2_addr", 1, argc, argv))){ + img2_addr = strtod(addr, NULL)/1024; + DBG_8195A(" image2 start address = %s, offset = %x\n\r", addr, img2_addr); + }else + img2_addr = 0; + + memset((void *) 0x10000300, 0, 0xbc0-0x300); + + // Load Efuse Setting + Value8 = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_SYSCFG6) & 0xFF000000) + >> 24); + + InitBaudRate = ((Value8 & 0xC)>>2); + + // Make sure InitBaudRate != 0 + if (!InitBaudRate) { + InitBaudRate +=1; + } + + CpuClk = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70)) >> 4); + SpicLoadInitParaFromClockRtl8195A(CpuClk, InitBaudRate, &SpicInitPara); + + // Reset to low speed + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1, 0x21); + + FlashDownloadHalInitialROMCodeGlobalVar(); + + //2 Need Modify + VectorTableInitRtl8195A(0x1FFFFFFC); + + //3 Initial Log Uart + PatchHalInitPlatformLogUart(); + + //3 Initial hardware timer + PatchHalInitPlatformTimer(); + + DBG_8195A("\r\n===> Flash Init \n\r"); + //4 Initialize the flash first + if (HAL_READ32(REG_SOC_FUNC_EN,BIT_SOC_FLASH_EN) & BIT_SOC_FLASH_EN) { + FLASH_FCTRL(OFF); + } + + FLASH_FCTRL(ON); + ACTCK_FLASH_CCTRL(ON); + SLPCK_FLASH_CCTRL(ON); + PinCtrl(SPI_FLASH,S0,ON); + + PatchSpicInitRtl8195A(SpicInitPara.BaudRate, SpicOneBitMode); + + SpicFlashInitRtl8195A(SpicOneBitMode); + + FlashType = SpicInitParaAllClk[SpicOneBitMode][0].flashtype; + + char* vendor[] = {"Others", "MXIC", "Winbond", "Micron"}; + DBG_8195A("\r\n===> Flash Init Done, vendor: \x1b[32m%s\x1b[m \n\r", vendor[FlashType]); + + first_write = 1; + rest_count = theFlashParams.block_size; + seg_head[0] = theFlashParams.block_size; + seg_head[1] = theFlashParams.offset_into_block; + if(is_head){ + seg_head[2] = 0xFFFF0000|img2_addr; + seg_head[3] = 0xFFFFFFFF; + }else{ + if(is_cascade==0){ + // Image2 signature + seg_head[2] = 0x35393138; //8195 + seg_head[3] = 0x31313738; //8711 + }else{ + seg_head[2] = 0xFFFFFFFF; + seg_head[3] = 0xFFFFFFFF; + } + } + + //DBG_8195A("link_address = %08x, flags = %08x ...\n\r", link_address, flags); + + if(is_cascade==0 && is_head==0){ + // mark partition 2 to old if existing + unsigned int ota_addr = HAL_READ32(SPI_FLASH_BASE, 0x9000); + + //check OTA address valid + if( ota_addr == 0xFFFFFFFF || ota_addr > 64*1024*1024 ){ + DBG_8195A("\r\n\x1b[31mOTA addr %8x is invalid\x1b[m\n\r", ota_addr ); + DBG_8195A("\x1b[31mOTA addr %8x is invalid\x1b[m\n\r", ota_addr ); + DBG_8195A("\x1b[31mOTA addr %8x is invalid\x1b[m\n\r", ota_addr ); + DBG_8195A("continue downloading...\n\r" ); + return RESULT_OK; + }else{ + DBG_8195A("\x1b[36mOTA addr is %x \x1b[m\n\r", ota_addr ); + } + + int sig0 = HAL_READ32(SPI_FLASH_BASE, ota_addr+8); + int sig1 = HAL_READ32(SPI_FLASH_BASE, ota_addr+12); + + if(sig0==0x35393138 && sig1==0x31313738){ + DBG_8195A("\r\n>>>> mark parition 2 as older \n\r" ); + HAL_WRITE32(SPI_FLASH_BASE, ota_addr+8, 0x35393130); // mark to older version + // wait spic busy done + SpicWaitBusyDoneRtl8195A(); + // wait flash busy done (wip=0) + if(FlashType == FLASH_MICRON) + SpicWaitOperationDoneRtl8195A(SpicInitPara); + else + SpicWaitWipDoneRefinedRtl8195A(SpicInitPara); + } + } + dump_flash_header(); + //SpicEraseFlashRtl8195A(); + return RESULT_OK; +} + +void write_spi_flash(uint32_t data) +{ + HAL_WRITE32(SPI_FLASH_BASE, flash_loc, data); + // wait spic busy done + SpicWaitBusyDoneRtl8195A(); + + // wait flash busy done (wip=0) + if(FlashType == FLASH_MICRON) + SpicWaitOperationDoneRtl8195A(SpicInitPara); + else + SpicWaitWipDoneRefinedRtl8195A(SpicInitPara); + flash_loc+=4; +} + +uint32_t FlashWrite(void *block_start, uint32_t offset_into_block, uint32_t count, char const *buffer) +{ + int write_cnt=0; + uint32_t* buffer32 = (uint32_t*)buffer; + + DBG_8195A("\r\n===> Flash Write, start %x, addr %x, offset %d, count %d, buf %x\n\r", block_start, flash_loc, offset_into_block, count, buffer); + + if(first_write){ + if(!is_cascade){ + flash_loc = (unsigned int)block_start; + } + if(is_head){ + unsigned int fw_head[4] = {PATTERN_1, PATTERN_2, PATTERN_3, PATTERN_4}; + DBGPRINT("Write FW header...."); + flash_loc=0; + write_spi_flash(fw_head[0]); + write_spi_flash(fw_head[1]); + write_spi_flash(fw_head[2]); + write_spi_flash(fw_head[3]); + DBGPRINT("Write FW header.... %x %x %x %x --> Done\n\r", fw_head[0], fw_head[1], fw_head[2], fw_head[3]); + } + DBGPRINT("Write SEG header...."); + first_write = 0; + write_spi_flash(seg_head[0]); + write_spi_flash(seg_head[1]); + write_spi_flash(seg_head[2]); + write_spi_flash(seg_head[3]); + DBGPRINT("Write SEG header.... %x %x %x %x --> Done\n\r", seg_head[0], seg_head[1], seg_head[2], seg_head[3]); + } + + if(rest_count < count) + count = rest_count; + + // DO Write Here + DBG_8195A("Write Binary...."); + while (write_cnt < count) + { + write_spi_flash(*buffer32); + write_cnt += 4; + buffer32++; + } + DBG_8195A("Write Binary....Done\n\r"); + + rest_count-=count; + DBG_8195A("\r\n<=== Flash Write Done %x\n\r", flash_loc); + DBGPRINT("first 4 bytes %2x %2x %2x %2x\n\r", buffer[0],buffer[1],buffer[2],buffer[3]); + DBGPRINT("last 4 bytes %2x %2x %2x %2x\n\r", buffer[count-4],buffer[count-3],buffer[count-2],buffer[count-1]); + return RESULT_OK; +} + +uint32_t FlashErase(void *block_start, uint32_t block_size) +{ + if(is_head == 1) + erase_loc = 0; + + if(!is_cascade) + erase_loc = (unsigned int)block_start; + + if(erase_loc != 0xa000){ + SpicSectorEraseFlashRtl8195A(erase_loc); + DBGPRINT("@erase %x, size %d, fw offset %x\n\r", erase_loc, block_size, block_start); + }else{ + if(is_erasecal){ + SpicSectorEraseFlashRtl8195A(erase_loc); + DBGPRINT("@erase %x, size %d, fw offset %x\n\r", erase_loc, block_size, block_start); + } + } + erase_loc += 4096; + + return 0; +} + diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_config.h b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_config.h new file mode 100644 index 0000000..d5c4c34 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_config.h @@ -0,0 +1,22 @@ +// You should create a copy of this file in your flash loader project +// and configure it as described below + +// when this macro is non-zero, your FlashInit function should accept +// extra 'argc' and 'argv' arguments as specified by the function +// prototype in 'flash_loader.h' +#define USE_ARGC_ARGV 1 + +// You can customize the memory reserved for passing arguments to FlashInit +// through argc and argv. +#if USE_ARGC_ARGV +// This specifies the maximum allowed number of arguments in argv +#define MAX_ARGS 5 +// This specifies the maximum combined size of the arguments, including +// a trailing null for each argument +#define MAX_ARG_SIZE 64 +#endif + +// If this is true (non-zero), the parameter designating the code destination +// in flash operations will be a 'void *', otherwise it will be a uint32_t. +// Targets where void * is smaller than a code pointer should set this to 0. +#define CODE_ADDR_AS_VOID_PTR 1 diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader.c b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader.c new file mode 100644 index 0000000..fcc21fe --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader.c @@ -0,0 +1,145 @@ +// Wrapper for target-specific flash loader code + +#include "flash_loader.h" +#include "flash_loader_extra.h" + +#ifndef MAX_ARGS +#define MAX_ARGS 7 +#endif + +// Maximum combined size of arguments, including a trailing null for each argument. +#ifndef MAX_ARG_SIZE +#define MAX_ARG_SIZE 64 +#endif + +// Functions in this file, called from the assembly wrapper +void Fl2FlashInitEntry(void); +void Fl2FlashWriteEntry(void); +void Fl2FlashEraseWriteEntry(void); +void Fl2FlashChecksumEntry(void); +void Fl2FlashSignoffEntry(void); +void FlashBreak(void); + +#if CODE_ADDR_AS_VOID_PTR +extern uint32_t FlashChecksum(void const *begin, uint32_t count); +#else +extern uint32_t FlashChecksum(uint32_t begin, uint32_t count); +#endif +extern uint32_t FlashSignoff(); + +uint16_t Crc16_helper(uint8_t const *p, uint32_t len, uint16_t sum); + +__root __no_init FlashParamsHolder theFlashParams; + +__no_init int __argc; +__no_init char __argvbuf[MAX_ARG_SIZE]; +#pragma required=__argvbuf +__no_init const char* __argv[MAX_ARGS]; + +#if CODE_ADDR_AS_VOID_PTR +#define CODE_REF void * +#else +#define CODE_REF uint32_t +#endif + +void Fl2FlashInitEntry() +{ +#if USE_ARGC_ARGV + theFlashParams.count = FlashInit((CODE_REF)theFlashParams.base_ptr, + theFlashParams.block_size, // Image size + theFlashParams.offset_into_block,// link adr + theFlashParams.count, // flags + __argc, + __argv); +#else + theFlashParams.count = FlashInit((CODE_REF)theFlashParams.base_ptr, + theFlashParams.block_size, // Image size + theFlashParams.offset_into_block,// link adr + theFlashParams.count); // flags +#endif +} + +// The normal flash write function ---------------------------------------------- +void Fl2FlashWriteEntry() +{ + theFlashParams.count = FlashWrite((CODE_REF)theFlashParams.base_ptr, + theFlashParams.offset_into_block, + theFlashParams.count, + theFlashParams.buffer); +} + +// The erase-first flash write function ----------------------------------------- +void Fl2FlashEraseWriteEntry() +{ + uint32_t tmp = theFlashParams.block_size; + if (tmp == 0) + { + FlashEraseData *p = (FlashEraseData*)theFlashParams.buffer; + for (uint32_t i = 0; i < theFlashParams.count; ++i) + { + tmp = FlashErase((CODE_REF)p->start, p->length); + if (tmp != 0) break; + ++p; + } + } + else + { + tmp = FlashErase((CODE_REF)theFlashParams.base_ptr, + theFlashParams.block_size); + if (tmp == 0) + { + tmp = FlashWrite((CODE_REF)theFlashParams.base_ptr, + theFlashParams.offset_into_block, + theFlashParams.count, + theFlashParams.buffer); + } + } + theFlashParams.count = tmp; +} + + +void Fl2FlashChecksumEntry() +{ + theFlashParams.count = FlashChecksum((CODE_REF)theFlashParams.base_ptr, + theFlashParams.count); +} + +void Fl2FlashSignoffEntry() +{ + theFlashParams.count = FlashSignoff(); +} + + +uint16_t Crc16(uint8_t const *p, uint32_t len) +{ + uint8_t zero[2] = { 0, 0 }; + uint16_t sum = Crc16_helper(p, len, 0); + return Crc16_helper(zero, 2, sum); +} + +uint16_t Crc16_helper(uint8_t const *p, uint32_t len, uint16_t sum) +{ + while (len--) + { + int i; + uint8_t byte = *p++; + + for (i = 0; i < 8; ++i) + { + uint32_t osum = sum; + sum <<= 1; + if (byte & 0x80) + sum |= 1 ; + if (osum & 0x8000) + sum ^= 0x1021; + byte <<= 1; + } + } + return sum; +} + +#pragma optimize=no_inline +__root void FlashBreak() +{ + while(1); +} diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader.h b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader.h new file mode 100644 index 0000000..c385c4c --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader.h @@ -0,0 +1,78 @@ + +#include "flash_config.h" +#include + +#define RESULT_OK 0 +#define RESULT_ERROR 1 +#define RESULT_OVERRIDE_DEVICE 2 +#define RESULT_ERASE_DONE 3 +#define RESULT_CUSTOM_FIRST 100 +#define RESULT_CUSTOM_LAST 200 + +#define FLAG_ERASE_ONLY 0x1 + +#ifndef CODE_ADDR_AS_VOID_PTR +#define CODE_ADDR_AS_VOID_PTR 1 +#endif + +// These are functions you MUST implement ------------------------------- +#if CODE_ADDR_AS_VOID_PTR + +#if USE_ARGC_ARGV +uint32_t FlashInit(void *base_of_flash, uint32_t image_size, + uint32_t link_address, uint32_t flags, + int argc, char const *argv[]); +#else +uint32_t FlashInit(void *base_of_flash, uint32_t image_size, + uint32_t link_address, uint32_t flags); +#endif + +uint32_t FlashWrite(void *block_start, + uint32_t offset_into_block, + uint32_t count, + char const *buffer); + +uint32_t FlashErase(void *block_start, + uint32_t block_size); + +#else // !CODE_ADDR_AS_VOID_PTR + +#if USE_ARGC_ARGV +uint32_t FlashInit(uint32_t base_of_flash, uint32_t image_size, + uint32_t link_address, uint32_t flags, + int argc, char const *argv[]); +#else +uint32_t FlashInit(uint32_t base_of_flash, uint32_t image_size, + uint32_t link_address, uint32_t flags); +#endif + +uint32_t FlashWrite(uint32_t block_start, + uint32_t offset_into_block, + uint32_t count, + char const *buffer); + +uint32_t FlashErase(uint32_t block_start, + uint32_t block_size); + +#endif // CODE_ADDR_AS_VOID_PTR + +// These are functions you MAY implement -------------------------------- + +#if CODE_ADDR_AS_VOID_PTR +uint32_t FlashChecksum(void const *begin, uint32_t count); +#else +uint32_t FlashChecksum(uint32_t begin, uint32_t count); +#endif + +uint32_t FlashSignoff(void); + +#define OPTIONAL_CHECKSUM _Pragma("required=FlashChecksumEntry") __root +#define OPTIONAL_SIGNOFF _Pragma("required=FlashSignoffEntry") __root +void FlashChecksumEntry(); +void FlashSignoffEntry(); + +// These are functions you may call ------------------------------------- + +// If your code cannot be accessed using data pointers, you will have to +// write your own Crc16 function. +uint16_t Crc16(uint8_t const *p, uint32_t len); diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader_asm.s b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader_asm.s new file mode 100644 index 0000000..db962cd --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader_asm.s @@ -0,0 +1,197 @@ +;--------------------------------- +; +; Functions accessed by the debugger to perform a flash download. +; All public symbols and the function FlashBreak() are looked up and called by the debugger. +; +; Copyright (c) 2008 IAR Systems +; +; $Revision: 38034 $ +; +;--------------------------------- + +#define _CORTEX_ ((__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__) || (__CORE__ == __ARM7M__) || (__CORE__ == __ARM7EM__)) + + PUBLIC FlashInitEntry + PUBLIC FlashWriteEntry + PUBLIC FlashEraseWriteEntry + PUBLIC FlashChecksumEntry + PUBLIC FlashSignoffEntry + PUBLIC FlashBufferStart + PUBLIC FlashBufferEnd + + EXTERN FlashBreak + EXTERN Fl2FlashInitEntry + EXTERN Fl2FlashWriteEntry + EXTERN Fl2FlashEraseWriteEntry + EXTERN Fl2FlashChecksumEntry + EXTERN Fl2FlashSignoffEntry + + SECTION CSTACK:DATA:NOROOT(3) + + +;--------------------------------- +; +; FlashInitEntry() +; Debugger interface function +; +;--------------------------------- + SECTION .text:CODE:ROOT(2) +#if !_CORTEX_ + ARM +#else + THUMB +#endif + +FlashInitEntry: +#if !_CORTEX_ + ;; Set up the normal stack pointer. + LDR sp, =SFE(CSTACK) ; End of CSTACK +#endif + BL Fl2FlashInitEntry + B FlashBreak + + +;--------------------------------- +; +; FlashWriteEntry() +; Debugger interface function +; +;--------------------------------- + SECTION .text:CODE:ROOT(2) +#if !_CORTEX_ + ARM +#else + THUMB +#endif + +FlashWriteEntry: + BL Fl2FlashWriteEntry + B FlashBreak + + +;--------------------------------- +; +; FlashEraseWriteEntry +; Debugger interface function +; +;--------------------------------- + SECTION .text:CODE:ROOT(2) +#if !_CORTEX_ + ARM +#else + THUMB +#endif + +FlashEraseWriteEntry: + BL Fl2FlashEraseWriteEntry + B FlashBreak + + +;--------------------------------- +; +; FlashChecksumEntry +; Debugger interface function +; +;--------------------------------- + SECTION .text:CODE:NOROOT(2) +#if !_CORTEX_ + ARM +#else + THUMB +#endif + +FlashChecksumEntry: + BL Fl2FlashChecksumEntry + B FlashBreak + + +;--------------------------------- +; +; FlashSignoffEntry +; Debugger interface function +; +;--------------------------------- + SECTION .text:CODE:NOROOT(2) +#if !_CORTEX_ + ARM +#else + THUMB +#endif + +FlashSignoffEntry: + BL Fl2FlashSignoffEntry + B FlashBreak + + +;--------------------------------- +; +; Flash buffer and Cortex stack +; +;--------------------------------- + SECTION LOWEND:DATA(8) + DATA +FlashBufferStart: + + SECTION HIGHSTART:DATA + DATA +FlashBufferEnd: + + + +#if _CORTEX_ + PUBLIC __vector_table + + SECTION .intvec:CODE:ROOT(2) + DATA + +__vector_table: +#if 0 + DC32 SFE(CSTACK) + DC32 FlashInitEntry +#endif +#endif + +;--------------------------------- +; Entry: 0x200006b4 +; ram start up, normal boot +; : 0x200006c4 +; ram wake up, use debugger, +; 0x40000218 BIT(31) must 1 +; Section: .start.ram.data, +; put to 0x200006b4 +; : .patch.start.ram.data, +; put to 0x200006bc +;--------------------------------- + +#if _CORTEX_ + PUBLIC __ram_start_table + + SECTION .start:CODE:ROOT(2) + DATA + +__ram_start_table: + DC32 FlashInitEntry + DC32 FlashInitEntry + DC32 FlashInitEntry + DC32 FlashInitEntry + +#endif + +#if _CORTEX_ + PUBLIC __patch_ram_start_table + + SECTION .patch:CODE:ROOT(2) + DATA + +__patch_ram_start_table: + DC32 FlashInitEntry + DC32 FlashInitEntry + DC32 FlashInitEntry + DC32 FlashInitEntry + +#endif + END + + + + diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader_extra.h b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader_extra.h new file mode 100644 index 0000000..3982fe6 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/framework2/flash_loader_extra.h @@ -0,0 +1,27 @@ + + +#define OVERRIDE_LAYOUT 0x010000 +#define OVERRIDE_BUFSIZE 0x020000 +#define OVERRIDE_PAGESIZE 0x040000 + +#define LAYOUT_OVERRIDE_BUFFER ((char*)theFlashParams.buffer) +#define SET_BUFSIZE_OVERRIDE(new_size) theFlashParams.block_size = (new_size) +#define SET_PAGESIZE_OVERRIDE(new_size) theFlashParams.offset_into_block = (new_size) + +// parameter passing structure +typedef struct { + uint32_t base_ptr; + uint32_t count; + uint32_t offset_into_block; + void *buffer; + uint32_t block_size; +} FlashParamsHolder; + +typedef struct { + uint32_t start; + uint32_t length; +} FlashEraseData; + +extern FlashParamsHolder theFlashParams; +extern char FlashBufferStart; +extern char FlashBufferEnd; diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/mx25l8008_flashloader_mp.icf b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/mx25l8008_flashloader_mp.icf new file mode 100644 index 0000000..ba8de8c --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/mx25l8008_flashloader_mp.icf @@ -0,0 +1,59 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x10000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00010000; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000bc0; +define symbol __ICFEDIT_region_RAM_end__ = 0x1006FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { section .intvec }; + +place at start of RAM_region { section .start, section .patch, block RamTop with fixed order {readonly, section LOWEND }}; +place at end of RAM_region { block RamBottom with fixed order {section HIGHSTART, readwrite, section .init, + block CSTACK, block HEAP}}; + +define exported symbol __ram_start_table_start__ = 0x10000bc0; +define exported symbol __rom_bss_start__ = 0x10000300; +define exported symbol __rom_bss_end__ = 0x10000bc0; + + +// rom symbols +define exported symbol DiagPrintf = 0x0000f39d; +define exported symbol SpicWaitBusyDoneRtl8195A = 0x00002ea5; +define exported symbol SpicWaitWipDoneRtl8195A = 0x00002f55; +define exported symbol SpicLoadInitParaFromClockRtl8195A = 0x00003081; +define exported symbol VectorTableInitForOSRtl8195A = 0x00004019; +define exported symbol HalPinCtrlRtl8195A =0x00002b39; +define exported symbol SpicInitCPUCLK = 0x00030c98 ; +define exported symbol VectorTableInitRtl8195A = 0x00003de5; +define exported symbol SpicCmpDataForCalibrationRtl8195A = 0x00003049; +define exported symbol HalTimerInitRtl8195a = 0x0000ef3d; +define exported symbol VectorIrqDisRtl8195A = 0x0000418d; +define exported symbol VectorIrqRegisterRtl8195A = 0x00004029; +define exported symbol SpicInitRtl8195A = 0x000030e5; +define exported symbol HalCpuClkConfig = 0x00000341; +define exported symbol HalDelayUs = 0x00000899; +define exported symbol HalGetCpuClk = 0x00000355; +define exported symbol _memcpy = 0x0000f465; + + +define exported symbol ConfigDebugErr = 0x10000314; +define exported symbol ConfigDebugInfo = 0x10000310; +define exported symbol ConfigDebugWarn = 0x1000030c; diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/platform_autoconf.h.1 b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/platform_autoconf.h.1 new file mode 100644 index 0000000..a30d475 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/platform_autoconf.h.1 @@ -0,0 +1,210 @@ +/* + * Automatically generated by make menuconfig: don't edit + */ +#define AUTOCONF_INCLUDED + +/* + * Target Platform Selection + */ +#define CONFIG_WITHOUT_MONITOR 1 + +#define CONFIG_RTL8195A 1 +#undef CONFIG_FPGA +#undef CONFIG_RTL_SIM +#undef CONFIG_POST_SIM + +/* + * < Mass Production Option + */ +#undef CONFIG_MP +#undef CONFIG_CP +#undef CONFIG_FT +#define RTL8195A 1 +#define CONFIG_CPU_CLK 1 +#define CONFIG_CPU_166_6MHZ 1 +#undef CONFIG_CPU_83_3MHZ +#undef CONFIG_CPU_41_6MHZ +#undef CONFIG_CPU_20_8MHZ +#undef CONFIG_CPU_10_4MHZ +#undef CONFIG_CPU_4MHZ +#undef CONFIG_FPGA_CLK +#define PLATFORM_CLOCK (166666666) +#define CPU_CLOCK_SEL_VALUE (0) +#define CONFIG_SDR_CLK 1 +#define CONFIG_SDR_100MHZ 1 +#undef CONFIG_SDR_50MHZ +#undef CONFIG_SDR_25MHZ +#undef CONFIG_SDR_12_5MHZ +#define SDR_CLOCK_SEL_VALUE (0) +#define CONFIG_BOOT_PROCEDURE 1 +#define CONFIG_IMAGE_PAGE_LOAD 1 +#undef CONFIG_IMAGE_AUTO_LOAD +#define CONFIG_BOOT_TO_UPGRADE_IMG2 1 +#undef CONFIG_PERI_UPDATE_IMG +#define CONFIG_BOOT_FROM_JTAG 1 +#undef CONFIG_ALIGNMENT_EXCEPTION_ENABLE +#define CONFIG_KERNEL 1 +#define PLATFORM_FREERTOS 1 +#undef PLATFORM_UCOSII +#undef PLATFORM_ECOS +#undef CONFIG_TASK_SCHEDUL_DIS +#define TASK_SCHEDULER_DISABLED (0) +#define CONFIG_NORMALL_MODE 1 +#undef CONFIG_MEMORY_VERIFY_MODE +#define CONFIG_TIMER_EN 1 +#define CONFIG_TIMER_NORMAL 1 +#undef CONFIG_TIMER_TEST +#define CONFIG_TIMER_MODULE 1 +#define CONFIG_WDG 1 +#undef CONFIG_WDG_NON +#define CONFIG_WDG_NORMAL 1 +#define CONFIG_GDMA_EN 1 +#define CONFIG_GDMA_NORMAL 1 +#undef CONFIG_GDMA_TEST +#define CONFIG_GDMA_MODULE 1 +#define CONFIG_WIFI_EN 1 +#define CONFIG_WIFI_NORMAL 1 +#undef CONFIG_WIFI_TEST +#define CONFIG_WIFI_MODULE 1 +#define CONFIG_GPIO_EN 1 +#define CONFIG_GPIO_NORMAL 1 +#undef CONFIG_GPIO_TEST +#define CONFIG_GPIO_MODULE 1 +#if defined(CONFIG_INIC) || (CONFIG_SDIOD) +#define CONFIG_SDIO_DEVICE_EN 1 +#define CONFIG_SDIO_DEVICE_NORMAL 1 +#undef CONFIG_SDIO_DEVICE_TEST +#define CONFIG_SDIO_DEVICE_MODULE 1 +#else +#undef CONFIG_SDIO_DEVICE_EN +#endif +#define CONFIG_SDIO_HOST_EN 1 +#define CONFIG_USB_EN 1 +#undef CONFIG_USB_NORMAL +#define CONFIG_USB_TEST 1 +#define CONFIG_USB_MODULE 1 +#define CONFIG_USB_VERIFY 1 +#undef CONFIG_USB_ROM_LIB +//#define CONFIG_USB_DBGINFO_EN 1 +#ifdef CONFIG_INIC//defined(CONFIG_INIC) +#define DWC_DEVICE_ONLY 1 +#else +#define DWC_HOST_ONLY 1 +#define CONFIG_USB_HOST_ONLY 1 +#endif +#define CONFIG_SPI_COM_EN 1 +#define CONFIG_SPI_COM_NORMAL 1 +#undef CONFIG_SPI_COM_TEST +#define CONFIG_SPI_COM_MODULE 1 +#define CONFIG_UART_EN 1 +#define CONFIG_UART_NORMAL 1 +#undef CONFIG_UART_TEST +#define CONFIG_UART_MODULE 1 +#define CONFIG_I2C_EN 1 +#define CONFIG_I2C_NORMAL 1 +#undef CONFIG_I2C_TEST +#define CONFIG_I2C_MODULE 1 +#undef CONFIG_DEBUG_LOG_I2C_HAL +#undef CONFIG_PCM_EN +#define CONFIG_I2S_EN 1 +#define CONFIG_I2S_NORMAL 1 +#undef CONFIG_I2S_TEST +#define CONFIG_I2S_MODULE 1 +#undef CONFIG_DEBUG_LOG_I2S_HAL +#define CONFIG_NFC_EN 1 +#define CONFIG_NFC_NORMAL 1 +#undef CONFIG_NFC_TEST +#define CONFIG_NFC_MODULE 1 +#define CONFIG_SOC_PS_EN 1 +#define CONFIG_SOC_PS_NORMAL 1 +#undef CONFIG_SOC_PS_TEST +#define CONFIG_SOC_PS_MODULE 1 +#define CONFIG_CRYPTO_EN 1 +#define CONFIG_CRYPTO_NORMAL 1 +#undef CONFIG_CRYPTO_TEST +#define CONFIG_CRYPTO_MODULE 1 +#define CONFIG_MII_EN 1 +#define CONFIG_PWM_EN 1 +#define CONFIG_PWM_NORMAL 1 +#undef CONFIG_PWM_TEST +#define CONFIG_PWM_MODULE 1 +#define CONFIG_EFUSE_EN 1 +#define CONFIG_EFUSE_NORMAL 1 +#undef CONFIG_EFUSE_TEST +#define CONFIG_EFUSE_MODULE 1 +#define CONFIG_SDR_EN 1 +#define CONFIG_SDR_NORMAL 1 +#undef CONFIG_SDR_TEST +#define CONFIG_SDR_MODULE 1 +#define CONFIG_SPIC_EN 1 +#define CONFIG_SPIC_NORMAL 1 +#undef CONFIG_SPIC_TEST +#define CONFIG_SPIC_MODULE 1 +#define CONFIG_ADC_EN 1 +#define CONFIG_DAC_EN 1 +#define CONFIG_NOR_FLASH 1 +#undef CONFIG_SPI_FLASH +#undef CONFIG_NAND_FLASH +#undef CONFIG_NONE_FLASH +#undef CONFIG_BTBX_EN + +/* + * < Engineer Mode Config + */ +#undef CONFIG_JTAG +#undef CONFIG_COMPILE_FLASH_DOWNLOAD_CODE +#undef CONIFG_COMPILE_EXTERNAL_SRAM_CALIBRATE +#undef CONFIG_CMSIS_MATH_LIB_EN + +/* + * < Application Config + */ +#define CONFIG_NETWORK 1 +#define CONFIG_RTLIB_EN 1 +#define CONFIG_RTLIB_NORMAL 1 +#undef CONFIG_RTLIB_TEST +#define CONFIG_RTLIB_MODULE 1 + +/* + * < System Debug Message Config + */ +#define CONFIG_UART_LOG_HISTORY 1 +#undef CONFIG_CONSOLE_NORMALL_MODE +#define CONFIG_CONSOLE_VERIFY_MODE 1 +#define CONFIG_DEBUG_LOG 1 +#define CONFIG_DEBUG_ERR_MSG 1 +#undef CONFIG_DEBUG_WARN_MSG +#undef CONFIG_DEBUG_INFO_MSG + +/* + * < SDK Option Config + */ +#undef CONFIG_MBED_ENABLED +#undef CONFIG_APP_DEMO + +/* + * < Select Chip Version + */ +#undef CONFIG_CHIP_A_CUT +#define CONFIG_CHIP_B_CUT 1 +#undef CONFIG_CHIP_C_CUT +#undef CONFIG_CHIP_E_CUT + +/* + * < Select toolchain + */ +#undef CONFIG_TOOLCHAIN_ASDK +#undef CONFIG_TOOLCHAIN_ARM_GCC + +/* + * < Build Option + */ +#define CONFIG_LINK_ROM_LIB 1 +#undef CONFIG_LINK_ROM_SYMB +#undef CONFIG_NORMAL_BUILD +#undef CONFIG_RELEASE_BUILD +#undef CONFIG_RELEASE_BUILD_LIBRARIES +#undef CONFIG_LIB_BUILD_RAM +#define CONFIG_RELEASE_BUILD_RAM_ALL 1 +#undef CONFIG_IMAGE_ALL +#define CONFIG_IMAGE_SEPARATE 1 diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/preload.mp.mac b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/preload.mp.mac new file mode 100644 index 0000000..5742875 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/preload.mp.mac @@ -0,0 +1,64 @@ +setup() +{ + __var tmp; + + __hwResetWithStrategy(0, 1); + __hwReset(1); + + __writeMemory32(0x21, 0x40000014, "Memory"); __delay(10); + __writeMemory32(0x1FC00002, 0x40000304, "Memory"); __delay(10); + __writeMemory32(0x400, 0x40000250, "Memory"); __delay(10); + __writeMemory32(0x0, 0x40000340, "Memory"); __delay(10); + __writeMemory32(0xc04, 0x40000230, "Memory"); __delay(10); + __writeMemory32(0x1157, 0x40000210, "Memory"); __delay(10); + __writeMemory32(0x110011, 0x400002c0, "Memory"); __delay(10); + __writeMemory32(0xffffffff, 0x40000320, "Memory"); __delay(10); + + __writeMemory32(0x1, 0x40005224, "Memory"); __delay(10); + __writeMemory32(0x2c8, 0x40005004, "Memory"); __delay(10); + __writeMemory32(0xffffd000, 0x40005008, "Memory"); __delay(10); + __delay(3); + __writeMemory32(0x22, 0x40005020, "Memory"); __delay(10); + __delay(3); + __writeMemory32(0x09032001, 0x40005010, "Memory"); __delay(10); + __delay(3); + __writeMemory32(0x2611, 0x40005014, "Memory"); __delay(10); + __delay(3); + __writeMemory32(0x68413, 0x40005018, "Memory"); __delay(10); + __delay(3); + __writeMemory32(0x42, 0x4000501c, "Memory"); __delay(10); + __delay(3); + + // Enable + __writeMemory32(0x700, 0x4000500c, "Memory"); __delay(10); + __delay(20); + __writeMemory32(0x1, 0x40005000, "Memory"); __delay(10); + __delay(100); + tmp = __readMemory32(0x40005000,"Memory"); __delay(10); + __writeMemory32(0x600, 0x4000500c, "Memory"); __delay(10); + __delay(30); +} + +execUserPreload() +{ + __var tmp; + //setup(); + tmp = __readMemory32(0x40000210, "Memory")|(1<<27); + __writeMemory32(tmp, 0x40000210, "Memory"); +} + +execUserSetup() +{ + //execUserPreload(); + //__loadImage("$TARGET_PATH$ ", 0, 0); + //__writeMemory32(0x80000000, 0x40000218, "Memory"); +} + +execUserFlashInit() // Called by debugger before loading flash loader in RAM. +{ + __var tmp; + __message "----- Prepare hardware for Flashloader -----\n"; + //setup(); + tmp = __readMemory32(0x40000210, "Memory")|(1<<27); + __writeMemory32(tmp, 0x40000210, "Memory"); +} \ No newline at end of file diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/rtl8195a/hal_misc.c b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/rtl8195a/hal_misc.c new file mode 100644 index 0000000..3520a32 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/EWARM_bcut/rtl8195a/hal_misc.c @@ -0,0 +1,359 @@ +#include "rtl8195a.h" + +typedef struct _UART_LOG_BUF_ { + u8 BufCount; //record the input cmd char number. + u8 UARTLogBuf[127]; //record the input command. +} UART_LOG_BUF, *PUART_LOG_BUF; + + + + +typedef struct _UART_LOG_CTL_ { + u8 NewIdx; + u8 SeeIdx; + u8 RevdNo; + u8 EscSTS; + u8 ExecuteCmd; + u8 ExecuteEsc; + u8 BootRdy; + u8 Resvd; + PUART_LOG_BUF pTmpLogBuf; + VOID *pfINPUT; + PCOMMAND_TABLE pCmdTbl; + u32 CmdTblSz; + + u32 CRSTS; + + u8 (*pHistoryBuf)[127]; + + u32 TaskRdy; + u32 Sema; +} UART_LOG_CTL, *PUART_LOG_CTL; + + volatile UART_LOG_CTL UartLogCtl; + + volatile UART_LOG_CTL *pUartLogCtl; + + u8 *ArgvArray[10]; + + UART_LOG_BUF UartLogBuf; + + + u8 UartLogHistoryBuf[5][127]; + +extern VOID +SpicLoadInitParaFromClockRtl8195A +( + IN u8 CpuClkMode, + IN u8 BaudRate, + IN PSPIC_INIT_PARA pSpicInitPara +); + +VOID +PatchSpicInitRtl8195A +( + IN u8 InitBaudRate, + IN u8 SpicBitMode +) +{ + + u32 Value32; + SPIC_INIT_PARA SpicInitPara; + +#ifdef CONFIG_FPGA + SpicInitPara.BaudRate = 1;//FPGASpicInitPara.BaudRate; + SpicInitPara.RdDummyCyle = 1;//FPGASpicInitPara.RdDummyCyle; + SpicInitPara.DelayLine = 0;//FPGASpicInitPara.DelayLine; +#else + u8 CpuClk; + CpuClk = (((u8)(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70))) >> 4); + SpicLoadInitParaFromClockRtl8195A(CpuClk, InitBaudRate, &SpicInitPara); +#endif + // Disable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + + HAL_SPI_WRITE32(REG_SPIC_BAUDR, BIT_SCKDV(InitBaudRate)); + + HAL_SPI_WRITE32(REG_SPIC_SER, BIT_SER); + + Value32 = HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH); + + HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, + ((Value32 & 0xFFFF0000) | BIT_RD_DUMMY_LENGTH(SpicInitPara.RdDummyCyle))); + + HAL_WRITE32(PERI_ON_BASE, REG_PESOC_MEM_CTRL, + ((HAL_READ32(PERI_ON_BASE, REG_PESOC_MEM_CTRL)&0xFFFFFF00)| + SpicInitPara.DelayLine)); + + HAL_SPI_WRITE32(REG_SPIC_CTRLR1, BIT_NDF(4)); + + switch (SpicBitMode) { + case SpicOneBitMode: + HAL_SPI_WRITE32(REG_SPIC_CTRLR0, + (HAL_SPI_READ32(REG_SPIC_CTRLR0) & (~(BIT_ADDR_CH(3)|BIT_DATA_CH(3))))); + break; + + case SpicDualBitMode: + HAL_SPI_WRITE32(REG_SPIC_CTRLR0, + ((HAL_SPI_READ32(REG_SPIC_CTRLR0) & (~(BIT_ADDR_CH(3)|BIT_DATA_CH(3)))) | + (BIT_ADDR_CH(1)|BIT_DATA_CH(1)))); + + break; + + case SpicQuadBitMode: + HAL_SPI_WRITE32(REG_SPIC_CTRLR0, + ((HAL_SPI_READ32(REG_SPIC_CTRLR0) & (~(BIT_ADDR_CH(3)|BIT_DATA_CH(3)))) | + (BIT_ADDR_CH(2)|BIT_DATA_CH(2)))); + break; + + } + + // Enable SPI_FLASH User Mode +// HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN); +} + + +#include "hal_timer.h" +extern BOOL +HalTimerInitRtl8195a( + IN VOID *Data +); + +VOID +PatchHalInitPlatformTimer( +VOID +) +{ + TIMER_ADAPTER TimerAdapter; + + OSC32K_CKGEN_CTRL(ON); + GTIMER_FCTRL(ON); + ACTCK_TIMER_CCTRL(ON); + SLPCK_TIMER_CCTRL(ON); + + TimerAdapter.IrqDis = ON; +// TimerAdapter.IrqHandle = (IRQ_FUN)NULL; + TimerAdapter.TimerId = 1; + TimerAdapter.TimerIrqPriority = 0; + TimerAdapter.TimerLoadValueUs = 0; + TimerAdapter.TimerMode = FREE_RUN_MODE; + + HalTimerInitRtl8195a((VOID*) &TimerAdapter); + +} + +#define UART_BAUD_RATE_2400 2400 +#define UART_BAUD_RATE_4800 4800 +#define UART_BAUD_RATE_9600 9600 +#define UART_BAUD_RATE_19200 19200 +#define UART_BAUD_RATE_38400 38400 +#define UART_BAUD_RATE_57600 57600 +#define UART_BAUD_RATE_115200 115200 +#define UART_BAUD_RATE_921600 921600 +#define UART_BAUD_RATE_1152000 1152000 + +#define UART_PARITY_ENABLE 0x08 +#define UART_PARITY_DISABLE 0 + +#define UART_DATA_LEN_5BIT 0x0 +#define UART_DATA_LEN_6BIT 0x1 +#define UART_DATA_LEN_7BIT 0x2 +#define UART_DATA_LEN_8BIT 0x3 + +#define UART_STOP_1BIT 0x0 +#define UART_STOP_2BIT 0x4 + + +extern u32 +HalLogUartInit( + IN LOG_UART_ADAPTER UartAdapter +); + +extern u32 +HalGetCpuClk( + VOID +); + +const u32 StartupCpkClkTbl[]= { + 200000000, + 100000000, + 50000000, + 25000000, + 12500000, + 4000000 +}; + + +u32 +StartupHalGetCpuClk( + VOID +) +{ + u32 CpuType = 0, CpuClk = 0, FreqDown = 0; + + CpuType = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70)) >> 4); + FreqDown = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) & BIT17; + + CpuClk = StartupCpkClkTbl[CpuType]; + + if ( !FreqDown ) { + if ( CpuClk > 4000000 ){ + CpuClk = (CpuClk*5/6); + } + } + + return CpuClk; +} + +u32 +PatchHalLogUartInit( + IN LOG_UART_ADAPTER UartAdapter +) +{ + u32 SetData; + u32 Divisor; + u32 Dlh; + u32 Dll; + u32 SysClock; + + /* + Interrupt enable Register + 7: THRE Interrupt Mode Enable + 2: Enable Receiver Line Status Interrupt + 1: Enable Transmit Holding Register Empty Interrupt + 0: Enable Received Data Available Interrupt + */ + // disable all interrupts + HAL_UART_WRITE32(UART_INTERRUPT_EN_REG_OFF, 0); + + /* + Line Control Register + 7: DLAB, enable reading and writing DLL and DLH register, and must be cleared after + initial baud rate setup + 3: PEN, parity enable/disable + 2: STOP, stop bit + 1:0 DLS, data length + */ + + // set DLAB bit to 1 + HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, 0x80); + + // set up buad rate division + +#ifdef CONFIG_FPGA + SysClock = SYSTEM_CLK; + Divisor = (SysClock / (16 * (UartAdapter.BaudRate))); +#else + { + u32 SampleRate,Remaind; + + //SysClock = (HalGetCpuClk()>>2); + SysClock = (StartupHalGetCpuClk()>>2); + + SampleRate = (16 * (UartAdapter.BaudRate)); + + Divisor= SysClock/SampleRate; + + Remaind = ((SysClock*10)/SampleRate) - (Divisor*10); + + if (Remaind>4) { + Divisor++; + } + } +#endif + + + Dll = Divisor & 0xff; + Dlh = (Divisor & 0xff00)>>8; + HAL_UART_WRITE32(UART_DLL_OFF, Dll); + HAL_UART_WRITE32(UART_DLH_OFF, Dlh); + + // clear DLAB bit + HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, 0); + + // set data format + SetData = UartAdapter.Parity | UartAdapter.Stop | UartAdapter.DataLength; + HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, SetData); + + /* FIFO Control Register + 7:6 level of receive data available interrupt + 5:4 level of TX empty trigger + 2 XMIT FIFO reset + 1 RCVR FIFO reset + 0 FIFO enable/disable + */ + // FIFO setting, enable FIFO and set trigger level (2 less than full when receive + // and empty when transfer + HAL_UART_WRITE32(UART_FIFO_CTL_REG_OFF, UartAdapter.FIFOControl); + + /* + Interrupt Enable Register + 7: THRE Interrupt Mode enable + 2: Enable Receiver Line status Interrupt + 1: Enable Transmit Holding register empty INT32 + 0: Enable received data available interrupt + */ + HAL_UART_WRITE32(UART_INTERRUPT_EN_REG_OFF, UartAdapter.IntEnReg); + + if (UartAdapter.IntEnReg) { + // Enable Peripheral_IRQ Setting for Log_Uart + HAL_WRITE32(VENDOR_REG_BASE, PERIPHERAL_IRQ_EN, 0x1000000); + + // Enable ARM Cortex-M3 IRQ + NVIC_SetPriorityGrouping(0x3); + NVIC_SetPriority(PERIPHERAL_IRQ, 14); + NVIC_EnableIRQ(PERIPHERAL_IRQ); + } + + + return 0; +} + +u32 log_uart_irq(VOID *Data) +{ + return 0; +} + +VOID +PatchHalInitPlatformLogUart( + VOID +) +{ + IRQ_HANDLE UartIrqHandle; + LOG_UART_ADAPTER UartAdapter; + + //4 Release log uart reset and clock + LOC_UART_FCTRL(OFF); + LOC_UART_FCTRL(ON); + ACTCK_LOG_UART_CCTRL(ON); + + PinCtrl(LOG_UART,S0,ON); + + //4 Register Log Uart Callback function + UartIrqHandle.Data = (u32)NULL;//(u32)&UartAdapter; + UartIrqHandle.IrqNum = UART_LOG_IRQ; + UartIrqHandle.IrqFun = (IRQ_FUN) log_uart_irq;//UartLogIrqHandleRam; + UartIrqHandle.Priority = 0; + + //4 Inital Log uart + UartAdapter.BaudRate = UART_BAUD_RATE_38400; + UartAdapter.DataLength = UART_DATA_LEN_8BIT; + UartAdapter.FIFOControl = 0xC1; + UartAdapter.IntEnReg = 0x00; + UartAdapter.Parity = UART_PARITY_DISABLE; + UartAdapter.Stop = UART_STOP_1BIT; + + //4 Initial Log Uart + PatchHalLogUartInit(UartAdapter); + + //4 Register Isr handle + InterruptRegister(&UartIrqHandle); + + UartAdapter.IntEnReg = 0x05; + + //4 Initial Log Uart for Interrupt + PatchHalLogUartInit(UartAdapter); + + //4 initial uart log parameters before any uartlog operation + //RtlConsolInit(ROM_STAGE,GetRomCmdNum(),(VOID*)&UartLogRomCmdTable);// executing boot seq., +} \ No newline at end of file diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP.board b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP.board new file mode 100644 index 0000000..a2c0b37 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP.board @@ -0,0 +1,24 @@ + + + + + CODE 0x10000bc0 0x10003FFF + $PROJ_DIR$\..\..\..\component\soc\realtek\8195a\misc\iar_utility\common\flashloader\FlashRTL8195aMP.flash + 0x00000000 + --head + + + CODE 0x10004000 0x1006FFFF + $PROJ_DIR$\..\..\..\component\soc\realtek\8195a\misc\iar_utility\common\flashloader\FlashRTL8195aMP.flash + 0x00000000 + --cascade + + + CODE 0x30000000 0x301FFFFF + $PROJ_DIR$\..\..\..\component\soc\realtek\8195a\misc\iar_utility\common\flashloader\FlashRTL8195aMP.flash + 0x00000000 + --cascade + + CODE 0x00000000 0x000FFFFF + CODE 0x10000000 0x10000bbf + diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP.flash b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP.flash new file mode 100644 index 0000000..a96f962 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP.flash @@ -0,0 +1,10 @@ + + + + $PROJ_DIR$\..\..\..\component\soc\realtek\8195a\misc\iar_utility\common\flashloader\FlashRTL8195aMP.out + 0x00000000 + 8 + 512 0x1000 + $PROJ_DIR$\..\..\..\component\soc\realtek\8195a\misc\iar_utility\common\flashloader\FlashRTL8195aMP.mac + 1 + diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP.mac b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP.mac new file mode 100644 index 0000000..c628625 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP.mac @@ -0,0 +1,72 @@ +setup() +{ + __var tmp; + + __hwResetWithStrategy(0, 2); + __hwReset(1); + + tmp = __readMemory32(0x40000014,"Memory"); __delay(10); + __message "0x40000014=",tmp:%x; + + __writeMemory32(0x21, 0x40000014, "Memory"); __delay(10); + + __writeMemory32(0x1FC00002, 0x40000304, "Memory"); __delay(10); + __writeMemory32(0x400, 0x40000250, "Memory"); __delay(10); + __writeMemory32(0x0, 0x40000340, "Memory"); __delay(10); + __writeMemory32(0xc04, 0x40000230, "Memory"); __delay(10); + __writeMemory32(0x1157, 0x40000210, "Memory"); __delay(10); + __writeMemory32(0x110011, 0x400002c0, "Memory"); __delay(10); + __writeMemory32(0xffffffff, 0x40000320, "Memory"); __delay(10); +/* + __writeMemory32(0x1, 0x40005224, "Memory"); __delay(10); + __writeMemory32(0x2c8, 0x40005004, "Memory"); __delay(10); + __writeMemory32(0xffffd000, 0x40005008, "Memory"); __delay(10); + __delay(3); + __writeMemory32(0x22, 0x40005020, "Memory"); __delay(10); + __delay(3); + __writeMemory32(0x09032001, 0x40005010, "Memory"); __delay(10); + __delay(3); + __writeMemory32(0x2611, 0x40005014, "Memory"); __delay(10); + __delay(3); + __writeMemory32(0x68413, 0x40005018, "Memory"); __delay(10); + __delay(3); + __writeMemory32(0x42, 0x4000501c, "Memory"); __delay(10); + __delay(3); + + // Enable + __writeMemory32(0x700, 0x4000500c, "Memory"); __delay(10); + __delay(20); + __writeMemory32(0x1, 0x40005000, "Memory"); __delay(10); + __delay(100); + tmp = __readMemory32(0x40005000,"Memory"); __delay(10); + __writeMemory32(0x600, 0x4000500c, "Memory"); __delay(10); + __delay(30); +*/ +} + +execUserPreload() +{ + __var tmp; + setup(); + tmp = __readMemory32(0x40000210, "Memory")|(1<<27); + __writeMemory32(tmp, 0x40000210, "Memory"); +} + +execUserSetup() +{ + //execUserPreload(); + //__loadImage("$TARGET_PATH$ ", 0, 0); + //__writeMemory32(0x80000000, 0x40000218, "Memory"); +} + +execUserFlashInit() // Called by debugger before loading flash loader in RAM. +{ + __var tmp; + __message "----- Prepare hardware for Flashloader -----\n"; + + __writeMemory32(0x1FFFFFF8, 0x10000000, "Memory"); + __writeMemory32(0x101, 0x10000004, "Memory"); + setup(); + tmp = __readMemory32(0x40000210, "Memory")|(1<<27); + __writeMemory32(tmp, 0x40000210, "Memory"); +} \ No newline at end of file diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP.out b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP.out new file 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zi~a!?@{kKm>nWOFY5dLy4goJV`CkEi7v_7Bz83fpaG@FB0Q^VnuO2XQBk+~x{7CiP z419-#BfyVHcsKBGC43>#V?KY(%w20iP$~_kh0+JX`P!f-m-8NuNyy7W$oV5eZMa$rQq@QuLf54Rk^E$9bbeKfI47s&-(6e?}aC`9)Zi{bwS9hp}$-P$^fk~%(4DCjUOVgJOh zM!!XQ3!5kuwibmE9Wf;v9}*8CGSn9NB08#Dj`>Y`oZ3lr)XvxiBBGmxkI0Y4aTGL5 zDZ;!&e#Am4SRuN9Fs2Dg9={}kt_ubKni?lvl+Q|h + + + + CODE 0x10000bc8 0x10005FFF + $PROJ_DIR$\..\..\..\component\soc\realtek\8195a\misc\iar_utility\common\flashloader\FlashRTL8195aMP.flash + 0x00000000 + --head + --img2_addr + 0xB000 + + + CODE 0x00000000 0x000FFFFF + CODE 0x10000000 0x10000bc7 + CODE 0x10006000 0x1006FFFF + CODE 0x30000000 0x301FFFFF + diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP_img1_v0.board b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP_img1_v0.board new file mode 100644 index 0000000..d4a9af7 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP_img1_v0.board @@ -0,0 +1,17 @@ + + + + + CODE 0x10000bc0 0x10005FFF + $PROJ_DIR$\..\..\..\component\soc\realtek\8195a\misc\iar_utility\common\flashloader\FlashRTL8195aMP.flash + 0x00000000 + --head + --img2_addr + 0xB000 + + + CODE 0x00000000 0x000FFFFF + CODE 0x10000000 0x10000bbf + CODE 0x10006000 0x1006FFFF + CODE 0x30000000 0x301FFFFF + diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP_img2.board b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP_img2.board new file mode 100644 index 0000000..661c2cb --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aMP_img2.board @@ -0,0 +1,26 @@ + + + + + CODE 0x10000bc8 0x10005FFF + $PROJ_DIR$\..\..\..\component\soc\realtek\8195a\misc\iar_utility\common\flashloader\FlashRTL8195aMP.flash + 0x00000000 + --head + --img2_addr + 0xB000 + + + CODE 0x10006000 0x1006FFFF + $PROJ_DIR$\..\..\..\component\soc\realtek\8195a\misc\iar_utility\common\flashloader\FlashRTL8195aMP.flash + 0xB000 + + + CODE 0x30000000 0x301FFFFF + $PROJ_DIR$\..\..\..\component\soc\realtek\8195a\misc\iar_utility\common\flashloader\FlashRTL8195aMP.flash + 0x0000 + --cascade + + CODE 0x00000000 0x000FFFFF + CODE 0x10000000 0x10000bc7 + CODE 0x1FFF0000 0x1FFFFFFF + diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aQA.board b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aQA.board new file mode 100644 index 0000000..2562be5 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aQA.board @@ -0,0 +1,30 @@ + + + + + CODE 0x200006b4 0x2002FFFF + $PROJ_DIR$\flashloader\FlashRTL8195aQA.flash + 0x00000000 + + + CODE 0x30000000 0x301FFFFF + $PROJ_DIR$\flashloader\FlashRTL8195aQA.flash + 0x00010000 + DATA_Z 0x30000000 0x301FFFFF + + + CODE 0x20080000 0x200BFFFF + $PROJ_DIR$\flashloader\FlashRTL8195aQA.flash + 0x00020000 + DATA_Z 0x20080000 0x200BFFFF + + + CODE 0x00000000 0x00000000 + $PROJ_DIR$\flashloader\FlashRTL8195aQA.flash + 0x00030000 + + CODE 0x00000001 0x000BFFFF + CODE 0x20000000 0x200006b3 + + + diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aQA.flash b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aQA.flash new file mode 100644 index 0000000..8613f80 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aQA.flash @@ -0,0 +1,10 @@ + + + + $PROJ_DIR$\flashloader\FlashRTL8195aQA.out + 0x00000000 + 8 + 256 0x1000 + $PROJ_DIR$\flashloader\FlashRTL8195aQA.mac + 1 + diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aQA.mac b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aQA.mac new file mode 100644 index 0000000..4d670e0 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aQA.mac @@ -0,0 +1,60 @@ +setup() +{ + __var tmp; + + __hwReset(1); + + __writeMemory32(0x21, 0x40000014, "Memory"); __delay(10); + __writeMemory32(0x1FC00002, 0x40000304, "Memory"); __delay(10); + __writeMemory32(0x400, 0x40000250, "Memory"); __delay(10); + __writeMemory32(0x0, 0x40000340, "Memory"); __delay(10); + __writeMemory32(0xc04, 0x40000230, "Memory"); __delay(10); + __writeMemory32(0x1157, 0x40000210, "Memory"); __delay(10); + __writeMemory32(0x110011, 0x400002c0, "Memory"); __delay(10); + __writeMemory32(0xffffffff, 0x40000320, "Memory"); __delay(10); + + __writeMemory32(0x1, 0x40005224, "Memory"); __delay(10); + __writeMemory32(0x2c8, 0x40005004, "Memory"); __delay(10); + __writeMemory32(0xffffd000, 0x40005008, "Memory"); __delay(10); + __delay(3); + __writeMemory32(0x22, 0x40005020, "Memory"); __delay(10); + __delay(3); + __writeMemory32(0x09032001, 0x40005010, "Memory"); __delay(10); + __delay(3); + __writeMemory32(0x2611, 0x40005014, "Memory"); __delay(10); + __delay(3); + __writeMemory32(0x68413, 0x40005018, "Memory"); __delay(10); + __delay(3); + __writeMemory32(0x42, 0x4000501c, "Memory"); __delay(10); + __delay(3); + + // Enable + __writeMemory32(0x700, 0x4000500c, "Memory"); __delay(10); + __delay(20); + __writeMemory32(0x1, 0x40005000, "Memory"); __delay(10); + __delay(100); + tmp = __readMemory32(0x40005000,"Memory"); __delay(10); + __writeMemory32(0x600, 0x4000500c, "Memory"); __delay(10); + __delay(30); +} + +execUserPreload() +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); + __writeMemory32(0x80000000, 0x40000218, "Memory"); +} + +execUserSetup() +{ + //execUserPreload(); + //__loadImage("$TARGET_PATH$ ", 0, 0); + //__writeMemory32(0x80000000, 0x40000218, "Memory"); +} + +execUserFlashInit() // Called by debugger before loading flash loader in RAM. +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); + __writeMemory32(0x80000000, 0x40000218, "Memory"); +} \ No newline at end of file diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aQA.out b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/iar_utility/common/flashloader/FlashRTL8195aQA.out new file mode 100644 index 0000000000000000000000000000000000000000..c89a9590d31352624a9c6b857b6ee0986d4b4877 GIT binary patch literal 151784 zcmdSC4P4Y!_CJ2_XJ(iO1{j_c0rdlDp(u^0g=Pr@41=N&Xj--lDCn@EjDSXMn^?AK zS!-ME*K+%=ZS8)0PE5a>ySZYuyH>Ve$lBFxH`*;})3yOg27KW6KKJwa%mb2c?fzf& zhu58Z@45G!d(OG%KHs^suAtb-IcM6R#L^kXR+lmP$$1hx05^g$!!#xXp3dU%Nom8m zyq-AD(_ZUgJonV*WT}%+T~?rLw=~CiE2Dhvc|A;rG@T_q!NWTuQWHI%Lbflv6<8AB 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