From 741520fa66c1f81cae23afefa6c7e35e99573562 Mon Sep 17 00:00:00 2001 From: pvvx Date: Wed, 1 Feb 2017 14:57:01 +0300 Subject: [PATCH] fix & update --- .../common/api/at_cmd/atcmd_ethernet.c | 34 +- .../component/common/api/at_cmd/atcmd_sys.c | 1060 +-- .../component/common/api/at_cmd/atcmd_wifi.c | 106 +- .../component/common/api/wifi/wifi_conf.c | 1 + .../component/common/api/wifi/wifi_conf.h | 2 +- .../component/common/api/wifi/wifi_ind.c | 8 + .../drivers/ethernet_mii/ethernet_mii.c | 10 +- .../drivers/sdio/realtek/sdio_host/src/sd.c | 4 +- .../sdio/realtek/sdio_host/src/sdio_host.c | 12 +- .../wlan/realtek/include/wifi_constants.h | 13 +- .../drivers/wlan/realtek/include/wifi_lib.h | 5894 ++++++++--------- .../wlan/realtek/include/wifi_structures.h | 2 +- .../drivers/wlan/realtek/include/wlan_lib.h | 26 +- .../wlan/realtek/src/osdep/freertos/wrapper.h | 2 +- .../drivers/wlan/realtek/src/osdep/wireless.h | 2 +- .../wlan/realtek/src/osdep/wlan_intf.h | 4 +- .../example/uart_atcmd/example_uart_atcmd.c | 5 + .../example/uart_atcmd/example_uart_atcmd.h | 25 +- .../file_system/fatfs/disk_if/src/sdcard.c | 1 - .../file_system/fatfs/r0.10c/include/ffconf.h | 4 +- .../common/file_system/fatfs/r0.10c/src/ff.c | 6 +- .../component/os/freertos/freertos_pmu.c | 26 +- .../soc/realtek/8195a/cmsis/core_cmFunc.h | 2 +- .../soc/realtek/8195a/cmsis/core_cmInstr.h | 2 +- .../realtek/8195a/cmsis/device/rtl_stdlib.h | 6 +- .../soc/realtek/8195a/cmsis/device/strproc.h | 3 +- .../realtek/8195a/cmsis/device/system_8195a.c | 2 +- .../soc/realtek/8195a/fwlib/hal_gdma.h | 20 +- .../soc/realtek/8195a/fwlib/hal_gpio.h | 2 +- .../soc/realtek/8195a/fwlib/hal_misc.h | 7 +- .../soc/realtek/8195a/fwlib/hal_sdio_host.h | 22 +- .../soc/realtek/8195a/fwlib/hal_spi_flash.h | 36 +- .../soc/realtek/8195a/fwlib/ram_lib/startup.c | 7 +- .../8195a/fwlib/rtl8195a/rtl8195a_sdio.h | 2 +- .../8195a/fwlib/rtl8195a/rtl8195a_sdio_host.h | 18 +- .../8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c | 2 +- .../8195a/fwlib/rtl8195a/src/rtl8195a_pcm.c | 18 +- .../fwlib/rtl8195a/src/rtl8195a_sdio_host.c | 3821 +++++------ .../8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c | 3 +- .../soc/realtek/8195a/fwlib/src/hal_adc.c | 5 +- .../soc/realtek/8195a/fwlib/src/hal_misc.c | 10 + .../soc/realtek/8195a/fwlib/src/hal_pcm.c | 1 + .../soc/realtek/8195a/fwlib/src/hal_pinmux.c | 3 +- .../realtek/8195a/fwlib/src/hal_sdio_host.c | 20 +- .../8195a/fwlib/src/hal_sdr_controller.c | 4 +- .../8195a/fwlib/src/hal_soc_ps_monitor.c | 4 +- .../8195a/fwlib/src/hal_spi_flash_ram.c | 2158 +++--- .../bsp/lib/common/GCC/lib_platform_new.a | Bin 161388 -> 161388 bytes .../bsp/lib/common/GCC/lib_platform_new.bat | 1 + .../common/GCC/rlx8195A-symbol-v03-img2.ld | 2 +- build/bin/ota.bin | Bin 307248 -> 307264 bytes build/bin/ota_mp.bin | Bin 305500 -> 305604 bytes build/bin/ram_2.bin | Bin 307228 -> 305584 bytes build/bin/ram_2.ns.bin | Bin 307244 -> 305600 bytes build/bin/ram_2.p.bin | Bin 307244 -> 305600 bytes build/bin/ram_all.bin | Bin 352300 -> 352316 bytes build/bin/ram_all_mp.bin | Bin 350552 -> 350656 bytes paths.mk | 2 +- 58 files changed, 6620 insertions(+), 6810 deletions(-) diff --git a/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_ethernet.c b/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_ethernet.c index db9c9f0..e17d0de 100644 --- a/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_ethernet.c +++ b/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_ethernet.c @@ -76,10 +76,38 @@ void fATE1(void *arg) printf("[ATE0]Usage to set wlan as default interface: ATE1=0\n"); } } +/* +void fATTT(void *arg){ +#if 1 + ConfigDebugErr = -1; + ConfigDebugInfo = ~(_DBG_GDMA_ | _DBG_SPI_FLASH_); + ConfigDebugWarn = -1; + CfgSysDebugErr = -1; + CfgSysDebugInfo = -1; + CfgSysDebugWarn = -1; +#endif + printf("ethernet_init = %d\n", ethernet_mii_init()); // ethernet_init()); // HalMiiInit()); //HalMiiInitRtl8195a(); +} + +void fATT1(void *arg){ +#if 1 + ConfigDebugErr = -1; + ConfigDebugInfo = ~(_DBG_GDMA_ | _DBG_SPI_FLASH_); + ConfigDebugWarn = -1; + CfgSysDebugErr = -1; + CfgSysDebugInfo = -1; + CfgSysDebugWarn = -1; +#endif + printf("ethernet_write = %d\n", ethernet_write((const char *)0x1000, 1024)); + printf("ethernet_send = %d\n", ethernet_send()); +} +*/ log_item_t at_ethernet_items[ ] = { - {"ATE0", fATE0,}, - {"ATE1", fATE1,} + {"ATE0", fATE0}, +// {"ATTT", fATTT}, // Test ! +// {"ATT1", fATT1}, // Test ! + {"ATE1", fATE1} }; void at_ethernet_init(void) @@ -89,4 +117,4 @@ void at_ethernet_init(void) log_module_init(at_ethernet_init); -#endif \ No newline at end of file +#endif diff --git a/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_sys.c b/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_sys.c index 87cb974..5779791 100644 --- a/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_sys.c +++ b/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_sys.c @@ -8,6 +8,7 @@ #include "hal_adc.h" #include "gpio_api.h" // mbed #include "sys_api.h" +#include "rtl8195a.h" #include "flash_api.h" #include "rtl_lib.h" #include "build_info.h" @@ -50,117 +51,88 @@ struct _dev_id2name { u8 *name; }; -struct _dev_id2name dev_id2name[] = { -{UART0, "UART0"}, {UART1, "UART1"}, {UART2, "UART2"}, -{SPI0, "SPI0"}, {SPI1, "SPI1"}, {SPI2, "SPI2"}, -{SPI0_MCS, "SPI0_MCS"}, -{I2C0, "I2C0"}, {I2C1, "I2C1"}, {I2C2, "I2C2"}, {I2C3, "I2C3"}, -{I2S0, "I2S0"}, {I2S1, "I2S1"}, -{PCM0, "PCM0"}, {PCM1, "PCM1"}, -{ADC0, "ADC0"}, -{DAC0, "DAC0"}, {DAC1, "DAC1"}, -{SDIOD, "SDIOD"}, {SDIOH, "SDIOH"}, -{USBOTG, "USBOTG"}, -{MII, "MII"}, -{WL_LED, "WL_LED"}, -{WL_ANT0,"WL_ANT0"}, {WL_ANT1,"WL_ANT1"}, -{WL_BTCOEX,"WL_BTCOEX"}, {WL_BTCMD,"WL_BTCMD"}, -{NFC,"NFC"}, -{PWM0,"PWM0"}, {PWM1,"PWM1"}, {PWM2,"PWM2"}, {PWM3,"PWM3"}, -{ETE0,"ETE0"}, {ETE1,"ETE1"}, {ETE2,"ETE2"}, {ETE3,"ETE3"}, -{EGTIM,"EGTIM"}, -{SPI_FLASH,"SPI_FLASH"}, -{SDR,"SDR"}, -{JTAG,"JTAG"}, -{TRACE,"TRACE"}, -{LOG_UART,"LOG_UART"}, {LOG_UART_IR,"LOG_UART_IR"}, -{SIC,"SIC"}, -{EEPROM,"EEPROM"}, -{DEBUG,"DEBUG"}, -{255,""}}; +struct _dev_id2name dev_id2name[] = { { UART0, "UART0" }, { UART1, "UART1" }, { +UART2, "UART2" }, { SPI0, "SPI0" }, { SPI1, "SPI1" }, { SPI2, "SPI2" }, { +SPI0_MCS, "SPI0_MCS" }, { I2C0, "I2C0" }, { I2C1, "I2C1" }, { I2C2, "I2C2" }, { +I2C3, "I2C3" }, { I2S0, "I2S0" }, { I2S1, "I2S1" }, { PCM0, "PCM0" }, { +PCM1, "PCM1" }, { ADC0, "ADC0" }, { DAC0, "DAC0" }, { DAC1, "DAC1" }, { +SDIOD, "SDIOD" }, { SDIOH, "SDIOH" }, { USBOTG, "USBOTG" }, { MII, "MII" }, { +WL_LED, "WL_LED" }, { WL_ANT0, "WL_ANT0" }, { WL_ANT1, "WL_ANT1" }, { +WL_BTCOEX, "WL_BTCOEX" }, { WL_BTCMD, "WL_BTCMD" }, { NFC, "NFC" }, { +PWM0, "PWM0" }, { PWM1, "PWM1" }, { PWM2, "PWM2" }, { PWM3, "PWM3" }, { +ETE0, "ETE0" }, { ETE1, "ETE1" }, { ETE2, "ETE2" }, { ETE3, "ETE3" }, { +EGTIM, "EGTIM" }, { SPI_FLASH, "SPI_FLASH" }, { SDR, "SDR" }, { JTAG, "JTAG" }, + { TRACE, "TRACE" }, { LOG_UART, "LOG_UART" }, { + LOG_UART_IR, "LOG_UART_IR" }, { SIC, "SIC" }, { EEPROM, "EEPROM" }, { + DEBUG, "DEBUG" }, { 255, "" } }; -#include "rtl8195a.h" -#include "rtl8195a_sdio_host.h" -#include "hal_sdio_host.h" -#include "sd.h" -#include "sdio_host.h" -extern HAL_SDIO_HOST_ADAPTER SdioHostAdapter; -extern void SdioHostSdBusPwrCtrl(uint8_t En); -extern int SdioHostSdClkCtrl(void *Data, int En, int Divisor); - -void fATXX(void *arg) -{ +void fATSI(void *arg) { uint32 x = 0; int i; u8 * s; - for(i = 0; dev_id2name[i].id != 255; i++ ) { + for (i = 0; dev_id2name[i].id != 255; i++) { ReadHWPwrState(dev_id2name[i].id, &x); s = "?"; - switch(x) { - case HWACT: - s = "ACT"; - break; - case HWCG: - s = "CG"; - break; - case HWINACT: - s = "WACT"; - break; - case UNDEF: - s = "UNDEF"; - break; - case ALLMET: - s = "ALLMET"; - break; + switch (x) { + case HWACT: + s = "ACT"; + break; + case HWCG: + s = "CG"; + break; + case HWINACT: + s = "WACT"; + break; + case UNDEF: + s = "UNDEF"; + break; + case ALLMET: + s = "ALLMET"; + break; } printf("Dev %s, state = %s\n", dev_id2name[i].name, s); } - for(i = 0; i < _PORT_MAX; i++) printf("Port %c state: 0x%04x\n", i+'A', GPIOState[i]); + for (i = 0; i < _PORT_MAX; i++) + printf("Port %c state: 0x%04x\n", i + 'A', GPIOState[i]); } -#ifdef CONFIG_SDR_EN -extern s32 MemTest(u32 LoopCnt); -void fATSM(void *arg) -{ - MemTest(1); -} -#endif + //-------- AT SYS commands --------------------------------------------------------------- -void fATSD(void *arg) -{ +void fATSD(void *arg) { int argc = 0; - char *argv[MAX_ARGC] = {0}; - SD_DeInit(); - AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSD]: _AT_SYSTEM_DUMP_REGISTER_"); - if(!arg){ + char *argv[MAX_ARGC] = { 0 }; + AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, + "[ATSD]: _AT_SYSTEM_DUMP_REGISTER_"); + if (!arg) { AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSD] Usage: ATSD=REGISTER"); return; } argc = parse_param(arg, argv); - if(argc == 2 || argc == 3) - CmdDumpWord(argc-1, (unsigned char**)(argv+1)); + if (argc == 2 || argc == 3) + CmdDumpWord(argc - 1, (unsigned char**) (argv + 1)); } #if ATCMD_VER == ATVER_2 -void fATXD(void *arg) -{ +void fATXD(void *arg) { int argc = 0; - char *argv[MAX_ARGC] = {0}; - - AT_DBG_MSG(AT_FLAG_EDIT, AT_DBG_ALWAYS, "[ATXD]: _AT_SYSTEM_WRITE_REGISTER_"); - if(!arg){ - AT_DBG_MSG(AT_FLAG_EDIT, AT_DBG_ALWAYS, "[ATXD] Usage: ATXD=REGISTER,VALUE"); + char *argv[MAX_ARGC] = { 0 }; + + AT_DBG_MSG(AT_FLAG_EDIT, AT_DBG_ALWAYS, + "[ATXD]: _AT_SYSTEM_WRITE_REGISTER_"); + if (!arg) { + AT_DBG_MSG(AT_FLAG_EDIT, AT_DBG_ALWAYS, + "[ATXD] Usage: ATXD=REGISTER,VALUE"); return; } argc = parse_param(arg, argv); - if(argc == 3) - CmdWriteWord(argc-1, (unsigned char**)(argv+1)); + if (argc == 3) + CmdWriteWord(argc - 1, (unsigned char**) (argv + 1)); } #endif #if ATCMD_VER == ATVER_1 void fATSC(void *arg) -{ +{ AT_DBG_MSG(AT_FLAG_OTA, AT_DBG_ALWAYS, "[ATSC]: _AT_SYSTEM_CLEAR_OTA_SIGNATURE_"); sys_clear_ota_signature(); } @@ -175,11 +147,10 @@ void fATSR(void *arg) void fATSY(void *arg) { // use xmodem to update, RX: PA_6, TX: PA_7, baudrate: 1M - OTU_FW_Update(0, 2, 115200); + OTU_FW_Update(0, 2, 115200); } #endif - #if SUPPORT_MP_MODE void fATSA(void *arg) { @@ -187,21 +158,21 @@ void fATSA(void *arg) int argc = 0, channel; char *argv[MAX_ARGC] = {0}, *ptmp; u16 offset, gain; - + AT_DBG_MSG(AT_FLAG_ADC, AT_DBG_ALWAYS, "[ATSA]: _AT_SYSTEM_ADC_TEST_"); - if(!arg){ + if(!arg) { AT_DBG_MSG(AT_FLAG_ADC, AT_DBG_ALWAYS, "[ATSA] Usage: ATSA=CHANNEL(0~2)"); AT_DBG_MSG(AT_FLAG_ADC, AT_DBG_ALWAYS, "[ATSA] Usage: ATSA=k_get"); AT_DBG_MSG(AT_FLAG_ADC, AT_DBG_ALWAYS, "[ATSA] Usage: ATSA=k_set[offet(hex),gain(hex)]"); return; } - + argc = parse_param(arg, argv); - if(strcmp(argv[1], "k_get") == 0){ + if(strcmp(argv[1], "k_get") == 0) { sys_adc_calibration(0, &offset, &gain); // AT_DBG_MSG(AT_FLAG_ADC, AT_DBG_ALWAYS, "[ATSA] offset = 0x%04X, gain = 0x%04X", offset, gain); - }else if(strcmp(argv[1], "k_set") == 0){ - if(argc != 4){ + } else if(strcmp(argv[1], "k_set") == 0) { + if(argc != 4) { AT_DBG_MSG(AT_FLAG_ADC, AT_DBG_ALWAYS, "[ATSA] Usage: ATSA=k_set[offet(hex),gain(hex)]"); return; } @@ -209,47 +180,47 @@ void fATSA(void *arg) gain = strtoul(argv[3], &ptmp, 16); sys_adc_calibration(1, &offset, &gain); // AT_DBG_MSG(AT_FLAG_ADC, AT_DBG_ALWAYS, "[ATSA] offset = 0x%04X, gain = 0x%04X", offset, gain); - }else{ + } else { channel = atoi(argv[1]); - if(channel < 0 || channel > 2){ + if(channel < 0 || channel > 2) { AT_DBG_MSG(AT_FLAG_ADC, AT_DBG_ALWAYS, "[ATSA] Usage: ATSA=CHANNEL(0~2)"); return; } - analogin_t adc; + analogin_t adc; u16 adcdat; - + // Remove debug info massage ConfigDebugInfo = 0; if(channel == 0) - analogin_init(&adc, AD_1); + analogin_init(&adc, AD_1); else if(channel == 1) - analogin_init(&adc, AD_2); + analogin_init(&adc, AD_2); else - analogin_init(&adc, AD_3); + analogin_init(&adc, AD_3); adcdat = analogin_read_u16(&adc)>>4; analogin_deinit(&adc); // Recover debug info massage ConfigDebugInfo = tConfigDebugInfo; - + AT_DBG_MSG(AT_FLAG_ADC, AT_DBG_ALWAYS, "[ATSA] A%d = 0x%04X", channel, adcdat); } } void fATSG(void *arg) { - gpio_t gpio_test; - int argc = 0, val; + gpio_t gpio_test; + int argc = 0, val; char *argv[MAX_ARGC] = {0}, port, num; PinName pin = NC; u32 tConfigDebugInfo = ConfigDebugInfo; - + AT_DBG_MSG(AT_FLAG_GPIO, AT_DBG_ALWAYS, "[ATSG]: _AT_SYSTEM_GPIO_TEST_"); - if(!arg){ + if(!arg) { AT_DBG_MSG(AT_FLAG_GPIO, AT_DBG_ALWAYS, "[ATSG] Usage: ATSG=PINNAME(ex:A0)"); return; - }else{ + } else { argc = parse_param(arg, argv); - if(argc != 2){ + if(argc != 2) { AT_DBG_MSG(AT_FLAG_GPIO, AT_DBG_ALWAYS, "[ATSG] Usage: ATSG=PINNAME(ex:A0)"); return; } @@ -257,81 +228,81 @@ void fATSG(void *arg) port = argv[1][0]; num = argv[1][1]; if(port >= 'a' && port <= 'z') - port -= ('a' - 'A'); + port -= ('a' - 'A'); if(num >= 'a' && num <= 'z') - num -= ('a' - 'A'); - switch(port){ + num -= ('a' - 'A'); + switch(port) { case 'A': - switch(num){ - case '0': pin = PA_0; break; case '1': pin = PA_1; break; case '2': pin = PA_2; break; case '3': pin = PA_3; break; - case '4': pin = PA_4; break; case '5': pin = PA_5; break; case '6': pin = PA_6; break; case '7': pin = PA_7; break; - } - break; + switch(num) { + case '0': pin = PA_0; break; case '1': pin = PA_1; break; case '2': pin = PA_2; break; case '3': pin = PA_3; break; + case '4': pin = PA_4; break; case '5': pin = PA_5; break; case '6': pin = PA_6; break; case '7': pin = PA_7; break; + } + break; case 'B': - switch(num){ - case '0': pin = PB_0; break; case '1': pin = PB_1; break; case '2': pin = PB_2; break; case '3': pin = PB_3; break; - case '4': pin = PB_4; break; case '5': pin = PB_5; break; case '6': pin = PB_6; break; case '7': pin = PB_7; break; - } - break; + switch(num) { + case '0': pin = PB_0; break; case '1': pin = PB_1; break; case '2': pin = PB_2; break; case '3': pin = PB_3; break; + case '4': pin = PB_4; break; case '5': pin = PB_5; break; case '6': pin = PB_6; break; case '7': pin = PB_7; break; + } + break; case 'C': - switch(num){ - case '0': pin = PC_0; break; case '1': pin = PC_1; break; case '2': pin = PC_2; break; case '3': pin = PC_3; break; - case '4': pin = PC_4; break; case '5': pin = PC_5; break; case '6': pin = PC_6; break; case '7': pin = PC_7; break; - case '8': pin = PC_8; break; case '9': pin = PC_9; break; - } - break; + switch(num) { + case '0': pin = PC_0; break; case '1': pin = PC_1; break; case '2': pin = PC_2; break; case '3': pin = PC_3; break; + case '4': pin = PC_4; break; case '5': pin = PC_5; break; case '6': pin = PC_6; break; case '7': pin = PC_7; break; + case '8': pin = PC_8; break; case '9': pin = PC_9; break; + } + break; case 'D': - switch(num){ - case '0': pin = PD_0; break; case '1': pin = PD_1; break; case '2': pin = PD_2; break; case '3': pin = PD_3; break; - case '4': pin = PD_4; break; case '5': pin = PD_5; break; case '6': pin = PD_6; break; case '7': pin = PD_7; break; - case '8': pin = PD_8; break; case '9': pin = PD_9; break; - } - break; + switch(num) { + case '0': pin = PD_0; break; case '1': pin = PD_1; break; case '2': pin = PD_2; break; case '3': pin = PD_3; break; + case '4': pin = PD_4; break; case '5': pin = PD_5; break; case '6': pin = PD_6; break; case '7': pin = PD_7; break; + case '8': pin = PD_8; break; case '9': pin = PD_9; break; + } + break; case 'E': - switch(num){ - case '0': pin = PE_0; break; case '1': pin = PE_1; break; case '2': pin = PE_2; break; case '3': pin = PE_3; break; - case '4': pin = PE_4; break; case '5': pin = PE_5; break; case '6': pin = PE_6; break; case '7': pin = PE_7; break; - case '8': pin = PE_8; break; case '9': pin = PE_9; break; case 'A': pin = PE_A; break; - } - break; + switch(num) { + case '0': pin = PE_0; break; case '1': pin = PE_1; break; case '2': pin = PE_2; break; case '3': pin = PE_3; break; + case '4': pin = PE_4; break; case '5': pin = PE_5; break; case '6': pin = PE_6; break; case '7': pin = PE_7; break; + case '8': pin = PE_8; break; case '9': pin = PE_9; break; case 'A': pin = PE_A; break; + } + break; case 'F': - switch(num){ - case '0': pin = PF_0; break; case '1': pin = PF_1; break; case '2': pin = PF_2; break; case '3': pin = PF_3; break; - case '4': pin = PF_4; break; case '5': pin = PF_5; break; - } - break; + switch(num) { + case '0': pin = PF_0; break; case '1': pin = PF_1; break; case '2': pin = PF_2; break; case '3': pin = PF_3; break; + case '4': pin = PF_4; break; case '5': pin = PF_5; break; + } + break; case 'G': - switch(num){ - case '0': pin = PG_0; break; case '1': pin = PG_1; break; case '2': pin = PG_2; break; case '3': pin = PG_3; break; - case '4': pin = PG_4; break; case '5': pin = PG_5; break; case '6': pin = PG_6; break; case '7': pin = PG_7; break; - } - break; + switch(num) { + case '0': pin = PG_0; break; case '1': pin = PG_1; break; case '2': pin = PG_2; break; case '3': pin = PG_3; break; + case '4': pin = PG_4; break; case '5': pin = PG_5; break; case '6': pin = PG_6; break; case '7': pin = PG_7; break; + } + break; case 'H': - switch(num){ - case '0': pin = PH_0; break; case '1': pin = PH_1; break; case '2': pin = PH_2; break; case '3': pin = PH_3; break; - case '4': pin = PH_4; break; case '5': pin = PH_5; break; case '6': pin = PH_6; break; case '7': pin = PH_7; break; - } - break; + switch(num) { + case '0': pin = PH_0; break; case '1': pin = PH_1; break; case '2': pin = PH_2; break; case '3': pin = PH_3; break; + case '4': pin = PH_4; break; case '5': pin = PH_5; break; case '6': pin = PH_6; break; case '7': pin = PH_7; break; + } + break; case 'I': - switch(num){ - case '0': pin = PI_0; break; case '1': pin = PI_1; break; case '2': pin = PI_2; break; case '3': pin = PI_3; break; - case '4': pin = PI_4; break; case '5': pin = PI_5; break; case '6': pin = PI_6; break; case '7': pin = PI_7; break; - } - break; + switch(num) { + case '0': pin = PI_0; break; case '1': pin = PI_1; break; case '2': pin = PI_2; break; case '3': pin = PI_3; break; + case '4': pin = PI_4; break; case '5': pin = PI_5; break; case '6': pin = PI_6; break; case '7': pin = PI_7; break; + } + break; case 'J': - switch(num){ - case '0': pin = PJ_0; break; case '1': pin = PJ_1; break; case '2': pin = PJ_2; break; case '3': pin = PJ_3; break; - case '4': pin = PJ_4; break; case '5': pin = PJ_5; break; case '6': pin = PJ_6; break; - } - break; + switch(num) { + case '0': pin = PJ_0; break; case '1': pin = PJ_1; break; case '2': pin = PJ_2; break; case '3': pin = PJ_3; break; + case '4': pin = PJ_4; break; case '5': pin = PJ_5; break; case '6': pin = PJ_6; break; + } + break; case 'K': - switch(num){ - case '0': pin = PK_0; break; case '1': pin = PK_1; break; case '2': pin = PK_2; break; case '3': pin = PK_3; break; - case '4': pin = PK_4; break; case '5': pin = PK_5; break; case '6': pin = PK_6; break; - } - break; + switch(num) { + case '0': pin = PK_0; break; case '1': pin = PK_1; break; case '2': pin = PK_2; break; case '3': pin = PK_3; break; + case '4': pin = PK_4; break; case '5': pin = PK_5; break; case '6': pin = PK_6; break; + } + break; } - if(pin == NC){ + if(pin == NC) { AT_DBG_MSG(AT_FLAG_GPIO, AT_DBG_ALWAYS, "[ATSG]: Invalid Pin Name"); return; } @@ -339,18 +310,17 @@ void fATSG(void *arg) ConfigDebugInfo = 0; // Initial input control pin gpio_init(&gpio_test, pin); - gpio_dir(&gpio_test, PIN_INPUT); // Direction: Input - gpio_mode(&gpio_test, PullUp); // Pull-High + gpio_dir(&gpio_test, PIN_INPUT);// Direction: Input + gpio_mode(&gpio_test, PullUp);// Pull-High val = gpio_read(&gpio_test); // Recover debug info massage ConfigDebugInfo = tConfigDebugInfo; AT_DBG_MSG(AT_FLAG_GPIO, AT_DBG_ALWAYS, "[ATSG] %c%c = %d", port, num, val); } - void fATSP(void *arg) { - int argc = 0; + int argc = 0; char *argv[MAX_ARGC] = {0}; unsigned long timeout; // ms @@ -381,11 +351,11 @@ void fATSP(void *arg) } // init gpiob1 test - test_result = 0; - timeout = strtoul(argv[2], NULL, 10); - expected_zerocount = atoi(argv[3]); - zerocount = 0; - val_old = 1; + test_result = 0; + timeout = strtoul(argv[2], NULL, 10); + expected_zerocount = atoi(argv[3]); + zerocount = 0; + val_old = 1; sys_log_uart_off(); @@ -427,23 +397,23 @@ int write_otu_to_system_data(flash_t *flash, uint32_t otu_addr) uint32_t data, i = 0; flash_read_word(flash, FLASH_SYSTEM_DATA_ADDR+0xc, &data); //printf("\n\r[%s] data 0x%x otu_addr 0x%x", __FUNCTION__, data, otu_addr); - AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSB]: data 0x%x otu_addr 0x%x", data, otu_addr); - if(data == ~0x0){ + AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSB]: data 0x%x otu_addr 0x%x", data, otu_addr); + if(data == ~0x0) { flash_write_word(flash, FLASH_SYSTEM_DATA_ADDR+0xc, otu_addr); - }else{ + } else { //erase backup sector flash_erase_sector(flash, FLASH_RESERVED_DATA_BASE); //backup system data to backup sector - for(i = 0; i < 0x1000; i+= 4){ + for(i = 0; i < 0x1000; i+= 4) { flash_read_word(flash, FLASH_SYSTEM_DATA_ADDR + i, &data); if(i == 0xc) - data = otu_addr; + data = otu_addr; flash_write_word(flash, FLASH_RESERVED_DATA_BASE + i,data); } //erase system data flash_erase_sector(flash, FLASH_SYSTEM_DATA_ADDR); //write data back to system data - for(i = 0; i < 0x1000; i+= 4){ + for(i = 0; i < 0x1000; i+= 4) { flash_read_word(flash, FLASH_RESERVED_DATA_BASE + i, &data); flash_write_word(flash, FLASH_SYSTEM_DATA_ADDR + i,data); } @@ -455,13 +425,13 @@ int write_otu_to_system_data(flash_t *flash, uint32_t otu_addr) void fATSB(void *arg) { - int argc = 0; + int argc = 0; char *argv[MAX_ARGC] = {0}; u32 boot_gpio, rb_boot_gpio; u8 gpio_pin; u8 uart_port, uart_index; u8 gpio_pin_bar; - u8 uart_port_bar; + u8 uart_port_bar; flash_t flash; // parameter check @@ -486,20 +456,20 @@ void fATSB(void *arg) } if ( strncmp(argv[1], "P", 1) == 0 && strlen(argv[1]) == 4 - && (strcmp(argv[2], "low_trigger") == 0 || strcmp(argv[2], "high_trigger") == 0) - && strncmp(argv[3], "UART", 4) == 0 && strlen(argv[3]) == 5) { - if((0x41 <= argv[1][1] <= 0x45) && (0x30 <= argv[1][3] <= 0x39) &&(0x30 <= argv[1][4] <= 0x32)){ + && (strcmp(argv[2], "low_trigger") == 0 || strcmp(argv[2], "high_trigger") == 0) + && strncmp(argv[3], "UART", 4) == 0 && strlen(argv[3]) == 5) { + if((0x41 <= argv[1][1] <= 0x45) && (0x30 <= argv[1][3] <= 0x39) &&(0x30 <= argv[1][4] <= 0x32)) { if(strcmp(argv[2], "high_trigger") == 0) - gpio_pin = 1<< 7 | ((argv[1][1]-0x41)<<4) | (argv[1][3] - 0x30); + gpio_pin = 1<< 7 | ((argv[1][1]-0x41)<<4) | (argv[1][3] - 0x30); else - gpio_pin = ((argv[1][1]-0x41)<<4) | (argv[1][3] - 0x30); + gpio_pin = ((argv[1][1]-0x41)<<4) | (argv[1][3] - 0x30); gpio_pin_bar = ~gpio_pin; uart_index = argv[3][4] - 0x30; if(uart_index == 0) - uart_port = (uart_index<<4)|2; + uart_port = (uart_index<<4)|2; else if(uart_index == 2) - uart_port = (uart_index<<4)|0; - else{ + uart_port = (uart_index<<4)|0; + else { AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSB]: Input UART index error. Please choose UART0 or UART2."); AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSB]: example: ATSB=[PC_2, low_trigger, UART2]"); return; @@ -512,16 +482,16 @@ void fATSB(void *arg) AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSB]:uart_port_bar 0x%x", uart_port_bar); AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSB]:boot_gpio 0x%x", boot_gpio); write_otu_to_system_data(&flash, boot_gpio); - flash_read_word(&flash, FLASH_SYSTEM_DATA_ADDR+0x0c, &rb_boot_gpio); + flash_read_word(&flash, FLASH_SYSTEM_DATA_ADDR+0x0c, &rb_boot_gpio); AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSB]:Read 0x900c 0x%x", rb_boot_gpio); - }else{ + } else { AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSB]: Usage: ATSB=[GPIO_PIN, TRIGER_MODE, UART]"); AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSB]: GPIO_PIN: PB_1, PC_4 ...."); AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSB]: TRIGER_MODE: low_trigger, high_trigger"); AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSB]: UART: UART0, UART2"); AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSB]: example: ATSB=[PC_2, low_trigger, UART2]"); - } - }else{ + } + } else { AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSB]: Usage: ATSB=[GPIO_PIN, TRIGER_MODE, UART]"); AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSB]: GPIO_PIN: PB_1, PC_4 ...."); AT_DBG_MSG(AT_FLAG_DUMP, AT_DBG_ALWAYS, "[ATSB]: TRIGER_MODE: low_trigger, high_trigger"); @@ -551,11 +521,11 @@ void fATSs(void *arg) char *argv[MAX_ARGC] = {0}; AT_PRINTK("[ATS@]: _AT_SYSTEM_DBG_SETTING_"); - if(!arg){ + if(!arg) { AT_PRINTK("[ATS@] Usage: ATS@=[LEVLE,FLAG]"); - }else{ + } else { argc = parse_param(arg, argv); - if(argc == 3){ + if(argc == 3) { char *ptmp; gDbgLevel = atoi(argv[1]); gDbgFlag = strtoul(argv[2], &ptmp, 16); @@ -570,19 +540,19 @@ void fATSc(void *arg) char *argv[MAX_ARGC] = {0}; AT_PRINTK("[ATS!]: _AT_SYSTEM_CONFIG_SETTING_"); - if(!arg){ + if(!arg) { AT_PRINTK("[ATS!] Usage: ATS!=[CONFIG(0,1,2),FLAG]"); - }else{ + } else { argc = parse_param(arg, argv); - if(argc == 3){ + if(argc == 3) { char *ptmp; config = atoi(argv[1]); if(config == 0) - ConfigDebugErr = strtoul(argv[2], &ptmp, 16); + ConfigDebugErr = strtoul(argv[2], &ptmp, 16); if(config == 1) - ConfigDebugInfo = strtoul(argv[2], &ptmp, 16); + ConfigDebugInfo = strtoul(argv[2], &ptmp, 16); if(config == 2) - ConfigDebugWarn = strtoul(argv[2], &ptmp, 16); + ConfigDebugWarn = strtoul(argv[2], &ptmp, 16); } } AT_PRINTK("[ATS!] ConfigDebugErr = 0x%08X", ConfigDebugErr); @@ -615,14 +585,14 @@ void fATSJ(void *arg) int argc = 0, config = 0; char *argv[MAX_ARGC] = {0}; AT_PRINTK("[ATSJ]: _AT_SYSTEM_JTAG_"); - if(!arg){ + if(!arg) { AT_PRINTK("[ATS!] Usage: ATSJ=off"); - }else{ + } else { argc = parse_param(arg, argv); if (strcmp(argv[1], "off" ) == 0) - sys_jtag_off(); + sys_jtag_off(); else - AT_PRINTK("ATSL=%s is not supported!", argv[1]); + AT_PRINTK("ATSL=%s is not supported!", argv[1]); } } @@ -630,7 +600,7 @@ void fATSx(void *arg) { // uint32_t ability = 0; char buf[64]; - + AT_PRINTK("[ATS?]: _AT_SYSTEM_HELP_"); AT_PRINTK("[ATS?]: COMPILE TIME: %s", RTL8195AFW_COMPILE_TIME); // wifi_get_drv_ability(&ability); @@ -654,12 +624,11 @@ extern void print_tcpip_at(void *arg); // uart version 2 echo info extern unsigned char gAT_Echo; - -void fATS0(void *arg){ +void fATS0(void *arg) { at_printf("\r\n[AT] OK"); } -void fATSh(void *arg){ +void fATSh(void *arg) { // print common AT command at_printf("\r\n[ATS?] "); at_printf("\r\nCommon AT Command:"); @@ -677,115 +646,132 @@ void fATSh(void *arg){ at_printf("\r\n[ATS?] OK"); } -void fATSR(void *arg){ +void fATSR(void *arg) { at_printf("\r\n[ATSR] OK"); sys_reset(); } -void fATSV(void *arg){ +void fATSV(void *arg) { char at_buf[32]; char fw_buf[32]; + char cspimode[4] = { 'S', 'D', 'Q', '?' }; + if (fspic_isinit == 0) { + flash_turnon(); + flash_init(&flashobj); + SpicDisableRtl8195A(); + } + printf( + "DeviceID: %02X, Flash Size: %d bytes, FlashID: %02X%02X%02X/%d, SpicMode: %cIO\n", + HalGetChipId(), (u32) (1 << flashobj.SpicInitPara.id[2]), + flashobj.SpicInitPara.id[0], flashobj.SpicInitPara.id[1], + flashobj.SpicInitPara.id[2], flashobj.SpicInitPara.flashtype, + cspimode[flashobj.SpicInitPara.Mode.BitMode]); // get at version strcpy(at_buf, ATCMD_VERSION"."ATCMD_SUBVERSION"."ATCMD_REVISION); // get fw version strcpy(fw_buf, SDK_VERSION); - - at_printf("\r\n[ATSV] OK:%s,%s(%s)",at_buf,fw_buf,RTL8195AFW_COMPILE_TIME); + printf("%s,%s(%s)\n", at_buf, fw_buf, RTL8195AFW_COMPILE_TIME); + at_printf("\r\n[ATSV] OK:%s,%s(%s)", at_buf, fw_buf, + RTL8195AFW_COMPILE_TIME); } #if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1) -void fATSP(void *arg){ +void fATSP(void *arg) { int argc = 0; - char *argv[MAX_ARGC] = {0}; + char *argv[MAX_ARGC] = { 0 }; uint32_t lock_id; uint32_t bitmap; - + if (!arg) { - AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR, "\r\n[ATSP] Usage: ATSP="); + AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR, + "\r\n[ATSP] Usage: ATSP="); at_printf("\r\n[ATSP] ERROR:1"); return; } else { - if((argc = parse_param(arg, argv)) != 2){ - AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR, "\r\n[ATSP] Usage: ATSP="); + if ((argc = parse_param(arg, argv)) != 2) { + AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR, + "\r\n[ATSP] Usage: ATSP="); at_printf("\r\n[ATSP] ERROR:1"); return; } } - switch(argv[1][0]) { - case 'a': // acquire - { - acquire_wakelock(WAKELOCK_OS); - //at_printf("\r\n[ATSP] wakelock:0x%08x", get_wakelock_status()); - break; - } + switch (argv[1][0]) { + case 'a': // acquire + { + acquire_wakelock(WAKELOCK_OS); + //at_printf("\r\n[ATSP] wakelock:0x%08x", get_wakelock_status()); + break; + } - case 'r': // release - { - release_wakelock(WAKELOCK_OS); - //at_printf("\r\n[ATSP] wakelock:0x%08x", get_wakelock_status()); - break; - } + case 'r': // release + { + release_wakelock(WAKELOCK_OS); + //at_printf("\r\n[ATSP] wakelock:0x%08x", get_wakelock_status()); + break; + } - case '?': // get status - break; - default: - AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR, "\r\n[ATSP] Usage: ATSP="); - at_printf("\r\n[ATSP] ERROR:2"); - return; + case '?': // get status + break; + default: + AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR, + "\r\n[ATSP] Usage: ATSP="); + at_printf("\r\n[ATSP] ERROR:2"); + return; } bitmap = get_wakelock_status(); at_printf("\r\n[ATSP] OK:%s", (bitmap&WAKELOCK_OS)?"1":"0"); } #endif -void fATSE(void *arg){ +void fATSE(void *arg) { int argc = 0; int echo = 0, mask = gDbgFlag, dbg_lv = gDbgLevel; - char *argv[MAX_ARGC] = {0}; + char *argv[MAX_ARGC] = { 0 }; int err_no = 0; - - AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ALWAYS, "[ATSE]: _AT_SYSTEM_ECHO_DBG_SETTING"); - if(!arg){ - AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR, "[ATSE] Usage: ATSE=,,"); + + AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ALWAYS, + "[ATSE]: _AT_SYSTEM_ECHO_DBG_SETTING"); + if (!arg) { + AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR, + "[ATSE] Usage: ATSE=,,"); err_no = 1; goto exit; } argc = parse_param(arg, argv); - if(argc < 2 || argc > 4){ + if (argc < 2 || argc > 4) { err_no = 2; goto exit; } #if CONFIG_EXAMPLE_UART_ATCMD - if(argv[1] != NULL){ + if (argv[1] != NULL) { echo = atoi(argv[1]); - if(echo>1 || echo <0){ + if (echo > 1 || echo < 0) { err_no = 3; goto exit; } - gAT_Echo = echo?1:0; + gAT_Echo = echo ? 1 : 0; } #endif - if((argc > 2) && (argv[2] != NULL)){ + if ((argc > 2) && (argv[2] != NULL)) { mask = strtoul(argv[2], NULL, 0); at_set_debug_mask(mask); } - - if((argc == 4) && (argv[3] != NULL)){ + + if ((argc == 4) && (argv[3] != NULL)) { dbg_lv = strtoul(argv[3], NULL, 0); at_set_debug_level(dbg_lv); } -exit: - if(err_no) + exit: if (err_no) at_printf("\r\n[ATSE] ERROR:%d", err_no); else at_printf("\r\n[ATSE] OK"); @@ -796,7 +782,7 @@ exit: #include "wifi_structures.h" #include "wifi_constants.h" extern rtw_wifi_setting_t wifi_setting; -void fATSW(void *arg){ +void fATSW(void *arg) { int argc = 0; char *argv[MAX_ARGC] = {0}; @@ -805,29 +791,29 @@ void fATSW(void *arg){ at_printf("\r\n[ATSW] ERROR:1"); return; } else { - if((argc = parse_param(arg, argv)) != 2){ + if((argc = parse_param(arg, argv)) != 2) { AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR, "\r\n[ATSW] Usage: ATSW="); at_printf("\r\n[ATSW] ERROR:1"); return; } } - if(argv[1][0]!='c'&&argv[1][0]!='s'){ + if(argv[1][0]!='c'&&argv[1][0]!='s') { AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR, "\r\n[ATSW] Usage: ATSW="); at_printf("\r\n[ATSW] ERROR:2"); return; } - + // make sure AP mode LoadWifiConfig(); - if(wifi_setting.mode != RTW_MODE_AP){ + if(wifi_setting.mode != RTW_MODE_AP) { at_printf("\r\n[ATSW] ERROR:3"); return; } - + switch(argv[1][0]) { case 'c': // create webserver - { + { start_web_server(); break; } @@ -844,7 +830,7 @@ void fATSW(void *arg){ extern int EraseApinfo(); //extern int Erase_Fastconnect_data(); -void fATSY(void *arg){ +void fATSY(void *arg) { #if CONFIG_EXAMPLE_WLAN_FAST_CONNECT // Erase_Fastconnect_data(); #endif @@ -854,7 +840,7 @@ void fATSY(void *arg){ #endif #if CONFIG_EXAMPLE_UART_ATCMD -extern int reset_uart_atcmd_setting(void); + extern int reset_uart_atcmd_setting(void); reset_uart_atcmd_setting(); #endif @@ -869,44 +855,46 @@ extern int reset_uart_atcmd_setting(void); } #if CONFIG_OTA_UPDATE -extern int wifi_is_connected_to_ap( void ); -void fATSO(void *arg){ +extern int wifi_is_connected_to_ap(void); +void fATSO(void *arg) { int argc = 0; - char *argv[MAX_ARGC] = {0}; - - if(!arg){ - AT_DBG_MSG(AT_FLAG_OTA, AT_DBG_ERROR, "\r\n[ATSO] Usage: ATSO=,"); + char *argv[MAX_ARGC] = { 0 }; + + if (!arg) { + AT_DBG_MSG(AT_FLAG_OTA, AT_DBG_ERROR, + "\r\n[ATSO] Usage: ATSO=,"); at_printf("\r\n[ATSO] ERROR:1"); return; } argv[0] = "update"; - if((argc = parse_param(arg, argv)) != 3){ - AT_DBG_MSG(AT_FLAG_OTA, AT_DBG_ERROR, "\r\n[ATSO] Usage: ATSO=,"); + if ((argc = parse_param(arg, argv)) != 3) { + AT_DBG_MSG(AT_FLAG_OTA, AT_DBG_ERROR, + "\r\n[ATSO] Usage: ATSO=,"); at_printf("\r\n[ATSO] ERROR:1"); return; } // check wifi connect first - if(wifi_is_connected_to_ap()==0){ + if (wifi_is_connected_to_ap() == 0) { cmd_update(argc, argv); at_printf("\r\n[ATSO] OK"); - - }else{ + + } else { at_printf("\r\n[ATSO] ERROR:3"); } } -void fATSC(void *arg){ +void fATSC(void *arg) { int argc = 0; - char *argv[MAX_ARGC] = {0}; + char *argv[MAX_ARGC] = { 0 }; int cmd = 0; - - if(!arg){ + + if (!arg) { AT_DBG_MSG(AT_FLAG_OTA, AT_DBG_ERROR, "\r\n[ATSC] Usage: ATSC=<0/1>"); at_printf("\r\n[ATSC] ERROR:1"); return; } - if((argc = parse_param(arg, argv)) != 2){ + if ((argc = parse_param(arg, argv)) != 2) { AT_DBG_MSG(AT_FLAG_OTA, AT_DBG_ERROR, "\r\n[ATSC] Usage: ATSC=<0/1>"); at_printf("\r\n[ATSC] ERROR:1"); return; @@ -914,17 +902,16 @@ void fATSC(void *arg){ cmd = atoi(argv[1]); - if((cmd!=0)&&(cmd!=1)){ + if ((cmd != 0) && (cmd != 1)) { at_printf("\r\n[ATSC] ERROR:2"); return; } - + at_printf("\r\n[ATSC] OK"); - if(cmd == 1){ - cmd_ota_image(1); - } - else{ + if (cmd == 1) { + cmd_ota_image(1); + } else { cmd_ota_image(0); } // reboot @@ -935,9 +922,9 @@ void fATSC(void *arg){ #if CONFIG_EXAMPLE_UART_ATCMD extern const u32 log_uart_support_rate[]; -void fATSU(void *arg){ +void fATSU(void *arg) { int argc = 0; - char *argv[MAX_ARGC] = {0}; + char *argv[MAX_ARGC] = { 0 }; u32 baud = 0; u8 databits = 0; u8 stopbits = 0; @@ -946,18 +933,18 @@ void fATSU(void *arg){ u8 configmode = 0; int i; UART_LOG_CONF uartconf; - - if(!arg){ - AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR, - "[ATSU] Usage: ATSU=,,,,,"); + + if (!arg) { + AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR, + "[ATSU] Usage: ATSU=,,,,,"); at_printf("\r\n[ATSU] ERROR:1"); return; } - if((argc = parse_param(arg, argv)) != 7){ - AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR, - "[ATSU] Usage: ATSU=,,,,,"); - at_printf("\r\n[ATSU] ERROR:1"); - return; + if ((argc = parse_param(arg, argv)) != 7) { + AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ERROR, + "[ATSU] Usage: ATSU=,,,,,"); + at_printf("\r\n[ATSU] ERROR:1"); + return; } baud = atoi(argv[1]); @@ -966,114 +953,110 @@ void fATSU(void *arg){ parity = atoi(argv[4]); flowcontrol = atoi(argv[5]); configmode = atoi(argv[6]); -/* - // Check Baud rate - for (i=0; log_uart_support_rate[i]!=0xFFFFFF; i++) { - if (log_uart_support_rate[i] == baud) { - break; - } - } - - if (log_uart_support_rate[i]== 0xFFFFFF) { - at_printf("\r\n[ATSU] ERROR:2"); - return; - } -*/ - if(((databits < 5) || (databits > 8))||\ - ((stopbits < 1) || (stopbits > 2))||\ - ((parity < 0) || (parity > 2))||\ - ((flowcontrol < 0) || (flowcontrol > 1))||\ - ((configmode < 0) || (configmode > 3))\ - ){ + /* + // Check Baud rate + for (i=0; log_uart_support_rate[i]!=0xFFFFFF; i++) { + if (log_uart_support_rate[i] == baud) { + break; + } + } + + if (log_uart_support_rate[i]== 0xFFFFFF) { + at_printf("\r\n[ATSU] ERROR:2"); + return; + } + */ + if (((databits < 5) || (databits > 8)) || ((stopbits < 1) || (stopbits > 2)) + || ((parity < 0) || (parity > 2)) + || ((flowcontrol < 0) || (flowcontrol > 1)) + || ((configmode < 0) || (configmode > 3))\ +) { at_printf("\r\n[ATSU] ERROR:2"); return; } - - memset((void*)&uartconf, 0, sizeof(UART_LOG_CONF)); + + memset((void*) &uartconf, 0, sizeof(UART_LOG_CONF)); uartconf.BaudRate = baud; uartconf.DataBits = databits; uartconf.StopBits = stopbits; uartconf.Parity = parity; uartconf.FlowControl = flowcontrol; - AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ALWAYS, - "AT_UART_CONF: %d,%d,%d,%d,%d", uartconf.BaudRate, uartconf.DataBits,uartconf.StopBits,uartconf.Parity,uartconf.FlowControl); - switch(configmode){ - case 0: // set current configuration, won't save - uart_atcmd_reinit(&uartconf); - break; - case 1: // set current configuration, and save - write_uart_atcmd_setting_to_system_data(&uartconf); - uart_atcmd_reinit(&uartconf); - break; - case 2: // set configuration, reboot to take effect - write_uart_atcmd_setting_to_system_data(&uartconf); - break; + AT_DBG_MSG(AT_FLAG_COMMON, AT_DBG_ALWAYS, "AT_UART_CONF: %d,%d,%d,%d,%d", + uartconf.BaudRate, uartconf.DataBits, uartconf.StopBits, + uartconf.Parity, uartconf.FlowControl); + switch (configmode) { + case 0: // set current configuration, won't save + uart_atcmd_reinit(&uartconf); + break; + case 1: // set current configuration, and save + write_uart_atcmd_setting_to_system_data(&uartconf); + uart_atcmd_reinit(&uartconf); + break; + case 2: // set configuration, reboot to take effect + write_uart_atcmd_setting_to_system_data(&uartconf); + break; } - + at_printf("\r\n[ATSU] OK"); } #endif //#if CONFIG_EXAMPLE_UART_ATCMD #endif //#if CONFIG_WLAN -void fATSG(void *arg) -{ +void fATSG(void *arg) { gpio_t gpio_ctrl; int argc = 0, val, error_no = 0; - char *argv[MAX_ARGC] = {0}, port, num; + char *argv[MAX_ARGC] = { 0 }, port, num; PinName pin = NC; AT_DBG_MSG(AT_FLAG_GPIO, AT_DBG_ALWAYS, "[ATSG]: _AT_SYSTEM_GPIO_CTRL_"); - if(!arg){ - AT_DBG_MSG(AT_FLAG_GPIO, AT_DBG_ERROR, - "[ATSG] Usage: ATSG=,,,,"); + if (!arg) { + AT_DBG_MSG(AT_FLAG_GPIO, AT_DBG_ERROR, + "[ATSG] Usage: ATSG=,,,,"); error_no = 1; goto exit; } - if((argc = parse_param(arg, argv)) < 3){ - AT_DBG_MSG(AT_FLAG_GPIO, AT_DBG_ERROR, - "[ATSG] Usage: ATSG=,,,,"); + if ((argc = parse_param(arg, argv)) < 3) { + AT_DBG_MSG(AT_FLAG_GPIO, AT_DBG_ERROR, + "[ATSG] Usage: ATSG=,,,,"); error_no = 2; goto exit; - } + } port = argv[2][1]; num = strtoul(&argv[2][3], NULL, 0); port -= 'A'; pin = (port << 4 | num); AT_DBG_MSG(AT_FLAG_GPIO, AT_DBG_ALWAYS, "PORT: %s[%d]", argv[2], pin); - - if(gpio_set(pin) == 0xff) - { - AT_DBG_MSG(AT_FLAG_GPIO, AT_DBG_ERROR, "[ATSG]: Invalid Pin Name [%d]", pin); + + if (gpio_set(pin) == 0xff) { + AT_DBG_MSG(AT_FLAG_GPIO, AT_DBG_ERROR, "[ATSG]: Invalid Pin Name [%d]", + pin); error_no = 3; goto exit; } gpio_init(&gpio_ctrl, pin); - if(argv[4]){ + if (argv[4]) { int dir = atoi(argv[4]); AT_DBG_MSG(AT_FLAG_GPIO, AT_DBG_ALWAYS, "DIR: %s", argv[4]); gpio_dir(&gpio_ctrl, dir); } - if(argv[5]){ + if (argv[5]) { int pull = atoi(argv[5]); AT_DBG_MSG(AT_FLAG_GPIO, AT_DBG_ALWAYS, "PULL: %s", argv[5]); gpio_mode(&gpio_ctrl, pull); } - if(argv[1][0] == 'R'){ + if (argv[1][0] == 'R') { val = gpio_read(&gpio_ctrl); - } - else{ + } else { val = atoi(argv[3]); gpio_write(&gpio_ctrl, val); } - -exit: - if(error_no){ + + exit: if (error_no) { at_printf("\r\n[ATSG] ERROR:%d", error_no); - } - else{ + } else { at_printf("\r\n[ATSG] OK:%d", val); } } @@ -1087,78 +1070,83 @@ exit: * bit2: LOGUART * bit3: SDIO */ -void fATSL(void *arg) -{ +void fATSL(void *arg) { int argc = 0; - char *argv[MAX_ARGC] = {0}; + char *argv[MAX_ARGC] = { 0 }; int err_no = 0; uint32_t lock_id; AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, "[ATSL]: _AT_SYS_WAKELOCK_TEST_"); if (!arg) { - AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, "[ATSL] Usage ATSL=[a/r/?][bitmask]"); + AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, + "[ATSL] Usage ATSL=[a/r/?][bitmask]"); err_no = 1; goto exit; } else { argc = parse_param(arg, argv); if (argc < 2) { - AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, "[ATSL] Usage ATSL=[a/r/?][bitmask]"); + AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, + "[ATSL] Usage ATSL=[a/r/?][bitmask]"); err_no = 2; goto exit; } } - switch(argv[1][0]) { - case 'a': // acquire - { - if (argc == 3) { - lock_id = strtoul(argv[2], NULL, 16); - acquire_wakelock(lock_id); - } - AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, "[ATSL] wakelock:0x%08x", get_wakelock_status()); - break; + switch (argv[1][0]) { + case 'a': // acquire + { + if (argc == 3) { + lock_id = strtoul(argv[2], NULL, 16); + acquire_wakelock(lock_id); } - - case 'r': // release - { - if (argc == 3) { - lock_id = strtoul(argv[2], NULL, 16); - release_wakelock(lock_id); - } - AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, "[ATSL] wakelock:0x%08x", get_wakelock_status()); - break; - } - - case '?': // get status - AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, "[ATSL] wakelock:0x%08x", get_wakelock_status()); -#if (configGENERATE_RUN_TIME_STATS == 1) - char *cBuffer = pvPortMalloc(512); - if(cBuffer != NULL) { - get_wakelock_hold_stats((char *)cBuffer); - AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, "%s", cBuffer); - } - vPortFree(cBuffer); -#endif - break; - -#if (configGENERATE_RUN_TIME_STATS == 1) - case 'c': // clean wakelock info (for recalculate wakelock hold time) - AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, "[ATSL] clean wakelock stat"); - clean_wakelock_stat(); - break; -#endif - default: - AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, "[ATSL] Usage ATSL=[a/r/?][bitmask]"); - err_no = 3; - break; + AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, "[ATSL] wakelock:0x%08x", + get_wakelock_status()); + break; } -exit: + + case 'r': // release + { + if (argc == 3) { + lock_id = strtoul(argv[2], NULL, 16); + release_wakelock(lock_id); + } + AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, "[ATSL] wakelock:0x%08x", + get_wakelock_status()); + break; + } + + case '?': // get status + AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, "[ATSL] wakelock:0x%08x", + get_wakelock_status()); +#if (configGENERATE_RUN_TIME_STATS == 1) + char *cBuffer = pvPortMalloc(512); + if (cBuffer != NULL) { + get_wakelock_hold_stats((char *) cBuffer); + AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, "%s", cBuffer); + } + vPortFree(cBuffer); +#endif + break; + +#if (configGENERATE_RUN_TIME_STATS == 1) + case 'c': // clean wakelock info (for recalculate wakelock hold time) + AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, "[ATSL] clean wakelock stat"); + clean_wakelock_stat(); + break; +#endif + default: + AT_DBG_MSG(AT_FLAG_OS, AT_DBG_ALWAYS, + "[ATSL] Usage ATSL=[a/r/?][bitmask]"); + err_no = 3; + break; + } + exit: #if ATCMD_VER == ATVER_2 - if(err_no) + if (err_no) at_printf("\r\n[ATSL] ERROR:%d", err_no); else - at_printf("\r\n[ATSL] OK:0x%08x",get_wakelock_status()); + at_printf("\r\n[ATSL] OK:0x%08x", get_wakelock_status()); #endif return; } @@ -1167,117 +1155,253 @@ exit: void fATSX(void *arg) { // use xmodem to update, RX: PA_6, TX: PA_7, baudrate: 1M - OTU_FW_Update(0, 2, 115200); + OTU_FW_Update(0, 2, 115200); at_printf("\r\n[ATSX] OK"); } #endif #endif +void print_hex_dump(uint8_t *buf, int len, unsigned char k) { + uint32_t ss[2]; + ss[0] = 0x78323025; // "%02x" + ss[1] = k; // ","...'\0' + uint8_t * ptr = buf; + while (len--) { + if (len == 0) + ss[1] = 0; + printf((uint8_t *) &ss[0], *ptr++); + } +} -void fATST(void *arg){ +//ATFD - Flash Data Dump +void fATFD(void *arg) { + int argc = 0; + char *argv[MAX_ARGC] = { 0 }; +#if DEBUG_AT_USER_LEVEL > 3 + printf("ATFD: _AT_FLASH_DUMP_\n"); +#endif + if (!arg) { + printf("Usage: ATFD=faddr(HEX),[size]\n"); + } else { + argc = parse_param(arg, argv); + if (argc >= 1) { + int addr; + sscanf(argv[1], "%x", &addr); + int size = 0; + if (argc > 2) + size = atoi(argv[2]); + if (size <= 0 || size > 16384) + size = 1; + u32 symbs_line = 32; + u32 rdsize = 8 * symbs_line; + uint8_t *flash_data = (uint8_t *) malloc(rdsize); + while (size) { + if (size < rdsize) + rdsize = size; + else + rdsize = 8 * symbs_line; + flash_stream_read(&flashobj, addr, rdsize, flash_data); + uint8_t *ptr = flash_data; + while (ptr < flash_data + rdsize) { + if (symbs_line > size) + symbs_line = size; + printf("%08X ", addr); + print_hex_dump(ptr, symbs_line, ' '); + printf("\r\n"); + addr += symbs_line; + ptr += symbs_line; + size -= symbs_line; + if (size == 0) + break; + } + } + free(flash_data); + } + } +} + +void fATFO(void *arg) { + int argc = 0; + char *argv[MAX_ARGC] = { 0 }; +#if DEBUG_AT_USER_LEVEL > 3 + printf("ATFO: _AT_FLASH_OTP_DUMP_\n"); +#endif + if (!arg) { + printf("Usage: ATFO=faddr(HEX),[size]\n"); + } else { + argc = parse_param(arg, argv); + if (argc >= 1) { + int addr; + sscanf(argv[1], "%x", &addr); + int size = 0; + if (argc > 2) + size = atoi(argv[2]); + if (size <= 0 || size > 16384) + size = 1; + u32 symbs_line = 32; + u32 rdsize = 8 * symbs_line; + uint8_t *flash_data = (uint8_t *) malloc(rdsize); + while (size) { + if (size < rdsize) + rdsize = size; + else + rdsize = 8 * symbs_line; + flash_otp_read(&flashobj, addr, rdsize, flash_data); + uint8_t *ptr = flash_data; + while (ptr < flash_data + rdsize) { + if (symbs_line > size) + symbs_line = size; + printf("%08X ", addr); + print_hex_dump(ptr, symbs_line, ' '); + printf("\r\n"); + addr += symbs_line; + ptr += symbs_line; + size -= symbs_line; + if (size == 0) + break; + } + } + free(flash_data); + } + } +} + +void fATST(void *arg) { extern void dump_mem_block_list(void); // heap_5.c - //DBG_INFO_MSG_ON(_DBG_TCM_HEAP_); // On Debug TCM MEM +//DBG_INFO_MSG_ON(_DBG_TCM_HEAP_); // On Debug TCM MEM #if DEBUG_AT_USER_LEVEL > 1 - printf("ATST: Mem info:\n"); + printf("ATST: Mem info:\n"); #endif // vPortFree(pvPortMalloc(4)); // Init RAM heap - printf("\nCLK CPU\t\t%d Hz\nRAM heap\t%d bytes\nTCM heap\t%d bytes\n", - HalGetCpuClk(), xPortGetFreeHeapSize(), tcm_heap_freeSpace()); - dump_mem_block_list(); - u32 saved = ConfigDebugInfo; - DBG_INFO_MSG_ON(_DBG_TCM_HEAP_); // On Debug TCM MEM - tcm_heap_dump(); - ConfigDebugInfo = saved; - printf("\n"); + printf("\nCLK CPU\t\t%d Hz\nRAM heap\t%d bytes\nTCM heap\t%d bytes\n", + HalGetCpuClk(), xPortGetFreeHeapSize(), tcm_heap_freeSpace()); + dump_mem_block_list(); + u32 saved = ConfigDebugInfo; + DBG_INFO_MSG_ON(_DBG_TCM_HEAP_); // On Debug TCM MEM + tcm_heap_dump(); + ConfigDebugInfo = saved; + printf("\n"); #if (configGENERATE_RUN_TIME_STATS == 1) - char *cBuffer = pvPortMalloc(512); - if(cBuffer != NULL) { - vTaskGetRunTimeStats((char *)cBuffer); - printf("%s", cBuffer); - } - vPortFree(cBuffer); + char *cBuffer = pvPortMalloc(512); + if (cBuffer != NULL) { + vTaskGetRunTimeStats((char *) cBuffer); + printf("%s", cBuffer); + } + vPortFree(cBuffer); #endif } +#if 0 +#include "wlan_lib.h" +#include "hal_com_reg.h" +// struct net_device *rltk_wlan_info; +void fATXT(void *arg) +{ +#if DEBUG_AT_USER_LEVEL > 3 + printf("ATWT: _AT_CFG_DUMP_\n"); +#endif + int size = 512; + int addr = 0; + uint8_t *blk_data = (uint8_t *)malloc(size); + memset(blk_data, 0xff, size); + if(blk_data) { + uint8_t * ptr = blk_data; + Hal_ReadEFuse(*(_adapter **)(rltk_wlan_info->priv), 0, 0, 512, ptr, 1); + //rtw_flash_map_update(*(_adapter **)(rltk_wlan_info->priv), 512); + u32 symbs_line = 32; + while(addr < size) { + if(symbs_line > size) symbs_line = size; + printf("%08X ", addr); + print_hex_dump(ptr, symbs_line, ' '); + printf("\r\n"); + addr += symbs_line; + ptr += symbs_line; + size -= symbs_line; + if(size == 0) break; + } + free(blk_data); + } +} +#endif log_item_t at_sys_items[] = { #if (ATCMD_VER == ATVER_1) - {"ATSD", fATSD,}, // Dump register - {"ATSE", fATSE,}, // Edit register - {"ATSC", fATSC,}, // Clear OTA signature - {"ATSR", fATSR,}, // Recover OTA signature + { "ATSD", fATSD}, // Dump register + { "ATSE", fATSE}, // Edit register + { "ATSC", fATSC}, // Clear OTA signature + { "ATSR", fATSR}, // Recover OTA signature #if CONFIG_UART_XMODEM - {"ATSY", fATSY,}, // uart ymodem upgrade + { "ATSY", fATSY}, // uart ymodem upgrade #endif #if SUPPORT_MP_MODE - {"ATSA", fATSA,}, // MP ADC test - {"ATSG", fATSG,}, // MP GPIO test - {"ATSP", fATSP,}, // MP Power related test - {"ATSB", fATSB,}, // OTU PIN setup + { "ATSA", fATSA}, // MP ADC test + { "ATSG", fATSG}, // MP GPIO test + { "ATSP", fATSP}, // MP Power related test + { "ATSB", fATSB}, // OTU PIN setup #endif #if (configGENERATE_RUN_TIME_STATS == 1) - {"ATSS", fATSS,}, // Show CPU stats + { "ATSS", fATSS}, // Show CPU stats #endif #if SUPPORT_CP_TEST - {"ATSM", fATSM,}, // Apple CP test + { "ATSM", fATSM}, // Apple CP test #endif - {"ATSJ", fATSJ,}, //trun off JTAG - {"ATS@", fATSs,}, // Debug message setting - {"ATS!", fATSc,}, // Debug config setting - {"ATS#", fATSt,}, // test command - {"ATS?", fATSx,}, // Help + { "ATSJ", fATSJ}, //trun off JTAG + { "ATS@", fATSs}, // Debug message setting + { "ATS!", fATSc}, // Debug config setting + { "ATS#", fATSt}, // test command + { "ATS?", fATSx}, // Help #elif ATCMD_VER == ATVER_2 //#if ATCMD_VER == ATVER_1 - {"AT", fATS0,}, // test AT command ready - {"ATS?", fATSh,}, // list all AT command - {"ATSR", fATSR,}, // system restart - {"ATSV", fATSV,}, // show version info - {"ATSP", fATSP,}, // power saving mode - {"ATSE", fATSE,}, // enable and disable echo + { "AT", fATS0 }, // test AT command ready + { "ATS?", fATSh }, // list all AT command + { "ATSR", fATSR }, // system restart + { "ATSV", fATSV }, // show version info + { "ATSP", fATSP }, // power saving mode + { "ATSE", fATSE }, // enable and disable echo #if CONFIG_WLAN #if CONFIG_WEBSERVER - {"ATSW", fATSW,}, // start webserver + { "ATSW", fATSW}, // start webserver #endif - {"ATSY", fATSY,}, // factory reset + { "ATSY", fATSY }, // factory reset #if CONFIG_OTA_UPDATE - {"ATSO", fATSO,}, // ota upgrate - {"ATSC", fATSC,}, // chose the activited image + { "ATSO", fATSO }, // ota upgrate + { "ATSC", fATSC }, // chose the activited image #endif #if CONFIG_EXAMPLE_UART_ATCMD - {"ATSU", fATSU,}, // AT uart configuration + { "ATSU", fATSU }, // AT uart configuration #endif #endif - {"ATSG", fATSG,}, // GPIO control + { "ATSG", fATSG }, // GPIO control #if CONFIG_UART_XMODEM - {"ATSX", fATSX,}, // uart xmodem upgrade + { "ATSX", fATSX}, // uart xmodem upgrade #endif - {"ATSD", fATSD,}, // Dump register - {"ATXD", fATXD,}, // Write register + { "ATSD", fATSD }, // Dump register + { "ATXD", fATXD }, // Write register #endif // end of #if ATCMD_VER == ATVER_1 // Following commands exist in two versions #if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1) - {"ATSL", fATSL,}, // wakelock test -#endif - {"ATST", fATST}, // add pvvx: mem info - {"ATXX", fATXX}, // test -#ifdef CONFIG_SDR_EN - {"ATSM", fATSM} // memtest + { "ATSL", fATSL }, // wakelock test #endif + { "ATFD", fATFD }, // Flash Data Damp + { "ATFO", fATFO }, // Flash OTP Damp + { "ATST", fATST }, // add pvvx: mem info +// { "ATXT", fATXT }, // add pvvx: cfg_wifi + { "ATSI", fATSI } // Dev/Ports Info }; #if ATCMD_VER == ATVER_2 -void print_system_at(void *arg){ +void print_system_at(void *arg) { int index; int cmd_len = 0; - cmd_len = sizeof(at_sys_items)/sizeof(at_sys_items[0]); - for(index = 0; index < cmd_len; index++) + cmd_len = sizeof(at_sys_items) / sizeof(at_sys_items[0]); + for (index = 0; index < cmd_len; index++) at_printf("\r\n%s", at_sys_items[index].log_cmd); } #endif -void at_sys_init(void) -{ - log_service_add_table(at_sys_items, sizeof(at_sys_items)/sizeof(at_sys_items[0])); +void at_sys_init(void) { + log_service_add_table(at_sys_items, + sizeof(at_sys_items) / sizeof(at_sys_items[0])); } #if SUPPORT_LOG_SERVICE diff --git a/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_wifi.c b/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_wifi.c index 442ac31..331cc6b 100644 --- a/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_wifi.c +++ b/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_wifi.c @@ -2593,57 +2593,6 @@ void print_wlan_help(void *arg){ } #endif // end of #if ATCMD_VER == ATVER_1 - -#endif // end of #if CONFIG_WLAN - -#if CONFIG_LWIP_LAYER -#if ATCMD_VER == ATVER_1 -void fATWL(void *arg){ -#if CONFIG_SSL_CLIENT - int argc; - char *argv[MAX_ARGC] = {0}; - printf("[ATWL]: _AT_WLAN_SSL_CLIENT_\n"); - argv[0] = "ssl_client"; - if(!arg){ - printf("ATWL=SSL_SERVER_HOST\n"); - return; - } - if((argc = parse_param(arg, argv)) > 1){ - if(argc != 2) { - printf("ATWL=SSL_SERVER_HOST\n"); - return; - } - - cmd_ssl_client(argc, argv); - } -#else - printf("Please set CONFIG_SSL_CLIENT 1 in platform_opts.h to enable ATWL command\n"); -#endif -} - -void fATWI(void *arg){ - int argc; - char *argv[MAX_ARGC] = {0}; - - printf("[ATWI]: _AT_WLAN_PING_TEST_\n"); - - if(!arg){ - printf("[ATWI] Usage: ATWI=[host],[options]\n"); - printf(" -t Ping the specified host until stopped\n"); - printf(" -n # Number of echo requests to send (default 4 times)\n"); - printf(" -l # Send buffer size (default 32 bytes)\n"); - printf(" Example:\n"); - printf(" ATWI=192.168.1.2,-n,100,-l,5000\n"); - return; - } - - argv[0] = "ping"; - - if((argc = parse_param(arg, argv)) > 1){ - cmd_ping(argc, argv); - } -} - void fATWT(void *arg) { #if CONFIG_BSD_TCP @@ -2719,6 +2668,57 @@ void fATWU(void *arg) printf("Please set CONFIG_BSD_TCP 1 in platform_opts.h to enable ATWU command\n"); #endif } + +#endif // end of #if CONFIG_WLAN + +#if CONFIG_LWIP_LAYER +#if ATCMD_VER == ATVER_1 +void fATWL(void *arg){ +#if CONFIG_SSL_CLIENT + int argc; + char *argv[MAX_ARGC] = {0}; + printf("[ATWL]: _AT_WLAN_SSL_CLIENT_\n"); + argv[0] = "ssl_client"; + if(!arg){ + printf("ATWL=SSL_SERVER_HOST\n"); + return; + } + if((argc = parse_param(arg, argv)) > 1){ + if(argc != 2) { + printf("ATWL=SSL_SERVER_HOST\n"); + return; + } + + cmd_ssl_client(argc, argv); + } +#else + printf("Please set CONFIG_SSL_CLIENT 1 in platform_opts.h to enable ATWL command\n"); +#endif +} + +void fATWI(void *arg){ + int argc; + char *argv[MAX_ARGC] = {0}; + + printf("[ATWI]: _AT_WLAN_PING_TEST_\n"); + + if(!arg){ + printf("[ATWI] Usage: ATWI=[host],[options]\n"); + printf(" -t Ping the specified host until stopped\n"); + printf(" -n # Number of echo requests to send (default 4 times)\n"); + printf(" -l # Send buffer size (default 32 bytes)\n"); + printf(" Example:\n"); + printf(" ATWI=192.168.1.2,-n,100,-l,5000\n"); + return; + } + + argv[0] = "ping"; + + if((argc = parse_param(arg, argv)) > 1){ + cmd_ping(argc, argv); + } +} + #elif ATCMD_VER == ATVER_2 // uart at command //move to atcmd_lwip.c #endif @@ -2813,6 +2813,10 @@ log_item_t at_wifi_items[ ] = { {"ATWL", fATWL,}, //p2p listen {"ATWP", fATWP,}, //p2p peers #endif +#if CONFIG_LWIP_LAYER + {"ATWT", fATWT,}, + {"ATWU", fATWU,}, +#endif #ifdef CONFIG_PROMISC {"ATWM", fATWM,}, // WIFI promisc Usage: ATWM=DURATION_SECONDS[with_len] #endif diff --git a/RTL00_SDKV35a/component/common/api/wifi/wifi_conf.c b/RTL00_SDKV35a/component/common/api/wifi/wifi_conf.c index 4dfe407..b49c7f8 100644 --- a/RTL00_SDKV35a/component/common/api/wifi/wifi_conf.c +++ b/RTL00_SDKV35a/component/common/api/wifi/wifi_conf.c @@ -23,6 +23,7 @@ extern int inic_start(void); extern int inic_stop(void); #endif +#include "wlan_lib.h" #if CONFIG_DEBUG_LOG > 0 #undef printf diff --git a/RTL00_SDKV35a/component/common/api/wifi/wifi_conf.h b/RTL00_SDKV35a/component/common/api/wifi/wifi_conf.h index bcd3786..8f2ebcb 100644 --- a/RTL00_SDKV35a/component/common/api/wifi/wifi_conf.h +++ b/RTL00_SDKV35a/component/common/api/wifi/wifi_conf.h @@ -683,7 +683,7 @@ enum CUSTOM_IE_TYPE{ typedef struct _cus_ie{ __u8 *ie; __u8 type; -}cus_ie, *p_cus_ie; +} cus_ie, *p_cus_ie; #endif /* _CUS_IE_ */ int wifi_add_custom_ie(void *cus_ie, int ie_num); diff --git a/RTL00_SDKV35a/component/common/api/wifi/wifi_ind.c b/RTL00_SDKV35a/component/common/api/wifi/wifi_ind.c index febde2c..a9f603f 100644 --- a/RTL00_SDKV35a/component/common/api/wifi/wifi_ind.c +++ b/RTL00_SDKV35a/component/common/api/wifi/wifi_ind.c @@ -86,6 +86,10 @@ static rtw_result_t rtw_indicate_event_handle(int event_cmd, char *buf, int buf_ return RTW_SUCCESS; } #endif +#if 0 // test beacon +#include "gpio_api.h" // mbed +extern gpio_t gpio_led; +#endif void wifi_indication( WIFI_EVENT_INDICATE event, char *buf, int buf_len, int flags) { @@ -194,6 +198,10 @@ void wifi_indication( WIFI_EVENT_INDICATE event, char *buf, int buf_len, int fla #if(WIFI_INDICATE_MSG>1) printf("%s(): WIFI_EVENT_BEACON_AFTER_DHCP\n", __func__); #endif +#if 0 // test beacon + gpio_write(&gpio_led, 1); + gpio_write(&gpio_led, 0); +#endif break; } diff --git a/RTL00_SDKV35a/component/common/drivers/ethernet_mii/ethernet_mii.c b/RTL00_SDKV35a/component/common/drivers/ethernet_mii/ethernet_mii.c index b81d027..94704ab 100644 --- a/RTL00_SDKV35a/component/common/drivers/ethernet_mii/ethernet_mii.c +++ b/RTL00_SDKV35a/component/common/drivers/ethernet_mii/ethernet_mii.c @@ -160,11 +160,11 @@ void ethernet_demo(void* param){ printf("TRX pre setting done\n"); ethernet_init(); - +#if 0 DBG_INFO_MSG_OFF(_DBG_MII_); DBG_WARN_MSG_OFF(_DBG_MII_); DBG_ERR_MSG_ON(_DBG_MII_); - +#endif /*get mac*/ ethernet_address(mac); memcpy((void*)xnetif[NET_IF_NUM - 1].hwaddr,(void*)mac, 6); @@ -172,7 +172,7 @@ void ethernet_demo(void* param){ rtw_init_sema(&mii_rx_sema,0); rtw_mutex_init(&mii_tx_mutex); - if(xTaskCreate(mii_rx_thread, ((const char*)"mii_rx_thread"), 1024, NULL, tskIDLE_PRIORITY+5, NULL) != pdPASS) + if(xTaskCreate(mii_rx_thread, ((const char*)"mii_rx_th"), 1024, NULL, tskIDLE_PRIORITY+5, NULL) != pdPASS) DBG_8195A("\n\r%s xTaskCreate(mii_rx_thread) failed", __FUNCTION__); DBG_8195A("\nEthernet_mii Init done, interface %d",NET_IF_NUM - 1); @@ -191,11 +191,11 @@ void ethernet_mii_init() ethernet_if_default = 1; rtw_init_sema(&mii_linkup_sema,0); - if( xTaskCreate((TaskFunction_t)dhcp_start_mii, "DHCP_START_MII", 1024, NULL, 2, NULL) != pdPASS) { + if( xTaskCreate((TaskFunction_t)dhcp_start_mii, "DHCP_MII", 1024, NULL, 2, NULL) != pdPASS) { DBG_8195A("Cannot create demo task\n\r"); } - if( xTaskCreate((TaskFunction_t)ethernet_demo, "ETHERNET DEMO", 1024, NULL, 2, NULL) != pdPASS) { + if( xTaskCreate((TaskFunction_t)ethernet_demo, "ETH_DEMO", 1024, NULL, 2, NULL) != pdPASS) { DBG_8195A("Cannot create demo task\n\r"); } diff --git a/RTL00_SDKV35a/component/common/drivers/sdio/realtek/sdio_host/src/sd.c b/RTL00_SDKV35a/component/common/drivers/sdio/realtek/sdio_host/src/sd.c index 9959b62..dd81f93 100644 --- a/RTL00_SDKV35a/component/common/drivers/sdio/realtek/sdio_host/src/sd.c +++ b/RTL00_SDKV35a/component/common/drivers/sdio/realtek/sdio_host/src/sd.c @@ -5,6 +5,7 @@ */ #include "rtl8195a.h" +#ifdef CONFIG_SDIO_HOST_EN #include "sd.h" #include "sdio_host.h" @@ -117,7 +118,7 @@ SD_RESULT SD_ReadBlocks(u32 sector, u8 *data, u32 count) { u32 end_sector = count + sector; while (sector < end_sector) { rd_count = sdio_read_blocks(sector, buf, 1); - rtl_printf("rd_counts = %d\n", rd_count); +// rtl_printf("rd_counts = %d\n", rd_count); if (rd_count == 0 && RtlDownSemaWithTimeout(&sdWSema, 1000) != 1) { DBG_SDIO_ERR("SD_ReadBlocks timeout\n"); return SD_ERROR; @@ -172,3 +173,4 @@ SD_RESULT SD_WriteBlocks(u32 sector, const u8 *data, u32 count) { return SD_ERROR; } +#endif // CONFIG_SDIO_HOST_EN diff --git a/RTL00_SDKV35a/component/common/drivers/sdio/realtek/sdio_host/src/sdio_host.c b/RTL00_SDKV35a/component/common/drivers/sdio/realtek/sdio_host/src/sdio_host.c index d6c243c..1d4c8a9 100644 --- a/RTL00_SDKV35a/component/common/drivers/sdio/realtek/sdio_host/src/sdio_host.c +++ b/RTL00_SDKV35a/component/common/drivers/sdio/realtek/sdio_host/src/sdio_host.c @@ -5,6 +5,7 @@ */ #include "rtl8195a.h" +#ifdef CONFIG_SDIO_HOST_EN #include "sd.h" #include "sdio_host.h" #include "hal_sdio_host.h" @@ -45,13 +46,17 @@ void xfer_err_callback(void *param) { } void card_insert_callback(void *param) { +#if CONFIG_DEBUG_LOG > 1 rtl_printf("SD card insert\n"); +#endif if (card_insert_irq_handler) card_insert_irq_handler((void *) card_insert_irq_data); } void card_remove_callback(void *param) { +#if CONFIG_DEBUG_LOG > 1 rtl_printf("SD card removed\n"); +#endif sdio_status = SDIO_SD_NONE; if (card_remove_irq_handler) card_remove_irq_handler((void *) card_remove_irq_data); @@ -208,7 +213,7 @@ s8 sdio_write_blocks(uint32_t sector, const uint8_t *buffer, uint32_t count) { HAL_Status result = HalSdioHostOp.HalSdioHostWriteBlocksDma( &SdioHostAdapter, (unsigned long long) sector * SIZE_BLOCK_ADMA, count); - if (result) { + if (result != HAL_OK) { DBG_SDIO_ERR("write fail(0x%02x)\n", result); return -1; } @@ -230,7 +235,7 @@ s8 sdio_sd_init(void) { } sdio_status = SDIO_SD_OK; if (HalSdioHostOp.HalSdioHostChangeSdClock(&SdioHostAdapter, - SD_CLK_41_6MHZ)) + SD_CLK_41_6MHZ) != HAL_OK) DBG_SDIO_INFO("SD card does not support high speed.\n"); } return 0; @@ -239,7 +244,7 @@ s8 sdio_sd_init(void) { //----- void sdio_sd_deinit() { if (sdio_status > SDIO_SD_NONE) - sdio_status = 1; + sdio_status = SDIO_INIT_OK; sdio_deinit_host(); // add pvvx (fix SD_DeInit()) } @@ -400,3 +405,4 @@ s8 sdio_sd_hook_xfer_err_cb(sdio_sd_irq_handler CallbackFun, void *param) { return 0; } +#endif // CONFIG_SDIO_HOST_EN diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_constants.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_constants.h index 1d29733..77bedab 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_constants.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_constants.h @@ -326,7 +326,7 @@ typedef enum { RTW_COUNTRY_MAX -}rtw_country_code_t; +} rtw_country_code_t; typedef enum { RTW_ADAPTIVITY_DISABLE = 0, @@ -341,14 +341,15 @@ typedef enum { RTW_MODE_AP, RTW_MODE_STA_AP, RTW_MODE_PROMISC, - RTW_MODE_P2P -}rtw_mode_t; + RTW_MODE_P2P, + RTW_MODE_MAX +} rtw_mode_t; typedef enum { RTW_SCAN_FULL = 0, RTW_SCAN_SOCIAL, RTW_SCAN_ONE -}rtw_scan_mode_t; +} rtw_scan_mode_t; typedef enum { RTW_LINK_DISCONNECTED = 0, @@ -421,7 +422,7 @@ typedef enum{ RTW_WRONG_PASSWORD = 3 , RTW_DHCP_FAIL = 4, RTW_UNKNOWN, -}rtw_connect_error_flag_t; +} rtw_connect_error_flag_t; typedef enum { RTW_TX_PWR_PERCENTAGE_100 = 0, /* 100%, default target output power. */ @@ -429,7 +430,7 @@ typedef enum { RTW_TX_PWR_PERCENTAGE_50 = 2, /* 50% */ RTW_TX_PWR_PERCENTAGE_25 = 3, /* 25% */ RTW_TX_PWR_PERCENTAGE_12_5 = 4, /* 12.5% */ -}rtw_tx_pwr_percentage_t; +} rtw_tx_pwr_percentage_t; typedef enum _WIFI_EVENT_INDICATE{ WIFI_EVENT_CONNECT = 0, diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_lib.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_lib.h index aefa7e1..3a3b51c 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_lib.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_lib.h @@ -1,74 +1,69 @@ /* - wifi_lib.h - RTL871x pvvx -*/ + wifi_lib.h + RTL871x pvvx + */ #ifndef _WLAN_LIB_H #define _WLAN_LIB_H #include "osdep_service.h" #include "freertos/wrapper.h" -#define __int8 char -#define __int16 short -#define __int32 int -#define __int64 long long +#define _atr_aligned2_ __attribute__((aligned(2))) +#define _atr_aligned4_ __attribute__((aligned(4))) +#define _atr_aligned8_ __attribute__((aligned(4))) + +#define sint8_t char +#define sint16_t short +#define sint32_t int +#define sint64_t long long /* -struct _ADAPTER; -struct dvobj_priv; -union recv_frame; -struct sk_buff; -struct sk_buff_head; -struct sta_info; -struct _cus_ie; -struct fifo_more_data; -struct hw_xmit; -struct tx_buf_desc; -struct recv_buf_stat; -struct _wpa_sta_info; -struct xmit_frame; -struct xmit_buf; -struct submit_ctx; -struct net_device; -struct iwreq; -struct co_data_priv; -*/ -//typedef int __int32_t; -//typedef char __int8_t; -//typedef __int8_t int8_t; -//typedef unsigned int __uint32_t; -//typedef __int32_t int32_t; + struct _ADAPTER; + struct dvobj_priv; + union recv_frame; + struct sk_buff; + struct sk_buff_head; + struct sta_info; + struct _cus_ie; + struct fifo_more_data; + struct hw_xmit; + struct tx_buf_desc; + struct recv_buf_stat; + struct _wpa_sta_info; + struct xmit_frame; + struct xmit_buf; + struct submit_ctx; + struct net_device; + struct iwreq; + struct co_data_priv; + */ +//typedef int sint32_t_t; +//typedef char sint8_t_t; +//typedef sint8_t_t int8_t; +//typedef uint32_t __uint32_t; +//typedef sint32_t_t int32_t; //typedef __uint32_t uint32_t; //typedef uint32_t dma_addr_t; // basic_types.h - -typedef unsigned __int8 __uint8_t; -typedef unsigned __int16 __uint16_t; -typedef unsigned __int64 __uint64_t; -typedef __uint8_t uint8_t; -typedef __uint16_t uint16_t; -typedef __uint64_t uint64_t; +//typedef uint8_t uint8_t; +//typedef uint16_t uint16_t; +//typedef unsigned sint64_t uint64_t; typedef int sint; -typedef unsigned __int8 BOOL; -typedef unsigned __int8 bool; -typedef unsigned __int8 BOOLEAN; -typedef unsigned __int16 __u16; -typedef int __s32; -typedef unsigned __int8 __u8; -typedef __int16 __s16; -typedef unsigned int __u32; +typedef uint8_t BOOL; +typedef uint8_t bool; +typedef uint8_t BOOLEAN; -typedef unsigned __int8 u1Byte; -typedef unsigned __int16 u2Byte; -typedef unsigned __int16 *pu2Byte; -typedef unsigned int u4Byte; -typedef unsigned __int64 u8Byte; -typedef char s1Byte; -typedef __int16 s2Byte; -typedef int s4Byte; -typedef char *ps1Byte; -typedef unsigned __int8 *pu1Byte; -typedef unsigned int *pu4Byte; +typedef uint8_t u1Byte; +typedef uint16_t u2Byte; +typedef uint32_t u4Byte; +typedef uint64_t u8Byte; +typedef sint8_t s1Byte; +typedef sint16_t s2Byte; +typedef sint32_t s4Byte; +typedef sint8_t *ps1Byte; +typedef uint8_t *pu1Byte; +typedef uint16_t *pu2Byte; +typedef uint32_t *pu4Byte; -typedef unsigned int sizetype; +typedef uint32_t sizetype; typedef struct _ADAPTER _adapter; typedef void *_lock; typedef struct list_head _list; @@ -78,2935 +73,2819 @@ typedef void *_mutex; typedef int (*init_done_ptr)(void); -enum _EFUSE_DEF_TYPE // : __int32 +enum _EFUSE_DEF_TYPE // : sint32_t { - TYPE_EFUSE_MAX_SECTION = 0x0, - TYPE_EFUSE_REAL_CONTENT_LEN = 0x1, - TYPE_AVAILABLE_EFUSE_BYTES_BANK = 0x2, - TYPE_AVAILABLE_EFUSE_BYTES_TOTAL = 0x3, - TYPE_EFUSE_MAP_LEN = 0x4, - TYPE_EFUSE_PROTECT_BYTES_BANK = 0x5, - TYPE_EFUSE_CONTENT_LEN_BANK = 0x6, + TYPE_EFUSE_MAX_SECTION = 0x0, + TYPE_EFUSE_REAL_CONTENT_LEN = 0x1, + TYPE_AVAILABLE_EFUSE_BYTES_BANK = 0x2, + TYPE_AVAILABLE_EFUSE_BYTES_TOTAL = 0x3, + TYPE_EFUSE_MAP_LEN = 0x4, + TYPE_EFUSE_PROTECT_BYTES_BANK = 0x5, + TYPE_EFUSE_CONTENT_LEN_BANK = 0x6, }; -enum _IFACE_TYPE //: __int32 +enum _IFACE_TYPE //: sint32_t { - IFACE_PORT0 = 0x0, - IFACE_PORT1 = 0x1, - MAX_IFACE_PORT = 0x2, + IFACE_PORT0 = 0x0, IFACE_PORT1 = 0x1, MAX_IFACE_PORT = 0x2, }; -enum _FW_ERR0_STATUS_ //: __int32 +enum _FW_ERR0_STATUS_ //: sint32_t { - FES0_H2C_CMDID = 0x1, - FES0_H2C_PTR = 0x2, - FES0_BB_RW = 0x4, - FES0_TXPKT_TXPAUSE = 0x8, - FES0_TSF_STABLE = 0x10, - FES0_TXSM_STABLE = 0x20, - FES0_RPWM_STABLE = 0x40, - FES0_C2H_TIMEOUT_ERR = 0x80, + FES0_H2C_CMDID = 0x1, + FES0_H2C_PTR = 0x2, + FES0_BB_RW = 0x4, + FES0_TXPKT_TXPAUSE = 0x8, + FES0_TSF_STABLE = 0x10, + FES0_TXSM_STABLE = 0x20, + FES0_RPWM_STABLE = 0x40, + FES0_C2H_TIMEOUT_ERR = 0x80, }; -enum _TRPC_ //: __int32 +enum _TRPC_ //: sint32_t { - TPRC_ISSUENULLDATA_1 = 0x26, - TPRC_ISSUENULLDATA_2 = 0x27, - TPRC_PSS2TS3 = 0x2B, - TPRC_PSS0TS1 = 0x2C, - TPRC_PSS2TS4 = 0x2D, - TPRC_PSS2TS5 = 0x2E, - TPRC_PSS0TS6 = 0x2F, + TPRC_ISSUENULLDATA_1 = 0x26, + TPRC_ISSUENULLDATA_2 = 0x27, + TPRC_PSS2TS3 = 0x2B, + TPRC_PSS0TS1 = 0x2C, + TPRC_PSS2TS4 = 0x2D, + TPRC_PSS2TS5 = 0x2E, + TPRC_PSS0TS6 = 0x2F, }; -enum _PS_MODE_SETTING_SELECTION_ // : __int32 +enum _PS_MODE_SETTING_SELECTION_ // : sint32_t { - MODE_SETTING_ACTIVE = 0x0, - MODE_SETTING_LEGACY = 0x1, - MODE_SETTING_WMMPS = 0x2, - MODE_SETTING_TDMA = 0x3, + MODE_SETTING_ACTIVE = 0x0, + MODE_SETTING_LEGACY = 0x1, + MODE_SETTING_WMMPS = 0x2, + MODE_SETTING_TDMA = 0x3, }; -enum _RxListenBeaconMode_ // : __int32 +enum _RxListenBeaconMode_ // : sint32_t { - RLBM_MIN = 0x0, - RLBM_MAX = 0x1, - RLBM_SELF_DEFINED = 0x2, + RLBM_MIN = 0x0, RLBM_MAX = 0x1, RLBM_SELF_DEFINED = 0x2, }; -enum _SMART_PS_MODE_FOR_LEGACY_ // : __int32 +enum _SMART_PS_MODE_FOR_LEGACY_ // : sint32_t { - SMART_PS_MODE_LEGACY_PWR1 = 0x0, - SMART_PS_MODE_TX_PWR0 = 0x1, - SMART_PS_MODE_TRX_PWR0 = 0x2, + SMART_PS_MODE_LEGACY_PWR1 = 0x0, + SMART_PS_MODE_TX_PWR0 = 0x1, + SMART_PS_MODE_TRX_PWR0 = 0x2, }; -enum $BFA04BDFA6C0C275C890D1E658AFCEEF // : __int32 +enum $BFA04BDFA6C0C275C890D1E658AFCEEF // : sint32_t { - ROM_E_RTW_MSGP_PWR_INDEX_1 = 0x0, - ROM_E_RTW_MSGP_PWR_INDEX_2 = 0x1, - ROM_E_RTW_MSGP_RX_INFO_1 = 0x2, - ROM_E_RTW_MSGP_RX_INFO_2 = 0x3, - ROM_E_RTW_MSGP_RX_INFO_3 = 0x4, - ROM_E_RTW_MSGP_RX_INFO_4 = 0x5, - ROM_E_RTW_MSGP_TX_RATE_1 = 0x6, - ROM_E_RTW_MSGP_TX_RATE_2 = 0x7, - ROM_E_RTW_MSGP_DM_RA_1 = 0x8, - ROM_E_RTW_MSGP_DM_RA_2 = 0x9, - ROM_E_RTW_MSGP_DM_RA_3 = 0xA, - ROM_E_RTW_MSGP_DM_RA_4 = 0xB, - ROM_E_RTW_MSGP_DM_DIG_1 = 0xC, - ROM_E_RTW_MSGP_PWR_TRACKING_1 = 0xD, - ROM_E_RTW_MSGP_PWR_TRACKING_2 = 0xE, - ROM_E_RTW_MSGP_PWR_TRACKING_3 = 0xF, - ROM_E_RTW_MSGP_PWR_TRACKING_4 = 0x10, - ROM_E_RTW_MSGP_PWR_TRACKING_5 = 0x11, - ROM_E_RTW_MSGP_PWR_TRACKING_6 = 0x12, - ROM_E_RTW_MSGP_PWR_TRACKING_7 = 0x13, - ROM_E_RTW_MSGP_RF_IQK_1 = 0x14, - ROM_E_RTW_MSGP_RF_IQK_2 = 0x15, - ROM_E_RTW_MSGP_RF_IQK_3 = 0x16, - ROM_E_RTW_MSGP_RF_IQK_4 = 0x17, - ROM_E_RTW_MSGP_RF_IQK_5 = 0x18, - ROM_E_RTW_MSGP_DM_ADAPTIVITY_1 = 0x19, - ROM_E_RTW_MSGP_DM_ADAPTIVITY_2 = 0x1A, - ROM_E_RTW_MSGP_DM_ADAPTIVITY_3 = 0x1B, - ROM_E_RTW_MSGP_DM_ANT_DIV_1 = 0x1C, - ROM_E_RTW_MSGP_DM_ANT_DIV_2 = 0x1D, - ROM_E_RTW_MSGP_DM_ANT_DIV_3 = 0x1E, - ROM_E_RTW_MSGP_DM_ANT_DIV_4 = 0x1F, - ROM_E_RTW_MSGP_DM_ANT_DIV_5 = 0x20, - ROM_E_RTW_MSGP_MAC_REG_DUMP_1 = 0x21, - ROM_E_RTW_MSGP_BB_REG_DUMP_1 = 0x22, - ROM_E_RTW_MSGP_RF_REG_DUMP_1 = 0x23, - ROM_E_RTW_MSGP_RF_REG_DUMP_2 = 0x24, - ROM_E_RTW_MSGP_REG_DUMP_1 = 0x25, - ROM_E_RTW_MSGP_REG_DUMP_2 = 0x26, - ROM_E_RTW_MSGP_REG_DUMP_3 = 0x27, - ROM_E_RTW_MSGP_READ_REG_1 = 0x28, - ROM_E_RTW_MSGP_READ_REG_2 = 0x29, - ROM_E_RTW_MSGP_READ_REG_3 = 0x2A, - ROM_E_RTW_MSGP_WRITE_REG_1 = 0x2B, - ROM_E_RTW_MSGP_WRITE_REG_2 = 0x2C, - ROM_E_RTW_MSGP_WRITE_REG_3 = 0x2D, - ROM_E_RTW_MSGP_READ_BB_1 = 0x2E, - ROM_E_RTW_MSGP_WRITE_BB_1 = 0x2F, - ROM_E_RTW_MSGP_READ_RF_1 = 0x30, - ROM_E_RTW_MSGP_WRITE_RF_1 = 0x31, - ROM_E_RTW_MSGP_READ_SYS_1 = 0x32, - ROM_E_RTW_MSGP_WRITE_SYS_1 = 0x33, - ROM_E_RTW_MSGP_FIX_CHANNEL_1 = 0x34, - ROM_E_RTW_MSGP_FIX_CHANNEL_2 = 0x35, - ROM_E_RTW_MSGP_PWR_SAVE_MODE_1 = 0x36, - ROM_E_RTW_MSGP_FIX_RATE_1 = 0x37, - ROM_E_RTW_MSGP_GET_ODM_DBG_FLAG_1 = 0x38, - ROM_E_RTW_MSGP_SET_ODM_DBG_FLAG_1 = 0x39, - ROM_E_RTW_MSGP_DUMP_PWR_IDX_1 = 0x3A, - ROM_E_RTW_MSGP_DUMP_INFO_1 = 0x3B, - ROM_E_RTW_MSGP_DUMP_INFO_2 = 0x3C, - ROM_E_RTW_MSGP_DUMP_INFO_3 = 0x3D, - ROM_E_RTW_MSGP_DUMP_INFO_4 = 0x3E, - ROM_E_RTW_MSGP_DUMP_INFO_5 = 0x3F, - ROM_E_RTW_MSGP_DUMP_INFO_6 = 0x40, - ROM_E_RTW_MSGP_DUMP_INFO_7 = 0x41, - ROM_E_RTW_MSGP_DUMP_INFO_8 = 0x42, - ROM_E_RTW_MSGP_DUMP_INFO_9 = 0x43, - ROM_E_RTW_MSGP_DM_FUNC_FLAG_1 = 0x44, - ROM_E_RTW_MSGP_DM_FUNC_FLAG_2 = 0x45, - ROM_E_RTW_MSGP_DM_FUNC_FLAG_3 = 0x46, - ROM_E_RTW_MSGP_DM_FUNC_FLAG_4 = 0x47, - ROM_E_RTW_MSGP_DM_FUNC_FLAG_5 = 0x48, - ROM_E_RTW_MSGP_DM_FUNC_FLAG_6 = 0x49, - ROM_E_RTW_MSGP_DM_FUNC_FLAG_7 = 0x4A, - ROM_E_RTW_MSGP_DM_FUNC_FLAG_8 = 0x4B, - ROM_E_RTW_MSGP_DM_FUNC_FLAG_9 = 0x4C, - ROM_E_RTW_MSGP_RX_MPDU_1 = 0x4D, - ROM_E_RTW_MSGP_AP_TIMEOUT_CHK_1 = 0x4E, - ROM_E_RTW_MSGP_INIT_DRV_SW_1 = 0x4F, - ROM_E_RTW_MSGP_SET_BSSID_1 = 0x50, - ROM_E_RTW_MSGP_SET_SSID_1 = 0x51, - ROM_E_RTW_MSGP_ON_BEACON_1 = 0x52, - ROM_E_RTW_MSGP_ON_AUTH_1 = 0x53, - ROM_E_RTW_MSGP_ON_AUTH_2 = 0x54, - ROM_E_RTW_MSGP_ON_AUTH_CLIENT_1 = 0x55, - ROM_E_RTW_MSGP_ON_ASSOC_REQ_1 = 0x56, - ROM_E_RTW_MSGP_ON_ASSOC_RSP_1 = 0x57, - ROM_E_RTW_MSGP_ON_DE_AUTH_1 = 0x58, - ROM_E_RTW_MSGP_ON_DE_AUTH_2 = 0x59, - ROM_E_RTW_MSGP_ON_DISASSOC_1 = 0x5A, - ROM_E_RTW_MSGP_ON_DISASSOC_2 = 0x5B, - ROM_E_RTW_MSGP_ISSUE_BEACON_1 = 0x5C, - ROM_E_RTW_MSGP_ISSUE_PROBERSP_1 = 0x5D, - ROM_E_RTW_MSGP_ISSUE_PROBEREQ_1 = 0x5E, - ROM_E_RTW_MSGP_ISSUE_AUTH_1 = 0x5F, - ROM_E_RTW_MSGP_ISSUE_ASSOCRSP_1 = 0x60, - ROM_E_RTW_MSGP_ISSUE_ASSOCREQ_1 = 0x61, - ROM_E_RTW_MSGP_ISSUE_NULLDATA_1 = 0x62, - ROM_E_RTW_MSGP_ISSUE_QOS_NULLDATA_1 = 0x63, - ROM_E_RTW_MSGP_ISSUE_DEAUTH_1 = 0x64, - ROM_E_RTW_MSGP_ISSUE_ACTION_BA_1 = 0x65, - ROM_E_RTW_MSGP_ISSUE_BSS_COEXIST_1 = 0x66, - ROM_E_RTW_MSGP_START_CLNT_AUTH_1 = 0x67, - ROM_E_RTW_MSGP_LINKED_STATUS_CHK_1 = 0x68, - ROM_E_RTW_MSGP_SETKEY_HDL_1 = 0x69, - ROM_E_RTW_MSGP_SET_STAKEY_HDL_1 = 0x6A, - ROM_E_RTW_MSGP_SET_STAKEY_HDL_2 = 0x6B, - ROM_E_RTW_MSGP_P2P_BUILD_MGNT_FRAME_1 = 0x6C, - ROM_E_RTW_MSGP_SEND_EAPOL_1 = 0x6D, - ROM_E_RTW_MSGP_SEND_EAPOL_2 = 0x6E, - ROM_E_RTW_MSGP_SEND_EAPOL_3 = 0x6F, - ROM_E_RTW_MSGP_EAPOL_KEY_RECVD_1 = 0x70, - ROM_E_RTW_MSGP_EAPOL_KEY_RECVD_2 = 0x71, - ROM_E_RTW_MSGP_EAPOL_KEY_RECVD_3 = 0x72, - ROM_E_RTW_MSGP_FREE_RECVFRAME_1 = 0x73, - ROM_E_RTW_MSGP_VAR_PORT_SWITCH_1 = 0x74, - ROM_E_RTW_MSGP_VAR_PORT_SWITCH_2 = 0x75, - ROM_E_RTW_MSGP_DOWN_SEMA_1 = 0x76, - ROM_E_RTW_MSGP_MAX = 0x77 + ROM_E_RTW_MSGP_PWR_INDEX_1 = 0x0, + ROM_E_RTW_MSGP_PWR_INDEX_2 = 0x1, + ROM_E_RTW_MSGP_RX_INFO_1 = 0x2, + ROM_E_RTW_MSGP_RX_INFO_2 = 0x3, + ROM_E_RTW_MSGP_RX_INFO_3 = 0x4, + ROM_E_RTW_MSGP_RX_INFO_4 = 0x5, + ROM_E_RTW_MSGP_TX_RATE_1 = 0x6, + ROM_E_RTW_MSGP_TX_RATE_2 = 0x7, + ROM_E_RTW_MSGP_DM_RA_1 = 0x8, + ROM_E_RTW_MSGP_DM_RA_2 = 0x9, + ROM_E_RTW_MSGP_DM_RA_3 = 0xA, + ROM_E_RTW_MSGP_DM_RA_4 = 0xB, + ROM_E_RTW_MSGP_DM_DIG_1 = 0xC, + ROM_E_RTW_MSGP_PWR_TRACKING_1 = 0xD, + ROM_E_RTW_MSGP_PWR_TRACKING_2 = 0xE, + ROM_E_RTW_MSGP_PWR_TRACKING_3 = 0xF, + ROM_E_RTW_MSGP_PWR_TRACKING_4 = 0x10, + ROM_E_RTW_MSGP_PWR_TRACKING_5 = 0x11, + ROM_E_RTW_MSGP_PWR_TRACKING_6 = 0x12, + ROM_E_RTW_MSGP_PWR_TRACKING_7 = 0x13, + ROM_E_RTW_MSGP_RF_IQK_1 = 0x14, + ROM_E_RTW_MSGP_RF_IQK_2 = 0x15, + ROM_E_RTW_MSGP_RF_IQK_3 = 0x16, + ROM_E_RTW_MSGP_RF_IQK_4 = 0x17, + ROM_E_RTW_MSGP_RF_IQK_5 = 0x18, + ROM_E_RTW_MSGP_DM_ADAPTIVITY_1 = 0x19, + ROM_E_RTW_MSGP_DM_ADAPTIVITY_2 = 0x1A, + ROM_E_RTW_MSGP_DM_ADAPTIVITY_3 = 0x1B, + ROM_E_RTW_MSGP_DM_ANT_DIV_1 = 0x1C, + ROM_E_RTW_MSGP_DM_ANT_DIV_2 = 0x1D, + ROM_E_RTW_MSGP_DM_ANT_DIV_3 = 0x1E, + ROM_E_RTW_MSGP_DM_ANT_DIV_4 = 0x1F, + ROM_E_RTW_MSGP_DM_ANT_DIV_5 = 0x20, + ROM_E_RTW_MSGP_MAC_REG_DUMP_1 = 0x21, + ROM_E_RTW_MSGP_BB_REG_DUMP_1 = 0x22, + ROM_E_RTW_MSGP_RF_REG_DUMP_1 = 0x23, + ROM_E_RTW_MSGP_RF_REG_DUMP_2 = 0x24, + ROM_E_RTW_MSGP_REG_DUMP_1 = 0x25, + ROM_E_RTW_MSGP_REG_DUMP_2 = 0x26, + ROM_E_RTW_MSGP_REG_DUMP_3 = 0x27, + ROM_E_RTW_MSGP_READ_REG_1 = 0x28, + ROM_E_RTW_MSGP_READ_REG_2 = 0x29, + ROM_E_RTW_MSGP_READ_REG_3 = 0x2A, + ROM_E_RTW_MSGP_WRITE_REG_1 = 0x2B, + ROM_E_RTW_MSGP_WRITE_REG_2 = 0x2C, + ROM_E_RTW_MSGP_WRITE_REG_3 = 0x2D, + ROM_E_RTW_MSGP_READ_BB_1 = 0x2E, + ROM_E_RTW_MSGP_WRITE_BB_1 = 0x2F, + ROM_E_RTW_MSGP_READ_RF_1 = 0x30, + ROM_E_RTW_MSGP_WRITE_RF_1 = 0x31, + ROM_E_RTW_MSGP_READ_SYS_1 = 0x32, + ROM_E_RTW_MSGP_WRITE_SYS_1 = 0x33, + ROM_E_RTW_MSGP_FIX_CHANNEL_1 = 0x34, + ROM_E_RTW_MSGP_FIX_CHANNEL_2 = 0x35, + ROM_E_RTW_MSGP_PWR_SAVE_MODE_1 = 0x36, + ROM_E_RTW_MSGP_FIX_RATE_1 = 0x37, + ROM_E_RTW_MSGP_GET_ODM_DBG_FLAG_1 = 0x38, + ROM_E_RTW_MSGP_SET_ODM_DBG_FLAG_1 = 0x39, + ROM_E_RTW_MSGP_DUMP_PWR_IDX_1 = 0x3A, + ROM_E_RTW_MSGP_DUMP_INFO_1 = 0x3B, + ROM_E_RTW_MSGP_DUMP_INFO_2 = 0x3C, + ROM_E_RTW_MSGP_DUMP_INFO_3 = 0x3D, + ROM_E_RTW_MSGP_DUMP_INFO_4 = 0x3E, + ROM_E_RTW_MSGP_DUMP_INFO_5 = 0x3F, + ROM_E_RTW_MSGP_DUMP_INFO_6 = 0x40, + ROM_E_RTW_MSGP_DUMP_INFO_7 = 0x41, + ROM_E_RTW_MSGP_DUMP_INFO_8 = 0x42, + ROM_E_RTW_MSGP_DUMP_INFO_9 = 0x43, + ROM_E_RTW_MSGP_DM_FUNC_FLAG_1 = 0x44, + ROM_E_RTW_MSGP_DM_FUNC_FLAG_2 = 0x45, + ROM_E_RTW_MSGP_DM_FUNC_FLAG_3 = 0x46, + ROM_E_RTW_MSGP_DM_FUNC_FLAG_4 = 0x47, + ROM_E_RTW_MSGP_DM_FUNC_FLAG_5 = 0x48, + ROM_E_RTW_MSGP_DM_FUNC_FLAG_6 = 0x49, + ROM_E_RTW_MSGP_DM_FUNC_FLAG_7 = 0x4A, + ROM_E_RTW_MSGP_DM_FUNC_FLAG_8 = 0x4B, + ROM_E_RTW_MSGP_DM_FUNC_FLAG_9 = 0x4C, + ROM_E_RTW_MSGP_RX_MPDU_1 = 0x4D, + ROM_E_RTW_MSGP_AP_TIMEOUT_CHK_1 = 0x4E, + ROM_E_RTW_MSGP_INIT_DRV_SW_1 = 0x4F, + ROM_E_RTW_MSGP_SET_BSSID_1 = 0x50, + ROM_E_RTW_MSGP_SET_SSID_1 = 0x51, + ROM_E_RTW_MSGP_ON_BEACON_1 = 0x52, + ROM_E_RTW_MSGP_ON_AUTH_1 = 0x53, + ROM_E_RTW_MSGP_ON_AUTH_2 = 0x54, + ROM_E_RTW_MSGP_ON_AUTH_CLIENT_1 = 0x55, + ROM_E_RTW_MSGP_ON_ASSOC_REQ_1 = 0x56, + ROM_E_RTW_MSGP_ON_ASSOC_RSP_1 = 0x57, + ROM_E_RTW_MSGP_ON_DE_AUTH_1 = 0x58, + ROM_E_RTW_MSGP_ON_DE_AUTH_2 = 0x59, + ROM_E_RTW_MSGP_ON_DISASSOC_1 = 0x5A, + ROM_E_RTW_MSGP_ON_DISASSOC_2 = 0x5B, + ROM_E_RTW_MSGP_ISSUE_BEACON_1 = 0x5C, + ROM_E_RTW_MSGP_ISSUE_PROBERSP_1 = 0x5D, + ROM_E_RTW_MSGP_ISSUE_PROBEREQ_1 = 0x5E, + ROM_E_RTW_MSGP_ISSUE_AUTH_1 = 0x5F, + ROM_E_RTW_MSGP_ISSUE_ASSOCRSP_1 = 0x60, + ROM_E_RTW_MSGP_ISSUE_ASSOCREQ_1 = 0x61, + ROM_E_RTW_MSGP_ISSUE_NULLDATA_1 = 0x62, + ROM_E_RTW_MSGP_ISSUE_QOS_NULLDATA_1 = 0x63, + ROM_E_RTW_MSGP_ISSUE_DEAUTH_1 = 0x64, + ROM_E_RTW_MSGP_ISSUE_ACTION_BA_1 = 0x65, + ROM_E_RTW_MSGP_ISSUE_BSS_COEXIST_1 = 0x66, + ROM_E_RTW_MSGP_START_CLNT_AUTH_1 = 0x67, + ROM_E_RTW_MSGP_LINKED_STATUS_CHK_1 = 0x68, + ROM_E_RTW_MSGP_SETKEY_HDL_1 = 0x69, + ROM_E_RTW_MSGP_SET_STAKEY_HDL_1 = 0x6A, + ROM_E_RTW_MSGP_SET_STAKEY_HDL_2 = 0x6B, + ROM_E_RTW_MSGP_P2P_BUILD_MGNT_FRAME_1 = 0x6C, + ROM_E_RTW_MSGP_SEND_EAPOL_1 = 0x6D, + ROM_E_RTW_MSGP_SEND_EAPOL_2 = 0x6E, + ROM_E_RTW_MSGP_SEND_EAPOL_3 = 0x6F, + ROM_E_RTW_MSGP_EAPOL_KEY_RECVD_1 = 0x70, + ROM_E_RTW_MSGP_EAPOL_KEY_RECVD_2 = 0x71, + ROM_E_RTW_MSGP_EAPOL_KEY_RECVD_3 = 0x72, + ROM_E_RTW_MSGP_FREE_RECVFRAME_1 = 0x73, + ROM_E_RTW_MSGP_VAR_PORT_SWITCH_1 = 0x74, + ROM_E_RTW_MSGP_VAR_PORT_SWITCH_2 = 0x75, + ROM_E_RTW_MSGP_DOWN_SEMA_1 = 0x76, + ROM_E_RTW_MSGP_MAX = 0x77 }; -struct __attribute__((aligned(4))) _PS_PARM_ -{ - uint8_t Enter32KHzPermission; - uint8_t bAllQueueUAPSD; - uint8_t ps_dtim_flag; - uint8_t pstrx_rxcnt_period; - uint8_t NoConnect32k; - uint8_t ack_last_rpwm; - uint8_t TxNull0; - uint8_t TxNull1; - uint8_t TxNull0ok; - uint8_t TxNull1ok; - uint8_t RfOffLicenseForBCNRx; - uint8_t BCNAggEn; - uint8_t IsGoingTo32K; - uint8_t bMaxTrackingBcnMode; - uint8_t BcnTraceDone; - unsigned __int8 smart_ps : 4; - unsigned __int8 RLBM : 4; - uint8_t AwakeInterval; - uint8_t ps_mode; - uint8_t ClkRequestEnable; - uint8_t last_rpwm; - uint8_t current_ps_state; - uint8_t ps_data_open; - uint8_t ps_bcn_pass_time; - uint8_t ps_dtim_period; - uint8_t ps_dtim_cnt; - uint8_t ps_bcn_to; - uint8_t bcn_to_cnt; - uint8_t bcn_to_times_cnt; - uint8_t min_rate_in_rrsr; - uint16_t ps_drv_early_itv; - uint32_t null1_ok_cnt; - uint8_t SlotPeriod; - uint8_t FirstOnPeriod; - uint8_t SecondOnPeriod; - uint8_t ThirdOnPeriod; - uint8_t CurrentSlot; - BOOLEAN TDMAOnPeriod; +struct _atr_aligned4_ _PS_PARM_ { + uint8_t Enter32KHzPermission; + uint8_t bAllQueueUAPSD; + uint8_t ps_dtim_flag; + uint8_t pstrx_rxcnt_period; + uint8_t NoConnect32k; + uint8_t ack_last_rpwm; + uint8_t TxNull0; + uint8_t TxNull1; + uint8_t TxNull0ok; + uint8_t TxNull1ok; + uint8_t RfOffLicenseForBCNRx; + uint8_t BCNAggEn; + uint8_t IsGoingTo32K; + uint8_t bMaxTrackingBcnMode; + uint8_t BcnTraceDone; + uint8_t smart_ps :4; + uint8_t RLBM :4; + uint8_t AwakeInterval; + uint8_t ps_mode; + uint8_t ClkRequestEnable; + uint8_t last_rpwm; + uint8_t current_ps_state; + uint8_t ps_data_open; + uint8_t ps_bcn_pass_time; + uint8_t ps_dtim_period; + uint8_t ps_dtim_cnt; + uint8_t ps_bcn_to; + uint8_t bcn_to_cnt; + uint8_t bcn_to_times_cnt; + uint8_t min_rate_in_rrsr; + uint16_t ps_drv_early_itv; + uint32_t null1_ok_cnt; + uint8_t SlotPeriod; + uint8_t FirstOnPeriod; + uint8_t SecondOnPeriod; + uint8_t ThirdOnPeriod; + uint8_t CurrentSlot; + BOOLEAN TDMAOnPeriod; }; typedef struct _PS_PARM_ PS_PARM; typedef struct _PS_PARM_ *PPS_PARM; -struct _LEGACY_PS_PPARM_ -{ - unsigned __int8 ps_mode : 7; - unsigned __int8 ClkRequestEnable : 1; - unsigned __int8 RLBM : 4; - unsigned __int8 smart_ps : 4; - uint8_t AwakeInterval; - unsigned __int8 bAllQueueUAPSD : 1; - unsigned __int8 bMaxTrackingBcnMode : 1; - unsigned __int8 rsvd : 6; - uint8_t PwrState; - unsigned __int8 LowPwrRxBCN : 1; - unsigned __int8 AntAutoSwitch : 1; - unsigned __int8 PSAllowBTHighPri : 1; - unsigned __int8 ProtectBCN : 1; - unsigned __int8 SilencePeriod : 1; - unsigned __int8 FastBTConnect : 1; - unsigned __int8 TwoAntennaEn : 1; - unsigned __int8 rsvd2 : 1; - unsigned __int8 AdoptUserSetting : 1; - unsigned __int8 DrvBcnEarlyShift : 3; - unsigned __int8 DrvBcnTimeOut : 4; - uint8_t SlotPeriod; - uint8_t FirstOnPeriod; - uint8_t SecondOnPeriod; - uint8_t ThirdOnPeriod; +struct _LEGACY_PS_PPARM_ { + uint8_t ps_mode :7; + uint8_t ClkRequestEnable :1; + uint8_t RLBM :4; + uint8_t smart_ps :4; + uint8_t AwakeInterval; + uint8_t bAllQueueUAPSD :1; + uint8_t bMaxTrackingBcnMode :1; + uint8_t rsvd :6; + uint8_t PwrState; + uint8_t LowPwrRxBCN :1; + uint8_t AntAutoSwitch :1; + uint8_t PSAllowBTHighPri :1; + uint8_t ProtectBCN :1; + uint8_t SilencePeriod :1; + uint8_t FastBTConnect :1; + uint8_t TwoAntennaEn :1; + uint8_t rsvd2 :1; + uint8_t AdoptUserSetting :1; + uint8_t DrvBcnEarlyShift :3; + uint8_t DrvBcnTimeOut :4; + uint8_t SlotPeriod; + uint8_t FirstOnPeriod; + uint8_t SecondOnPeriod; + uint8_t ThirdOnPeriod; }; typedef struct _LEGACY_PS_PPARM_ LEGACY_PS_PARM; typedef struct _LEGACY_PS_PPARM_ *PLEGACY_PS_PARM; -struct _H2CParam_SetPwrMode_parm_ -{ - LEGACY_PS_PARM PwrModeParm; +struct _H2CParam_SetPwrMode_parm_ { + LEGACY_PS_PARM PwrModeParm; }; typedef struct _H2CParam_SetPwrMode_parm_ *PH2CParam_PwrMode; -struct atomic_t -{ - volatile int counter; +struct atomic_t { + volatile int counter; }; /* -// dlist.h -struct list_head -{ - _list *next; - _list *prev; + // dlist.h + struct list_head + { + _list *next; + _list *prev; + }; + + // freertos_service.h + struct __queue + { + _list queue; + _lock lock; + }; + */ + +struct iw_request_info { + uint16_t cmd; + uint16_t flags; }; -// freertos_service.h -struct __queue -{ - _list queue; - _lock lock; -}; -*/ +typedef int (*iw_handler)(struct net_device *, struct iw_request_info *, + union iwreq_data *, char *); -struct iw_request_info -{ - uint16_t cmd; - uint16_t flags; -}; - -typedef int (*iw_handler)(struct net_device *, struct iw_request_info *, union iwreq_data *, char *); - - -struct _NDIS_802_11_SSID -{ - uint32_t SsidLength; - uint8_t Ssid[36]; +struct _NDIS_802_11_SSID { + uint32_t SsidLength; + uint8_t Ssid[36]; }; typedef struct _NDIS_802_11_SSID NDIS_802_11_SSID; -typedef unsigned __int8 NDIS_802_11_MAC_ADDRESS[6]; +typedef uint8_t NDIS_802_11_MAC_ADDRESS[6]; typedef int NDIS_802_11_RSSI; -enum _NDIS_802_11_NETWORK_TYPE //__int32 +enum _NDIS_802_11_NETWORK_TYPE //sint32_t { - Ndis802_11FH = 0x0, - Ndis802_11DS = 0x1, - Ndis802_11OFDM5 = 0x2, - Ndis802_11OFDM24 = 0x3, - Ndis802_11NetworkTypeMax = 0x4, + Ndis802_11FH = 0x0, + Ndis802_11DS = 0x1, + Ndis802_11OFDM5 = 0x2, + Ndis802_11OFDM24 = 0x3, + Ndis802_11NetworkTypeMax = 0x4, }; typedef enum _NDIS_802_11_NETWORK_TYPE NDIS_802_11_NETWORK_TYPE; -struct _NDIS_802_11_CONFIGURATION_FH -{ - uint32_t Length; - uint32_t HopPattern; - uint32_t HopSet; - uint32_t DwellTime; +struct _NDIS_802_11_CONFIGURATION_FH { + uint32_t Length; + uint32_t HopPattern; + uint32_t HopSet; + uint32_t DwellTime; }; typedef struct _NDIS_802_11_CONFIGURATION_FH NDIS_802_11_CONFIGURATION_FH; -struct _NDIS_802_11_CONFIGURATION -{ - uint32_t Length; - uint32_t BeaconPeriod; - uint32_t ATIMWindow; - uint32_t DSConfig; - NDIS_802_11_CONFIGURATION_FH FHConfig; +struct _NDIS_802_11_CONFIGURATION { + uint32_t Length; + uint32_t BeaconPeriod; + uint32_t ATIMWindow; + uint32_t DSConfig; + NDIS_802_11_CONFIGURATION_FH FHConfig; }; typedef struct _NDIS_802_11_CONFIGURATION NDIS_802_11_CONFIGURATION; -enum _NDIS_802_11_NETWORK_INFRASTRUCTURE // : __int32 +enum _NDIS_802_11_NETWORK_INFRASTRUCTURE // : sint32_t { - Ndis802_11IBSS = 0x0, - Ndis802_11Infrastructure = 0x1, - Ndis802_11AutoUnknown = 0x2, - Ndis802_11InfrastructureMax = 0x3, - Ndis802_11APMode = 0x4, + Ndis802_11IBSS = 0x0, + Ndis802_11Infrastructure = 0x1, + Ndis802_11AutoUnknown = 0x2, + Ndis802_11InfrastructureMax = 0x3, + Ndis802_11APMode = 0x4, }; typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE NDIS_802_11_NETWORK_INFRASTRUCTURE; -typedef unsigned __int8 NDIS_802_11_RATES_EX[16]; +typedef uint8_t NDIS_802_11_RATES_EX[16]; -struct _WLAN_PHY_INFO -{ - uint8_t SignalStrength; - uint8_t SignalQuality; - uint8_t Optimum_antenna; - uint8_t Reserved_0; +struct _WLAN_PHY_INFO { + uint8_t SignalStrength; + uint8_t SignalQuality; + uint8_t Optimum_antenna; + uint8_t Reserved_0; }; typedef struct _WLAN_PHY_INFO WLAN_PHY_INFO; -struct _WLAN_BSSID_EX -{ - uint32_t Length; - NDIS_802_11_MAC_ADDRESS MacAddress; - uint8_t Reserved[2]; - NDIS_802_11_SSID Ssid; - uint32_t Privacy; - NDIS_802_11_RSSI Rssi; - NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; - NDIS_802_11_CONFIGURATION Configuration; - NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; - NDIS_802_11_RATES_EX SupportedRates; - WLAN_PHY_INFO PhyInfo; - uint32_t IELength; - uint8_t IEs[768]; +struct _WLAN_BSSID_EX { + uint32_t Length; + NDIS_802_11_MAC_ADDRESS MacAddress; + uint8_t Reserved[2]; + NDIS_802_11_SSID Ssid; + uint32_t Privacy; + NDIS_802_11_RSSI Rssi; + NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; + NDIS_802_11_CONFIGURATION Configuration; + NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; + NDIS_802_11_RATES_EX SupportedRates; + WLAN_PHY_INFO PhyInfo; + uint32_t IELength; + uint8_t IEs[768]; }; typedef struct _WLAN_BSSID_EX WLAN_BSSID_EX; -struct __attribute__((aligned(2))) _WLAN_BCN_INFO -{ - uint8_t encryp_protocol; - int group_cipher; - int pairwise_cipher; - int is_8021x; - unsigned __int16 ht_cap_info; - unsigned __int8 ht_info_infos_0; +struct _atr_aligned2_ _WLAN_BCN_INFO { // __attribute__((packed))!? + uint8_t encryp_protocol; + int group_cipher; + int pairwise_cipher; + int is_8021x; + uint16_t ht_cap_info; + uint8_t ht_info_infos_0; }; typedef struct _WLAN_BCN_INFO WLAN_BCN_INFO; -struct wlan_network -{ - _list list; - int network_type; - int fixed; - unsigned int last_scanned; - int aid; - int join_res; - WLAN_BSSID_EX network; - WLAN_BCN_INFO BcnInfo; +struct wlan_network { + _list list; + int network_type; + int fixed; + uint32_t last_scanned; + int aid; + int join_res; + WLAN_BSSID_EX network; + WLAN_BCN_INFO BcnInfo; }; /* osdep_service.h -typedef void *_timerHandle; + typedef void *_timerHandle; -struct timer_list -{ - _timerHandle timer_hdl; - unsigned int data; - void (*function)(void *); + struct timer_list + { + _timerHandle timer_hdl; + uint32_t data; + void (*function)(void *); + }; + + typedef struct timer_list _timer; + */ + +struct qos_priv { + uint32_t qos_option; }; -typedef struct timer_list _timer; -*/ - -struct qos_priv -{ - uint32_t qos_option; +struct __attribute__((packed)) _atr_aligned2_ rtw_ieee80211_ht_cap { + uint16_t cap_info; + uint8_t ampdu_params_info; + uint8_t supp_mcs_set[16]; + uint16_t extended_ht_cap_info; + uint32_t tx_BF_cap_info; + uint8_t antenna_selection_info; }; -struct __attribute__((packed)) __attribute__((aligned(2))) rtw_ieee80211_ht_cap -{ - unsigned __int16 cap_info; - unsigned __int8 ampdu_params_info; - unsigned __int8 supp_mcs_set[16]; - unsigned __int16 extended_ht_cap_info; - unsigned int tx_BF_cap_info; - unsigned __int8 antenna_selection_info; +struct ht_priv { + uint32_t ht_option; + uint32_t ampdu_enable; + uint8_t bwmode; + uint8_t ch_offset; + uint8_t sgi; + uint8_t agg_enable_bitmap; + uint8_t candidate_tid_bitmap; + uint8_t stbc_cap; + struct rtw_ieee80211_ht_cap ht_cap; }; -struct ht_priv -{ - uint32_t ht_option; - uint32_t ampdu_enable; - uint8_t bwmode; - uint8_t ch_offset; - uint8_t sgi; - uint8_t agg_enable_bitmap; - uint8_t candidate_tid_bitmap; - uint8_t stbc_cap; - struct rtw_ieee80211_ht_cap ht_cap; -}; - -struct __attribute__((aligned(4))) _RT_LINK_DETECT_T -{ - uint32_t NumTxOkInPeriod; - uint32_t NumRxOkInPeriod; - uint32_t NumRxUnicastOkInPeriod; - BOOLEAN bBusyTraffic; - BOOLEAN bTxBusyTraffic; - BOOLEAN bRxBusyTraffic; - BOOLEAN bHigherBusyTraffic; - BOOLEAN bHigherBusyRxTraffic; - BOOLEAN bHigherBusyTxTraffic; +struct _atr_aligned4_ _RT_LINK_DETECT_T { + uint32_t NumTxOkInPeriod; + uint32_t NumRxOkInPeriod; + uint32_t NumRxUnicastOkInPeriod; + BOOLEAN bBusyTraffic; + BOOLEAN bTxBusyTraffic; + BOOLEAN bRxBusyTraffic; + BOOLEAN bHigherBusyTraffic; + BOOLEAN bHigherBusyRxTraffic; + BOOLEAN bHigherBusyTxTraffic; }; typedef struct _RT_LINK_DETECT_T RT_LINK_DETECT_T; -enum _RT_SCAN_TYPE //: __int32 +enum _RT_SCAN_TYPE //: sint32_t { - SCAN_PASSIVE = 0x0, - SCAN_ACTIVE = 0x1, - SCAN_MIX = 0x2, + SCAN_PASSIVE = 0x0, SCAN_ACTIVE = 0x1, SCAN_MIX = 0x2 }; typedef enum _RT_SCAN_TYPE RT_SCAN_TYPE; -struct mlme_priv -{ - _lock lock; - sint fw_state; - uint8_t bScanInProcess; - uint8_t to_join; - uint8_t *nic_hdl; - _list *pscanned; - _queue free_bss_pool; - _queue scanned_queue; - uint8_t *free_bss_buf; - uint16_t num_of_scanned; - uint8_t *scan_buf; - uint32_t scan_buf_len; - uint16_t scan_cnt; - uint16_t scan_type; - NDIS_802_11_SSID assoc_ssid; - uint8_t assoc_bssid[6]; - struct wlan_network cur_network; - uint32_t scan_interval; - _timer assoc_timer; - uint8_t assoc_by_bssid; - uint8_t assoc_by_rssi; - _timer scan_to_timer; - uint32_t scan_start_time; - struct qos_priv qospriv; - uint16_t num_sta_no_ht; - uint16_t num_FortyMHzIntolerant; - struct ht_priv htpriv; - RT_LINK_DETECT_T LinkDetectInfo; - _timer dynamic_chk_timer; - uint8_t key_mask; - uint8_t acm_mask; - uint8_t ChannelPlan; - RT_SCAN_TYPE scan_mode; - uint8_t *wps_probe_req_ie; - uint32_t wps_probe_req_ie_len; - uint8_t *wps_assoc_req_ie; - uint32_t wps_assoc_req_ie_len; - uint16_t num_sta_non_erp; - uint16_t num_sta_no_short_slot_time; - uint16_t num_sta_no_short_preamble; - uint16_t num_sta_ht_no_gf; - uint16_t num_sta_ht_20mhz; - uint8_t olbc_ht; - uint16_t ht_op_mode; - uint8_t *wps_beacon_ie; - uint8_t *wps_probe_resp_ie; - uint8_t *wps_assoc_resp_ie; - uint32_t wps_beacon_ie_len; - uint32_t wps_probe_resp_ie_len; - uint32_t wps_assoc_resp_ie_len; - _lock bcn_update_lock; - uint8_t update_bcn; - uint8_t scanning_via_buddy_intf; - union recv_frame *p_copy_recv_frame; +struct mlme_priv { + _lock lock; + sint fw_state; + uint8_t bScanInProcess; + uint8_t to_join; + uint8_t *nic_hdl; + _list *pscanned; + _queue free_bss_pool; + _queue scanned_queue; + uint8_t *free_bss_buf; + uint16_t num_of_scanned; + uint8_t *scan_buf; + uint32_t scan_buf_len; + uint16_t scan_cnt; + uint16_t scan_type; + NDIS_802_11_SSID assoc_ssid; + uint8_t assoc_bssid[6]; + struct wlan_network cur_network; + uint32_t scan_interval; + _timer assoc_timer; + uint8_t assoc_by_bssid; + uint8_t assoc_by_rssi; + _timer scan_to_timer; + uint32_t scan_start_time; + struct qos_priv qospriv; + uint16_t num_sta_no_ht; + uint16_t num_FortyMHzIntolerant; + struct ht_priv htpriv; + RT_LINK_DETECT_T LinkDetectInfo; + _timer dynamic_chk_timer; + uint8_t key_mask; + uint8_t acm_mask; + uint8_t ChannelPlan; + RT_SCAN_TYPE scan_mode; + uint8_t *wps_probe_req_ie; + uint32_t wps_probe_req_ie_len; + uint8_t *wps_assoc_req_ie; + uint32_t wps_assoc_req_ie_len; + uint16_t num_sta_non_erp; + uint16_t num_sta_no_short_slot_time; + uint16_t num_sta_no_short_preamble; + uint16_t num_sta_ht_no_gf; + uint16_t num_sta_ht_20mhz; + uint8_t olbc_ht; + uint16_t ht_op_mode; + uint8_t *wps_beacon_ie; + uint8_t *wps_probe_resp_ie; + uint8_t *wps_assoc_resp_ie; + uint32_t wps_beacon_ie_len; + uint32_t wps_probe_resp_ie_len; + uint32_t wps_assoc_resp_ie_len; + _lock bcn_update_lock; + uint8_t update_bcn; + uint8_t scanning_via_buddy_intf; + union recv_frame *p_copy_recv_frame; }; -struct __attribute__((aligned(4))) _RT_CHANNEL_INFO -{ - uint8_t ChannelNum; - RT_SCAN_TYPE ScanType; - uint8_t pscan_config; +struct _atr_aligned4_ _RT_CHANNEL_INFO { + uint8_t ChannelNum; + RT_SCAN_TYPE ScanType; + uint8_t pscan_config; }; typedef struct _RT_CHANNEL_INFO RT_CHANNEL_INFO; -struct ss_res -{ - int state; - int bss_cnt; - int channel_idx; - int scan_mode; - NDIS_802_11_SSID ssid[1]; +struct ss_res { + int state; + int bss_cnt; + int channel_idx; + int scan_mode; + NDIS_802_11_SSID ssid[1]; }; -struct __attribute__((packed)) __attribute__((aligned(1))) ADDBA_request -{ - unsigned __int8 dialog_token; - unsigned __int16 BA_para_set; - unsigned __int16 BA_timeout_value; - unsigned __int16 BA_starting_seqctrl; +struct __attribute__((packed)) __attribute__((aligned(1))) ADDBA_request { + uint8_t dialog_token; + uint16_t BA_para_set; + uint16_t BA_timeout_value; + uint16_t BA_starting_seqctrl; }; -struct AC_param -{ - unsigned __int8 ACI_AIFSN; - unsigned __int8 CW; - unsigned __int16 TXOP_limit; +struct AC_param { + uint8_t ACI_AIFSN; + uint8_t CW; + uint16_t TXOP_limit; }; -struct WMM_para_element -{ - unsigned __int8 QoS_info; - unsigned __int8 reserved; - struct AC_param ac_param[4]; +struct WMM_para_element { + uint8_t QoS_info; + uint8_t reserved; + struct AC_param ac_param[4]; }; -struct __attribute__((aligned(4))) $FE810F6EACF8FAA6CBF1198AEAF43F3A -{ - unsigned __int16 HT_caps_info; - unsigned __int8 AMPDU_para; - unsigned __int8 MCS_rate[16]; - unsigned __int16 HT_ext_caps; - unsigned int Beamforming_caps; - unsigned __int8 ASEL_caps; +struct _atr_aligned4_ $FE810F6EACF8FAA6CBF1198AEAF43F3A { + uint16_t HT_caps_info; + uint8_t AMPDU_para; + uint8_t MCS_rate[16]; + uint16_t HT_ext_caps; + uint32_t Beamforming_caps; + uint8_t ASEL_caps; }; -union $4DB0E692E0E1D0D49E1F34B7B8486D8E -{ +union $4DB0E692E0E1D0D49E1F34B7B8486D8E { struct $FE810F6EACF8FAA6CBF1198AEAF43F3A HT_cap_element; - unsigned __int8 HT_cap[26]; + uint8_t HT_cap[26]; }; -struct HT_caps_element -{ +struct HT_caps_element { union $4DB0E692E0E1D0D49E1F34B7B8486D8E u; }; -struct HT_info_element -{ - unsigned __int8 primary_channel; - unsigned __int8 infos[5]; - unsigned __int8 MCS_rate[16]; +struct HT_info_element { + uint8_t primary_channel; + uint8_t infos[5]; + uint8_t MCS_rate[16]; }; -struct FW_Sta_Info -{ +struct FW_Sta_Info { struct sta_info *psta; - uint32_t status; - uint32_t rx_pkt; - uint32_t retry; - NDIS_802_11_RATES_EX SupportedRates; + uint32_t status; + uint32_t rx_pkt; + uint32_t retry; + NDIS_802_11_RATES_EX SupportedRates; }; -struct mlme_ext_info -{ - uint32_t state; - uint32_t reauth_count; - uint32_t reassoc_count; - uint32_t link_count; - uint32_t auth_seq; - uint32_t auth_algo; - uint32_t authModeToggle; - uint32_t enc_algo; - uint32_t key_index; - uint32_t iv; - uint8_t chg_txt[128]; - uint16_t aid; - uint16_t bcn_interval; - uint16_t capability; - uint8_t assoc_AP_vendor; - uint8_t slotTime; - uint8_t preamble_mode; - uint8_t WMM_enable; - uint8_t ERP_enable; - uint8_t ERP_IE; - uint8_t HT_enable; - uint8_t HT_caps_enable; - uint8_t HT_info_enable; - uint8_t HT_protection; - uint8_t turboMode_cts2self; - uint8_t turboMode_rtsen; - uint8_t SM_PS; - uint8_t agg_enable_bitmap; - uint8_t ADDBA_retry_count; - uint8_t candidate_tid_bitmap; - uint8_t dialogToken; - uint8_t bwmode_updated; - uint8_t hidden_ssid_mode; - struct ADDBA_request ADDBA_req; - struct WMM_para_element WMM_param; - struct __attribute__((packed)) __attribute__((aligned(1))) HT_caps_element HT_caps; - struct HT_info_element HT_info; - struct FW_Sta_Info FW_sta_info[5]; +struct mlme_ext_info { + uint32_t state; + uint32_t reauth_count; + uint32_t reassoc_count; + uint32_t link_count; + uint32_t auth_seq; + uint32_t auth_algo; + uint32_t authModeToggle; + uint32_t enc_algo; + uint32_t key_index; + uint32_t iv; + uint8_t chg_txt[128]; + uint16_t aid; + uint16_t bcn_interval; + uint16_t capability; + uint8_t assoc_AP_vendor; + uint8_t slotTime; + uint8_t preamble_mode; + uint8_t WMM_enable; + uint8_t ERP_enable; + uint8_t ERP_IE; + uint8_t HT_enable; + uint8_t HT_caps_enable; + uint8_t HT_info_enable; + uint8_t HT_protection; + uint8_t turboMode_cts2self; + uint8_t turboMode_rtsen; + uint8_t SM_PS; + uint8_t agg_enable_bitmap; + uint8_t ADDBA_retry_count; + uint8_t candidate_tid_bitmap; + uint8_t dialogToken; + uint8_t bwmode_updated; + uint8_t hidden_ssid_mode; + struct ADDBA_request ADDBA_req; + struct WMM_para_element WMM_param; + struct __attribute__((packed)) __attribute__((aligned(1))) HT_caps_element HT_caps; + struct HT_info_element HT_info; + struct FW_Sta_Info FW_sta_info[5]; }; -typedef struct _cus_ie *p_cus_ie; +#ifndef _CUS_IE_ +#define _CUS_IE_ +typedef struct _cus_ie{ + __u8 *ie; + __u8 type; +} cus_ie, *p_cus_ie; +#endif /* _CUS_IE_ */ +// typedef struct _cus_ie *p_cus_ie; -struct __attribute__((aligned(2))) mlme_ext_priv -{ - _adapter *padapter; - uint8_t mlmeext_init; - struct atomic_t event_seq; - uint16_t mgnt_seq; - uint8_t cur_channel; - uint8_t cur_bwmode; - uint8_t cur_ch_offset; - uint8_t cur_wireless_mode; - uint8_t max_chan_nums; - RT_CHANNEL_INFO channel_set[14]; - uint8_t basicrate[13]; - uint8_t datarate[13]; - struct ss_res sitesurvey_res; - struct mlme_ext_info mlmext_info; - _timer survey_timer; - _timer link_timer; - uint16_t chan_scan_time; - uint8_t scan_abort; - uint8_t tx_rate; - uint8_t retry; - uint64_t TSFValue; - unsigned __int8 bstart_bss; - uint16_t action_public_rxseq; - _timer reconnect_timer; - uint8_t reconnect_deauth_filtered; - uint8_t reconnect_times; - uint8_t reconnect_cnt; - uint16_t reconnect_timeout; - uint8_t saved_alg; - uint8_t saved_essid[33]; - uint8_t saved_key[32]; - uint16_t saved_key_len; - uint8_t saved_key_idx; - uint8_t saved_wpa_passphrase[65]; - uint8_t saved_eap_method; - uint8_t auto_reconnect; - uint8_t partial_scan; - p_cus_ie cus_ven_ie; - uint8_t ie_num; - uint8_t bChDeauthDisabled; - uint8_t bConcurrentFlushingSTA; -}; - -struct cmd_priv -{ - _queue cmd_queue; - uint8_t cmdthd_running; - _adapter *padapter; -}; - -struct evt_priv -{ +struct _atr_aligned2_ mlme_ext_priv { //__attribute__((packed))? + _adapter *padapter; + uint8_t mlmeext_init; struct atomic_t event_seq; - uint8_t *evt_buf; - uint8_t *evt_allocated_buf; - uint32_t evt_done_cnt; + uint16_t mgnt_seq; + uint8_t cur_channel; + uint8_t cur_bwmode; + uint8_t cur_ch_offset; + uint8_t cur_wireless_mode; + uint8_t max_chan_nums; + RT_CHANNEL_INFO channel_set[14]; + uint8_t basicrate[13]; + uint8_t datarate[13]; + struct ss_res sitesurvey_res; + struct mlme_ext_info mlmext_info; + _timer survey_timer; + _timer link_timer; + uint16_t chan_scan_time; + uint8_t scan_abort; + uint8_t tx_rate; + uint8_t retry; + uint64_t TSFValue; + uint8_t bstart_bss; + uint16_t action_public_rxseq; + _timer reconnect_timer; + uint8_t reconnect_deauth_filtered; + uint8_t reconnect_times; + uint8_t reconnect_cnt; + uint16_t reconnect_timeout; + uint8_t saved_alg; + uint8_t saved_essid[33]; + uint8_t saved_key[32]; + uint16_t saved_key_len; + uint8_t saved_key_idx; + uint8_t saved_wpa_passphrase[65]; + uint8_t saved_eap_method; + uint8_t auto_reconnect; + uint8_t partial_scan; + p_cus_ie cus_ven_ie; + uint8_t ie_num; + uint8_t bChDeauthDisabled; + uint8_t bConcurrentFlushingSTA; }; -struct _io_ops -{ - int (*init_io_priv)(struct dvobj_priv *); - int (*write8_endian)(struct dvobj_priv *, uint32_t, uint32_t, uint32_t); - uint8_t (*_read8)(struct dvobj_priv *, uint32_t, int32_t *); - uint16_t (*_read16)(struct dvobj_priv *, uint32_t, int32_t *); - uint32_t (*_read32)(struct dvobj_priv *, uint32_t, int32_t *); - int32_t (*_write8)(struct dvobj_priv *, uint32_t, uint8_t, int32_t *); - int32_t (*_write16)(struct dvobj_priv *, uint32_t, uint16_t, int32_t *); - int32_t (*_write32)(struct dvobj_priv *, uint32_t, uint32_t, int32_t *); - int (*read_rx_fifo)(struct dvobj_priv *, uint32_t, uint8_t *, uint32_t, struct fifo_more_data *); - int (*write_tx_fifo)(struct dvobj_priv *, uint32_t, uint8_t *, uint32_t); +struct cmd_priv { + _queue cmd_queue; + uint8_t cmdthd_running; + _adapter *padapter; }; -struct io_priv -{ +struct evt_priv { + struct atomic_t event_seq; + uint8_t *evt_buf; + uint8_t *evt_allocated_buf; + uint32_t evt_done_cnt; +}; + +struct _io_ops { + int (*init_io_priv)(struct dvobj_priv *); + int (*write8_endian)(struct dvobj_priv *, uint32_t, uint32_t, uint32_t); + uint8_t (*_read8)(struct dvobj_priv *, uint32_t, int32_t *); + uint16_t (*_read16)(struct dvobj_priv *, uint32_t, int32_t *); + uint32_t (*_read32)(struct dvobj_priv *, uint32_t, int32_t *); + int32_t (*_write8)(struct dvobj_priv *, uint32_t, uint8_t, int32_t *); + int32_t (*_write16)(struct dvobj_priv *, uint32_t, uint16_t, int32_t *); + int32_t (*_write32)(struct dvobj_priv *, uint32_t, uint32_t, int32_t *); + int (*read_rx_fifo)(struct dvobj_priv *, uint32_t, uint8_t *, uint32_t, + struct fifo_more_data *); + int (*write_tx_fifo)(struct dvobj_priv *, uint32_t, uint8_t *, uint32_t); +}; + +struct io_priv { struct _io_ops io_ops; }; -struct rtw_tx_ring -{ +struct rtw_tx_ring { struct tx_buf_desc *desc; - dma_addr_t dma; - unsigned int idx; - unsigned int entries; - _queue queue; - uint32_t qlen; + dma_addr_t dma; + uint32_t idx; + uint32_t entries; + _queue queue; + uint32_t qlen; }; -struct __attribute__((aligned(8))) xmit_priv -{ - _lock lock; - _queue be_pending; - _queue bk_pending; - _queue vi_pending; - _queue vo_pending; - _queue bm_pending; - uint8_t *pallocated_frame_buf; - uint8_t *pxmit_frame_buf; - unsigned int free_xmitframe_cnt; - _queue free_xmit_queue; - _adapter *adapter; - uint8_t vcs_setting; - uint8_t vcs; - uint8_t vcs_type; - uint64_t tx_bytes; - uint64_t tx_pkts; - uint64_t tx_drop; - uint64_t last_tx_bytes; - uint64_t last_tx_pkts; - struct hw_xmit *hwxmits; - uint8_t hwxmit_entry; - struct rtw_tx_ring tx_ring[8]; - int txringcount[8]; - uint8_t beaconDMAing; - _queue free_xmitbuf_queue; - _queue pending_xmitbuf_queue; - uint8_t *pallocated_xmitbuf; - uint8_t *pxmitbuf; - unsigned int free_xmitbuf_cnt; - _queue free_xmit_extbuf_queue; - uint8_t *pallocated_xmit_extbuf; - uint8_t *pxmit_extbuf; - unsigned int free_xmit_extbuf_cnt; - uint16_t nqos_ssn; +struct _atr_aligned8_ xmit_priv { + _lock lock; + _queue be_pending; + _queue bk_pending; + _queue vi_pending; + _queue vo_pending; + _queue bm_pending; + uint8_t *pallocated_frame_buf; + uint8_t *pxmit_frame_buf; + uint32_t free_xmitframe_cnt; + _queue free_xmit_queue; + _adapter *adapter; + uint8_t vcs_setting; + uint8_t vcs; + uint8_t vcs_type; + uint64_t tx_bytes; + uint64_t tx_pkts; + uint64_t tx_drop; + uint64_t last_tx_bytes; + uint64_t last_tx_pkts; + struct hw_xmit *hwxmits; + uint8_t hwxmit_entry; + struct rtw_tx_ring tx_ring[8]; + int txringcount[8]; + uint8_t beaconDMAing; + _queue free_xmitbuf_queue; + _queue pending_xmitbuf_queue; + uint8_t *pallocated_xmitbuf; + uint8_t *pxmitbuf; + uint32_t free_xmitbuf_cnt; + _queue free_xmit_extbuf_queue; + uint8_t *pallocated_xmit_extbuf; + uint8_t *pxmit_extbuf; + uint32_t free_xmit_extbuf_cnt; + uint16_t nqos_ssn; }; -struct rtw_rx_ring -{ +struct rtw_rx_ring { struct recv_buf_stat *desc; - dma_addr_t dma; - unsigned int idx; - struct sk_buff *rx_buf[4]; + dma_addr_t dma; + uint32_t idx; + struct sk_buff *rx_buf[4]; }; -struct signal_stat -{ - uint8_t update_req; - uint8_t avg_val; - uint32_t total_num; - uint32_t total_val; +struct signal_stat { + uint8_t update_req; + uint8_t avg_val; + uint32_t total_num; + uint32_t total_val; }; -struct __attribute__((aligned(8))) recv_priv -{ - _lock lock; - _queue free_recv_queue; - _queue recv_pending_queue; - _queue uc_swdec_pending_queue; - uint8_t *pallocated_frame_buf; - uint8_t *precv_frame_buf; - unsigned int free_recvframe_cnt; - _adapter *adapter; - uint32_t bIsAnyNonBEPkts; - uint64_t rx_bytes; - uint64_t rx_pkts; - uint64_t rx_drop; - uint64_t rx_overflow; - uint64_t last_rx_bytes; - unsigned int rx_icv_err; - unsigned int rx_largepacket_crcerr; - unsigned int rx_smallpacket_crcerr; - unsigned int rx_middlepacket_crcerr; - uint8_t *pallocated_recv_buf; - uint8_t *precv_buf; - _queue free_recv_buf_queue; - uint32_t free_recv_buf_queue_cnt; - struct rtw_rx_ring rx_ring[1]; - int rxringcount; - uint16_t rxbuffersize; - uint8_t is_signal_dbg; - uint8_t signal_strength_dbg; - int8_t rssi; - int8_t rxpwdb; - uint8_t signal_strength; - uint8_t signal_qual; - uint8_t noise; - int RxSNRdB[2]; - int8_t RxRssi[2]; - int FalseAlmCnt_all; - _timer signal_stat_timer; - uint32_t signal_stat_sampling_interval; - struct signal_stat signal_qual_data; - struct signal_stat signal_strength_data; - uint8_t promisc_enabled; - uint8_t promisc_len_used; - _list promisc_list; - _lock promisc_lock; - uint32_t promisc_bk_rcr; - uint16_t promisc_bk_rxfltmap2; - uint8_t promisc_mgntframe_enabled; +struct _atr_aligned8_ recv_priv { + _lock lock; + _queue free_recv_queue; + _queue recv_pending_queue; + _queue uc_swdec_pending_queue; + uint8_t *pallocated_frame_buf; + uint8_t *precv_frame_buf; + uint32_t free_recvframe_cnt; + _adapter *adapter; + uint32_t bIsAnyNonBEPkts; + uint64_t rx_bytes; + uint64_t rx_pkts; + uint64_t rx_drop; + uint64_t rx_overflow; + uint64_t last_rx_bytes; + uint32_t rx_icv_err; + uint32_t rx_largepacket_crcerr; + uint32_t rx_smallpacket_crcerr; + uint32_t rx_middlepacket_crcerr; + uint8_t *pallocated_recv_buf; + uint8_t *precv_buf; + _queue free_recv_buf_queue; + uint32_t free_recv_buf_queue_cnt; + struct rtw_rx_ring rx_ring[1]; + int rxringcount; + uint16_t rxbuffersize; + uint8_t is_signal_dbg; + uint8_t signal_strength_dbg; + int8_t rssi; + int8_t rxpwdb; + uint8_t signal_strength; + uint8_t signal_qual; + uint8_t noise; + int RxSNRdB[2]; + int8_t RxRssi[2]; + int FalseAlmCnt_all; + _timer signal_stat_timer; + uint32_t signal_stat_sampling_interval; + struct signal_stat signal_qual_data; + struct signal_stat signal_strength_data; + uint8_t promisc_enabled; + uint8_t promisc_len_used; + _list promisc_list; + _lock promisc_lock; + uint32_t promisc_bk_rcr; + uint16_t promisc_bk_rxfltmap2; + uint8_t promisc_mgntframe_enabled; }; -struct __attribute__((aligned(4))) sta_priv -{ - uint8_t *pallocated_stainfo_buf; - uint32_t allocated_stainfo_size; - uint8_t *pstainfo_buf; - _queue free_sta_queue; - _lock sta_hash_lock; - _list sta_hash[5]; - int asoc_sta_count; - _queue sleep_q; - _queue wakeup_q; - _adapter *padapter; - _list asoc_list; - _list auth_list; - _lock asoc_list_lock; - _lock auth_list_lock; - unsigned int auth_to; - unsigned int assoc_to; - unsigned int expire_to; - struct sta_info *sta_aid[5]; - uint16_t sta_dz_bitmap; - uint16_t tim_bitmap; - uint16_t max_num_sta; +struct _atr_aligned4_ sta_priv { + uint8_t *pallocated_stainfo_buf; + uint32_t allocated_stainfo_size; + uint8_t *pstainfo_buf; + _queue free_sta_queue; + _lock sta_hash_lock; + _list sta_hash[5]; + int asoc_sta_count; + _queue sleep_q; + _queue wakeup_q; + _adapter *padapter; + _list asoc_list; + _list auth_list; + _lock asoc_list_lock; + _lock auth_list_lock; + uint32_t auth_to; + uint32_t assoc_to; + uint32_t expire_to; + struct sta_info *sta_aid[5]; + uint16_t sta_dz_bitmap; + uint16_t tim_bitmap; + uint16_t max_num_sta; }; -union Keytype -{ - uint8_t skey[16]; - uint32_t lkey[4]; +union Keytype { + uint8_t skey[16]; + uint32_t lkey[4]; }; -struct $7EAAF07643C317F97751F130E632CB13 -{ - uint8_t TSC0; - uint8_t TSC1; - uint8_t TSC2; - uint8_t TSC3; - uint8_t TSC4; - uint8_t TSC5; - uint8_t TSC6; - uint8_t TSC7; +struct $7EAAF07643C317F97751F130E632CB13 { + uint8_t TSC0; + uint8_t TSC1; + uint8_t TSC2; + uint8_t TSC3; + uint8_t TSC4; + uint8_t TSC5; + uint8_t TSC6; + uint8_t TSC7; }; -union pn48 -{ - uint64_t val; - struct $7EAAF07643C317F97751F130E632CB13 _byte_; +union pn48 { + uint64_t val; + struct $7EAAF07643C317F97751F130E632CB13 _byte_; }; -struct _NDIS_802_11_WEP -{ - uint32_t Length; - uint32_t KeyIndex; - uint32_t KeyLength; - uint8_t KeyMaterial[16]; +struct _NDIS_802_11_WEP { + uint32_t Length; + uint32_t KeyIndex; + uint32_t KeyLength; + uint8_t KeyMaterial[16]; }; typedef struct _NDIS_802_11_WEP NDIS_802_11_WEP; -struct $D75518714447A990003EBC933C23F70E -{ - unsigned int HighPart; - unsigned int LowPart; +struct $D75518714447A990003EBC933C23F70E { + uint32_t HighPart; + uint32_t LowPart; }; -union _LARGE_INTEGER -{ - unsigned __int8 charData[8]; - struct $D75518714447A990003EBC933C23F70E field; +union _LARGE_INTEGER { + uint8_t charData[8]; + struct $D75518714447A990003EBC933C23F70E field; }; typedef union _LARGE_INTEGER LARGE_INTEGER; -struct $121C25F90E4E195D1524BBC5399ADEBE -{ - LARGE_INTEGER HighPart; - LARGE_INTEGER LowPart; +struct $121C25F90E4E195D1524BBC5399ADEBE { + LARGE_INTEGER HighPart; + LARGE_INTEGER LowPart; }; -union _OCTET16_INTEGER -{ - unsigned __int8 charData[16]; - struct $121C25F90E4E195D1524BBC5399ADEBE field; +union _OCTET16_INTEGER { + uint8_t charData[16]; + struct $121C25F90E4E195D1524BBC5399ADEBE field; }; typedef union _OCTET16_INTEGER OCTET16_INTEGER; -struct $BB6DA6E37D48DEE353E02A8C8F92DDF7 -{ - OCTET16_INTEGER HighPart; - OCTET16_INTEGER LowPart; +struct $BB6DA6E37D48DEE353E02A8C8F92DDF7 { + OCTET16_INTEGER HighPart; + OCTET16_INTEGER LowPart; }; -union _OCTET32_INTEGER -{ - unsigned __int8 charData[32]; - struct $BB6DA6E37D48DEE353E02A8C8F92DDF7 field; +union _OCTET32_INTEGER { + uint8_t charData[32]; + struct $BB6DA6E37D48DEE353E02A8C8F92DDF7 field; }; typedef union _OCTET32_INTEGER OCTET32_INTEGER; -struct _OCTET_STRING -{ - unsigned __int8 *Octet; - int Length; +struct _OCTET_STRING { + uint8_t *Octet; + int Length; }; typedef struct _OCTET_STRING OCTET_STRING; -struct _wpa_global_info -{ - OCTET32_INTEGER Counter; - int GTKAuthenticator; - int GKeyDoneStations; - int GInitAKeys; - int GUpdateStationKeys; - int GkeyReady; - OCTET_STRING AuthInfoElement; - unsigned __int8 AuthInfoBuf[128]; - unsigned __int8 MulticastCipher; - OCTET_STRING GNonce; - unsigned __int8 GNonceBuf[32]; - unsigned __int8 GTK[4][32]; - unsigned __int8 GMK[32]; - int GN; - int GM; - int GTKRekey; +struct _wpa_global_info { + OCTET32_INTEGER Counter; + int GTKAuthenticator; + int GKeyDoneStations; + int GInitAKeys; + int GUpdateStationKeys; + int GkeyReady; + OCTET_STRING AuthInfoElement; + uint8_t AuthInfoBuf[128]; + uint8_t MulticastCipher; + OCTET_STRING GNonce; + uint8_t GNonceBuf[32]; + uint8_t GTK[4][32]; + uint8_t GMK[32]; + int GN; + int GM; + int GTKRekey; }; typedef struct _wpa_global_info WPA_GLOBAL_INFO; typedef struct _wpa_sta_info WPA_STA_INFO; -struct __attribute__((aligned(4))) security_priv -{ - uint32_t dot11AuthAlgrthm; - uint32_t dot11PrivacyAlgrthm; - uint32_t dot11PrivacyKeyIndex; - union Keytype dot11DefKey[4]; - uint32_t dot11DefKeylen[4]; - uint32_t dot118021XGrpPrivacy; - uint32_t dot118021XGrpKeyid; - union Keytype dot118021XGrpKey[4]; - union Keytype dot118021XGrptxmickey[4]; - union Keytype dot118021XGrprxmickey[4]; - union pn48 dot11Grptxpn; - union pn48 dot11Grprxpn; - unsigned int dot8021xalg; - unsigned int wpa_psk; - unsigned int wpa_group_cipher; - unsigned int wpa2_group_cipher; - unsigned int wpa_pairwise_cipher; - unsigned int wpa2_pairwise_cipher; - uint8_t wps_ie[512]; - int wps_ie_len; - uint8_t binstallGrpkey; - uint8_t busetkipkey; - uint8_t bcheck_grpkey; - uint8_t bgrpkey_handshake; - int32_t sw_encrypt; - int32_t sw_decrypt; - int32_t hw_decrypted; - uint32_t ndisauthtype; - uint32_t ndisencryptstatus; - NDIS_802_11_WEP ndiswep; - uint8_t supplicant_ie[256]; - uint32_t last_mic_err_time; - uint8_t btkip_countermeasure; - uint8_t btkip_wait_report; - uint32_t btkip_countermeasure_time; - WPA_GLOBAL_INFO wpa_global_info; - uint8_t *palloc_wpastainfo_buf; - uint32_t alloc_wpastainfo_size; - WPA_STA_INFO *wpa_sta_info[3]; - uint8_t wpa_passphrase[65]; - uint8_t wps_phase; +struct _atr_aligned4_ security_priv { + uint32_t dot11AuthAlgrthm; + uint32_t dot11PrivacyAlgrthm; + uint32_t dot11PrivacyKeyIndex; + union Keytype dot11DefKey[4]; + uint32_t dot11DefKeylen[4]; + uint32_t dot118021XGrpPrivacy; + uint32_t dot118021XGrpKeyid; + union Keytype dot118021XGrpKey[4]; + union Keytype dot118021XGrptxmickey[4]; + union Keytype dot118021XGrprxmickey[4]; + union pn48 dot11Grptxpn; + union pn48 dot11Grprxpn; + uint32_t dot8021xalg; + uint32_t wpa_psk; + uint32_t wpa_group_cipher; + uint32_t wpa2_group_cipher; + uint32_t wpa_pairwise_cipher; + uint32_t wpa2_pairwise_cipher; + uint8_t wps_ie[512]; + int wps_ie_len; + uint8_t binstallGrpkey; + uint8_t busetkipkey; + uint8_t bcheck_grpkey; + uint8_t bgrpkey_handshake; + int32_t sw_encrypt; + int32_t sw_decrypt; + int32_t hw_decrypted; + uint32_t ndisauthtype; + uint32_t ndisencryptstatus; + NDIS_802_11_WEP ndiswep; + uint8_t supplicant_ie[256]; + uint32_t last_mic_err_time; + uint8_t btkip_countermeasure; + uint8_t btkip_wait_report; + uint32_t btkip_countermeasure_time; + WPA_GLOBAL_INFO wpa_global_info; + uint8_t *palloc_wpastainfo_buf; + uint32_t alloc_wpastainfo_size; + WPA_STA_INFO *wpa_sta_info[3]; + uint8_t wpa_passphrase[65]; + uint8_t wps_phase; }; -struct __attribute__((aligned(4))) registry_priv -{ - uint8_t chip_version; - uint8_t hci; - NDIS_802_11_SSID ssid; - uint8_t channel; - uint8_t wireless_mode; - uint8_t scan_mode; - uint8_t vrtl_carrier_sense; - uint8_t vcs_type; - uint16_t rts_thresh; - uint8_t soft_ap; - uint8_t power_mgnt; - uint8_t ps_enable; - uint8_t ips_mode; - uint8_t smart_ps; - uint8_t mp_mode; - uint8_t software_encrypt; - uint8_t software_decrypt; - uint8_t acm_method; - uint8_t wmm_enable; - uint8_t uapsd_enable; - uint32_t beacon_period; - uint8_t ht_enable; - uint8_t ampdu_enable; - uint8_t rx_stbc; - uint8_t ampdu_amsdu; - uint8_t rf_config; - uint8_t power_percentage_idx; - uint8_t wifi_spec; - uint8_t channel_plan; - uint8_t ifname[16]; - uint8_t if2name[16]; - uint8_t RegEnableTxPowerLimit; - uint8_t RegEnableTxPowerByRate; - uint8_t RegEnableKFree; - uint8_t RegPowerBase; - uint8_t RegPwrTblSel; - uint8_t adaptivity_en; - uint8_t adaptivity_mode; - uint8_t adaptivity_dml; - uint8_t adaptivity_dc_backoff; - int8_t adaptivity_th_l2h_ini; +struct _atr_aligned4_ registry_priv { + uint8_t chip_version; + uint8_t hci; + NDIS_802_11_SSID ssid; + uint8_t channel; + uint8_t wireless_mode; + uint8_t scan_mode; + uint8_t vrtl_carrier_sense; + uint8_t vcs_type; + uint16_t rts_thresh; + uint8_t soft_ap; + uint8_t power_mgnt; + uint8_t ps_enable; + uint8_t ips_mode; + uint8_t smart_ps; + uint8_t mp_mode; + uint8_t software_encrypt; + uint8_t software_decrypt; + uint8_t acm_method; + uint8_t wmm_enable; + uint8_t uapsd_enable; + uint32_t beacon_period; + uint8_t ht_enable; + uint8_t ampdu_enable; + uint8_t rx_stbc; + uint8_t ampdu_amsdu; + uint8_t rf_config; + uint8_t power_percentage_idx; + uint8_t wifi_spec; + uint8_t channel_plan; + uint8_t ifname[16]; + uint8_t if2name[16]; + uint8_t RegEnableTxPowerLimit; + uint8_t RegEnableTxPowerByRate; + uint8_t RegEnableKFree; + uint8_t RegPowerBase; + uint8_t RegPwrTblSel; + uint8_t adaptivity_en; + uint8_t adaptivity_mode; + uint8_t adaptivity_dml; + uint8_t adaptivity_dc_backoff; + int8_t adaptivity_th_l2h_ini; }; typedef void *_sema; typedef _sema _pwrlock; -enum _rt_rf_power_state //: __int32 +enum _rt_rf_power_state //: sint32_t { - rf_on = 0x0, - rf_sleep = 0x1, - rf_off = 0x2, - rf_max = 0x3, + rf_on = 0x0, rf_sleep = 0x1, rf_off = 0x2, rf_max = 0x3, }; typedef enum _rt_rf_power_state rt_rf_power_state; -struct __attribute__((aligned(4))) pwrctrl_priv -{ - _pwrlock lock; - volatile uint8_t rpwm; - volatile uint8_t cpwm; - volatile uint8_t tog; - volatile uint8_t cpwm_tog; - uint8_t pwr_mode; - uint8_t smart_ps; - uint8_t bcn_ant_mode; - uint32_t alives; - uint64_t wowlan_fw_iv; - uint8_t bpower_saving; - uint8_t b_hw_radio_off; - uint8_t reg_rfoff; - uint8_t reg_pdnmode; - uint32_t rfoff_reason; - uint32_t cur_ps_level; - uint32_t reg_rfps_level; - uint8_t b_support_aspm; - uint8_t b_support_backdoor; - uint8_t const_amdpci_aspm; - unsigned int ips_enter_cnts; - unsigned int ips_leave_cnts; - uint8_t ps_enable; - uint8_t ips_mode; - uint8_t ips_org_mode; - uint8_t ips_mode_req; - unsigned int bips_processing; - uint32_t ips_deny_time; - uint8_t ps_processing; - uint8_t bLeisurePs; - uint8_t LpsIdleCount; - uint8_t power_mgnt; - uint8_t org_power_mgnt; - uint8_t bFwCurrentInPSMode; - uint32_t DelayLPSLastTimeStamp; - uint8_t btcoex_rfon; - int32_t pnp_current_pwr_state; - uint8_t pnp_bstop_trx; - uint8_t bInternalAutoSuspend; - uint8_t bInSuspend; - uint8_t bSupportRemoteWakeup; - _timer pwr_state_check_timer; - int pwr_state_check_interval; - uint8_t pwr_state_check_cnts; - int ps_flag; - rt_rf_power_state rf_pwrstate; - rt_rf_power_state change_rfpwrstate; - uint8_t wepkeymask; - uint8_t bHWPowerdown; - uint8_t bHWPwrPindetect; - uint8_t bkeepfwalive; - uint8_t brfoffbyhw; - unsigned int PS_BBRegBackup[4]; - uint8_t tdma_slot_period; - uint8_t tdma_rfon_period_len_1; - uint8_t tdma_rfon_period_len_2; - uint8_t tdma_rfon_period_len_3; - uint8_t lps_dtim; +struct _atr_aligned4_ pwrctrl_priv { + _pwrlock lock; + volatile uint8_t rpwm; + volatile uint8_t cpwm; + volatile uint8_t tog; + volatile uint8_t cpwm_tog; + uint8_t pwr_mode; + uint8_t smart_ps; + uint8_t bcn_ant_mode; + uint32_t alives; + uint64_t wowlan_fw_iv; + uint8_t bpower_saving; + uint8_t b_hw_radio_off; + uint8_t reg_rfoff; + uint8_t reg_pdnmode; + uint32_t rfoff_reason; + uint32_t cur_ps_level; + uint32_t reg_rfps_level; + uint8_t b_support_aspm; + uint8_t b_support_backdoor; + uint8_t const_amdpci_aspm; + uint32_t ips_enter_cnts; + uint32_t ips_leave_cnts; + uint8_t ps_enable; + uint8_t ips_mode; + uint8_t ips_org_mode; + uint8_t ips_mode_req; + uint32_t bips_processing; + uint32_t ips_deny_time; + uint8_t ps_processing; + uint8_t bLeisurePs; + uint8_t LpsIdleCount; + uint8_t power_mgnt; + uint8_t org_power_mgnt; + uint8_t bFwCurrentInPSMode; + uint32_t DelayLPSLastTimeStamp; + uint8_t btcoex_rfon; + int32_t pnp_current_pwr_state; + uint8_t pnp_bstop_trx; + uint8_t bInternalAutoSuspend; + uint8_t bInSuspend; + uint8_t bSupportRemoteWakeup; + _timer pwr_state_check_timer; + int pwr_state_check_interval; + uint8_t pwr_state_check_cnts; + int ps_flag; + rt_rf_power_state rf_pwrstate; + rt_rf_power_state change_rfpwrstate; + uint8_t wepkeymask; + uint8_t bHWPowerdown; + uint8_t bHWPwrPindetect; + uint8_t bkeepfwalive; + uint8_t brfoffbyhw; + uint32_t PS_BBRegBackup[4]; + uint8_t tdma_slot_period; + uint8_t tdma_rfon_period_len_1; + uint8_t tdma_rfon_period_len_2; + uint8_t tdma_rfon_period_len_3; + uint8_t lps_dtim; }; -struct __attribute__((aligned(2))) eeprom_priv -{ - uint8_t bautoload_fail_flag; - uint8_t mac_addr[6]; - uint16_t CustomerID; - uint8_t EepromOrEfuse; - uint8_t efuse_eeprom_data[512]; - uint8_t EEPROMRFGainOffset; - uint8_t EEPROMRFGainVal; +struct _atr_aligned2_ eeprom_priv { // __attribute__((packed))!? + uint8_t bautoload_fail_flag; + uint8_t mac_addr[6]; + uint16_t CustomerID; + uint8_t EepromOrEfuse; + uint8_t efuse_eeprom_data[512]; + uint8_t EEPROMRFGainOffset; + uint8_t EEPROMRFGainVal; }; -enum _CHANNEL_WIDTH // : __int32 +enum _CHANNEL_WIDTH // : sint32_t { - CHANNEL_WIDTH_20 = 0x0, - CHANNEL_WIDTH_40 = 0x1, - CHANNEL_WIDTH_80 = 0x2, - CHANNEL_WIDTH_160 = 0x3, - CHANNEL_WIDTH_80_80 = 0x4, - CHANNEL_WIDTH_MAX = 0x5, + CHANNEL_WIDTH_20 = 0x0, + CHANNEL_WIDTH_40 = 0x1, + CHANNEL_WIDTH_80 = 0x2, + CHANNEL_WIDTH_160 = 0x3, + CHANNEL_WIDTH_80_80 = 0x4, + CHANNEL_WIDTH_MAX = 0x5, }; typedef enum _CHANNEL_WIDTH CHANNEL_WIDTH; -enum _HAL_DEF_VARIABLE // : __int32 +enum _HAL_DEF_VARIABLE // : sint32_t { - HAL_DEF_UNDERCORATEDSMOOTHEDPWDB = 0x0, - HAL_DEF_IS_SUPPORT_ANT_DIV = 0x1, - HAL_DEF_CURRENT_ANTENNA = 0x2, - HAL_DEF_DRVINFO_SZ = 0x3, - HAL_DEF_MAX_RECVBUF_SZ = 0x4, - HAL_DEF_RX_PACKET_OFFSET = 0x5, - HAL_DEF_RX_DMA_SZ_WOW = 0x6, - HAL_DEF_RX_DMA_SZ = 0x7, - HAL_DEF_RX_PAGE_SIZE = 0x8, - HAL_DEF_DBG_DM_FUNC = 0x9, - HAL_DEF_RA_DECISION_RATE = 0xA, - HAL_DEF_RA_SGI = 0xB, - HAL_DEF_PT_PWR_STATUS = 0xC, - HW_VAR_MAX_RX_AMPDU_FACTOR = 0xD, - HW_DEF_RA_INFO_DUMP = 0xE, - HAL_DEF_DBG_DUMP_TXPKT = 0xF, - HW_DEF_ODM_DBG_FLAG = 0x10, - HW_DEF_ODM_DBG_LEVEL = 0x11, - HAL_DEF_TX_PAGE_SIZE = 0x12, - HAL_DEF_TX_PAGE_BOUNDARY = 0x13, - HAL_DEF_MACID_SLEEP = 0x14, - HAL_DEF_DBG_RX_INFO_DUMP = 0x15, + HAL_DEF_UNDERCORATEDSMOOTHEDPWDB = 0x0, + HAL_DEF_IS_SUPPORT_ANT_DIV = 0x1, + HAL_DEF_CURRENT_ANTENNA = 0x2, + HAL_DEF_DRVINFO_SZ = 0x3, + HAL_DEF_MAX_RECVBUF_SZ = 0x4, + HAL_DEF_RX_PACKET_OFFSET = 0x5, + HAL_DEF_RX_DMA_SZ_WOW = 0x6, + HAL_DEF_RX_DMA_SZ = 0x7, + HAL_DEF_RX_PAGE_SIZE = 0x8, + HAL_DEF_DBG_DM_FUNC = 0x9, + HAL_DEF_RA_DECISION_RATE = 0xA, + HAL_DEF_RA_SGI = 0xB, + HAL_DEF_PT_PWR_STATUS = 0xC, + HW_VAR_MAX_RX_AMPDU_FACTOR = 0xD, + HW_DEF_RA_INFO_DUMP = 0xE, + HAL_DEF_DBG_DUMP_TXPKT = 0xF, + HW_DEF_ODM_DBG_FLAG = 0x10, + HW_DEF_ODM_DBG_LEVEL = 0x11, + HAL_DEF_TX_PAGE_SIZE = 0x12, + HAL_DEF_TX_PAGE_BOUNDARY = 0x13, + HAL_DEF_MACID_SLEEP = 0x14, + HAL_DEF_DBG_RX_INFO_DUMP = 0x15, }; typedef enum _HAL_DEF_VARIABLE HAL_DEF_VARIABLE; -enum _HAL_ODM_VARIABLE // : __int32 +enum _HAL_ODM_VARIABLE // : sint32_t { - HAL_ODM_STA_INFO = 0x0, - HAL_ODM_DBG_FLAG = 0x1, - HAL_ODM_RX_INFO_DUMP = 0x2, - HAL_ODM_NOISE_MONITOR = 0x3, - HAL_ODM_REGULATION = 0x4, + HAL_ODM_STA_INFO = 0x0, + HAL_ODM_DBG_FLAG = 0x1, + HAL_ODM_RX_INFO_DUMP = 0x2, + HAL_ODM_NOISE_MONITOR = 0x3, + HAL_ODM_REGULATION = 0x4, }; typedef enum _HAL_ODM_VARIABLE HAL_ODM_VARIABLE; - typedef void *_thread_hdl_; /* -// osdep_service.h -struct task_struct -{ - const char *task_name; - _thread_hdl_ task; - _sema wakeup_sema; - _sema terminate_sema; - uint32_t blocked; - uint32_t callback_running; -}; -*/ + // osdep_service.h + struct task_struct + { + const char *task_name; + _thread_hdl_ task; + _sema wakeup_sema; + _sema terminate_sema; + uint32_t blocked; + uint32_t callback_running; + }; + */ typedef struct net_device *_nic_hdl; /* -// wrapper.h -struct net_device_stats -{ - unsigned int rx_packets; - unsigned int tx_packets; - unsigned int rx_dropped; - unsigned int tx_dropped; - unsigned int rx_bytes; - unsigned int tx_bytes; - unsigned int rx_overflow; -}; -*/ + // wrapper.h + struct net_device_stats + { + uint32_t rx_packets; + uint32_t tx_packets; + uint32_t rx_dropped; + uint32_t tx_dropped; + uint32_t rx_bytes; + uint32_t tx_bytes; + uint32_t rx_overflow; + }; + */ - -struct dvobj_priv -{ - void *if1; - void *if2; - void *padapters[2]; - uint8_t iface_nums; - uint8_t RtOutPipe[3]; - uint8_t Queue2Pipe[8]; - uint8_t irq_alloc; - uint8_t irq_enabled; - _lock irq_th_lock; +struct dvobj_priv { + void *if1; + void *if2; + void *padapters[2]; + uint8_t iface_nums; + uint8_t RtOutPipe[3]; + uint8_t Queue2Pipe[8]; + uint8_t irq_alloc; + uint8_t irq_enabled; + _lock irq_th_lock; }; -struct phy_info -{ - uint8_t RxPWDBAll; - uint8_t SignalQuality; - uint8_t RxMIMOSignalStrength[1]; - int8_t RecvSignalPower; - uint8_t SignalStrength; +struct phy_info { + uint8_t RxPWDBAll; + uint8_t SignalQuality; + uint8_t RxMIMOSignalStrength[1]; + int8_t RecvSignalPower; + uint8_t SignalStrength; }; -struct __attribute__((aligned(4))) rx_pkt_attrib -{ - uint16_t pkt_len; - uint8_t physt; - uint8_t drvinfo_sz; - uint8_t shift_sz; - uint8_t hdrlen; - uint8_t to_fr_ds; - uint8_t amsdu; - uint8_t qos; - uint8_t priority; - uint8_t pw_save; - uint8_t mdata; - uint16_t seq_num; - uint8_t frag_num; - uint8_t mfrag; - uint8_t order; - uint8_t privacy; - uint8_t bdecrypted; - uint8_t encrypt; - uint8_t iv_len; - uint8_t icv_len; - uint8_t crc_err; - uint8_t icv_err; - uint16_t eth_type; - uint8_t dst[6]; - uint8_t src[6]; - uint8_t ta[6]; - uint8_t ra[6]; - uint8_t bssid[6]; - uint8_t ack_policy; - uint8_t tcpchk_valid; - uint8_t ip_chkrpt; - uint8_t tcp_chkrpt; - uint8_t key_index; - uint8_t mcs_rate; - uint8_t rxht; - uint8_t sgi; - uint8_t pkt_rpt_type; - uint32_t MacIDValidEntry[2]; - uint8_t data_rate; - struct phy_info phy_info; +struct _atr_aligned4_ rx_pkt_attrib { + uint16_t pkt_len; + uint8_t physt; + uint8_t drvinfo_sz; + uint8_t shift_sz; + uint8_t hdrlen; + uint8_t to_fr_ds; + uint8_t amsdu; + uint8_t qos; + uint8_t priority; + uint8_t pw_save; + uint8_t mdata; + uint16_t seq_num; + uint8_t frag_num; + uint8_t mfrag; + uint8_t order; + uint8_t privacy; + uint8_t bdecrypted; + uint8_t encrypt; + uint8_t iv_len; + uint8_t icv_len; + uint8_t crc_err; + uint8_t icv_err; + uint16_t eth_type; + uint8_t dst[6]; + uint8_t src[6]; + uint8_t ta[6]; + uint8_t ra[6]; + uint8_t bssid[6]; + uint8_t ack_policy; + uint8_t tcpchk_valid; + uint8_t ip_chkrpt; + uint8_t tcp_chkrpt; + uint8_t key_index; + uint8_t mcs_rate; + uint8_t rxht; + uint8_t sgi; + uint8_t pkt_rpt_type; + uint32_t MacIDValidEntry[2]; + uint8_t data_rate; + struct phy_info phy_info; }; -struct recv_frame_hdr -{ - _list list; - struct sk_buff *pkt; - struct sk_buff *pkt_newalloc; - _adapter *adapter; - uint8_t fragcnt; - int frame_tag; - struct rx_pkt_attrib attrib; - unsigned int len; - uint8_t *rx_head; - uint8_t *rx_data; - uint8_t *rx_tail; - uint8_t *rx_end; - void *precvbuf; - struct sta_info *psta; +struct recv_frame_hdr { + _list list; + struct sk_buff *pkt; + struct sk_buff *pkt_newalloc; + _adapter *adapter; + uint8_t fragcnt; + int frame_tag; + struct rx_pkt_attrib attrib; + uint32_t len; + uint8_t *rx_head; + uint8_t *rx_data; + uint8_t *rx_tail; + uint8_t *rx_end; + void *precvbuf; + struct sta_info *psta; }; -union $AB04817EA6EB89125E28056B7464A4D7 -{ - _list list; - struct recv_frame_hdr hdr; - unsigned int mem[32]; +union recv_frame { + _list list; + struct recv_frame_hdr hdr; + uint32_t mem[32]; +}; +/* +union $AB04817EA6EB89125E28056B7464A4D7 { + _list list; + struct recv_frame_hdr hdr; + uint32_t mem[32]; }; -union recv_frame -{ +union recv_frame { union $AB04817EA6EB89125E28056B7464A4D7 u; }; - -/* -// skbuff.h -struct sk_buff -{ - struct sk_buff *next; - struct sk_buff *prev; - struct sk_buff_head *list; - unsigned __int8 *head; - unsigned __int8 *data; - unsigned __int8 *tail; - unsigned __int8 *end; - void *dev; - unsigned int len; -}; - -struct sk_buff_head -{ - struct list_head *next; - struct list_head *prev; - unsigned int qlen; -}; */ +/* + // skbuff.h + struct sk_buff + { + struct sk_buff *next; + struct sk_buff *prev; + struct sk_buff_head *list; + uint8_t *head; + uint8_t *data; + uint8_t *tail; + uint8_t *end; + void *dev; + uint32_t len; + }; -struct tx_servq -{ - _list tx_pending; - _queue sta_pending; - int qcnt; + struct sk_buff_head + { + struct list_head *next; + struct list_head *prev; + uint32_t qlen; + }; + */ + +struct tx_servq { + _list tx_pending; + _queue sta_pending; + int qcnt; }; -struct sta_xmit_priv -{ - _lock lock; - sint option; - sint apsd_setting; - struct tx_servq be_q; - struct tx_servq bk_q; - struct tx_servq vi_q; - struct tx_servq vo_q; - _list legacy_dz; - _list apsd; - uint16_t txseq_tid[16]; +struct sta_xmit_priv { + _lock lock; + sint option; + sint apsd_setting; + struct tx_servq be_q; + struct tx_servq bk_q; + struct tx_servq vi_q; + struct tx_servq vo_q; + _list legacy_dz; + _list apsd; + uint16_t txseq_tid[16]; }; -struct stainfo_rxcache -{ - uint16_t tid_rxseq[16]; +struct stainfo_rxcache { + uint16_t tid_rxseq[16]; }; -struct sta_recv_priv -{ - _lock lock; - sint option; - _queue defrag_q; - struct stainfo_rxcache rxcache; +struct sta_recv_priv { + _lock lock; + sint option; + _queue defrag_q; + struct stainfo_rxcache rxcache; }; -struct stainfo_stats -{ - uint64_t rx_mgnt_pkts; - uint64_t rx_ctrl_pkts; - uint64_t rx_data_pkts; - uint64_t last_rx_mgnt_pkts; - uint64_t last_rx_ctrl_pkts; - uint64_t last_rx_data_pkts; - uint64_t rx_bytes; - uint64_t tx_pkts; - uint64_t tx_bytes; +struct stainfo_stats { + uint64_t rx_mgnt_pkts; + uint64_t rx_ctrl_pkts; + uint64_t rx_data_pkts; + uint64_t last_rx_mgnt_pkts; + uint64_t last_rx_ctrl_pkts; + uint64_t last_rx_data_pkts; + uint64_t rx_bytes; + uint64_t tx_pkts; + uint64_t tx_bytes; }; -struct _RSSI_STA -{ - int32_t UndecoratedSmoothedPWDB; - int32_t UndecoratedSmoothedCCK; - int32_t UndecoratedSmoothedOFDM; - uint64_t PacketMap; - uint8_t ValidBit; - uint32_t OFDM_pkt; +struct _RSSI_STA { + int32_t UndecoratedSmoothedPWDB; + int32_t UndecoratedSmoothedCCK; + int32_t UndecoratedSmoothedOFDM; + uint64_t PacketMap; + uint8_t ValidBit; + uint32_t OFDM_pkt; }; typedef struct _RSSI_STA RSSI_STA; -struct sta_info -{ - _lock lock; - _list list; - _list hash_list; - _adapter *padapter; - struct sta_xmit_priv sta_xmitpriv; - struct sta_recv_priv sta_recvpriv; - _queue sleep_q; - unsigned int sleepq_len; - unsigned int state; - unsigned int aid; - unsigned int mac_id; - unsigned int qos_option; - uint8_t hwaddr[6]; - unsigned int ieee8021x_blocked; - unsigned int dot118021XPrivacy; - union Keytype dot11tkiptxmickey; - union Keytype dot11tkiprxmickey; - union Keytype dot118021x_UncstKey; - union pn48 dot11txpn; - union pn48 dot11rxpn; - uint8_t bssrateset[16]; - uint32_t bssratelen; - int32_t rssi; - int32_t signal_quality; - uint8_t cts2self; - uint8_t rtsen; - uint8_t raid; - uint8_t init_rate; - uint32_t ra_mask; - uint8_t wireless_mode; - struct stainfo_stats sta_stats; - _timer addba_retry_timer; - uint16_t BA_starting_seqctrl[16]; - struct ht_priv htpriv; - _list asoc_list; - _list auth_list; - unsigned int expire_to; - unsigned int auth_seq; - unsigned int authalg; - unsigned __int8 chg_txt[128]; - uint16_t capability; - uint32_t flags; - int dot8021xalg; - int wpa_psk; - int wpa_group_cipher; - int wpa2_group_cipher; - int wpa_pairwise_cipher; - int wpa2_pairwise_cipher; - uint8_t bpairwise_key_installed; - uint8_t wpa_ie[32]; - uint8_t nonerp_set; - uint8_t no_short_slot_time_set; - uint8_t no_short_preamble_set; - uint8_t no_ht_gf_set; - uint8_t no_ht_set; - uint8_t ht_20mhz_set; - unsigned int tx_ra_bitmap; - uint8_t qos_info; - uint8_t max_sp_len; - uint8_t uapsd_bk; - uint8_t uapsd_be; - uint8_t uapsd_vi; - uint8_t uapsd_vo; - uint8_t has_legacy_ac; - unsigned int sleepq_ac_len; - RSSI_STA rssi_stat; - uint8_t bValid; - uint8_t IOTPeer; - uint8_t rssi_level; - uint8_t RSSI_Path[4]; - uint8_t RSSI_Ave; - uint8_t RXEVM[4]; - uint8_t RXSNR[4]; +struct sta_info { + _lock lock; + _list list; + _list hash_list; + _adapter *padapter; + struct sta_xmit_priv sta_xmitpriv; + struct sta_recv_priv sta_recvpriv; + _queue sleep_q; + uint32_t sleepq_len; + uint32_t state; + uint32_t aid; + uint32_t mac_id; + uint32_t qos_option; + uint8_t hwaddr[6]; + uint32_t ieee8021x_blocked; + uint32_t dot118021XPrivacy; + union Keytype dot11tkiptxmickey; + union Keytype dot11tkiprxmickey; + union Keytype dot118021x_UncstKey; + union pn48 dot11txpn; + union pn48 dot11rxpn; + uint8_t bssrateset[16]; + uint32_t bssratelen; + int32_t rssi; + int32_t signal_quality; + uint8_t cts2self; + uint8_t rtsen; + uint8_t raid; + uint8_t init_rate; + uint32_t ra_mask; + uint8_t wireless_mode; + struct stainfo_stats sta_stats; + _timer addba_retry_timer; + uint16_t BA_starting_seqctrl[16]; + struct ht_priv htpriv; + _list asoc_list; + _list auth_list; + uint32_t expire_to; + uint32_t auth_seq; + uint32_t authalg; + uint8_t chg_txt[128]; + uint16_t capability; + uint32_t flags; + int dot8021xalg; + int wpa_psk; + int wpa_group_cipher; + int wpa2_group_cipher; + int wpa_pairwise_cipher; + int wpa2_pairwise_cipher; + uint8_t bpairwise_key_installed; + uint8_t wpa_ie[32]; + uint8_t nonerp_set; + uint8_t no_short_slot_time_set; + uint8_t no_short_preamble_set; + uint8_t no_ht_gf_set; + uint8_t no_ht_set; + uint8_t ht_20mhz_set; + uint32_t tx_ra_bitmap; + uint8_t qos_info; + uint8_t max_sp_len; + uint8_t uapsd_bk; + uint8_t uapsd_be; + uint8_t uapsd_vi; + uint8_t uapsd_vo; + uint8_t has_legacy_ac; + uint32_t sleepq_ac_len; + RSSI_STA rssi_stat; + uint8_t bValid; + uint8_t IOTPeer; + uint8_t rssi_level; + uint8_t RSSI_Path[4]; + uint8_t RSSI_Ave; + uint8_t RXEVM[4]; + uint8_t RXSNR[4]; }; /* -// wifi_conf.h -struct __attribute__((aligned(4))) _cus_ie -{ - uint8_t *ie; - uint8_t type; -}; -*/ + // wifi_conf.h + struct _atr_aligned4_ _cus_ie + { + uint8_t *ie; + uint8_t type; + }; + */ -struct fifo_more_data -{ - uint32_t more_data; - uint32_t len; +struct fifo_more_data { + uint32_t more_data; + uint32_t len; }; -struct hw_xmit -{ - _queue *sta_queue; - int accnt; +struct hw_xmit { + _queue *sta_queue; + int accnt; }; -struct tx_buf_desc -{ - unsigned int txdw0; - unsigned int txdw1; - unsigned int txdw2; - unsigned int txdw3; - unsigned int txdw4; - unsigned int txdw5; - unsigned int txdw6; - unsigned int txdw7; +struct tx_buf_desc { + uint32_t txdw0; + uint32_t txdw1; + uint32_t txdw2; + uint32_t txdw3; + uint32_t txdw4; + uint32_t txdw5; + uint32_t txdw6; + uint32_t txdw7; }; -struct recv_buf_stat -{ - unsigned int rxdw0; - unsigned int rxdw1; +struct recv_buf_stat { + uint32_t rxdw0; + uint32_t rxdw1; }; -struct _wpa_sta_info -{ - int state; - int gstate; - int RSNEnabled; - int PInitAKeys; - unsigned __int8 UnicastCipher; - LARGE_INTEGER CurrentReplayCounter; - LARGE_INTEGER ReplayCounterStarted; - OCTET_STRING ANonce; - OCTET_STRING SNonce; - unsigned __int8 AnonceBuf[32]; - unsigned __int8 SnonceBuf[32]; - unsigned __int8 PMK[32]; - unsigned __int8 PTK[64]; - OCTET_STRING EAPOLMsgRecvd; - OCTET_STRING EAPOLMsgSend; - OCTET_STRING EapolKeyMsgRecvd; - OCTET_STRING EapolKeyMsgSend; - unsigned __int8 eapSendBuf[512]; - struct timer_list resendTimer; - int resendCnt; - int clientHndshkProcessing; - int clientHndshkDone; - int clientGkeyUpdate; - LARGE_INTEGER clientMICReportReplayCounter; +struct _wpa_sta_info { + int state; + int gstate; + int RSNEnabled; + int PInitAKeys; + uint8_t UnicastCipher; + LARGE_INTEGER CurrentReplayCounter; + LARGE_INTEGER ReplayCounterStarted; + OCTET_STRING ANonce; + OCTET_STRING SNonce; + uint8_t AnonceBuf[32]; + uint8_t SnonceBuf[32]; + uint8_t PMK[32]; + uint8_t PTK[64]; + OCTET_STRING EAPOLMsgRecvd; + OCTET_STRING EAPOLMsgSend; + OCTET_STRING EapolKeyMsgRecvd; + OCTET_STRING EapolKeyMsgSend; + uint8_t eapSendBuf[512]; + struct timer_list resendTimer; + int resendCnt; + int clientHndshkProcessing; + int clientHndshkDone; + int clientGkeyUpdate; + LARGE_INTEGER clientMICReportReplayCounter; }; -struct pkt_attrib -{ - uint8_t type; - uint8_t subtype; - uint8_t bswenc; - uint8_t dhcp_pkt; - uint16_t ether_type; - uint16_t seqnum; - uint16_t pkt_hdrlen; - uint16_t hdrlen; - uint32_t pktlen; - uint32_t last_txcmdsz; - uint8_t encrypt; - uint8_t iv_len; - uint8_t icv_len; - uint8_t iv[18]; - uint8_t icv[16]; - uint8_t priority; - uint8_t ack_policy; - uint8_t mac_id; - uint8_t vcs_mode; - uint8_t dst[6]; - uint8_t src[6]; - uint8_t ta[6]; - uint8_t ra[6]; - uint8_t key_idx; - uint8_t qos_en; - uint8_t ht_en; - uint8_t raid; - uint8_t bwmode; - uint8_t ch_offset; - uint8_t sgi; - uint8_t ampdu_en; - uint8_t mdata; - uint8_t pctrl; - uint8_t triggered; - uint8_t qsel; - uint8_t eosp; - uint8_t rate; - uint8_t intel_proxim; - uint8_t retry_ctrl; - struct sta_info *psta; +struct pkt_attrib { + uint8_t type; + uint8_t subtype; + uint8_t bswenc; + uint8_t dhcp_pkt; + uint16_t ether_type; + uint16_t seqnum; + uint16_t pkt_hdrlen; + uint16_t hdrlen; + uint32_t pktlen; + uint32_t last_txcmdsz; + uint8_t encrypt; + uint8_t iv_len; + uint8_t icv_len; + uint8_t iv[18]; + uint8_t icv[16]; + uint8_t priority; + uint8_t ack_policy; + uint8_t mac_id; + uint8_t vcs_mode; + uint8_t dst[6]; + uint8_t src[6]; + uint8_t ta[6]; + uint8_t ra[6]; + uint8_t key_idx; + uint8_t qos_en; + uint8_t ht_en; + uint8_t raid; + uint8_t bwmode; + uint8_t ch_offset; + uint8_t sgi; + uint8_t ampdu_en; + uint8_t mdata; + uint8_t pctrl; + uint8_t triggered; + uint8_t qsel; + uint8_t eosp; + uint8_t rate; + uint8_t intel_proxim; + uint8_t retry_ctrl; + struct sta_info *psta; }; typedef struct sk_buff _pkt; -struct _XIMT_BUF_ -{ - uint32_t AllocatBufAddr; - uint32_t BufAddr; - uint32_t BufLen; +struct _XIMT_BUF_ { + uint32_t AllocatBufAddr; + uint32_t BufAddr; + uint32_t BufLen; }; typedef struct _XIMT_BUF_ XIMT_BUF; -struct __attribute__((aligned(4))) xmit_frame -{ - _list list; - struct pkt_attrib attrib; - _pkt *pkt; - int frame_tag; - _adapter *padapter; - uint8_t *buf_addr; - struct xmit_buf *pxmitbuf; - uint32_t TxDexAddr; - uint32_t HdrLen; - uint32_t PayLoadAddr; - uint32_t PayLoadLen; - uint32_t TotalLen; - uint32_t BlockNum; - XIMT_BUF BufInfo[4]; - BOOLEAN NoCoalesce; +struct _atr_aligned4_ xmit_frame { + _list list; + struct pkt_attrib attrib; + _pkt *pkt; + int frame_tag; + _adapter *padapter; + uint8_t *buf_addr; + struct xmit_buf *pxmitbuf; + uint32_t TxDexAddr; + uint32_t HdrLen; + uint32_t PayLoadAddr; + uint32_t PayLoadLen; + uint32_t TotalLen; + uint32_t BlockNum; + XIMT_BUF BufInfo[4]; + BOOLEAN NoCoalesce; }; -struct xmit_buf -{ - _list list; - _adapter *padapter; - _pkt *pkt; - uint8_t *pbuf; - void *priv_data; - uint16_t buf_tag; - uint16_t flags; - uint32_t alloc_sz; - uint32_t len; - struct submit_ctx *sctx; - XIMT_BUF BufInfo[4]; - uint32_t BlockNum; +struct xmit_buf { + _list list; + _adapter *padapter; + _pkt *pkt; + uint8_t *pbuf; + void *priv_data; + uint16_t buf_tag; + uint16_t flags; + uint32_t alloc_sz; + uint32_t len; + struct submit_ctx *sctx; + XIMT_BUF BufInfo[4]; + uint32_t BlockNum; }; -struct submit_ctx -{ - uint32_t submit_time; - uint32_t timeout_ms; - int status; +struct submit_ctx { + uint32_t submit_time; + uint32_t timeout_ms; + int status; }; /* -// wrapper.h -struct net_device -{ - char name[16]; - void *priv; - unsigned __int8 dev_addr[6]; - int (*init)(void); - int (*open)(struct net_device *); - int (*stop)(struct net_device *); - int (*hard_start_xmit)(struct sk_buff *, struct net_device *); - int (*do_ioctl)(struct net_device *, struct iwreq *, int); - struct net_device_stats *(*get_stats)(struct net_device *); -}; -*/ + // wrapper.h + struct net_device + { + char name[16]; + void *priv; + uint8_t dev_addr[6]; + int (*init)(void); + int (*open)(struct net_device *); + int (*stop)(struct net_device *); + int (*hard_start_xmit)(struct sk_buff *, struct net_device *); + int (*do_ioctl)(struct net_device *, struct iwreq *, int); + struct net_device_stats *(*get_stats)(struct net_device *); + }; + */ /* -// wireless.h -struct iw_point -{ - void *pointer; - __u16 length; - __u16 flags; -}; + // wireless.h + struct iw_point + { + void *pointer; + uint16_t length; + uint16_t flags; + }; -struct iw_param -{ - __s32 value; - __u8 fixed; - __u8 disabled; - __u16 flags; -}; + struct iw_param + { + sint32_t value; + uint8_t fixed; + uint8_t disabled; + uint16_t flags; + }; -struct iw_freq -{ - __s32 m; - __s16 e; - __u8 i; - __u8 flags; + struct iw_freq + { + sint32_t m; + sint16_t e; + uint8_t i; + uint8_t flags; + }; + + struct iw_quality + { + uint8_t qual; + uint8_t level; + uint8_t noise; + uint8_t updated; + }; + + struct sockaddr_t + { + uint8_t sa_len; + uint8_t sa_family; + char sa_data[14]; + }; + + union iwreq_data + { + char name[16]; + struct iw_point essid; + struct iw_param nwid; + struct iw_freq freq; + struct iw_param sens; + struct iw_param bitrate; + struct iw_param txpower; + struct iw_param rts; + struct iw_param frag; + uint32_t mode; + struct iw_param retry; + struct iw_point encoding; + struct iw_param power; + struct iw_quality qual; + struct sockaddr_t ap_addr; + struct sockaddr_t addr; + struct iw_param param; + struct iw_point data; + struct iw_point passphrase; + }; + + struct iwreq + { + char ifr_name[16]; + union iwreq_data u; + }; + */ +struct co_data_priv { + uint8_t co_ch; + uint8_t co_bw; + uint8_t co_ch_offset; + uint8_t rsvd; }; -struct iw_quality +enum _HARDWARE_TYPE // : sint32_t { - __u8 qual; - __u8 level; - __u8 noise; - __u8 updated; + HARDWARE_TYPE_RTL8180 = 0x0, + HARDWARE_TYPE_RTL8185 = 0x1, + HARDWARE_TYPE_RTL8187 = 0x2, + HARDWARE_TYPE_RTL8188 = 0x3, + HARDWARE_TYPE_RTL8190P = 0x4, + HARDWARE_TYPE_RTL8192E = 0x5, + HARDWARE_TYPE_RTL819xU = 0x6, + HARDWARE_TYPE_RTL8192SE = 0x7, + HARDWARE_TYPE_RTL8192SU = 0x8, + HARDWARE_TYPE_RTL8192CE = 0x9, + HARDWARE_TYPE_RTL8192CU = 0xA, + HARDWARE_TYPE_RTL8192DE = 0xB, + HARDWARE_TYPE_RTL8192DU = 0xC, + HARDWARE_TYPE_RTL8723AE = 0xD, + HARDWARE_TYPE_RTL8723AU = 0xE, + HARDWARE_TYPE_RTL8723AS = 0xF, + HARDWARE_TYPE_RTL8188EE = 0x10, + HARDWARE_TYPE_RTL8188EU = 0x11, + HARDWARE_TYPE_RTL8188ES = 0x12, + HARDWARE_TYPE_RTL8192EE = 0x13, + HARDWARE_TYPE_RTL8192EU = 0x14, + HARDWARE_TYPE_RTL8192ES = 0x15, + HARDWARE_TYPE_RTL8812E = 0x16, + HARDWARE_TYPE_RTL8812AU = 0x17, + HARDWARE_TYPE_RTL8811AU = 0x18, + HARDWARE_TYPE_RTL8821E = 0x19, + HARDWARE_TYPE_RTL8821U = 0x1A, + HARDWARE_TYPE_RTL8821S = 0x1B, + HARDWARE_TYPE_RTL8723BE = 0x1C, + HARDWARE_TYPE_RTL8723BU = 0x1D, + HARDWARE_TYPE_RTL8723BS = 0x1E, + HARDWARE_TYPE_RTL8195A = 0x1F, + HARDWARE_TYPE_RTL8711B = 0x20, + HARDWARE_TYPE_RTL8188FE = 0x21, + HARDWARE_TYPE_RTL8188FU = 0x22, + HARDWARE_TYPE_RTL8188FS = 0x23, + HARDWARE_TYPE_MAX = 0x24, }; -struct sockaddr_t -{ - __u8 sa_len; - __u8 sa_family; - char sa_data[14]; -}; - -union iwreq_data -{ - char name[16]; - struct iw_point essid; - struct iw_param nwid; - struct iw_freq freq; - struct iw_param sens; - struct iw_param bitrate; - struct iw_param txpower; - struct iw_param rts; - struct iw_param frag; - __u32 mode; - struct iw_param retry; - struct iw_point encoding; - struct iw_param power; - struct iw_quality qual; - struct sockaddr_t ap_addr; - struct sockaddr_t addr; - struct iw_param param; - struct iw_point data; - struct iw_point passphrase; -}; - -struct iwreq -{ - char ifr_name[16]; - union iwreq_data u; -}; -*/ -struct co_data_priv -{ - uint8_t co_ch; - uint8_t co_bw; - uint8_t co_ch_offset; - uint8_t rsvd; -}; - -enum _HARDWARE_TYPE // : __int32 -{ - HARDWARE_TYPE_RTL8180 = 0x0, - HARDWARE_TYPE_RTL8185 = 0x1, - HARDWARE_TYPE_RTL8187 = 0x2, - HARDWARE_TYPE_RTL8188 = 0x3, - HARDWARE_TYPE_RTL8190P = 0x4, - HARDWARE_TYPE_RTL8192E = 0x5, - HARDWARE_TYPE_RTL819xU = 0x6, - HARDWARE_TYPE_RTL8192SE = 0x7, - HARDWARE_TYPE_RTL8192SU = 0x8, - HARDWARE_TYPE_RTL8192CE = 0x9, - HARDWARE_TYPE_RTL8192CU = 0xA, - HARDWARE_TYPE_RTL8192DE = 0xB, - HARDWARE_TYPE_RTL8192DU = 0xC, - HARDWARE_TYPE_RTL8723AE = 0xD, - HARDWARE_TYPE_RTL8723AU = 0xE, - HARDWARE_TYPE_RTL8723AS = 0xF, - HARDWARE_TYPE_RTL8188EE = 0x10, - HARDWARE_TYPE_RTL8188EU = 0x11, - HARDWARE_TYPE_RTL8188ES = 0x12, - HARDWARE_TYPE_RTL8192EE = 0x13, - HARDWARE_TYPE_RTL8192EU = 0x14, - HARDWARE_TYPE_RTL8192ES = 0x15, - HARDWARE_TYPE_RTL8812E = 0x16, - HARDWARE_TYPE_RTL8812AU = 0x17, - HARDWARE_TYPE_RTL8811AU = 0x18, - HARDWARE_TYPE_RTL8821E = 0x19, - HARDWARE_TYPE_RTL8821U = 0x1A, - HARDWARE_TYPE_RTL8821S = 0x1B, - HARDWARE_TYPE_RTL8723BE = 0x1C, - HARDWARE_TYPE_RTL8723BU = 0x1D, - HARDWARE_TYPE_RTL8723BS = 0x1E, - HARDWARE_TYPE_RTL8195A = 0x1F, - HARDWARE_TYPE_RTL8711B = 0x20, - HARDWARE_TYPE_RTL8188FE = 0x21, - HARDWARE_TYPE_RTL8188FU = 0x22, - HARDWARE_TYPE_RTL8188FS = 0x23, - HARDWARE_TYPE_MAX = 0x24, -}; - -struct RF_Shadow_Compare_Map -{ - uint32_t Value; - uint8_t Compare; - uint8_t ErrorOrNot; - uint8_t Recorver; - uint8_t Driver_Write; +struct RF_Shadow_Compare_Map { + uint32_t Value; + uint8_t Compare; + uint8_t ErrorOrNot; + uint8_t Recorver; + uint8_t Driver_Write; }; typedef struct RF_Shadow_Compare_Map RF_SHADOW_T; -enum _PS_BBRegBackup_ // : __int32 +enum _PS_BBRegBackup_ // : sint32_t { - PSBBREG_RF0 = 0x0, - PSBBREG_RF1 = 0x1, - PSBBREG_RF2 = 0x2, - PSBBREG_AFE0 = 0x3, - PSBBREG_TOTALCNT = 0x4, + PSBBREG_RF0 = 0x0, + PSBBREG_RF1 = 0x1, + PSBBREG_RF2 = 0x2, + PSBBREG_AFE0 = 0x3, + PSBBREG_TOTALCNT = 0x4, }; /* -// hal_irqn.h -enum _IRQn_Type_ // : __int32 -{ - NonMaskableInt_IRQn = 0xFFFFFFF2, - HardFault_IRQn = 0xFFFFFFF3, - MemoryManagement_IRQn = 0xFFFFFFF4, - BusFault_IRQn = 0xFFFFFFF5, - UsageFault_IRQn = 0xFFFFFFF6, - SVCall_IRQn = 0xFFFFFFFB, - DebugMonitor_IRQn = 0xFFFFFFFC, - PendSV_IRQn = 0xFFFFFFFE, - SysTick_IRQn = 0xFFFFFFFF, - SYSTEM_ON_IRQ = 0x0, - WDG_IRQ = 0x1, - TIMER0_IRQ = 0x2, - TIMER1_IRQ = 0x3, - I2C3_IRQ = 0x4, - TIMER2_7_IRQ = 0x5, - SPI0_IRQ = 0x6, - GPIO_IRQ = 0x7, - UART0_IRQ = 0x8, - SPI_FLASH_IRQ = 0x9, - USB_OTG_IRQ = 0xA, - SDIO_HOST_IRQ = 0xB, - SDIO_DEVICE_IRQ = 0xC, - I2S0_PCM0_IRQ = 0xD, - I2S1_PCM1_IRQ = 0xE, - WL_DMA_IRQ = 0xF, - WL_PROTOCOL_IRQ = 0x10, - CRYPTO_IRQ = 0x11, - GMAC_IRQ = 0x12, - PERIPHERAL_IRQ = 0x13, - GDMA0_CHANNEL0_IRQ = 0x14, - GDMA0_CHANNEL1_IRQ = 0x15, - GDMA0_CHANNEL2_IRQ = 0x16, - GDMA0_CHANNEL3_IRQ = 0x17, - GDMA0_CHANNEL4_IRQ = 0x18, - GDMA0_CHANNEL5_IRQ = 0x19, - GDMA1_CHANNEL0_IRQ = 0x1A, - GDMA1_CHANNEL1_IRQ = 0x1B, - GDMA1_CHANNEL2_IRQ = 0x1C, - GDMA1_CHANNEL3_IRQ = 0x1D, - GDMA1_CHANNEL4_IRQ = 0x1E, - GDMA1_CHANNEL5_IRQ = 0x1F, - I2C0_IRQ = 0x40, - I2C1_IRQ = 0x41, - I2C2_IRQ = 0x42, - SPI1_IRQ = 0x48, - SPI2_IRQ = 0x49, - UART1_IRQ = 0x50, - UART2_IRQ = 0x51, - UART_LOG_IRQ = 0x58, - ADC_IRQ = 0x59, - DAC0_IRQ = 0x5B, - DAC1_IRQ = 0x5C, - LP_EXTENSION_IRQ = 0x5D, - PTA_TRX_IRQ = 0x5F, - RXI300_IRQ = 0x60, - NFC_IRQ = 0x61, -}; + // hal_irqn.h + enum _IRQn_Type_ // : sint32_t + { + NonMaskableInt_IRQn = 0xFFFFFFF2, + HardFault_IRQn = 0xFFFFFFF3, + MemoryManagement_IRQn = 0xFFFFFFF4, + BusFault_IRQn = 0xFFFFFFF5, + UsageFault_IRQn = 0xFFFFFFF6, + SVCall_IRQn = 0xFFFFFFFB, + DebugMonitor_IRQn = 0xFFFFFFFC, + PendSV_IRQn = 0xFFFFFFFE, + SysTick_IRQn = 0xFFFFFFFF, + SYSTEM_ON_IRQ = 0x0, + WDG_IRQ = 0x1, + TIMER0_IRQ = 0x2, + TIMER1_IRQ = 0x3, + I2C3_IRQ = 0x4, + TIMER2_7_IRQ = 0x5, + SPI0_IRQ = 0x6, + GPIO_IRQ = 0x7, + UART0_IRQ = 0x8, + SPI_FLASH_IRQ = 0x9, + USB_OTG_IRQ = 0xA, + SDIO_HOST_IRQ = 0xB, + SDIO_DEVICE_IRQ = 0xC, + I2S0_PCM0_IRQ = 0xD, + I2S1_PCM1_IRQ = 0xE, + WL_DMA_IRQ = 0xF, + WL_PROTOCOL_IRQ = 0x10, + CRYPTO_IRQ = 0x11, + GMAC_IRQ = 0x12, + PERIPHERAL_IRQ = 0x13, + GDMA0_CHANNEL0_IRQ = 0x14, + GDMA0_CHANNEL1_IRQ = 0x15, + GDMA0_CHANNEL2_IRQ = 0x16, + GDMA0_CHANNEL3_IRQ = 0x17, + GDMA0_CHANNEL4_IRQ = 0x18, + GDMA0_CHANNEL5_IRQ = 0x19, + GDMA1_CHANNEL0_IRQ = 0x1A, + GDMA1_CHANNEL1_IRQ = 0x1B, + GDMA1_CHANNEL2_IRQ = 0x1C, + GDMA1_CHANNEL3_IRQ = 0x1D, + GDMA1_CHANNEL4_IRQ = 0x1E, + GDMA1_CHANNEL5_IRQ = 0x1F, + I2C0_IRQ = 0x40, + I2C1_IRQ = 0x41, + I2C2_IRQ = 0x42, + SPI1_IRQ = 0x48, + SPI2_IRQ = 0x49, + UART1_IRQ = 0x50, + UART2_IRQ = 0x51, + UART_LOG_IRQ = 0x58, + ADC_IRQ = 0x59, + DAC0_IRQ = 0x5B, + DAC1_IRQ = 0x5C, + LP_EXTENSION_IRQ = 0x5D, + PTA_TRX_IRQ = 0x5F, + RXI300_IRQ = 0x60, + NFC_IRQ = 0x61, + }; -typedef enum _IRQn_Type_ IRQn_Type; + typedef enum _IRQn_Type_ IRQn_Type; -typedef void (*IRQ_FUN)(void *); + typedef void (*IRQ_FUN)(void *); -struct _IRQ_HANDLE_ -{ - IRQ_FUN IrqFun; - IRQn_Type IrqNum; - uint32_t Data; - uint32_t Priority; -}; -typedef struct _IRQ_HANDLE_ IRQ_HANDLE; -*/ + struct _IRQ_HANDLE_ + { + IRQ_FUN IrqFun; + IRQn_Type IrqNum; + uint32_t Data; + uint32_t Priority; + }; + typedef struct _IRQ_HANDLE_ IRQ_HANDLE; + */ /* -// hal_soc_ps_monitor.h -struct _power_state_ -{ - uint8_t FuncIdx; - uint8_t PowerState; + // hal_soc_ps_monitor.h + struct _power_state_ + { + uint8_t FuncIdx; + uint8_t PowerState; + }; + + typedef struct _power_state_ POWER_STATE; + + struct _atr_aligned4_ _power_mgn_ + { + uint8_t ActFuncCount; + POWER_STATE PwrState[10]; + uint8_t CurrentState; + uint8_t SDREn; + uint32_t MSPbackup[129]; + uint32_t CPURegbackup[25]; + uint32_t CPUPSP; + uint32_t WakeEventFlag; + BOOL SleepFlag; + }; + typedef struct _power_mgn_ Power_Mgn; + + /* + // hal_gpio.h + enum $E1AD70AB12E7AA6E98B8D89D9B965EB5 //: sint32_t + { + _PORT_A = 0x0, + _PORT_B = 0x1, + _PORT_C = 0x2, + _PORT_D = 0x3, + _PORT_E = 0x4, + _PORT_F = 0x5, + _PORT_G = 0x6, + _PORT_H = 0x7, + _PORT_I = 0x8, + _PORT_J = 0x9, + _PORT_K = 0xA, + _PORT_MAX = 0xB, + }; + + typedef void (*GPIO_IRQ_FUN)(void *, uint32_t); + + typedef void (*GPIO_USER_IRQ_FUN)(uint32_t); + + struct _atr_aligned4_ _HAL_GPIO_ADAPTER_ + { + IRQ_HANDLE IrqHandle; + GPIO_USER_IRQ_FUN UserIrqHandler; + GPIO_IRQ_FUN PortA_IrqHandler[32]; + void *PortA_IrqData[32]; + void (*EnterCritical)(void); + void (*ExitCritical)(void); + uint32_t Local_Gpio_Dir[3]; + uint8_t Gpio_Func_En; + uint8_t Locked; + }; + typedef struct _HAL_GPIO_ADAPTER_ *PHAL_GPIO_ADAPTER; + */ + +struct hal_ops { + uint32_t (*hal_power_on)(_adapter *); + uint32_t (*hal_init)(_adapter *); + uint32_t (*hal_deinit)(_adapter *); + void (*free_hal_data)(_adapter *); + uint32_t (*inirp_init)(_adapter *); + uint32_t (*inirp_deinit)(_adapter *); + void (*irp_reset)(_adapter *); + int32_t (*init_xmit_priv)(_adapter *); + void (*free_xmit_priv)(_adapter *); + int32_t (*init_recv_priv)(_adapter *); + void (*free_recv_priv)(_adapter *); + void (*update_txdesc)(struct xmit_frame *, uint8_t *); + void (*InitSwLeds)(_adapter *); + void (*DeInitSwLeds)(_adapter *); + void (*dm_init)(_adapter *); + void (*dm_deinit)(_adapter *); + void (*read_chip_version)(_adapter *); + void (*init_default_value)(_adapter *); + void (*intf_chip_configure)(_adapter *); + void (*read_adapter_info)(_adapter *); + void (*enable_interrupt)(_adapter *); + void (*disable_interrupt)(_adapter *); + int32_t (*interrupt_handler)(_adapter *); + void (*set_bwmode_handler)(_adapter *, CHANNEL_WIDTH, uint8_t); + void (*set_channel_handler)(_adapter *, uint8_t); + void (*set_chnl_bw_handler)(_adapter *, uint8_t, CHANNEL_WIDTH, uint8_t, + uint8_t); + void (*hal_dm_watchdog)(_adapter *); + void (*SetHwRegHandler)(_adapter *, uint8_t, uint8_t *); + void (*GetHwRegHandler)(_adapter *, uint8_t, uint8_t *); + uint8_t (*GetHalDefVarHandler)(_adapter *, HAL_DEF_VARIABLE, PVOID); + uint8_t (*SetHalDefVarHandler)(_adapter *, HAL_DEF_VARIABLE, PVOID); + void (*GetHalODMVarHandler)(_adapter *, HAL_ODM_VARIABLE, PVOID, BOOLEAN); + void (*SetHalODMVarHandler)(_adapter *, HAL_ODM_VARIABLE, PVOID, BOOLEAN); + void (*UpdateRAMaskHandler)(_adapter *, uint32_t, uint8_t); + void (*Add_RateATid)(_adapter *, uint32_t, uint8_t *, uint8_t); + void (*clone_haldata)(_adapter *, _adapter *); + void (*run_thread)(_adapter *); + void (*cancel_thread)(_adapter *); + int32_t (*hal_xmit)(_adapter *, struct xmit_frame *); + int32_t (*mgnt_xmit)(_adapter *, struct xmit_frame *); + uint32_t (*read_bbreg)(_adapter *, uint32_t, uint32_t); + void (*write_bbreg)(_adapter *, uint32_t, uint32_t, uint32_t); + uint32_t (*read_rfreg)(_adapter *, uint32_t, uint32_t, uint32_t); + void (*write_rfreg)(_adapter *, uint32_t, uint32_t, uint32_t, uint32_t); + void (*EfusePowerSwitch)(_adapter *, uint8_t, uint8_t); + void (*ReadEFuse)(_adapter *, uint8_t, uint16_t, uint16_t, uint8_t *, + BOOLEAN); + void (*EFUSEGetEfuseDefinition)(_adapter *, uint8_t, uint8_t, void *, + BOOLEAN); + uint16_t (*EfuseGetCurrentSize)(_adapter *, uint8_t, BOOLEAN); + int (*Efuse_PgPacketWrite)(_adapter *, uint8_t, uint8_t, uint8_t *, + BOOLEAN); + uint8_t (*Efuse_WordEnableDataWrite)(_adapter *, uint16_t, uint8_t, + uint8_t *, BOOLEAN); + void (*recv_tasklet)(void *); + int32_t (*fill_h2c_cmd)(_adapter *, uint8_t, uint32_t, uint8_t *); + void (*fill_fake_txdesc)(_adapter *, uint8_t *, uint32_t, uint8_t, uint8_t, + uint8_t); + uint8_t (*hal_get_tx_buff_rsvd_page_num)(_adapter *, bool); }; -typedef struct _power_state_ POWER_STATE; - -struct __attribute__((aligned(4))) _power_mgn_ -{ - uint8_t ActFuncCount; - POWER_STATE PwrState[10]; - uint8_t CurrentState; - uint8_t SDREn; - uint32_t MSPbackup[129]; - uint32_t CPURegbackup[25]; - uint32_t CPUPSP; - uint32_t WakeEventFlag; - BOOL SleepFlag; -}; -typedef struct _power_mgn_ Power_Mgn; - -/* -// hal_gpio.h -enum $E1AD70AB12E7AA6E98B8D89D9B965EB5 //: __int32 -{ - _PORT_A = 0x0, - _PORT_B = 0x1, - _PORT_C = 0x2, - _PORT_D = 0x3, - _PORT_E = 0x4, - _PORT_F = 0x5, - _PORT_G = 0x6, - _PORT_H = 0x7, - _PORT_I = 0x8, - _PORT_J = 0x9, - _PORT_K = 0xA, - _PORT_MAX = 0xB, -}; - -typedef void (*GPIO_IRQ_FUN)(void *, uint32_t); - -typedef void (*GPIO_USER_IRQ_FUN)(uint32_t); - -struct __attribute__((aligned(4))) _HAL_GPIO_ADAPTER_ -{ - IRQ_HANDLE IrqHandle; - GPIO_USER_IRQ_FUN UserIrqHandler; - GPIO_IRQ_FUN PortA_IrqHandler[32]; - void *PortA_IrqData[32]; - void (*EnterCritical)(void); - void (*ExitCritical)(void); - uint32_t Local_Gpio_Dir[3]; - uint8_t Gpio_Func_En; - uint8_t Locked; -}; -typedef struct _HAL_GPIO_ADAPTER_ *PHAL_GPIO_ADAPTER; -*/ - - -struct hal_ops -{ - uint32_t (*hal_power_on)(_adapter *); - uint32_t (*hal_init)(_adapter *); - uint32_t (*hal_deinit)(_adapter *); - void (*free_hal_data)(_adapter *); - uint32_t (*inirp_init)(_adapter *); - uint32_t (*inirp_deinit)(_adapter *); - void (*irp_reset)(_adapter *); - int32_t (*init_xmit_priv)(_adapter *); - void (*free_xmit_priv)(_adapter *); - int32_t (*init_recv_priv)(_adapter *); - void (*free_recv_priv)(_adapter *); - void (*update_txdesc)(struct xmit_frame *, uint8_t *); - void (*InitSwLeds)(_adapter *); - void (*DeInitSwLeds)(_adapter *); - void (*dm_init)(_adapter *); - void (*dm_deinit)(_adapter *); - void (*read_chip_version)(_adapter *); - void (*init_default_value)(_adapter *); - void (*intf_chip_configure)(_adapter *); - void (*read_adapter_info)(_adapter *); - void (*enable_interrupt)(_adapter *); - void (*disable_interrupt)(_adapter *); - int32_t (*interrupt_handler)(_adapter *); - void (*set_bwmode_handler)(_adapter *, CHANNEL_WIDTH, uint8_t); - void (*set_channel_handler)(_adapter *, uint8_t); - void (*set_chnl_bw_handler)(_adapter *, uint8_t, CHANNEL_WIDTH, uint8_t, uint8_t); - void (*hal_dm_watchdog)(_adapter *); - void (*SetHwRegHandler)(_adapter *, uint8_t, uint8_t *); - void (*GetHwRegHandler)(_adapter *, uint8_t, uint8_t *); - uint8_t (*GetHalDefVarHandler)(_adapter *, HAL_DEF_VARIABLE, PVOID); - uint8_t (*SetHalDefVarHandler)(_adapter *, HAL_DEF_VARIABLE, PVOID); - void (*GetHalODMVarHandler)(_adapter *, HAL_ODM_VARIABLE, PVOID, BOOLEAN); - void (*SetHalODMVarHandler)(_adapter *, HAL_ODM_VARIABLE, PVOID, BOOLEAN); - void (*UpdateRAMaskHandler)(_adapter *, uint32_t, uint8_t); - void (*Add_RateATid)(_adapter *, uint32_t, uint8_t *, uint8_t); - void (*clone_haldata)(_adapter *, _adapter *); - void (*run_thread)(_adapter *); - void (*cancel_thread)(_adapter *); - int32_t (*hal_xmit)(_adapter *, struct xmit_frame *); - int32_t (*mgnt_xmit)(_adapter *, struct xmit_frame *); - uint32_t (*read_bbreg)(_adapter *, uint32_t, uint32_t); - void (*write_bbreg)(_adapter *, uint32_t, uint32_t, uint32_t); - uint32_t (*read_rfreg)(_adapter *, uint32_t, uint32_t, uint32_t); - void (*write_rfreg)(_adapter *, uint32_t, uint32_t, uint32_t, uint32_t); - void (*EfusePowerSwitch)(_adapter *, uint8_t, uint8_t); - void (*ReadEFuse)(_adapter *, uint8_t, uint16_t, uint16_t, uint8_t *, BOOLEAN); - void (*EFUSEGetEfuseDefinition)(_adapter *, uint8_t, uint8_t, void *, BOOLEAN); - uint16_t (*EfuseGetCurrentSize)(_adapter *, uint8_t, BOOLEAN); - int (*Efuse_PgPacketWrite)(_adapter *, uint8_t, uint8_t, uint8_t *, BOOLEAN); - uint8_t (*Efuse_WordEnableDataWrite)(_adapter *, uint16_t, uint8_t, uint8_t *, BOOLEAN); - void (*recv_tasklet)(void *); - int32_t (*fill_h2c_cmd)(_adapter *, uint8_t, uint32_t, uint8_t *); - void (*fill_fake_txdesc)(_adapter *, uint8_t *, uint32_t, uint8_t, uint8_t, uint8_t); - uint8_t (*hal_get_tx_buff_rsvd_page_num)(_adapter *, bool); -}; - -struct __attribute__((aligned(4))) _ADAPTER -{ - uint16_t HardwareType; - uint16_t interface_type; - uint32_t work_mode; - struct dvobj_priv *dvobj; - struct mlme_priv mlmepriv; - struct mlme_ext_priv mlmeextpriv; - struct cmd_priv cmdpriv; - struct evt_priv evtpriv; - struct io_priv iopriv; - struct xmit_priv xmitpriv; - struct recv_priv recvpriv; - struct sta_priv stapriv; - struct security_priv securitypriv; - struct registry_priv registrypriv; - struct pwrctrl_priv pwrctrlpriv; - struct eeprom_priv eeprompriv; - PVOID HalData; - uint32_t hal_data_sz; - struct hal_ops HalFunc; - int32_t bDriverStopped; - int32_t bSurpriseRemoved; - int32_t bCardDisableWOHSM; - uint8_t RxStop; - uint32_t IsrContent; - uint32_t ImrContent; - uint8_t EepromAddressSize; - uint8_t hw_init_completed; - uint8_t bDriverIsGoingToUnload; - uint8_t init_adpt_in_progress; - uint8_t bMpDriver; - uint8_t bForwardingDisabled; - struct task_struct isrThread; - struct task_struct cmdThread; - struct task_struct recvtasklet_thread; - struct task_struct xmittasklet_thread; - void (*intf_start)(_adapter *); - void (*intf_stop)(_adapter *); - _nic_hdl pnetdev; - int bup; - struct net_device_stats stats; - uint8_t net_closed; - uint8_t bFWReady; - uint8_t bLinkInfoDump; - uint8_t bRxRSSIDisplay; - _adapter *pbuddy_adapter; - _mutex *hw_init_mutex; - uint8_t isprimary; - uint8_t adapter_type; - uint8_t iface_type; - _mutex *ph2c_fwcmd_mutex; - _mutex *psetch_mutex; - _mutex *psetbw_mutex; - struct co_data_priv *pcodatapriv; - uint8_t fix_rate; +struct _atr_aligned4_ _ADAPTER { + uint16_t HardwareType; + uint16_t interface_type; + uint32_t work_mode; + struct dvobj_priv *dvobj; + struct mlme_priv mlmepriv; + struct mlme_ext_priv mlmeextpriv; + struct cmd_priv cmdpriv; + struct evt_priv evtpriv; + struct io_priv iopriv; + struct xmit_priv xmitpriv; + struct recv_priv recvpriv; + struct sta_priv stapriv; + struct security_priv securitypriv; + struct registry_priv registrypriv; + struct pwrctrl_priv pwrctrlpriv; + struct eeprom_priv eeprompriv; + PVOID HalData; + uint32_t hal_data_sz; + struct hal_ops HalFunc; + int32_t bDriverStopped; + int32_t bSurpriseRemoved; + int32_t bCardDisableWOHSM; + uint8_t RxStop; + uint32_t IsrContent; + uint32_t ImrContent; + uint8_t EepromAddressSize; + uint8_t hw_init_completed; + uint8_t bDriverIsGoingToUnload; + uint8_t init_adpt_in_progress; + uint8_t bMpDriver; + uint8_t bForwardingDisabled; + struct task_struct isrThread; + struct task_struct cmdThread; + struct task_struct recvtasklet_thread; + struct task_struct xmittasklet_thread; + void (*intf_start)(_adapter *); + void (*intf_stop)(_adapter *); + _nic_hdl pnetdev; + int bup; + struct net_device_stats stats; + uint8_t net_closed; + uint8_t bFWReady; + uint8_t bLinkInfoDump; + uint8_t bRxRSSIDisplay; + _adapter *pbuddy_adapter; + _mutex *hw_init_mutex; + uint8_t isprimary; + uint8_t adapter_type; + uint8_t iface_type; + _mutex *ph2c_fwcmd_mutex; + _mutex *psetch_mutex; + _mutex *psetbw_mutex; + struct co_data_priv *pcodatapriv; + uint8_t fix_rate; }; typedef struct _ADAPTER *PADAPTER; - -enum tag_HAL_IC_Type_Definition // : __int32 +enum tag_HAL_IC_Type_Definition // : sint32_t { - CHIP_8192S = 0x0, - CHIP_8188C = 0x1, - CHIP_8192C = 0x2, - CHIP_8192D = 0x3, - CHIP_8723A = 0x4, - CHIP_8188E = 0x5, - CHIP_8812 = 0x6, - CHIP_8821 = 0x7, - CHIP_8723B = 0x8, - CHIP_8192E = 0x9, - CHIP_8195A = 0xA, - CHIP_8711B = 0xB, - CHIP_8188F = 0xC, + CHIP_8192S = 0x0, + CHIP_8188C = 0x1, + CHIP_8192C = 0x2, + CHIP_8192D = 0x3, + CHIP_8723A = 0x4, + CHIP_8188E = 0x5, + CHIP_8812 = 0x6, + CHIP_8821 = 0x7, + CHIP_8723B = 0x8, + CHIP_8192E = 0x9, + CHIP_8195A = 0xA, + CHIP_8711B = 0xB, + CHIP_8188F = 0xC, }; typedef enum tag_HAL_IC_Type_Definition HAL_IC_TYPE_E; -enum tag_HAL_CHIP_Type_Definition // : __int32 +enum tag_HAL_CHIP_Type_Definition // : sint32_t { - TEST_CHIP = 0x0, - NORMAL_CHIP = 0x1, - FPGA = 0x2, + TEST_CHIP = 0x0, NORMAL_CHIP = 0x1, FPGA = 0x2, }; typedef enum tag_HAL_CHIP_Type_Definition HAL_CHIP_TYPE_E; - -enum tag_HAL_Cut_Version_Definition // : __int32 +enum tag_HAL_Cut_Version_Definition // : sint32_t { - A_CUT_VERSION = 0x0, - B_CUT_VERSION = 0x1, - C_CUT_VERSION = 0x2, - D_CUT_VERSION = 0x3, - E_CUT_VERSION = 0x4, - F_CUT_VERSION = 0x5, - G_CUT_VERSION = 0x6, - H_CUT_VERSION = 0x7, - I_CUT_VERSION = 0x8, - J_CUT_VERSION = 0x9, - K_CUT_VERSION = 0xA, + A_CUT_VERSION = 0x0, + B_CUT_VERSION = 0x1, + C_CUT_VERSION = 0x2, + D_CUT_VERSION = 0x3, + E_CUT_VERSION = 0x4, + F_CUT_VERSION = 0x5, + G_CUT_VERSION = 0x6, + H_CUT_VERSION = 0x7, + I_CUT_VERSION = 0x8, + J_CUT_VERSION = 0x9, + K_CUT_VERSION = 0xA, }; typedef enum tag_HAL_Cut_Version_Definition HAL_CUT_VERSION_E; - -enum tag_HAL_Manufacturer_Version_Definition //: __int32 +enum tag_HAL_Manufacturer_Version_Definition //: sint32_t { - CHIP_VENDOR_TSMC = 0x0, - CHIP_VENDOR_UMC = 0x1, - CHIP_VENDOR_SMIC = 0x2, + CHIP_VENDOR_TSMC = 0x0, CHIP_VENDOR_UMC = 0x1, CHIP_VENDOR_SMIC = 0x2, }; typedef enum tag_HAL_Manufacturer_Version_Definition HAL_VENDOR_E; -enum tag_HAL_RF_Type_Definition //: __int32 +enum tag_HAL_RF_Type_Definition //: sint32_t { - RF_TYPE_1T1R = 0x0, - RF_TYPE_1T2R = 0x1, - RF_TYPE_2T2R = 0x2, - RF_TYPE_2T3R = 0x3, - RF_TYPE_2T4R = 0x4, - RF_TYPE_3T3R = 0x5, - RF_TYPE_3T4R = 0x6, - RF_TYPE_4T4R = 0x7, + RF_TYPE_1T1R = 0x0, + RF_TYPE_1T2R = 0x1, + RF_TYPE_2T2R = 0x2, + RF_TYPE_2T3R = 0x3, + RF_TYPE_2T4R = 0x4, + RF_TYPE_3T3R = 0x5, + RF_TYPE_3T4R = 0x6, + RF_TYPE_4T4R = 0x7, }; typedef enum tag_HAL_RF_Type_Definition HAL_RF_TYPE_E; -struct __attribute__((aligned(4))) tag_HAL_VERSION -{ - HAL_IC_TYPE_E ICType; - HAL_CHIP_TYPE_E ChipType; - HAL_CUT_VERSION_E CUTVersion; - HAL_VENDOR_E VendorType; - HAL_RF_TYPE_E RFType; - uint8_t ROMVer; +struct _atr_aligned4_ tag_HAL_VERSION { + HAL_IC_TYPE_E ICType; + HAL_CHIP_TYPE_E ChipType; + HAL_CUT_VERSION_E CUTVersion; + HAL_VENDOR_E VendorType; + HAL_RF_TYPE_E RFType; + uint8_t ROMVer; }; typedef struct tag_HAL_VERSION HAL_VERSION; -enum _HW_VARIABLES //: __int32 +enum _HW_VARIABLES //: sint32_t { - HW_VAR_MEDIA_STATUS = 0x0, - HW_VAR_MEDIA_STATUS1 = 0x1, - HW_VAR_SET_OPMODE = 0x2, - HW_VAR_MAC_ADDR = 0x3, - HW_VAR_BSSID = 0x4, - HW_VAR_INIT_RTS_RATE = 0x5, - HW_VAR_BASIC_RATE = 0x6, - HW_VAR_TXPAUSE = 0x7, - HW_VAR_BCN_FUNC = 0x8, - HW_VAR_CORRECT_TSF = 0x9, - HW_VAR_CHECK_BSSID = 0xA, - HW_VAR_MLME_DISCONNECT = 0xB, - HW_VAR_MLME_SITESURVEY = 0xC, - HW_VAR_MLME_JOIN = 0xD, - HW_VAR_ON_RCR_AM = 0xE, - HW_VAR_OFF_RCR_AM = 0xF, - HW_VAR_BEACON_INTERVAL = 0x10, - HW_VAR_SLOT_TIME = 0x11, - HW_VAR_RESP_SIFS = 0x12, - HW_VAR_ACK_PREAMBLE = 0x13, - HW_VAR_SEC_CFG = 0x14, - HW_VAR_SEC_DK_CFG = 0x15, - HW_VAR_RF_TYPE = 0x16, - HW_VAR_DM_FLAG = 0x17, - HW_VAR_DM_FUNC_OP = 0x18, - HW_VAR_DM_FUNC_SET = 0x19, - HW_VAR_DM_FUNC_CLR = 0x1A, - HW_VAR_CAM_EMPTY_ENTRY = 0x1B, - HW_VAR_CAM_INVALID_ALL = 0x1C, - HW_VAR_CAM_WRITE = 0x1D, - HW_VAR_CAM_READ = 0x1E, - HW_VAR_AC_PARAM_VO = 0x1F, - HW_VAR_AC_PARAM_VI = 0x20, - HW_VAR_AC_PARAM_BE = 0x21, - HW_VAR_AC_PARAM_BK = 0x22, - HW_VAR_ACM_CTRL = 0x23, - HW_VAR_AMPDU_MIN_SPACE = 0x24, - HW_VAR_AMPDU_FACTOR = 0x25, - HW_VAR_RXDMA_AGG_PG_TH = 0x26, - HW_VAR_SET_RPWM = 0x27, - HW_VAR_GET_RPWM = 0x28, - HW_VAR_CPWM = 0x29, - HW_VAR_H2C_FW_PWRMODE = 0x2A, - HW_VAR_H2C_PS_TUNE_PARAM = 0x2B, - HW_VAR_H2C_FW_JOINBSSRPT = 0x2C, - HW_VAR_FWLPS_RF_ON = 0x2D, - HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x2E, - HW_VAR_TDLS_WRCR = 0x2F, - HW_VAR_TDLS_INIT_CH_SEN = 0x30, - HW_VAR_TDLS_RS_RCR = 0x31, - HW_VAR_TDLS_DONE_CH_SEN = 0x32, - HW_VAR_INITIAL_GAIN = 0x33, - HW_VAR_TRIGGER_GPIO_0 = 0x34, - HW_VAR_CURRENT_ANTENNA = 0x35, - HW_VAR_ANTENNA_DIVERSITY_LINK = 0x36, - HW_VAR_ANTENNA_DIVERSITY_SELECT = 0x37, - HW_VAR_SWITCH_EPHY_WoWLAN = 0x38, - HW_VAR_EFUSE_USAGE = 0x39, - HW_VAR_EFUSE_BYTES = 0x3A, - HW_VAR_FIFO_CLEARN_UP = 0x3B, - HW_VAR_RESTORE_HW_SEQ = 0x3C, - HW_VAR_HCI_SUS_STATE = 0x3D, - HW_VAR_CHECK_TXBUF = 0x3E, - HW_VAR_APFM_ON_MAC = 0x3F, - HW_VAR_NAV_UPPER = 0x40, - HW_VAR_C2H_HANDLE = 0x41, - HW_VAR_RPT_TIMER_SETTING = 0x42, - HW_VAR_TX_RPT_MAX_MACID = 0x43, - HW_VAR_H2C_MEDIA_STATUS_RPT = 0x44, - HW_VAR_CHK_HI_QUEUE_EMPTY = 0x45, - HW_VAR_DL_BCN_SEL = 0x46, - HW_VAR_PORT_SWITCH = 0x47, - HW_VAR_DM_IN_LPS = 0x48, - HW_VAR_SET_REQ_FW_PS = 0x49, - HW_VAR_FW_PS_STATE = 0x4A, - HW_VAR_DL_RSVD_PAGE = 0x4B, - HW_VAR_MACID_SLEEP = 0x4C, - HW_VAR_MACID_WAKEUP = 0x4D, - HW_VAR_DUMP_MAC_QUEUE_INFO = 0x4E, - HW_VAR_ASIX_IOT = 0x4F, - HW_VAR_PROMISC = 0x50, + HW_VAR_MEDIA_STATUS = 0x0, + HW_VAR_MEDIA_STATUS1 = 0x1, + HW_VAR_SET_OPMODE = 0x2, + HW_VAR_MAC_ADDR = 0x3, + HW_VAR_BSSID = 0x4, + HW_VAR_INIT_RTS_RATE = 0x5, + HW_VAR_BASIC_RATE = 0x6, + HW_VAR_TXPAUSE = 0x7, + HW_VAR_BCN_FUNC = 0x8, + HW_VAR_CORRECT_TSF = 0x9, + HW_VAR_CHECK_BSSID = 0xA, + HW_VAR_MLME_DISCONNECT = 0xB, + HW_VAR_MLME_SITESURVEY = 0xC, + HW_VAR_MLME_JOIN = 0xD, + HW_VAR_ON_RCR_AM = 0xE, + HW_VAR_OFF_RCR_AM = 0xF, + HW_VAR_BEACON_INTERVAL = 0x10, + HW_VAR_SLOT_TIME = 0x11, + HW_VAR_RESP_SIFS = 0x12, + HW_VAR_ACK_PREAMBLE = 0x13, + HW_VAR_SEC_CFG = 0x14, + HW_VAR_SEC_DK_CFG = 0x15, + HW_VAR_RF_TYPE = 0x16, + HW_VAR_DM_FLAG = 0x17, + HW_VAR_DM_FUNC_OP = 0x18, + HW_VAR_DM_FUNC_SET = 0x19, + HW_VAR_DM_FUNC_CLR = 0x1A, + HW_VAR_CAM_EMPTY_ENTRY = 0x1B, + HW_VAR_CAM_INVALID_ALL = 0x1C, + HW_VAR_CAM_WRITE = 0x1D, + HW_VAR_CAM_READ = 0x1E, + HW_VAR_AC_PARAM_VO = 0x1F, + HW_VAR_AC_PARAM_VI = 0x20, + HW_VAR_AC_PARAM_BE = 0x21, + HW_VAR_AC_PARAM_BK = 0x22, + HW_VAR_ACM_CTRL = 0x23, + HW_VAR_AMPDU_MIN_SPACE = 0x24, + HW_VAR_AMPDU_FACTOR = 0x25, + HW_VAR_RXDMA_AGG_PG_TH = 0x26, + HW_VAR_SET_RPWM = 0x27, + HW_VAR_GET_RPWM = 0x28, + HW_VAR_CPWM = 0x29, + HW_VAR_H2C_FW_PWRMODE = 0x2A, + HW_VAR_H2C_PS_TUNE_PARAM = 0x2B, + HW_VAR_H2C_FW_JOINBSSRPT = 0x2C, + HW_VAR_FWLPS_RF_ON = 0x2D, + HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x2E, + HW_VAR_TDLS_WRCR = 0x2F, + HW_VAR_TDLS_INIT_CH_SEN = 0x30, + HW_VAR_TDLS_RS_RCR = 0x31, + HW_VAR_TDLS_DONE_CH_SEN = 0x32, + HW_VAR_INITIAL_GAIN = 0x33, + HW_VAR_TRIGGER_GPIO_0 = 0x34, + HW_VAR_CURRENT_ANTENNA = 0x35, + HW_VAR_ANTENNA_DIVERSITY_LINK = 0x36, + HW_VAR_ANTENNA_DIVERSITY_SELECT = 0x37, + HW_VAR_SWITCH_EPHY_WoWLAN = 0x38, + HW_VAR_EFUSE_USAGE = 0x39, + HW_VAR_EFUSE_BYTES = 0x3A, + HW_VAR_FIFO_CLEARN_UP = 0x3B, + HW_VAR_RESTORE_HW_SEQ = 0x3C, + HW_VAR_HCI_SUS_STATE = 0x3D, + HW_VAR_CHECK_TXBUF = 0x3E, + HW_VAR_APFM_ON_MAC = 0x3F, + HW_VAR_NAV_UPPER = 0x40, + HW_VAR_C2H_HANDLE = 0x41, + HW_VAR_RPT_TIMER_SETTING = 0x42, + HW_VAR_TX_RPT_MAX_MACID = 0x43, + HW_VAR_H2C_MEDIA_STATUS_RPT = 0x44, + HW_VAR_CHK_HI_QUEUE_EMPTY = 0x45, + HW_VAR_DL_BCN_SEL = 0x46, + HW_VAR_PORT_SWITCH = 0x47, + HW_VAR_DM_IN_LPS = 0x48, + HW_VAR_SET_REQ_FW_PS = 0x49, + HW_VAR_FW_PS_STATE = 0x4A, + HW_VAR_DL_RSVD_PAGE = 0x4B, + HW_VAR_MACID_SLEEP = 0x4C, + HW_VAR_MACID_WAKEUP = 0x4D, + HW_VAR_DUMP_MAC_QUEUE_INFO = 0x4E, + HW_VAR_ASIX_IOT = 0x4F, + HW_VAR_PROMISC = 0x50, }; - -enum _BAND_TYPE // : __int32 +enum _BAND_TYPE // : sint32_t { - BAND_ON_2_4G = 0x0, - BAND_ON_5G = 0x1, - BAND_ON_BOTH = 0x2, - BANDMAX = 0x3, + BAND_ON_2_4G = 0x0, BAND_ON_5G = 0x1, BAND_ON_BOTH = 0x2, BANDMAX = 0x3, }; typedef enum _BAND_TYPE BAND_TYPE; - -struct _BB_REGISTER_DEFINITION -{ - uint32_t rfintfs; - uint32_t rfintfo; - uint32_t rfintfe; - uint32_t rf3wireOffset; - uint32_t rfHSSIPara2; - uint32_t rfLSSIReadBack; - uint32_t rfLSSIReadBackPi; +struct _BB_REGISTER_DEFINITION { + uint32_t rfintfs; + uint32_t rfintfo; + uint32_t rfintfe; + uint32_t rf3wireOffset; + uint32_t rfHSSIPara2; + uint32_t rfLSSIReadBack; + uint32_t rfLSSIReadBackPi; }; typedef struct _BB_REGISTER_DEFINITION BB_REGISTER_DEFINITION_T; -enum dot11AuthAlgrthmNum //: __int32 +enum dot11AuthAlgrthmNum //: sint32_t { - dot11AuthAlgrthm_Open = 0x0, - dot11AuthAlgrthm_Shared = 0x1, - dot11AuthAlgrthm_8021X = 0x2, - dot11AuthAlgrthm_Auto = 0x3, - dot11AuthAlgrthm_WAPI = 0x4, - dot11AuthAlgrthm_MaxNum = 0x5, + dot11AuthAlgrthm_Open = 0x0, + dot11AuthAlgrthm_Shared = 0x1, + dot11AuthAlgrthm_8021X = 0x2, + dot11AuthAlgrthm_Auto = 0x3, + dot11AuthAlgrthm_WAPI = 0x4, + dot11AuthAlgrthm_MaxNum = 0x5, }; -enum _RT_CHANNEL_DOMAIN //: __int32 +enum _RT_CHANNEL_DOMAIN //: sint32_t { - RT_CHANNEL_DOMAIN_FCC = 0x0, - RT_CHANNEL_DOMAIN_IC = 0x1, - RT_CHANNEL_DOMAIN_ETSI = 0x2, - RT_CHANNEL_DOMAIN_SPAIN = 0x3, - RT_CHANNEL_DOMAIN_FRANCE = 0x4, - RT_CHANNEL_DOMAIN_MKK = 0x5, - RT_CHANNEL_DOMAIN_MKK1 = 0x6, - RT_CHANNEL_DOMAIN_ISRAEL = 0x7, - RT_CHANNEL_DOMAIN_TELEC = 0x8, - RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN = 0x9, - RT_CHANNEL_DOMAIN_WORLD_WIDE_13 = 0xA, - RT_CHANNEL_DOMAIN_TAIWAN = 0xB, - RT_CHANNEL_DOMAIN_CHINA = 0xC, - RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO = 0xD, - RT_CHANNEL_DOMAIN_KOREA = 0xE, - RT_CHANNEL_DOMAIN_TURKEY = 0xF, - RT_CHANNEL_DOMAIN_JAPAN = 0x10, - RT_CHANNEL_DOMAIN_FCC_NO_DFS = 0x11, - RT_CHANNEL_DOMAIN_JAPAN_NO_DFS = 0x12, - RT_CHANNEL_DOMAIN_WORLD_WIDE_5G = 0x13, - RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS = 0x14, - RT_CHANNEL_DOMAIN_WORLD_NULL = 0x20, - RT_CHANNEL_DOMAIN_ETSI1_NULL = 0x21, - RT_CHANNEL_DOMAIN_FCC1_NULL = 0x22, - RT_CHANNEL_DOMAIN_MKK1_NULL = 0x23, - RT_CHANNEL_DOMAIN_ETSI2_NULL = 0x24, - RT_CHANNEL_DOMAIN_FCC1_FCC1 = 0x25, - RT_CHANNEL_DOMAIN_WORLD_ETSI1 = 0x26, - RT_CHANNEL_DOMAIN_MKK1_MKK1 = 0x27, - RT_CHANNEL_DOMAIN_WORLD_KCC1 = 0x28, - RT_CHANNEL_DOMAIN_WORLD_FCC2 = 0x29, - RT_CHANNEL_DOMAIN_FCC2_NULL = 0x2A, - RT_CHANNEL_DOMAIN_WORLD_FCC3 = 0x30, - RT_CHANNEL_DOMAIN_WORLD_FCC4 = 0x31, - RT_CHANNEL_DOMAIN_WORLD_FCC5 = 0x32, - RT_CHANNEL_DOMAIN_WORLD_FCC6 = 0x33, - RT_CHANNEL_DOMAIN_FCC1_FCC7 = 0x34, - RT_CHANNEL_DOMAIN_WORLD_ETSI2 = 0x35, - RT_CHANNEL_DOMAIN_WORLD_ETSI3 = 0x36, - RT_CHANNEL_DOMAIN_MKK1_MKK2 = 0x37, - RT_CHANNEL_DOMAIN_MKK1_MKK3 = 0x38, - RT_CHANNEL_DOMAIN_FCC1_NCC1 = 0x39, - RT_CHANNEL_DOMAIN_FCC1_NCC2 = 0x40, - RT_CHANNEL_DOMAIN_GLOBAL_NULL = 0x41, - RT_CHANNEL_DOMAIN_ETSI1_ETSI4 = 0x42, - RT_CHANNEL_DOMAIN_FCC1_FCC2 = 0x43, - RT_CHANNEL_DOMAIN_FCC1_NCC3 = 0x44, - RT_CHANNEL_DOMAIN_WORLD_ETSI5 = 0x45, - RT_CHANNEL_DOMAIN_FCC1_FCC8 = 0x46, - RT_CHANNEL_DOMAIN_WORLD_ETSI6 = 0x47, - RT_CHANNEL_DOMAIN_WORLD_ETSI7 = 0x48, - RT_CHANNEL_DOMAIN_WORLD_ETSI8 = 0x49, - RT_CHANNEL_DOMAIN_WORLD_ETSI9 = 0x50, - RT_CHANNEL_DOMAIN_WORLD_ETSI10 = 0x51, - RT_CHANNEL_DOMAIN_WORLD_ETSI11 = 0x52, - RT_CHANNEL_DOMAIN_FCC1_NCC4 = 0x53, - RT_CHANNEL_DOMAIN_WORLD_ETSI12 = 0x54, - RT_CHANNEL_DOMAIN_FCC1_FCC9 = 0x55, - RT_CHANNEL_DOMAIN_WORLD_ETSI13 = 0x56, - RT_CHANNEL_DOMAIN_FCC1_FCC10 = 0x57, - RT_CHANNEL_DOMAIN_MKK2_MKK4 = 0x58, - RT_CHANNEL_DOMAIN_MAX = 0x59, - RT_CHANNEL_DOMAIN_REALTEK_DEFINE = 0x7F, + RT_CHANNEL_DOMAIN_FCC = 0x0, + RT_CHANNEL_DOMAIN_IC = 0x1, + RT_CHANNEL_DOMAIN_ETSI = 0x2, + RT_CHANNEL_DOMAIN_SPAIN = 0x3, + RT_CHANNEL_DOMAIN_FRANCE = 0x4, + RT_CHANNEL_DOMAIN_MKK = 0x5, + RT_CHANNEL_DOMAIN_MKK1 = 0x6, + RT_CHANNEL_DOMAIN_ISRAEL = 0x7, + RT_CHANNEL_DOMAIN_TELEC = 0x8, + RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN = 0x9, + RT_CHANNEL_DOMAIN_WORLD_WIDE_13 = 0xA, + RT_CHANNEL_DOMAIN_TAIWAN = 0xB, + RT_CHANNEL_DOMAIN_CHINA = 0xC, + RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO = 0xD, + RT_CHANNEL_DOMAIN_KOREA = 0xE, + RT_CHANNEL_DOMAIN_TURKEY = 0xF, + RT_CHANNEL_DOMAIN_JAPAN = 0x10, + RT_CHANNEL_DOMAIN_FCC_NO_DFS = 0x11, + RT_CHANNEL_DOMAIN_JAPAN_NO_DFS = 0x12, + RT_CHANNEL_DOMAIN_WORLD_WIDE_5G = 0x13, + RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS = 0x14, + RT_CHANNEL_DOMAIN_WORLD_NULL = 0x20, + RT_CHANNEL_DOMAIN_ETSI1_NULL = 0x21, + RT_CHANNEL_DOMAIN_FCC1_NULL = 0x22, + RT_CHANNEL_DOMAIN_MKK1_NULL = 0x23, + RT_CHANNEL_DOMAIN_ETSI2_NULL = 0x24, + RT_CHANNEL_DOMAIN_FCC1_FCC1 = 0x25, + RT_CHANNEL_DOMAIN_WORLD_ETSI1 = 0x26, + RT_CHANNEL_DOMAIN_MKK1_MKK1 = 0x27, + RT_CHANNEL_DOMAIN_WORLD_KCC1 = 0x28, + RT_CHANNEL_DOMAIN_WORLD_FCC2 = 0x29, + RT_CHANNEL_DOMAIN_FCC2_NULL = 0x2A, + RT_CHANNEL_DOMAIN_WORLD_FCC3 = 0x30, + RT_CHANNEL_DOMAIN_WORLD_FCC4 = 0x31, + RT_CHANNEL_DOMAIN_WORLD_FCC5 = 0x32, + RT_CHANNEL_DOMAIN_WORLD_FCC6 = 0x33, + RT_CHANNEL_DOMAIN_FCC1_FCC7 = 0x34, + RT_CHANNEL_DOMAIN_WORLD_ETSI2 = 0x35, + RT_CHANNEL_DOMAIN_WORLD_ETSI3 = 0x36, + RT_CHANNEL_DOMAIN_MKK1_MKK2 = 0x37, + RT_CHANNEL_DOMAIN_MKK1_MKK3 = 0x38, + RT_CHANNEL_DOMAIN_FCC1_NCC1 = 0x39, + RT_CHANNEL_DOMAIN_FCC1_NCC2 = 0x40, + RT_CHANNEL_DOMAIN_GLOBAL_NULL = 0x41, + RT_CHANNEL_DOMAIN_ETSI1_ETSI4 = 0x42, + RT_CHANNEL_DOMAIN_FCC1_FCC2 = 0x43, + RT_CHANNEL_DOMAIN_FCC1_NCC3 = 0x44, + RT_CHANNEL_DOMAIN_WORLD_ETSI5 = 0x45, + RT_CHANNEL_DOMAIN_FCC1_FCC8 = 0x46, + RT_CHANNEL_DOMAIN_WORLD_ETSI6 = 0x47, + RT_CHANNEL_DOMAIN_WORLD_ETSI7 = 0x48, + RT_CHANNEL_DOMAIN_WORLD_ETSI8 = 0x49, + RT_CHANNEL_DOMAIN_WORLD_ETSI9 = 0x50, + RT_CHANNEL_DOMAIN_WORLD_ETSI10 = 0x51, + RT_CHANNEL_DOMAIN_WORLD_ETSI11 = 0x52, + RT_CHANNEL_DOMAIN_FCC1_NCC4 = 0x53, + RT_CHANNEL_DOMAIN_WORLD_ETSI12 = 0x54, + RT_CHANNEL_DOMAIN_FCC1_FCC9 = 0x55, + RT_CHANNEL_DOMAIN_WORLD_ETSI13 = 0x56, + RT_CHANNEL_DOMAIN_FCC1_FCC10 = 0x57, + RT_CHANNEL_DOMAIN_MKK2_MKK4 = 0x58, + RT_CHANNEL_DOMAIN_MAX = 0x59, + RT_CHANNEL_DOMAIN_REALTEK_DEFINE = 0x7F, }; -struct _driver_priv -{ - int drv_registered; - _mutex hw_init_mutex; - _mutex h2c_fwcmd_mutex; - _mutex setch_mutex; - _mutex setbw_mutex; +struct _driver_priv { + int drv_registered; + _mutex hw_init_mutex; + _mutex h2c_fwcmd_mutex; + _mutex setch_mutex; + _mutex setbw_mutex; }; typedef struct _driver_priv drv_priv; -struct _ADAPTIVITY_STATISTICS -{ - s1Byte TH_L2H_ini_mode2; - s1Byte TH_EDCCA_HL_diff_mode2; - s1Byte TH_EDCCA_HL_diff_backup; - s1Byte IGI_Base; - u1Byte IGI_target; - u1Byte NHMWait; - s1Byte H2L_lb; - s1Byte L2H_lb; - BOOLEAN bFirstLink; - BOOLEAN bCheck; - BOOLEAN DynamicLinkAdaptivity; - u1Byte APNumTH; - u1Byte AdajustIGILevel; +struct _ADAPTIVITY_STATISTICS { + s1Byte TH_L2H_ini_mode2; + s1Byte TH_EDCCA_HL_diff_mode2; + s1Byte TH_EDCCA_HL_diff_backup; + s1Byte IGI_Base; + u1Byte IGI_target; + u1Byte NHMWait; + s1Byte H2L_lb; + s1Byte L2H_lb; + BOOLEAN bFirstLink; + BOOLEAN bCheck; + BOOLEAN DynamicLinkAdaptivity; + u1Byte APNumTH; + u1Byte AdajustIGILevel; }; typedef struct _ADAPTIVITY_STATISTICS ADAPTIVITY_STATISTICS; -struct _ODM_NOISE_MONITOR_ -{ - s1Byte noise[1]; - s2Byte noise_all; +struct _ODM_NOISE_MONITOR_ { + s1Byte noise[1]; + s2Byte noise_all; }; typedef struct _ODM_NOISE_MONITOR_ ODM_NOISE_MONITOR; -struct _FALSE_ALARM_STATISTICS -{ - u4Byte Cnt_Parity_Fail; - u4Byte Cnt_Rate_Illegal; - u4Byte Cnt_Crc8_fail; - u4Byte Cnt_Mcs_fail; - u4Byte Cnt_Ofdm_fail; - u4Byte Cnt_Ofdm_fail_pre; - u4Byte Cnt_Cck_fail; - u4Byte Cnt_all; - u4Byte Cnt_Fast_Fsync; - u4Byte Cnt_SB_Search_fail; - u4Byte Cnt_OFDM_CCA; - u4Byte Cnt_CCK_CCA; - u4Byte Cnt_CCA_all; - u4Byte Cnt_BW_USC; - u4Byte Cnt_BW_LSC; +struct _FALSE_ALARM_STATISTICS { + u4Byte Cnt_Parity_Fail; + u4Byte Cnt_Rate_Illegal; + u4Byte Cnt_Crc8_fail; + u4Byte Cnt_Mcs_fail; + u4Byte Cnt_Ofdm_fail; + u4Byte Cnt_Ofdm_fail_pre; + u4Byte Cnt_Cck_fail; + u4Byte Cnt_all; + u4Byte Cnt_Fast_Fsync; + u4Byte Cnt_SB_Search_fail; + u4Byte Cnt_OFDM_CCA; + u4Byte Cnt_CCK_CCA; + u4Byte Cnt_CCA_all; + u4Byte Cnt_BW_USC; + u4Byte Cnt_BW_LSC; }; typedef struct _FALSE_ALARM_STATISTICS FALSE_ALARM_STATISTICS; - -enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE //: __int32 +enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE //: sint32_t { - PHY_REG_PG_RELATIVE_VALUE = 0x0, - PHY_REG_PG_EXACT_VALUE = 0x1, + PHY_REG_PG_RELATIVE_VALUE = 0x0, PHY_REG_PG_EXACT_VALUE = 0x1, }; typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE PHY_REG_PG_TYPE; -struct __attribute__((aligned(4))) _CFO_TRACKING_ -{ - BOOLEAN bATCStatus; - BOOLEAN largeCFOHit; - BOOLEAN bAdjust; - u1Byte CrystalCap; - u1Byte DefXCap; - int CFO_tail[2]; - int CFO_ave_pre; - u4Byte packetCount; - u4Byte packetCount_pre; - BOOLEAN bForceXtalCap; - BOOLEAN bReset; - u1Byte CFO_TH_XTAL_HIGH; - u1Byte CFO_TH_XTAL_LOW; - u1Byte CFO_TH_ATC; +struct _atr_aligned4_ _CFO_TRACKING_ { + BOOLEAN bATCStatus; + BOOLEAN largeCFOHit; + BOOLEAN bAdjust; + u1Byte CrystalCap; + u1Byte DefXCap; + int CFO_tail[2]; + int CFO_ave_pre; + u4Byte packetCount; + u4Byte packetCount_pre; + BOOLEAN bForceXtalCap; + BOOLEAN bReset; + u1Byte CFO_TH_XTAL_HIGH; + u1Byte CFO_TH_XTAL_LOW; + u1Byte CFO_TH_ATC; }; typedef struct _CFO_TRACKING_ CFO_TRACKING; -struct __attribute__((aligned(8))) _ROM_INFO -{ - u1Byte EEPROMVersion; - u1Byte CrystalCap; - u8Byte DebugComponents; - u4Byte DebugLevel; +struct _atr_aligned8_ _ROM_INFO { + u1Byte EEPROMVersion; + u1Byte CrystalCap; + u8Byte DebugComponents; + u4Byte DebugLevel; }; typedef struct _ROM_INFO ROM_INFO; typedef struct _ROM_INFO *PROM_INFO; typedef struct sta_info *PSTA_INFO_T; -struct _ODM_Phy_Dbg_Info_ -{ - s1Byte RxSNRdB[4]; - u4Byte NumQryPhyStatus; - u4Byte NumQryPhyStatusCCK; - u4Byte NumQryPhyStatusOFDM; - u1Byte NumQryBeaconPkt; - s4Byte RxEVM[4]; +struct _ODM_Phy_Dbg_Info_ { + s1Byte RxSNRdB[4]; + u4Byte NumQryPhyStatus; + u4Byte NumQryPhyStatusCCK; + u4Byte NumQryPhyStatusOFDM; + u1Byte NumQryBeaconPkt; + s4Byte RxEVM[4]; }; typedef struct _ODM_Phy_Dbg_Info_ ODM_PHY_DBG_INFO_T; -struct _ODM_Mac_Status_Info_ -{ - u1Byte test; +struct _ODM_Mac_Status_Info_ { + u1Byte test; }; typedef struct _ODM_Mac_Status_Info_ ODM_MAC_INFO; -struct __attribute__((aligned(4))) _ODM_RA_Info_ -{ - u1Byte RateID; - u4Byte RateMask; - u4Byte RAUseRate; - u1Byte RateSGI; - u1Byte RssiStaRA; - u1Byte PreRssiStaRA; - u1Byte SGIEnable; - u1Byte DecisionRate; - u1Byte PreRate; - u1Byte HighestRate; - u1Byte LowestRate; - u4Byte NscUp; - u4Byte NscDown; - u2Byte RTY[5]; - u4Byte TOTAL; - u2Byte DROP; - u1Byte Active; - u2Byte RptTime; - u1Byte RAWaitingCounter; - u1Byte RAPendingCounter; - u1Byte RAINFO; - u1Byte Initial_BW; - u1Byte BW_setting; - u1Byte DISPT; - u1Byte DISRA; - u1Byte Stage_RA; - u1Byte PRE_BW; - u1Byte MacID; - u1Byte Try_state; - u1Byte Try_done_cnt; - u2Byte RA_counter; - u1Byte Init_Rate_H; - u1Byte Init_Rate_M; - u1Byte Init_Rate_L; - u4Byte Total_TX; - u1Byte TRAINING_RATE; - u1Byte STOP_PT_COUNTER; - u1Byte MODE_SS; - u1Byte PT_smooth_factor; - u1Byte PTActive; - u1Byte PTTryState; - u1Byte PTStage; - u1Byte PTStopCount; - u1Byte PTPreRate; - u1Byte PTPreRssi; - u1Byte PTModeSS; - u1Byte RAstage; - u1Byte PTSmoothFactor; +struct _atr_aligned4_ _ODM_RA_Info_ { + u1Byte RateID; + u4Byte RateMask; + u4Byte RAUseRate; + u1Byte RateSGI; + u1Byte RssiStaRA; + u1Byte PreRssiStaRA; + u1Byte SGIEnable; + u1Byte DecisionRate; + u1Byte PreRate; + u1Byte HighestRate; + u1Byte LowestRate; + u4Byte NscUp; + u4Byte NscDown; + u2Byte RTY[5]; + u4Byte TOTAL; + u2Byte DROP; + u1Byte Active; + u2Byte RptTime; + u1Byte RAWaitingCounter; + u1Byte RAPendingCounter; + u1Byte RAINFO; + u1Byte Initial_BW; + u1Byte BW_setting; + u1Byte DISPT; + u1Byte DISRA; + u1Byte Stage_RA; + u1Byte PRE_BW; + u1Byte MacID; + u1Byte Try_state; + u1Byte Try_done_cnt; + u2Byte RA_counter; + u1Byte Init_Rate_H; + u1Byte Init_Rate_M; + u1Byte Init_Rate_L; + u4Byte Total_TX; + u1Byte TRAINING_RATE; + u1Byte STOP_PT_COUNTER; + u1Byte MODE_SS; + u1Byte PT_smooth_factor; + u1Byte PTActive; + u1Byte PTTryState; + u1Byte PTStage; + u1Byte PTStopCount; + u1Byte PTPreRate; + u1Byte PTPreRssi; + u1Byte PTModeSS; + u1Byte RAstage; + u1Byte PTSmoothFactor; }; typedef struct _ODM_RA_Info_ ODM_RA_INFO_T; typedef struct _ODM_RA_Info_ *PODM_RA_INFO_T; -struct _FAST_ANTENNA_TRAINNING_ -{ - u1Byte Bssid[6]; - u1Byte antsel_rx_keep_0; - u1Byte antsel_rx_keep_1; - u1Byte antsel_rx_keep_2; - u4Byte antSumRSSI[7]; - u4Byte antRSSIcnt[7]; - u4Byte antAveRSSI[7]; - u1Byte FAT_State; - u4Byte TrainIdx; - u1Byte antsel_a[7]; - u1Byte antsel_b[7]; - u1Byte antsel_c[7]; - u4Byte MainAnt_Sum[7]; - u4Byte AuxAnt_Sum[7]; - u4Byte MainAnt_Cnt[7]; - u4Byte AuxAnt_Cnt[7]; - u4Byte MainAnt_Sum_CCK[7]; - u4Byte AuxAnt_Sum_CCK[7]; - u4Byte MainAnt_Cnt_CCK[7]; - u4Byte AuxAnt_Cnt_CCK[7]; - u1Byte RxIdleAnt; - BOOLEAN bBecomeLinked; - u4Byte MinMaxRSSI; - u1Byte idx_AntDiv_counter_2G; - u1Byte idx_AntDiv_counter_5G; - u4Byte AntDiv_2G_5G; - u4Byte CCK_counter_main; - u4Byte CCK_counter_aux; - u4Byte OFDM_counter_main; - u4Byte OFDM_counter_aux; +struct _FAST_ANTENNA_TRAINNING_ { + u1Byte Bssid[6]; + u1Byte antsel_rx_keep_0; + u1Byte antsel_rx_keep_1; + u1Byte antsel_rx_keep_2; + u4Byte antSumRSSI[7]; + u4Byte antRSSIcnt[7]; + u4Byte antAveRSSI[7]; + u1Byte FAT_State; + u4Byte TrainIdx; + u1Byte antsel_a[7]; + u1Byte antsel_b[7]; + u1Byte antsel_c[7]; + u4Byte MainAnt_Sum[7]; + u4Byte AuxAnt_Sum[7]; + u4Byte MainAnt_Cnt[7]; + u4Byte AuxAnt_Cnt[7]; + u4Byte MainAnt_Sum_CCK[7]; + u4Byte AuxAnt_Sum_CCK[7]; + u4Byte MainAnt_Cnt_CCK[7]; + u4Byte AuxAnt_Cnt_CCK[7]; + u1Byte RxIdleAnt; + BOOLEAN bBecomeLinked; + u4Byte MinMaxRSSI; + u1Byte idx_AntDiv_counter_2G; + u1Byte idx_AntDiv_counter_5G; + u4Byte AntDiv_2G_5G; + u4Byte CCK_counter_main; + u4Byte CCK_counter_aux; + u4Byte OFDM_counter_main; + u4Byte OFDM_counter_aux; }; typedef struct _FAST_ANTENNA_TRAINNING_ FAT_T; -struct _Dynamic_Initial_Gain_Threshold_ -{ - BOOLEAN bStopDIG; - BOOLEAN bPauseDIG; - BOOLEAN bIgnoreDIG; - BOOLEAN bPSDInProgress; - u1Byte Dig_Enable_Flag; - u1Byte Dig_Ext_Port_Stage; - int RssiLowThresh; - int RssiHighThresh; - u4Byte FALowThresh; - u4Byte FAHighThresh; - u1Byte CurSTAConnectState; - u1Byte PreSTAConnectState; - u1Byte CurMultiSTAConnectState; - u1Byte PreIGValue; - u1Byte CurIGValue; - u1Byte BackupIGValue; - u1Byte BT30_CurIGI; - u1Byte IGIBackup; - s1Byte BackoffVal; - s1Byte BackoffVal_range_max; - s1Byte BackoffVal_range_min; - u1Byte rx_gain_range_max; - u1Byte rx_gain_range_min; - u1Byte Rssi_val_min; - u1Byte PreCCK_CCAThres; - u1Byte CurCCK_CCAThres; - u1Byte PreCCKPDState; - u1Byte CurCCKPDState; - u1Byte CCKPDBackup; - u1Byte LargeFAHit; - u1Byte ForbiddenIGI; - u4Byte Recover_cnt; - u1Byte DIG_Dynamic_MIN_0; - u1Byte DIG_Dynamic_MIN_1; - BOOLEAN bMediaConnect_0; - BOOLEAN bMediaConnect_1; - u4Byte AntDiv_RSSI_max; - u4Byte RSSI_max; - u1Byte *pbP2pLinkInProgress; +struct _Dynamic_Initial_Gain_Threshold_ { + BOOLEAN bStopDIG; + BOOLEAN bPauseDIG; + BOOLEAN bIgnoreDIG; + BOOLEAN bPSDInProgress; + u1Byte Dig_Enable_Flag; + u1Byte Dig_Ext_Port_Stage; + int RssiLowThresh; + int RssiHighThresh; + u4Byte FALowThresh; + u4Byte FAHighThresh; + u1Byte CurSTAConnectState; + u1Byte PreSTAConnectState; + u1Byte CurMultiSTAConnectState; + u1Byte PreIGValue; + u1Byte CurIGValue; + u1Byte BackupIGValue; + u1Byte BT30_CurIGI; + u1Byte IGIBackup; + s1Byte BackoffVal; + s1Byte BackoffVal_range_max; + s1Byte BackoffVal_range_min; + u1Byte rx_gain_range_max; + u1Byte rx_gain_range_min; + u1Byte Rssi_val_min; + u1Byte PreCCK_CCAThres; + u1Byte CurCCK_CCAThres; + u1Byte PreCCKPDState; + u1Byte CurCCKPDState; + u1Byte CCKPDBackup; + u1Byte LargeFAHit; + u1Byte ForbiddenIGI; + u4Byte Recover_cnt; + u1Byte DIG_Dynamic_MIN_0; + u1Byte DIG_Dynamic_MIN_1; + BOOLEAN bMediaConnect_0; + BOOLEAN bMediaConnect_1; + u4Byte AntDiv_RSSI_max; + u4Byte RSSI_max; + u1Byte *pbP2pLinkInProgress; }; typedef struct _Dynamic_Initial_Gain_Threshold_ DIG_T; -struct _ODM_RATE_ADAPTIVE -{ - u1Byte Type; - u1Byte HighRSSIThresh; - u1Byte LowRSSIThresh; - u1Byte RATRState; - u1Byte LdpcThres; - BOOLEAN bLowerRtsRate; - BOOLEAN bUseLdpc; +struct _ODM_RATE_ADAPTIVE { + u1Byte Type; + u1Byte HighRSSIThresh; + u1Byte LowRSSIThresh; + u1Byte RATRState; + u1Byte LdpcThres; + BOOLEAN bLowerRtsRate; + BOOLEAN bUseLdpc; }; typedef struct _ODM_RATE_ADAPTIVE ODM_RATE_ADAPTIVE; -struct _Dynamic_Power_Saving_ -{ - u1Byte PreCCAState; - u1Byte CurCCAState; - u1Byte PreRFState; - u1Byte CurRFState; - int Rssi_val_min; - u1Byte initialize; - u4Byte Reg874; - u4Byte RegC70; - u4Byte Reg85C; - u4Byte RegA74; +struct _Dynamic_Power_Saving_ { + u1Byte PreCCAState; + u1Byte CurCCAState; + u1Byte PreRFState; + u1Byte CurRFState; + int Rssi_val_min; + u1Byte initialize; + u4Byte Reg874; + u4Byte RegC70; + u4Byte Reg85C; + u4Byte RegA74; }; typedef struct _Dynamic_Power_Saving_ PS_T; -struct _Dynamic_Primary_CCA -{ - u1Byte PriCCA_flag; - u1Byte intf_flag; - u1Byte intf_type; - u1Byte DupRTS_flag; - u1Byte Monitor_flag; - u1Byte CH_offset; - u1Byte MF_state; +struct _Dynamic_Primary_CCA { + u1Byte PriCCA_flag; + u1Byte intf_flag; + u1Byte intf_type; + u1Byte DupRTS_flag; + u1Byte Monitor_flag; + u1Byte CH_offset; + u1Byte MF_state; }; typedef struct _Dynamic_Primary_CCA Pri_CCA_T; -struct _RX_High_Power_ -{ - u1Byte RXHP_flag; - u1Byte PSD_func_trigger; - u1Byte PSD_bitmap_RXHP[80]; - u1Byte Pre_IGI; - u1Byte Cur_IGI; - u1Byte Pre_pw_th; - u1Byte Cur_pw_th; - BOOLEAN First_time_enter; - BOOLEAN RXHP_enable; - u1Byte TP_Mode; +struct _RX_High_Power_ { + u1Byte RXHP_flag; + u1Byte PSD_func_trigger; + u1Byte PSD_bitmap_RXHP[80]; + u1Byte Pre_IGI; + u1Byte Cur_IGI; + u1Byte Pre_pw_th; + u1Byte Cur_pw_th; + BOOLEAN First_time_enter; + BOOLEAN RXHP_enable; + u1Byte TP_Mode; }; typedef struct _RX_High_Power_ RXHP_T; -struct _Rate_Adaptive_Table_ -{ - u1Byte firstconnect; +struct _Rate_Adaptive_Table_ { + u1Byte firstconnect; }; typedef struct _Rate_Adaptive_Table_ RA_T; -struct __attribute__((aligned(8))) _SW_Antenna_Switch_ -{ - u1Byte Double_chk_flag; - u1Byte try_flag; - s4Byte PreRSSI; - u1Byte CurAntenna; - u1Byte PreAntenna; - u1Byte RSSI_Trying; - u1Byte TestMode; - u1Byte bTriggerAntennaSwitch; - u1Byte SelectAntennaMap; - u1Byte RSSI_target; - u1Byte reset_idx; - u1Byte SWAS_NoLink_State; - u4Byte SWAS_NoLink_BK_Reg860; - u4Byte SWAS_NoLink_BK_Reg92c; - BOOLEAN ANTA_ON; - BOOLEAN ANTB_ON; - u1Byte Ant5G; - u1Byte Ant2G; - s4Byte RSSI_sum_A; - s4Byte RSSI_sum_B; - s4Byte RSSI_cnt_A; - s4Byte RSSI_cnt_B; - u8Byte lastTxOkCnt; - u8Byte lastRxOkCnt; - u8Byte TXByteCnt_A; - u8Byte TXByteCnt_B; - u8Byte RXByteCnt_A; - u8Byte RXByteCnt_B; - u1Byte TrafficLoad; - u1Byte Train_time; - u1Byte Train_time_flag; +struct _atr_aligned8_ _SW_Antenna_Switch_ { + u1Byte Double_chk_flag; + u1Byte try_flag; + s4Byte PreRSSI; + u1Byte CurAntenna; + u1Byte PreAntenna; + u1Byte RSSI_Trying; + u1Byte TestMode; + u1Byte bTriggerAntennaSwitch; + u1Byte SelectAntennaMap; + u1Byte RSSI_target; + u1Byte reset_idx; + u1Byte SWAS_NoLink_State; + u4Byte SWAS_NoLink_BK_Reg860; + u4Byte SWAS_NoLink_BK_Reg92c; + BOOLEAN ANTA_ON; + BOOLEAN ANTB_ON; + u1Byte Ant5G; + u1Byte Ant2G; + s4Byte RSSI_sum_A; + s4Byte RSSI_sum_B; + s4Byte RSSI_cnt_A; + s4Byte RSSI_cnt_B; + u8Byte lastTxOkCnt; + u8Byte lastRxOkCnt; + u8Byte TXByteCnt_A; + u8Byte TXByteCnt_B; + u8Byte RXByteCnt_A; + u8Byte RXByteCnt_B; + u1Byte TrafficLoad; + u1Byte Train_time; + u1Byte Train_time_flag; }; typedef struct _SW_Antenna_Switch_ SWAT_T; -struct _EDCA_TURBO_ -{ - BOOLEAN bCurrentTurboEDCA; - BOOLEAN bIsCurRDLState; +struct _EDCA_TURBO_ { + BOOLEAN bCurrentTurboEDCA; + BOOLEAN bIsCurRDLState; }; typedef struct _EDCA_TURBO_ EDCA_T; -struct _ANT_DETECTED_INFO -{ - BOOLEAN bAntDetected; - u4Byte dBForAntA; - u4Byte dBForAntB; - u4Byte dBForAntO; +struct _ANT_DETECTED_INFO { + BOOLEAN bAntDetected; + u4Byte dBForAntA; + u4Byte dBForAntB; + u4Byte dBForAntO; }; typedef struct _ANT_DETECTED_INFO ANT_DETECTED_INFO; -struct _IQK_MATRIX_REGS_SETTING -{ - BOOLEAN bIQKDone; - s4Byte Value[1][8]; +struct _IQK_MATRIX_REGS_SETTING { + BOOLEAN bIQKDone; + s4Byte Value[1][8]; }; typedef struct _IQK_MATRIX_REGS_SETTING IQK_MATRIX_REGS_SETTING; -struct __attribute__((aligned(8))) ODM_RF_Calibration_Structure -{ - u4Byte RegA24; - s4Byte RegE94; - s4Byte RegE9C; - s4Byte RegEB4; - s4Byte RegEBC; - u1Byte TXPowercount; - BOOLEAN bTXPowerTrackingInit; - BOOLEAN bTXPowerTracking; - u1Byte TxPowerTrackControl; - u1Byte TM_Trigger; - u1Byte InternalPA5G[2]; - u1Byte ThermalMeter[2]; - u1Byte ThermalValue; - u1Byte ThermalValue_LCK; - u1Byte ThermalValue_IQK; - u1Byte ThermalValue_DPK; - u1Byte ThermalValue_AVG[8]; - u1Byte ThermalValue_AVG_index; - u1Byte ThermalValue_RxGain; - u1Byte ThermalValue_Crystal; - u1Byte ThermalValue_DPKstore; - u1Byte ThermalValue_DPKtrack; - BOOLEAN TxPowerTrackingInProgress; - BOOLEAN bReloadtxpowerindex; - u1Byte bRfPiEnable; - u4Byte TXPowerTrackingCallbackCnt; - u1Byte bCCKinCH14; - u1Byte CCK_index[1]; - s1Byte PowerIndexOffset_CCK[1]; - s1Byte DeltaPowerIndex_CCK[1]; - s1Byte DeltaPowerIndexLast_CCK[1]; - u1Byte OFDM_index[1]; - s1Byte PowerIndexOffset_OFDM[1]; - s1Byte DeltaPowerIndex_OFDM[1]; - s1Byte DeltaPowerIndexLast_OFDM[1]; - BOOLEAN bTxPowerChanged; - s1Byte XtalOffset; - s1Byte XtalOffsetLast; - u1Byte ThermalValue_HP[8]; - u1Byte ThermalValue_HP_index; - IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[14]; - u1Byte Delta_LCK; - s1Byte BBSwingDiff2G; - s1Byte BBSwingDiff5G; - s1Byte DeltaSwingTableIdx_2GCCKA_P[30]; - s1Byte DeltaSwingTableIdx_2GCCKA_N[30]; - s1Byte DeltaSwingTableIdx_2GA_P[30]; - s1Byte DeltaSwingTableIdx_2GA_N[30]; - s1Byte DeltaSwingTableXtal_P[30]; - s1Byte DeltaSwingTableXtal_N[30]; - u4Byte RegC04; - u4Byte Reg874; - u4Byte RegC08; - u4Byte RegB68; - u4Byte RegB6C; - u4Byte Reg870; - u4Byte Reg860; - u4Byte Reg864; - BOOLEAN bIQKInitialized; - BOOLEAN bLCKInProgress; - BOOLEAN bAntennaDetected; - BOOLEAN bNeedIQK; - BOOLEAN bIQKInProgress; - u1Byte Delta_IQK; - u4Byte ADDA_backup[16]; - u4Byte IQK_MAC_backup[4]; - u4Byte IQK_BB_backup_recover[9]; - u4Byte IQK_BB_backup[9]; - u4Byte TxIQC_8723B[2][3][2]; - u4Byte RxIQC_8723B[2][2][2]; - u8Byte IQK_StartTime; - u8Byte IQK_ProgressingTime; - u4Byte LOK_Result; - u4Byte APKoutput[2][2]; - u1Byte bAPKdone; - u1Byte bAPKThermalMeterIgnore; - BOOLEAN bDPKFail; - u1Byte bDPdone; - u1Byte bDPPathAOK; - u1Byte bDPPathBOK; - u4Byte TxLOK[2]; - u4Byte DpkTxAGC; - s4Byte DpkGain; - u4Byte DpkThermal[4]; +struct _atr_aligned8_ ODM_RF_Calibration_Structure { + u4Byte RegA24; + s4Byte RegE94; + s4Byte RegE9C; + s4Byte RegEB4; + s4Byte RegEBC; + u1Byte TXPowercount; + BOOLEAN bTXPowerTrackingInit; + BOOLEAN bTXPowerTracking; + u1Byte TxPowerTrackControl; + u1Byte TM_Trigger; + u1Byte InternalPA5G[2]; + u1Byte ThermalMeter[2]; + u1Byte ThermalValue; + u1Byte ThermalValue_LCK; + u1Byte ThermalValue_IQK; + u1Byte ThermalValue_DPK; + u1Byte ThermalValue_AVG[8]; + u1Byte ThermalValue_AVG_index; + u1Byte ThermalValue_RxGain; + u1Byte ThermalValue_Crystal; + u1Byte ThermalValue_DPKstore; + u1Byte ThermalValue_DPKtrack; + BOOLEAN TxPowerTrackingInProgress; + BOOLEAN bReloadtxpowerindex; + u1Byte bRfPiEnable; + u4Byte TXPowerTrackingCallbackCnt; + u1Byte bCCKinCH14; + u1Byte CCK_index[1]; + s1Byte PowerIndexOffset_CCK[1]; + s1Byte DeltaPowerIndex_CCK[1]; + s1Byte DeltaPowerIndexLast_CCK[1]; + u1Byte OFDM_index[1]; + s1Byte PowerIndexOffset_OFDM[1]; + s1Byte DeltaPowerIndex_OFDM[1]; + s1Byte DeltaPowerIndexLast_OFDM[1]; + BOOLEAN bTxPowerChanged; + s1Byte XtalOffset; + s1Byte XtalOffsetLast; + u1Byte ThermalValue_HP[8]; + u1Byte ThermalValue_HP_index; + IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[14]; + u1Byte Delta_LCK; + s1Byte BBSwingDiff2G; + s1Byte BBSwingDiff5G; + s1Byte DeltaSwingTableIdx_2GCCKA_P[30]; + s1Byte DeltaSwingTableIdx_2GCCKA_N[30]; + s1Byte DeltaSwingTableIdx_2GA_P[30]; + s1Byte DeltaSwingTableIdx_2GA_N[30]; + s1Byte DeltaSwingTableXtal_P[30]; + s1Byte DeltaSwingTableXtal_N[30]; + u4Byte RegC04; + u4Byte Reg874; + u4Byte RegC08; + u4Byte RegB68; + u4Byte RegB6C; + u4Byte Reg870; + u4Byte Reg860; + u4Byte Reg864; + BOOLEAN bIQKInitialized; + BOOLEAN bLCKInProgress; + BOOLEAN bAntennaDetected; + BOOLEAN bNeedIQK; + BOOLEAN bIQKInProgress; + u1Byte Delta_IQK; + u4Byte ADDA_backup[16]; + u4Byte IQK_MAC_backup[4]; + u4Byte IQK_BB_backup_recover[9]; + u4Byte IQK_BB_backup[9]; + u4Byte TxIQC_8723B[2][3][2]; + u4Byte RxIQC_8723B[2][2][2]; + u8Byte IQK_StartTime; + u8Byte IQK_ProgressingTime; + u4Byte LOK_Result; + u4Byte APKoutput[2][2]; + u1Byte bAPKdone; + u1Byte bAPKThermalMeterIgnore; + BOOLEAN bDPKFail; + u1Byte bDPdone; + u1Byte bDPPathAOK; + u1Byte bDPPathBOK; + u4Byte TxLOK[2]; + u4Byte DpkTxAGC; + s4Byte DpkGain; + u4Byte DpkThermal[4]; }; typedef struct ODM_RF_Calibration_Structure ODM_RF_CAL_T; - -struct __attribute__((aligned(8))) DM_Out_Source_Dynamic_Mechanism_Structure -{ - PADAPTER Adapter; - BOOLEAN odm_ready; - PHY_REG_PG_TYPE PhyRegPgValueType; - u1Byte PhyRegPgVersion; - u4Byte NumQryPhyStatusAll; - u4Byte LastNumQryPhyStatusAll; - u4Byte RxPWDBAve; - BOOLEAN MPDIG_2G; - u1Byte Times_2G; - BOOLEAN bCckHighPower; - u1Byte RFPathRxEnable; - u1Byte ControlChannel; - u1Byte SupportPlatform; - u4Byte SupportAbility; - u1Byte SupportInterface; - u4Byte SupportICType; - u1Byte CutVersion; - u1Byte FabVersion; - u1Byte RFType; - u1Byte RFEType; - u1Byte BoardType; - u1Byte PackageType; - u1Byte TypeGLNA; - u1Byte TypeGPA; - u1Byte TypeALNA; - u1Byte TypeAPA; - u1Byte ExtLNA; - u1Byte ExtLNA5G; - u1Byte ExtPA; - u1Byte ExtPA5G; - u1Byte ExtTRSW; - u1Byte PatchID; - BOOLEAN bInHctTest; - BOOLEAN bWIFITest; - BOOLEAN bDualMacSmartConcurrent; - u4Byte BK_SupportAbility; - u1Byte AntDivType; - u1Byte odm_Regulation2_4G; - u1Byte odm_Regulation5G; - u1Byte u1Byte_temp; - PADAPTER PADAPTER_temp; - u1Byte *pMacPhyMode; - u8Byte *pNumTxBytesUnicast; - u8Byte *pNumRxBytesUnicast; - u1Byte *pWirelessMode; - u1Byte *pBandType; - u1Byte *pSecChOffset; - u1Byte *pSecurity; - u1Byte *pBandWidth; - u1Byte *pChannel; - BOOLEAN DPK_Done; - BOOLEAN *pbGetValueFromOtherMac; - PADAPTER *pBuddyAdapter; - BOOLEAN *pbMasterOfDMSP; - BOOLEAN *pbScanInProcess; - BOOLEAN *pbPowerSaving; - u1Byte *pOnePathCCA; - u1Byte *pAntennaTest; - BOOLEAN *pbNet_closed; - u1Byte *mp_mode; - u1Byte *pu1ForcedIgiLb; - BOOLEAN *pIsFcsModeEnable; - pu2Byte pForcedDataRate; - BOOLEAN bLinkInProcess; - BOOLEAN bWIFI_Direct; - BOOLEAN bWIFI_Display; - BOOLEAN bLinked; - BOOLEAN bsta_state; - u1Byte RSSI_Min; - u1Byte InterfaceIndex; - BOOLEAN bIsMPChip; - BOOLEAN bOneEntryOnly; - BOOLEAN bBtEnabled; - BOOLEAN bBtConnectProcess; - u1Byte btHsRssi; - BOOLEAN bBtHsOperation; - BOOLEAN bBtDisableEdcaTurbo; - BOOLEAN bBtLimitedDig; - u1Byte RSSI_A; - u1Byte RSSI_B; - u8Byte RSSI_TRSW; - u8Byte RSSI_TRSW_H; - u8Byte RSSI_TRSW_L; - u8Byte RSSI_TRSW_iso; - u1Byte RxRate; - BOOLEAN bNoisyState; - u1Byte TxRate; - u1Byte LinkedInterval; - u1Byte preChannel; - u4Byte TxagcOffsetValueA; - BOOLEAN IsTxagcOffsetPositiveA; - u4Byte TxagcOffsetValueB; - BOOLEAN IsTxagcOffsetPositiveB; - u8Byte lastTxOkCnt; - u8Byte lastRxOkCnt; - u4Byte BbSwingOffsetA; - BOOLEAN IsBbSwingOffsetPositiveA; - u4Byte BbSwingOffsetB; - BOOLEAN IsBbSwingOffsetPositiveB; - u1Byte antdiv_rssi; - u1Byte AntType; - u1Byte pre_AntType; - u1Byte antdiv_period; - u1Byte antdiv_select; - u1Byte NdpaPeriod; - BOOLEAN H2C_RARpt_connect; - u2Byte NHM_cnt_0; - u2Byte NHM_cnt_1; - s1Byte TH_L2H_ini; - s1Byte TH_EDCCA_HL_diff; - s1Byte TH_L2H_ini_backup; - BOOLEAN Carrier_Sense_enable; - u1Byte Adaptivity_IGI_upper; - BOOLEAN adaptivity_flag; - u1Byte DCbackoff; - BOOLEAN Adaptivity_enable; - u1Byte APTotalNum; - ADAPTIVITY_STATISTICS Adaptivity; - ODM_NOISE_MONITOR noise_level; - PSTA_INFO_T pODM_StaInfo[7]; - u2Byte CurrminRptTime; - ODM_RA_INFO_T RAInfo[7]; - BOOLEAN RaSupport88E; - ODM_PHY_DBG_INFO_T PhyDbgInfo; - ODM_MAC_INFO *pMacInfo; - FAT_T DM_FatTable; - DIG_T DM_DigTable; - PS_T DM_PSTable; - Pri_CCA_T DM_PriCCA; - RXHP_T DM_RXHP_Table; - RA_T DM_RA_Table; - PROM_INFO pROMInfo; - FALSE_ALARM_STATISTICS FalseAlmCnt; - CFO_TRACKING DM_CfoTrack; - FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; - SWAT_T DM_SWAT_Table; - BOOLEAN RSSI_test; - BOOLEAN bNoBeaconIn2s; - EDCA_T DM_EDCA_Table; - u4Byte WMMEDCA_BE; - BOOLEAN *pbDriverStopped; - BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep; - BOOLEAN *pinit_adpt_in_progress; - u1Byte bUseRAMask; - ODM_RATE_ADAPTIVE RateAdaptive; - ANT_DETECTED_INFO AntDetectedInfo; - ODM_RF_CAL_T RFCalibrateInfo; - u1Byte BbSwingIdxOfdm[1]; - u1Byte BbSwingIdxOfdmCurrent; - u1Byte BbSwingIdxOfdmBase[1]; - BOOLEAN BbSwingFlagOfdm; - u1Byte BbSwingIdxCck[1]; - u1Byte BbSwingIdxCckCurrent; - u1Byte BbSwingIdxCckBase[1]; - u1Byte DefaultOfdmIndex; - u1Byte DefaultCckIndex; - BOOLEAN BbSwingFlagCck; - s1Byte Absolute_OFDMSwingIdx[1]; - s1Byte Absolute_CCKSwingIdx[1]; - s1Byte Remnant_OFDMSwingIdx[1]; - s1Byte Remnant_CCKSwingIdx[1]; - s1Byte Modify_TxAGC_Value; - BOOLEAN Modify_TxAGC_Flag_PathA; - BOOLEAN Modify_TxAGC_Flag_PathB; - BOOLEAN Modify_TxAGC_Flag_PathA_CCK; +struct _atr_aligned8_ DM_Out_Source_Dynamic_Mechanism_Structure { + PADAPTER Adapter; + BOOLEAN odm_ready; + PHY_REG_PG_TYPE PhyRegPgValueType; + u1Byte PhyRegPgVersion; + u4Byte NumQryPhyStatusAll; + u4Byte LastNumQryPhyStatusAll; + u4Byte RxPWDBAve; + BOOLEAN MPDIG_2G; + u1Byte Times_2G; + BOOLEAN bCckHighPower; + u1Byte RFPathRxEnable; + u1Byte ControlChannel; + u1Byte SupportPlatform; + u4Byte SupportAbility; + u1Byte SupportInterface; + u4Byte SupportICType; + u1Byte CutVersion; + u1Byte FabVersion; + u1Byte RFType; + u1Byte RFEType; + u1Byte BoardType; + u1Byte PackageType; + u1Byte TypeGLNA; + u1Byte TypeGPA; + u1Byte TypeALNA; + u1Byte TypeAPA; + u1Byte ExtLNA; + u1Byte ExtLNA5G; + u1Byte ExtPA; + u1Byte ExtPA5G; + u1Byte ExtTRSW; + u1Byte PatchID; + BOOLEAN bInHctTest; + BOOLEAN bWIFITest; + BOOLEAN bDualMacSmartConcurrent; + u4Byte BK_SupportAbility; + u1Byte AntDivType; + u1Byte odm_Regulation2_4G; + u1Byte odm_Regulation5G; + u1Byte u1Byte_temp; + PADAPTER PADAPTER_temp; + u1Byte *pMacPhyMode; + u8Byte *pNumTxBytesUnicast; + u8Byte *pNumRxBytesUnicast; + u1Byte *pWirelessMode; + u1Byte *pBandType; + u1Byte *pSecChOffset; + u1Byte *pSecurity; + u1Byte *pBandWidth; + u1Byte *pChannel; + BOOLEAN DPK_Done; + BOOLEAN *pbGetValueFromOtherMac; + PADAPTER *pBuddyAdapter; + BOOLEAN *pbMasterOfDMSP; + BOOLEAN *pbScanInProcess; + BOOLEAN *pbPowerSaving; + u1Byte *pOnePathCCA; + u1Byte *pAntennaTest; + BOOLEAN *pbNet_closed; + u1Byte *mp_mode; + u1Byte *pu1ForcedIgiLb; + BOOLEAN *pIsFcsModeEnable; + pu2Byte pForcedDataRate; + BOOLEAN bLinkInProcess; + BOOLEAN bWIFI_Direct; + BOOLEAN bWIFI_Display; + BOOLEAN bLinked; + BOOLEAN bsta_state; + u1Byte RSSI_Min; + u1Byte InterfaceIndex; + BOOLEAN bIsMPChip; + BOOLEAN bOneEntryOnly; + BOOLEAN bBtEnabled; + BOOLEAN bBtConnectProcess; + u1Byte btHsRssi; + BOOLEAN bBtHsOperation; + BOOLEAN bBtDisableEdcaTurbo; + BOOLEAN bBtLimitedDig; + u1Byte RSSI_A; + u1Byte RSSI_B; + u8Byte RSSI_TRSW; + u8Byte RSSI_TRSW_H; + u8Byte RSSI_TRSW_L; + u8Byte RSSI_TRSW_iso; + u1Byte RxRate; + BOOLEAN bNoisyState; + u1Byte TxRate; + u1Byte LinkedInterval; + u1Byte preChannel; + u4Byte TxagcOffsetValueA; + BOOLEAN IsTxagcOffsetPositiveA; + u4Byte TxagcOffsetValueB; + BOOLEAN IsTxagcOffsetPositiveB; + u8Byte lastTxOkCnt; + u8Byte lastRxOkCnt; + u4Byte BbSwingOffsetA; + BOOLEAN IsBbSwingOffsetPositiveA; + u4Byte BbSwingOffsetB; + BOOLEAN IsBbSwingOffsetPositiveB; + u1Byte antdiv_rssi; + u1Byte AntType; + u1Byte pre_AntType; + u1Byte antdiv_period; + u1Byte antdiv_select; + u1Byte NdpaPeriod; + BOOLEAN H2C_RARpt_connect; + u2Byte NHM_cnt_0; + u2Byte NHM_cnt_1; + s1Byte TH_L2H_ini; + s1Byte TH_EDCCA_HL_diff; + s1Byte TH_L2H_ini_backup; + BOOLEAN Carrier_Sense_enable; + u1Byte Adaptivity_IGI_upper; + BOOLEAN adaptivity_flag; + u1Byte DCbackoff; + BOOLEAN Adaptivity_enable; + u1Byte APTotalNum; + ADAPTIVITY_STATISTICS Adaptivity; + ODM_NOISE_MONITOR noise_level; + PSTA_INFO_T pODM_StaInfo[7]; + u2Byte CurrminRptTime; + ODM_RA_INFO_T RAInfo[7]; + BOOLEAN RaSupport88E; + ODM_PHY_DBG_INFO_T PhyDbgInfo; + ODM_MAC_INFO *pMacInfo; + FAT_T DM_FatTable; + DIG_T DM_DigTable; + PS_T DM_PSTable; + Pri_CCA_T DM_PriCCA; + RXHP_T DM_RXHP_Table; + RA_T DM_RA_Table; + PROM_INFO pROMInfo; + FALSE_ALARM_STATISTICS FalseAlmCnt; + CFO_TRACKING DM_CfoTrack; + FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; + SWAT_T DM_SWAT_Table; + BOOLEAN RSSI_test; + BOOLEAN bNoBeaconIn2s; + EDCA_T DM_EDCA_Table; + u4Byte WMMEDCA_BE; + BOOLEAN *pbDriverStopped; + BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep; + BOOLEAN *pinit_adpt_in_progress; + u1Byte bUseRAMask; + ODM_RATE_ADAPTIVE RateAdaptive; + ANT_DETECTED_INFO AntDetectedInfo; + ODM_RF_CAL_T RFCalibrateInfo; + u1Byte BbSwingIdxOfdm[1]; + u1Byte BbSwingIdxOfdmCurrent; + u1Byte BbSwingIdxOfdmBase[1]; + BOOLEAN BbSwingFlagOfdm; + u1Byte BbSwingIdxCck[1]; + u1Byte BbSwingIdxCckCurrent; + u1Byte BbSwingIdxCckBase[1]; + u1Byte DefaultOfdmIndex; + u1Byte DefaultCckIndex; + BOOLEAN BbSwingFlagCck; + s1Byte Absolute_OFDMSwingIdx[1]; + s1Byte Absolute_CCKSwingIdx[1]; + s1Byte Remnant_OFDMSwingIdx[1]; + s1Byte Remnant_CCKSwingIdx[1]; + s1Byte Modify_TxAGC_Value; + BOOLEAN Modify_TxAGC_Flag_PathA; + BOOLEAN Modify_TxAGC_Flag_PathB; + BOOLEAN Modify_TxAGC_Flag_PathA_CCK; }; typedef struct DM_Out_Source_Dynamic_Mechanism_Structure DM_ODM_T; typedef struct DM_Out_Source_Dynamic_Mechanism_Structure *PDM_ODM_T; - -enum _PWRTRACK_CONTROL_METHOD //: __int32 +enum _PWRTRACK_CONTROL_METHOD //: sint32_t { - BBSWING = 0x0, - TXAGC = 0x1, - MIX_MODE = 0x2, + BBSWING = 0x0, TXAGC = 0x1, MIX_MODE = 0x2, }; typedef enum _PWRTRACK_CONTROL_METHOD PWRTRACK_METHOD; @@ -3017,115 +2896,110 @@ typedef void (*FuncSwing)(PDM_ODM_T, ps1Byte *, ps1Byte *, ps1Byte *, ps1Byte *) typedef void (*FuncSwingXtal)(PDM_ODM_T, ps1Byte *, ps1Byte *); typedef void (*FuncSetXtal)(PDM_ODM_T); -struct _TXPWRTRACK_CFG -{ - u1Byte SwingTableSize_CCK; - u1Byte SwingTableSize_OFDM; - u1Byte Threshold_IQK; - u1Byte AverageThermalNum; - u1Byte RfPathCount; - u4Byte ThermalRegAddr; - FuncSetPwr ODM_TxPwrTrackSetPwr; - FuncIQK DoIQK; - FuncLCK PHY_LCCalibrate; - FuncSwing GetDeltaSwingTable; - FuncSwingXtal GetDeltaSwingXtalTable; - FuncSetXtal ODM_TxXtalTrackSetXtal; +struct _TXPWRTRACK_CFG { + u1Byte SwingTableSize_CCK; + u1Byte SwingTableSize_OFDM; + u1Byte Threshold_IQK; + u1Byte AverageThermalNum; + u1Byte RfPathCount; + u4Byte ThermalRegAddr; + FuncSetPwr ODM_TxPwrTrackSetPwr; + FuncIQK DoIQK; + FuncLCK PHY_LCCalibrate; + FuncSwing GetDeltaSwingTable; + FuncSwingXtal GetDeltaSwingXtalTable; + FuncSetXtal ODM_TxXtalTrackSetXtal; }; typedef struct _TXPWRTRACK_CFG *PTXPWRTRACK_CFG; -struct _RSVDPAGE_LOC -{ - uint8_t LocProbeRsp; - uint8_t LocPsPoll; - uint8_t LocNullData; - uint8_t LocQosNull; - uint8_t LocBTQosNull; +struct _RSVDPAGE_LOC { + uint8_t LocProbeRsp; + uint8_t LocPsPoll; + uint8_t LocNullData; + uint8_t LocQosNull; + uint8_t LocBTQosNull; }; typedef struct _RSVDPAGE_LOC RSVDPAGE_LOC_8195A; typedef struct _RSVDPAGE_LOC *PRSVDPAGE_LOC_8195A; -enum _RT_MEDIA_STATUS //: __int32 +enum _RT_MEDIA_STATUS //: sint32_t { - RT_MEDIA_DISCONNECT = 0x0, - RT_MEDIA_CONNECT = 0x1, + RT_MEDIA_DISCONNECT = 0x0, RT_MEDIA_CONNECT = 0x1, }; -struct _H2CParam_RsvdPage_ -{ - RSVDPAGE_LOC_8195A RsvdPageLoc; - uint8_t *ReservedPagePacket; - uint32_t TotalPacketLen; +struct _H2CParam_RsvdPage_ { + RSVDPAGE_LOC_8195A RsvdPageLoc; + uint8_t *ReservedPagePacket; + uint32_t TotalPacketLen; }; typedef struct _H2CParam_RsvdPage_ H2CParam_RsvdPage; typedef struct _H2CParam_RsvdPage_ *PH2CParam_RsvdPage; -struct _NDIS_802_11_VARIABLE_IEs -{ - uint8_t ElementID; - uint8_t Length; - uint8_t data[1]; +struct _NDIS_802_11_VARIABLE_IEs { + uint8_t ElementID; + uint8_t Length; + uint8_t data[1]; }; typedef struct _NDIS_802_11_VARIABLE_IEs *PNDIS_802_11_VARIABLE_IEs; -enum _NDIS_802_11_AUTHENTICATION_MODE //: __int32 +enum _NDIS_802_11_AUTHENTICATION_MODE //: sint32_t { - Ndis802_11AuthModeOpen = 0x0, - Ndis802_11AuthModeShared = 0x1, - Ndis802_11AuthModeAutoSwitch = 0x2, - Ndis802_11AuthModeWPA = 0x3, - Ndis802_11AuthModeWPAPSK = 0x4, - Ndis802_11AuthModeWPANone = 0x5, - Ndis802_11AuthModeWAPI = 0x6, - Ndis802_11AuthModeMax = 0x7, + Ndis802_11AuthModeOpen = 0x0, + Ndis802_11AuthModeShared = 0x1, + Ndis802_11AuthModeAutoSwitch = 0x2, + Ndis802_11AuthModeWPA = 0x3, + Ndis802_11AuthModeWPAPSK = 0x4, + Ndis802_11AuthModeWPANone = 0x5, + Ndis802_11AuthModeWAPI = 0x6, + Ndis802_11AuthModeMax = 0x7, }; typedef enum _NDIS_802_11_AUTHENTICATION_MODE NDIS_802_11_AUTHENTICATION_MODE; -enum _NDIS_802_11_WEP_STATUS //: __int32 +enum _NDIS_802_11_WEP_STATUS //: sint32_t { - Ndis802_11WEPEnabled = 0x0, - Ndis802_11Encryption1Enabled = 0x0, - Ndis802_11WEPDisabled = 0x1, - Ndis802_11EncryptionDisabled = 0x1, - Ndis802_11WEPKeyAbsent = 0x2, - Ndis802_11Encryption1KeyAbsent = 0x2, - Ndis802_11WEPNotSupported = 0x3, - Ndis802_11EncryptionNotSupported = 0x3, - Ndis802_11Encryption2Enabled = 0x4, - Ndis802_11Encryption2KeyAbsent = 0x5, - Ndis802_11Encryption3Enabled = 0x6, - Ndis802_11Encryption3KeyAbsent = 0x7, - Ndis802_11_EncrypteionWAPI = 0x8, + Ndis802_11WEPEnabled = 0x0, + Ndis802_11Encryption1Enabled = 0x0, + Ndis802_11WEPDisabled = 0x1, + Ndis802_11EncryptionDisabled = 0x1, + Ndis802_11WEPKeyAbsent = 0x2, + Ndis802_11Encryption1KeyAbsent = 0x2, + Ndis802_11WEPNotSupported = 0x3, + Ndis802_11EncryptionNotSupported = 0x3, + Ndis802_11Encryption2Enabled = 0x4, + Ndis802_11Encryption2KeyAbsent = 0x5, + Ndis802_11Encryption3Enabled = 0x6, + Ndis802_11Encryption3KeyAbsent = 0x7, + Ndis802_11_EncrypteionWAPI = 0x8, }; typedef enum _NDIS_802_11_WEP_STATUS NDIS_802_11_WEP_STATUS; -struct __attribute__((packed)) __attribute__((aligned(1))) rtk_sc -{ - u8 pattern_type; - u8 smac[6]; - u8 bssid[2][6]; - u8 ssid[32]; - u8 password[64]; - u32 ip_addr; - u8 sync_pkt[9][6]; - u8 profile_pkt[256][6]; - u32 profile_pkt_len; - u8 plain_buf[256]; - u32 plain_len; - u8 key_buf[32]; - u32 key_len; - u8 crypt_buf[256]; - u32 crypt_len; - s32 pattern_index; - struct pattern_ops *pattern[5]; - u8 max_pattern_num; - u8 pin[65]; - u8 default_pin[65]; - u8 have_pin; - u16 device_type; - u8 device_name[64]; - u8 bcast_crypt_buf[256]; +struct __attribute__((packed)) __attribute__((aligned(1))) rtk_sc { + u8 pattern_type; + u8 smac[6]; + u8 bssid[2][6]; + u8 ssid[32]; + u8 password[64]; + u32 ip_addr; + u8 sync_pkt[9][6]; + u8 profile_pkt[256][6]; + u32 profile_pkt_len; + u8 plain_buf[256]; + u32 plain_len; + u8 key_buf[32]; + u32 key_len; + u8 crypt_buf[256]; + u32 crypt_len; + s32 pattern_index; + struct pattern_ops *pattern[5]; + u8 max_pattern_num; + u8 pin[65]; + u8 default_pin[65]; + u8 have_pin; + u16 device_type; + u8 device_name[64]; + u8 bcast_crypt_buf[256]; }; + struct pattern_ops; typedef s32 (*sc_check_pattern_call_back)(struct pattern_ops *, struct rtk_sc *); @@ -3134,446 +3008,422 @@ typedef s32 (*sc_generate_key_call_back)(struct pattern_ops *, struct rtk_sc *); typedef s32 (*sc_decode_profile_call_back)(struct pattern_ops *, struct rtk_sc *); typedef s32 (*sc_get_tlv_info_call_back)(struct pattern_ops *, struct rtk_sc *); -struct pattern_ops -{ - u32 index; - u32 flag; - u8 name[32]; - sc_check_pattern_call_back check_pattern; - sc_get_cipher_info_call_back get_cipher_info; - sc_generate_key_call_back generate_key; - sc_decode_profile_call_back decode_profile; - sc_get_tlv_info_call_back get_tlv_info; +struct pattern_ops { + u32 index; + u32 flag; + u8 name[32]; + sc_check_pattern_call_back check_pattern; + sc_get_cipher_info_call_back get_cipher_info; + sc_generate_key_call_back generate_key; + sc_decode_profile_call_back decode_profile; + sc_get_tlv_info_call_back get_tlv_info; }; -struct __attribute__((aligned(2))) _WL_PWR_CFG_ -{ - uint16_t offset; - uint8_t cut_msk; - u8 fab_msk : 4; - u8 interface_msk : 4; - u8 base : 4; - u8 cmd : 4; - uint8_t msk; - uint8_t value; +struct _atr_aligned2_ _WL_PWR_CFG_ { // __attribute__((packed))!? + uint16_t offset; + uint8_t cut_msk; + u8 fab_msk :4; + u8 interface_msk :4; + u8 base :4; + u8 cmd :4; + uint8_t msk; + uint8_t value; }; typedef struct _WL_PWR_CFG_ WLAN_PWR_CFG; - -struct cmd_hdl -{ - unsigned int parmsize; - uint8_t (*h2cfuns)(struct _ADAPTER *, uint8_t *); +struct cmd_hdl { + uint32_t parmsize; + uint8_t (*h2cfuns)(struct _ADAPTER *, uint8_t *); }; -struct _cmd_callback -{ - uint32_t cmd_code; - void (*callback)(_adapter *, struct cmd_obj *); +struct _cmd_callback { + uint32_t cmd_code; + void (*callback)(_adapter *, struct cmd_obj *); }; -enum _ODM_Common_Info_Definition //: __int32 +enum _ODM_Common_Info_Definition //: sint32_t { - ODM_CMNINFO_PLATFORM = 0x0, - ODM_CMNINFO_ABILITY = 0x1, - ODM_CMNINFO_INTERFACE = 0x2, - ODM_CMNINFO_MP_TEST_CHIP = 0x3, - ODM_CMNINFO_IC_TYPE = 0x4, - ODM_CMNINFO_CUT_VER = 0x5, - ODM_CMNINFO_FAB_VER = 0x6, - ODM_CMNINFO_RF_TYPE = 0x7, - ODM_CMNINFO_RFE_TYPE = 0x8, - ODM_CMNINFO_BOARD_TYPE = 0x9, - ODM_CMNINFO_PACKAGE_TYPE = 0xA, - ODM_CMNINFO_EXT_LNA = 0xB, - ODM_CMNINFO_5G_EXT_LNA = 0xC, - ODM_CMNINFO_EXT_PA = 0xD, - ODM_CMNINFO_5G_EXT_PA = 0xE, - ODM_CMNINFO_GPA = 0xF, - ODM_CMNINFO_APA = 0x10, - ODM_CMNINFO_GLNA = 0x11, - ODM_CMNINFO_ALNA = 0x12, - ODM_CMNINFO_EXT_TRSW = 0x13, - ODM_CMNINFO_PATCH_ID = 0x14, - ODM_CMNINFO_BINHCT_TEST = 0x15, - ODM_CMNINFO_BWIFI_TEST = 0x16, - ODM_CMNINFO_SMART_CONCURRENT = 0x17, - ODM_CMNINFO_DOMAIN_CODE_2G = 0x18, - ODM_CMNINFO_DOMAIN_CODE_5G = 0x19, - ODM_CMNINFO_EEPROMVERSION = 0x1A, - ODM_CMNINFO_CRYSTALCAP = 0x1B, - ODM_CMNINFO_MAC_PHY_MODE = 0x1C, - ODM_CMNINFO_TX_UNI = 0x1D, - ODM_CMNINFO_RX_UNI = 0x1E, - ODM_CMNINFO_WM_MODE = 0x1F, - ODM_CMNINFO_BAND = 0x20, - ODM_CMNINFO_SEC_CHNL_OFFSET = 0x21, - ODM_CMNINFO_SEC_MODE = 0x22, - ODM_CMNINFO_BW = 0x23, - ODM_CMNINFO_CHNL = 0x24, - ODM_CMNINFO_FORCED_RATE = 0x25, - ODM_CMNINFO_DMSP_GET_VALUE = 0x26, - ODM_CMNINFO_BUDDY_ADAPTOR = 0x27, - ODM_CMNINFO_DMSP_IS_MASTER = 0x28, - ODM_CMNINFO_SCAN = 0x29, - ODM_CMNINFO_POWER_SAVING = 0x2A, - ODM_CMNINFO_ONE_PATH_CCA = 0x2B, - ODM_CMNINFO_DRV_STOP = 0x2C, - ODM_CMNINFO_PNP_IN = 0x2D, - ODM_CMNINFO_INIT_ON = 0x2E, - ODM_CMNINFO_ANT_TEST = 0x2F, - ODM_CMNINFO_NET_CLOSED = 0x30, - ODM_CMNINFO_MP_MODE = 0x31, - ODM_CMNINFO_FORCED_IGI_LB = 0x32, - ODM_CMNINFO_P2P_LINK = 0x33, - ODM_CMNINFO_FCS_MODE = 0x34, - ODM_CMNINFO_WIFI_DIRECT = 0x35, - ODM_CMNINFO_WIFI_DISPLAY = 0x36, - ODM_CMNINFO_LINK_IN_PROGRESS = 0x37, - ODM_CMNINFO_LINK = 0x38, - ODM_CMNINFO_STATION_STATE = 0x39, - ODM_CMNINFO_RSSI_MIN = 0x3A, - ODM_CMNINFO_DBG_COMP = 0x3B, - ODM_CMNINFO_DBG_LEVEL = 0x3C, - ODM_CMNINFO_RA_THRESHOLD_HIGH = 0x3D, - ODM_CMNINFO_RA_THRESHOLD_LOW = 0x3E, - ODM_CMNINFO_RF_ANTENNA_TYPE = 0x3F, - ODM_CMNINFO_BT_ENABLED = 0x40, - ODM_CMNINFO_BT_HS_CONNECT_PROCESS = 0x41, - ODM_CMNINFO_BT_HS_RSSI = 0x42, - ODM_CMNINFO_BT_OPERATION = 0x43, - ODM_CMNINFO_BT_LIMITED_DIG = 0x44, - ODM_CMNINFO_BT_DISABLE_EDCA = 0x45, - ODM_CMNINFO_NO_BEACON_IN_2S = 0x46, - ODM_CMNINFO_STA_STATUS = 0x47, - ODM_CMNINFO_PHY_STATUS = 0x48, - ODM_CMNINFO_MAC_STATUS = 0x49, - ODM_CMNINFO_MAX = 0x4A, + ODM_CMNINFO_PLATFORM = 0x0, + ODM_CMNINFO_ABILITY = 0x1, + ODM_CMNINFO_INTERFACE = 0x2, + ODM_CMNINFO_MP_TEST_CHIP = 0x3, + ODM_CMNINFO_IC_TYPE = 0x4, + ODM_CMNINFO_CUT_VER = 0x5, + ODM_CMNINFO_FAB_VER = 0x6, + ODM_CMNINFO_RF_TYPE = 0x7, + ODM_CMNINFO_RFE_TYPE = 0x8, + ODM_CMNINFO_BOARD_TYPE = 0x9, + ODM_CMNINFO_PACKAGE_TYPE = 0xA, + ODM_CMNINFO_EXT_LNA = 0xB, + ODM_CMNINFO_5G_EXT_LNA = 0xC, + ODM_CMNINFO_EXT_PA = 0xD, + ODM_CMNINFO_5G_EXT_PA = 0xE, + ODM_CMNINFO_GPA = 0xF, + ODM_CMNINFO_APA = 0x10, + ODM_CMNINFO_GLNA = 0x11, + ODM_CMNINFO_ALNA = 0x12, + ODM_CMNINFO_EXT_TRSW = 0x13, + ODM_CMNINFO_PATCH_ID = 0x14, + ODM_CMNINFO_BINHCT_TEST = 0x15, + ODM_CMNINFO_BWIFI_TEST = 0x16, + ODM_CMNINFO_SMART_CONCURRENT = 0x17, + ODM_CMNINFO_DOMAIN_CODE_2G = 0x18, + ODM_CMNINFO_DOMAIN_CODE_5G = 0x19, + ODM_CMNINFO_EEPROMVERSION = 0x1A, + ODM_CMNINFO_CRYSTALCAP = 0x1B, + ODM_CMNINFO_MAC_PHY_MODE = 0x1C, + ODM_CMNINFO_TX_UNI = 0x1D, + ODM_CMNINFO_RX_UNI = 0x1E, + ODM_CMNINFO_WM_MODE = 0x1F, + ODM_CMNINFO_BAND = 0x20, + ODM_CMNINFO_SEC_CHNL_OFFSET = 0x21, + ODM_CMNINFO_SEC_MODE = 0x22, + ODM_CMNINFO_BW = 0x23, + ODM_CMNINFO_CHNL = 0x24, + ODM_CMNINFO_FORCED_RATE = 0x25, + ODM_CMNINFO_DMSP_GET_VALUE = 0x26, + ODM_CMNINFO_BUDDY_ADAPTOR = 0x27, + ODM_CMNINFO_DMSP_IS_MASTER = 0x28, + ODM_CMNINFO_SCAN = 0x29, + ODM_CMNINFO_POWER_SAVING = 0x2A, + ODM_CMNINFO_ONE_PATH_CCA = 0x2B, + ODM_CMNINFO_DRV_STOP = 0x2C, + ODM_CMNINFO_PNP_IN = 0x2D, + ODM_CMNINFO_INIT_ON = 0x2E, + ODM_CMNINFO_ANT_TEST = 0x2F, + ODM_CMNINFO_NET_CLOSED = 0x30, + ODM_CMNINFO_MP_MODE = 0x31, + ODM_CMNINFO_FORCED_IGI_LB = 0x32, + ODM_CMNINFO_P2P_LINK = 0x33, + ODM_CMNINFO_FCS_MODE = 0x34, + ODM_CMNINFO_WIFI_DIRECT = 0x35, + ODM_CMNINFO_WIFI_DISPLAY = 0x36, + ODM_CMNINFO_LINK_IN_PROGRESS = 0x37, + ODM_CMNINFO_LINK = 0x38, + ODM_CMNINFO_STATION_STATE = 0x39, + ODM_CMNINFO_RSSI_MIN = 0x3A, + ODM_CMNINFO_DBG_COMP = 0x3B, + ODM_CMNINFO_DBG_LEVEL = 0x3C, + ODM_CMNINFO_RA_THRESHOLD_HIGH = 0x3D, + ODM_CMNINFO_RA_THRESHOLD_LOW = 0x3E, + ODM_CMNINFO_RF_ANTENNA_TYPE = 0x3F, + ODM_CMNINFO_BT_ENABLED = 0x40, + ODM_CMNINFO_BT_HS_CONNECT_PROCESS = 0x41, + ODM_CMNINFO_BT_HS_RSSI = 0x42, + ODM_CMNINFO_BT_OPERATION = 0x43, + ODM_CMNINFO_BT_LIMITED_DIG = 0x44, + ODM_CMNINFO_BT_DISABLE_EDCA = 0x45, + ODM_CMNINFO_NO_BEACON_IN_2S = 0x46, + ODM_CMNINFO_STA_STATUS = 0x47, + ODM_CMNINFO_PHY_STATUS = 0x48, + ODM_CMNINFO_MAC_STATUS = 0x49, + ODM_CMNINFO_MAX = 0x4A, }; typedef enum _ODM_Common_Info_Definition ODM_CMNINFO_E; -enum _ODM_Support_Ability_Definition // : __int32 +enum _ODM_Support_Ability_Definition // : sint32_t { - ODM_BB_DIG = 0x1, - ODM_BB_RA_MASK = 0x2, - ODM_BB_DYNAMIC_TXPWR = 0x4, - ODM_BB_FA_CNT = 0x8, - ODM_BB_RSSI_MONITOR = 0x10, - ODM_BB_CCK_PD = 0x20, - ODM_BB_ANT_DIV = 0x40, - ODM_BB_PWR_SAVE = 0x80, - ODM_BB_PWR_TRAIN = 0x100, - ODM_BB_RATE_ADAPTIVE = 0x200, - ODM_BB_PATH_DIV = 0x400, - ODM_BB_PSD = 0x800, - ODM_BB_RXHP = 0x1000, - ODM_BB_ADAPTIVITY = 0x2000, - ODM_BB_CFO_TRACKING = 0x4000, - ODM_BB_NHM_CNT = 0x8000, - ODM_BB_PRIMARY_CCA = 0x10000, - ODM_MAC_EDCA_TURBO = 0x100000, - ODM_MAC_EARLY_MODE = 0x200000, - ODM_RF_TX_PWR_TRACK = 0x1000000, - ODM_RF_RX_GAIN_TRACK = 0x2000000, - ODM_RF_CALIBRATION = 0x4000000, + ODM_BB_DIG = 0x1, + ODM_BB_RA_MASK = 0x2, + ODM_BB_DYNAMIC_TXPWR = 0x4, + ODM_BB_FA_CNT = 0x8, + ODM_BB_RSSI_MONITOR = 0x10, + ODM_BB_CCK_PD = 0x20, + ODM_BB_ANT_DIV = 0x40, + ODM_BB_PWR_SAVE = 0x80, + ODM_BB_PWR_TRAIN = 0x100, + ODM_BB_RATE_ADAPTIVE = 0x200, + ODM_BB_PATH_DIV = 0x400, + ODM_BB_PSD = 0x800, + ODM_BB_RXHP = 0x1000, + ODM_BB_ADAPTIVITY = 0x2000, + ODM_BB_CFO_TRACKING = 0x4000, + ODM_BB_NHM_CNT = 0x8000, + ODM_BB_PRIMARY_CCA = 0x10000, + ODM_MAC_EDCA_TURBO = 0x100000, + ODM_MAC_EARLY_MODE = 0x200000, + ODM_RF_TX_PWR_TRACK = 0x1000000, + ODM_RF_RX_GAIN_TRACK = 0x2000000, + ODM_RF_CALIBRATION = 0x4000000, }; -enum _RF_PATH //: __int32 +enum _RF_PATH //: sint32_t { - RF_PATH_A = 0x0, - RF_PATH_B = 0x1, - RF_PATH_C = 0x2, - RF_PATH_D = 0x3, + RF_PATH_A = 0x0, RF_PATH_B = 0x1, RF_PATH_C = 0x2, RF_PATH_D = 0x3, }; typedef enum _RF_PATH RF_PATH; -enum _EXTCHNL_OFFSET //: __int32 +enum _EXTCHNL_OFFSET //: sint32_t { - EXTCHNL_OFFSET_NO_EXT = 0x0, - EXTCHNL_OFFSET_UPPER = 0x1, - EXTCHNL_OFFSET_NO_DEF = 0x2, - EXTCHNL_OFFSET_LOWER = 0x3, + EXTCHNL_OFFSET_NO_EXT = 0x0, + EXTCHNL_OFFSET_UPPER = 0x1, + EXTCHNL_OFFSET_NO_DEF = 0x2, + EXTCHNL_OFFSET_LOWER = 0x3, }; typedef enum _EXTCHNL_OFFSET EXTCHNL_OFFSET; -enum MGN_RATE //: __int32 +enum MGN_RATE //: sint32_t { - MGN_1M = 0x2, - MGN_2M = 0x4, - MGN_5_5M = 0xB, - MGN_6M = 0xC, - MGN_9M = 0x12, - MGN_11M = 0x16, - MGN_12M = 0x18, - MGN_18M = 0x24, - MGN_24M = 0x30, - MGN_36M = 0x48, - MGN_48M = 0x60, - MGN_54M = 0x6C, - MGN_MCS32 = 0x7F, - MGN_MCS0 = 0x80, - MGN_MCS1 = 0x81, - MGN_MCS2 = 0x82, - MGN_MCS3 = 0x83, - MGN_MCS4 = 0x84, - MGN_MCS5 = 0x85, - MGN_MCS6 = 0x86, - MGN_MCS7 = 0x87, - MGN_MCS8 = 0x88, - MGN_MCS9 = 0x89, - MGN_MCS10 = 0x8A, - MGN_MCS11 = 0x8B, - MGN_MCS12 = 0x8C, - MGN_MCS13 = 0x8D, - MGN_MCS14 = 0x8E, - MGN_MCS15 = 0x8F, - MGN_MCS16 = 0x90, - MGN_MCS17 = 0x91, - MGN_MCS18 = 0x92, - MGN_MCS19 = 0x93, - MGN_MCS20 = 0x94, - MGN_MCS21 = 0x95, - MGN_MCS22 = 0x96, - MGN_MCS23 = 0x97, - MGN_MCS24 = 0x98, - MGN_MCS25 = 0x99, - MGN_MCS26 = 0x9A, - MGN_MCS27 = 0x9B, - MGN_MCS28 = 0x9C, - MGN_MCS29 = 0x9D, - MGN_MCS30 = 0x9E, - MGN_MCS31 = 0x9F, - MGN_VHT1SS_MCS0 = 0xA0, - MGN_VHT1SS_MCS1 = 0xA1, - MGN_VHT1SS_MCS2 = 0xA2, - MGN_VHT1SS_MCS3 = 0xA3, - MGN_VHT1SS_MCS4 = 0xA4, - MGN_VHT1SS_MCS5 = 0xA5, - MGN_VHT1SS_MCS6 = 0xA6, - MGN_VHT1SS_MCS7 = 0xA7, - MGN_VHT1SS_MCS8 = 0xA8, - MGN_VHT1SS_MCS9 = 0xA9, - MGN_VHT2SS_MCS0 = 0xAA, - MGN_VHT2SS_MCS1 = 0xAB, - MGN_VHT2SS_MCS2 = 0xAC, - MGN_VHT2SS_MCS3 = 0xAD, - MGN_VHT2SS_MCS4 = 0xAE, - MGN_VHT2SS_MCS5 = 0xAF, - MGN_VHT2SS_MCS6 = 0xB0, - MGN_VHT2SS_MCS7 = 0xB1, - MGN_VHT2SS_MCS8 = 0xB2, - MGN_VHT2SS_MCS9 = 0xB3, - MGN_VHT3SS_MCS0 = 0xB4, - MGN_VHT3SS_MCS1 = 0xB5, - MGN_VHT3SS_MCS2 = 0xB6, - MGN_VHT3SS_MCS3 = 0xB7, - MGN_VHT3SS_MCS4 = 0xB8, - MGN_VHT3SS_MCS5 = 0xB9, - MGN_VHT3SS_MCS6 = 0xBA, - MGN_VHT3SS_MCS7 = 0xBB, - MGN_VHT3SS_MCS8 = 0xBC, - MGN_VHT3SS_MCS9 = 0xBD, - MGN_VHT4SS_MCS0 = 0xBE, - MGN_VHT4SS_MCS1 = 0xBF, - MGN_VHT4SS_MCS2 = 0xC0, - MGN_VHT4SS_MCS3 = 0xC1, - MGN_VHT4SS_MCS4 = 0xC2, - MGN_VHT4SS_MCS5 = 0xC3, - MGN_VHT4SS_MCS6 = 0xC4, - MGN_VHT4SS_MCS7 = 0xC5, - MGN_VHT4SS_MCS8 = 0xC6, - MGN_VHT4SS_MCS9 = 0xC7, - MGN_UNKNOWN = 0xC8, + MGN_1M = 0x2, + MGN_2M = 0x4, + MGN_5_5M = 0xB, + MGN_6M = 0xC, + MGN_9M = 0x12, + MGN_11M = 0x16, + MGN_12M = 0x18, + MGN_18M = 0x24, + MGN_24M = 0x30, + MGN_36M = 0x48, + MGN_48M = 0x60, + MGN_54M = 0x6C, + MGN_MCS32 = 0x7F, + MGN_MCS0 = 0x80, + MGN_MCS1 = 0x81, + MGN_MCS2 = 0x82, + MGN_MCS3 = 0x83, + MGN_MCS4 = 0x84, + MGN_MCS5 = 0x85, + MGN_MCS6 = 0x86, + MGN_MCS7 = 0x87, + MGN_MCS8 = 0x88, + MGN_MCS9 = 0x89, + MGN_MCS10 = 0x8A, + MGN_MCS11 = 0x8B, + MGN_MCS12 = 0x8C, + MGN_MCS13 = 0x8D, + MGN_MCS14 = 0x8E, + MGN_MCS15 = 0x8F, + MGN_MCS16 = 0x90, + MGN_MCS17 = 0x91, + MGN_MCS18 = 0x92, + MGN_MCS19 = 0x93, + MGN_MCS20 = 0x94, + MGN_MCS21 = 0x95, + MGN_MCS22 = 0x96, + MGN_MCS23 = 0x97, + MGN_MCS24 = 0x98, + MGN_MCS25 = 0x99, + MGN_MCS26 = 0x9A, + MGN_MCS27 = 0x9B, + MGN_MCS28 = 0x9C, + MGN_MCS29 = 0x9D, + MGN_MCS30 = 0x9E, + MGN_MCS31 = 0x9F, + MGN_VHT1SS_MCS0 = 0xA0, + MGN_VHT1SS_MCS1 = 0xA1, + MGN_VHT1SS_MCS2 = 0xA2, + MGN_VHT1SS_MCS3 = 0xA3, + MGN_VHT1SS_MCS4 = 0xA4, + MGN_VHT1SS_MCS5 = 0xA5, + MGN_VHT1SS_MCS6 = 0xA6, + MGN_VHT1SS_MCS7 = 0xA7, + MGN_VHT1SS_MCS8 = 0xA8, + MGN_VHT1SS_MCS9 = 0xA9, + MGN_VHT2SS_MCS0 = 0xAA, + MGN_VHT2SS_MCS1 = 0xAB, + MGN_VHT2SS_MCS2 = 0xAC, + MGN_VHT2SS_MCS3 = 0xAD, + MGN_VHT2SS_MCS4 = 0xAE, + MGN_VHT2SS_MCS5 = 0xAF, + MGN_VHT2SS_MCS6 = 0xB0, + MGN_VHT2SS_MCS7 = 0xB1, + MGN_VHT2SS_MCS8 = 0xB2, + MGN_VHT2SS_MCS9 = 0xB3, + MGN_VHT3SS_MCS0 = 0xB4, + MGN_VHT3SS_MCS1 = 0xB5, + MGN_VHT3SS_MCS2 = 0xB6, + MGN_VHT3SS_MCS3 = 0xB7, + MGN_VHT3SS_MCS4 = 0xB8, + MGN_VHT3SS_MCS5 = 0xB9, + MGN_VHT3SS_MCS6 = 0xBA, + MGN_VHT3SS_MCS7 = 0xBB, + MGN_VHT3SS_MCS8 = 0xBC, + MGN_VHT3SS_MCS9 = 0xBD, + MGN_VHT4SS_MCS0 = 0xBE, + MGN_VHT4SS_MCS1 = 0xBF, + MGN_VHT4SS_MCS2 = 0xC0, + MGN_VHT4SS_MCS3 = 0xC1, + MGN_VHT4SS_MCS4 = 0xC2, + MGN_VHT4SS_MCS5 = 0xC3, + MGN_VHT4SS_MCS6 = 0xC4, + MGN_VHT4SS_MCS7 = 0xC5, + MGN_VHT4SS_MCS8 = 0xC6, + MGN_VHT4SS_MCS9 = 0xC7, + MGN_UNKNOWN = 0xC8, }; -struct _RT_CHANNEL_PLAN_2G -{ - unsigned __int8 Channel[14]; - unsigned __int8 Len; +struct _RT_CHANNEL_PLAN_2G { + uint8_t Channel[14]; + uint8_t Len; }; typedef struct _RT_CHANNEL_PLAN_2G RT_CHANNEL_PLAN_2G; -struct _RT_CHANNEL_PLAN_MAP -{ - unsigned __int8 ChannelPlan; - unsigned __int8 Index2G; - unsigned __int8 PwrLmt; +struct _RT_CHANNEL_PLAN_MAP { + uint8_t ChannelPlan; + uint8_t Index2G; + uint8_t PwrLmt; }; typedef struct _RT_CHANNEL_PLAN_MAP RT_CHANNEL_PLAN_MAP; +typedef int (*mac_monitor_ptr)(uint8_t *, char); -typedef int (*mac_monitor_ptr)(unsigned __int8 *, char); - -struct mlme_handler -{ - unsigned int num; - unsigned int (*func)(_adapter *, union recv_frame *); +struct mlme_handler { + uint32_t num; + uint32_t (*func)(_adapter *, union recv_frame *); }; -struct fwevent -{ - uint32_t parmsize; - void (*event_callback)(_adapter *, uint8_t *); +struct fwevent { + uint32_t parmsize; + void (*event_callback)(_adapter *, uint8_t *); }; -struct recv_buf -{ - _list list; - PADAPTER adapter; - uint32_t len; - uint8_t *phead; - uint8_t *pdata; - uint8_t *ptail; - uint8_t *pend; - _pkt *pskb; +struct recv_buf { + _list list; + PADAPTER adapter; + uint32_t len; + uint8_t *phead; + uint8_t *pdata; + uint8_t *ptail; + uint8_t *pend; + _pkt *pskb; }; -struct recv_reorder_ctrl -{ - _adapter *padapter; - uint8_t enable; - uint16_t indicate_seq; - uint16_t wend_b; - uint8_t wsize_b; - _queue pending_recvframe_queue; - _timer reordering_ctrl_timer; +struct recv_reorder_ctrl { + _adapter *padapter; + uint8_t enable; + uint16_t indicate_seq; + uint16_t wend_b; + uint8_t wsize_b; + _queue pending_recvframe_queue; + _timer reordering_ctrl_timer; }; -enum _ODM_RF_RADIO_PATH // : __int32 +enum _ODM_RF_RADIO_PATH // : sint32_t { - ODM_RF_PATH_A = 0x0, - ODM_RF_PATH_B = 0x1, - ODM_RF_PATH_C = 0x2, - ODM_RF_PATH_D = 0x3, - ODM_RF_PATH_AB = 0x4, - ODM_RF_PATH_AC = 0x5, - ODM_RF_PATH_AD = 0x6, - ODM_RF_PATH_BC = 0x7, - ODM_RF_PATH_BD = 0x8, - ODM_RF_PATH_CD = 0x9, - ODM_RF_PATH_ABC = 0xA, - ODM_RF_PATH_ACD = 0xB, - ODM_RF_PATH_BCD = 0xC, - ODM_RF_PATH_ABCD = 0xD, + ODM_RF_PATH_A = 0x0, + ODM_RF_PATH_B = 0x1, + ODM_RF_PATH_C = 0x2, + ODM_RF_PATH_D = 0x3, + ODM_RF_PATH_AB = 0x4, + ODM_RF_PATH_AC = 0x5, + ODM_RF_PATH_AD = 0x6, + ODM_RF_PATH_BC = 0x7, + ODM_RF_PATH_BD = 0x8, + ODM_RF_PATH_CD = 0x9, + ODM_RF_PATH_ABC = 0xA, + ODM_RF_PATH_ACD = 0xB, + ODM_RF_PATH_BCD = 0xC, + ODM_RF_PATH_ABCD = 0xD, }; typedef enum _ODM_RF_RADIO_PATH ODM_RF_RADIO_PATH_E; -enum tag_PhyDM_TRx_MUX_Type //: __int32 +enum tag_PhyDM_TRx_MUX_Type //: sint32_t { - PhyDM_SHUTDOWN = 0x0, - PhyDM_STANDBY_MODE = 0x1, - PhyDM_TX_MODE = 0x2, - PhyDM_RX_MODE = 0x3, + PhyDM_SHUTDOWN = 0x0, + PhyDM_STANDBY_MODE = 0x1, + PhyDM_TX_MODE = 0x2, + PhyDM_RX_MODE = 0x3, }; typedef enum tag_PhyDM_TRx_MUX_Type PhyDM_Trx_MUX_Type; -enum tag_PhyDM_MACEDCCA_Type //: __int32 +enum tag_PhyDM_MACEDCCA_Type //: sint32_t { - PhyDM_IGNORE_EDCCA = 0x0, - PhyDM_DONT_IGNORE_EDCCA = 0x1, + PhyDM_IGNORE_EDCCA = 0x0, PhyDM_DONT_IGNORE_EDCCA = 0x1, }; typedef enum tag_PhyDM_MACEDCCA_Type PhyDM_MACEDCCA_Type; -enum tag_ODM_PauseDIG_Type //: __int32 +enum tag_ODM_PauseDIG_Type //: sint32_t { - ODM_PAUSE_DIG = 0x1, - ODM_RESUME_DIG = 0x2, + ODM_PAUSE_DIG = 0x1, ODM_RESUME_DIG = 0x2, }; typedef enum tag_ODM_PauseDIG_Type ODM_Pause_DIG_TYPE; -enum tag_ODM_PauseCCKPD_Type //: __int32 +enum tag_ODM_PauseCCKPD_Type //: sint32_t { - ODM_PAUSE_CCKPD = 0x1, - ODM_RESUME_CCKPD = 0x2, + ODM_PAUSE_CCKPD = 0x1, ODM_RESUME_CCKPD = 0x2, }; typedef enum tag_ODM_PauseCCKPD_Type ODM_Pause_CCKPD_TYPE; -struct _ODM_Per_Pkt_Info_ -{ - u1Byte DataRate; - u1Byte StationID; - BOOLEAN bPacketMatchBSSID; - BOOLEAN bPacketToSelf; - BOOLEAN bPacketBeacon; +struct _ODM_Per_Pkt_Info_ { + u1Byte DataRate; + u1Byte StationID; + BOOLEAN bPacketMatchBSSID; + BOOLEAN bPacketToSelf; + BOOLEAN bPacketBeacon; }; typedef struct _ODM_Per_Pkt_Info_ *PODM_PACKET_INFO_T; -enum _HAL_STATUS //: __int32 +enum _HAL_STATUS //: sint32_t { - HAL_STATUS_SUCCESS = 0x0, - HAL_STATUS_FAILURE = 0x1, + HAL_STATUS_SUCCESS = 0x0, HAL_STATUS_FAILURE = 0x1, }; typedef enum _HAL_STATUS HAL_STATUS; -struct _ODM_Phy_Status_Info_ -{ - u1Byte RxPWDBAll; - u1Byte SignalQuality; - u1Byte RxMIMOSignalStrength[1]; - s1Byte RecvSignalPower; - u1Byte SignalStrength; +struct _ODM_Phy_Status_Info_ { + u1Byte RxPWDBAll; + u1Byte SignalQuality; + u1Byte RxMIMOSignalStrength[1]; + s1Byte RecvSignalPower; + u1Byte SignalStrength; }; typedef struct _ODM_Phy_Status_Info_ *PODM_PHY_INFO_T; -enum _ODM_RF_Config_Type // : __int32 +enum _ODM_RF_Config_Type // : sint32_t { - CONFIG_RF_RADIO = 0x0, - CONFIG_RF_TXPWR_LMT = 0x1, + CONFIG_RF_RADIO = 0x0, CONFIG_RF_TXPWR_LMT = 0x1, }; typedef enum _ODM_RF_Config_Type ODM_RF_Config_Type; -enum _ODM_BB_Config_Type //: __int32 +enum _ODM_BB_Config_Type //: sint32_t { - CONFIG_BB_PHY_REG = 0x0, - CONFIG_BB_AGC_TAB = 0x1, - CONFIG_BB_AGC_TAB_2G = 0x2, - CONFIG_BB_AGC_TAB_5G = 0x3, - CONFIG_BB_PHY_REG_PG = 0x4, - CONFIG_BB_PHY_REG_MP = 0x5, - CONFIG_BB_AGC_TAB_DIFF = 0x6, + CONFIG_BB_PHY_REG = 0x0, + CONFIG_BB_AGC_TAB = 0x1, + CONFIG_BB_AGC_TAB_2G = 0x2, + CONFIG_BB_AGC_TAB_5G = 0x3, + CONFIG_BB_PHY_REG_PG = 0x4, + CONFIG_BB_PHY_REG_MP = 0x5, + CONFIG_BB_AGC_TAB_DIFF = 0x6, }; typedef enum _ODM_BB_Config_Type ODM_BB_Config_Type; -enum _ODM_FW_Config_Type //: __int32 +enum _ODM_FW_Config_Type //: sint32_t { - CONFIG_FW_NIC = 0x0, - CONFIG_FW_NIC_2 = 0x1, - CONFIG_FW_AP = 0x2, - CONFIG_FW_MP = 0x3, - CONFIG_FW_WoWLAN = 0x4, - CONFIG_FW_WoWLAN_2 = 0x5, - CONFIG_FW_AP_WoWLAN = 0x6, - CONFIG_FW_BT = 0x7, + CONFIG_FW_NIC = 0x0, + CONFIG_FW_NIC_2 = 0x1, + CONFIG_FW_AP = 0x2, + CONFIG_FW_MP = 0x3, + CONFIG_FW_WoWLAN = 0x4, + CONFIG_FW_WoWLAN_2 = 0x5, + CONFIG_FW_AP_WoWLAN = 0x6, + CONFIG_FW_BT = 0x7, }; typedef enum _ODM_FW_Config_Type ODM_FW_Config_Type; -enum _RATE_SECTION //: __int32 +enum _RATE_SECTION //: sint32_t { - CCK = 0x0, - OFDM = 0x1, - HT_MCS0_MCS7 = 0x2, - HT_MCS8_MCS15 = 0x3, - HT_MCS16_MCS23 = 0x4, - HT_MCS24_MCS31 = 0x5, - VHT_1SSMCS0_1SSMCS9 = 0x6, - VHT_2SSMCS0_2SSMCS9 = 0x7, - VHT_3SSMCS0_3SSMCS9 = 0x8, - VHT_4SSMCS0_4SSMCS9 = 0x9, + CCK = 0x0, + OFDM = 0x1, + HT_MCS0_MCS7 = 0x2, + HT_MCS8_MCS15 = 0x3, + HT_MCS16_MCS23 = 0x4, + HT_MCS24_MCS31 = 0x5, + VHT_1SSMCS0_1SSMCS9 = 0x6, + VHT_2SSMCS0_2SSMCS9 = 0x7, + VHT_3SSMCS0_3SSMCS9 = 0x8, + VHT_4SSMCS0_4SSMCS9 = 0x9, }; typedef enum _RATE_SECTION RATE_SECTION; -struct map_mask_s -{ - uint16_t mask_start; - uint16_t mask_end; +struct map_mask_s { + uint16_t mask_start; + uint16_t mask_end; }; -struct _TxPowerInfo24G -{ - uint8_t IndexCCK_Base[1][6]; - uint8_t IndexBW40_Base[1][6]; - int8_t OFDM_Diff[1][1]; - int8_t BW20_Diff[1][1]; +struct _TxPowerInfo24G { + uint8_t IndexCCK_Base[1][6]; + uint8_t IndexBW40_Base[1][6]; + int8_t OFDM_Diff[1][1]; + int8_t BW20_Diff[1][1]; }; typedef struct _TxPowerInfo24G TxPowerInfo24G; typedef struct _TxPowerInfo24G *PTxPowerInfo24G; diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_structures.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_structures.h index 58f1873..8bd0f20 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_structures.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_structures.h @@ -80,7 +80,7 @@ typedef struct rtw_wifi_setting { rtw_security_t security_type; unsigned char password[65]; unsigned char key_idx; -}rtw_wifi_setting_t; +} rtw_wifi_setting_t; #if defined(__IAR_SYSTEMS_ICC__) #pragma pack() #endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_lib.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_lib.h index 561fbde..111e677 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_lib.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_lib.h @@ -38,19 +38,19 @@ extern int rtw_wx_set_freq(struct net_device *dev, struct iw_request_info *info, extern int rtw_ex_set(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wdata, char *extra); extern void wireless_send_event(struct net_device *dev, unsigned int cmd, union iwreq_data *wrqu, char *extra); extern void indicate_wx_custom_event(_adapter *padapter, char *msg); -extern void indicate_wx_scan_result_present(__int64 padapter, __int64 a2); -extern void indicate_wx_scan_complete_event(__int64 padapter, __int64 a2); -extern void rtw_indicate_sta_assoc(__int64 padapter, __int64 buf); +extern void indicate_wx_scan_result_present(uint64_t padapter, uint64_t a2); +extern void indicate_wx_scan_complete_event(uint64_t padapter, uint64_t a2); +extern void rtw_indicate_sta_assoc(uint64_t padapter, uint64_t buf); extern void rtw_indicate_sta_disassoc(_adapter *padapter, uint8_t *addr); -extern void rtw_indicate_wx_assoc_event(__int64 padapter, __int64 a2); -extern void rtw_indicate_wx_disassoc_event(__int64 padapter, __int64 a2); +extern void rtw_indicate_wx_assoc_event(uint64_t padapter, uint64_t a2); +extern void rtw_indicate_wx_disassoc_event(uint64_t padapter, uint64_t a2); extern int rtw_set_wpa_ie(_adapter *padapter, char *pie, int ielen); extern void strtopsk(uint8_t *des, uint8_t *src, int len); extern int rtw_wx_get_passphrase(struct net_device *dev, struct iw_request_info *a, union iwreq_data *wrqu, char *extra); extern int rtw_wx_set_ap_essid(struct net_device *dev, struct iw_request_info *a, union iwreq_data *wrqu, char *extra); extern void mac_reg_dump(_adapter *padapter); extern void bb_reg_dump(_adapter *padapter); -extern void rf_reg_dump(_adapter *padapter, int a2, int a3); +extern void rf_reg_dump(_adapter *padapter); // , int a2, int a3); extern int rtw_dbg_port(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); extern int rtw_get_auto_channel(struct net_device *dev, u8 *channel_set, int channel_num); extern int rtw_set_sta_num(int ap_sta_num); @@ -277,7 +277,7 @@ extern int max_timer_used_num; //-------------------------------- // rtl8195a_cmd.o // Function declarations -extern int32_t FillH2CCmd8195A(PADAPTER padapter, int ElementID, __int64 CmdLen); +extern int32_t FillH2CCmd8195A(PADAPTER padapter, int ElementID, uint64_t CmdLen); extern void rtl8195a_set_FwRsvdPage_cmd(PADAPTER padapter, PH2CParam_RsvdPage pRsvdPage); extern void rtl8195a_set_FwMediaStatusRpt_cmd(PADAPTER padapter, int mstatus, int macid); extern void rtl8195a_set_FwMacIdConfig_cmd(_adapter *padapter, int mac_id, int raid, int bw, uint8_t sgi, uint32_t mask); @@ -1082,12 +1082,12 @@ extern signed int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame); extern void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, int blnbc); extern void issue_auth(_adapter *padapter, struct sta_info *psta, int status); extern signed int OnAuth(_adapter *padapter, union recv_frame *precv_frame); -extern void issue_asocrsp(_adapter *padapter, unsigned __int16 status, struct sta_info *pstat, int pkt_type); +extern void issue_asocrsp(_adapter *padapter, uint16_t status, struct sta_info *pstat, int pkt_type); extern void issue_assocreq(_adapter *padapter); extern void issue_nulldata(_adapter *padapter, unsigned int power_mode); extern void issue_qos_nulldata(_adapter *padapter, u8 *da, uint16_t tid); extern void issue_deauth(_adapter *padapter, u8 *da, uint32_t reason); -extern void issue_action_BA(_adapter *padapter, u8 *raddr, u8 action, unsigned __int16 status); +extern void issue_action_BA(_adapter *padapter, u8 *raddr, u8 action, uint16_t status); extern signed int OnAction_back(_adapter *padapter, union recv_frame *precv_frame); extern signed int send_beacon(_adapter *padapter); extern signed int collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid); @@ -1101,8 +1101,8 @@ extern signed int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame); extern void report_surveydone_event(_adapter *padapter); extern void report_join_res(_adapter *padapter, int res); extern signed int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame); -extern void report_del_sta_event(_adapter *padapter, u8 *MacAddr, unsigned __int16 reason); -extern signed int receive_disconnect(_adapter *padapter, u8 *MacAddr, unsigned __int16 reason); +extern void report_del_sta_event(_adapter *padapter, u8 *MacAddr, uint16_t reason); +extern signed int receive_disconnect(_adapter *padapter, u8 *MacAddr, uint16_t reason); extern signed int OnBeacon(_adapter *padapter, union recv_frame *precv_frame); extern signed int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame); extern signed int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame); @@ -1240,7 +1240,7 @@ extern void (*promisc_callback)(u8 *, unsigned int, void *); //-------------------------------- // rtw_psk.o // Function declarations -extern void SetEAPOL_KEYIV(OCTET_STRING ocDst, __int64 a2, OCTET32_INTEGER oc32Counter); +extern void SetEAPOL_KEYIV(OCTET_STRING ocDst, uint64_t a2, OCTET32_INTEGER oc32Counter); extern void ToDrv_SetPTK(_adapter *padapter, struct sta_info *psta); extern void Message_ReplayCounter_OC2LI(int a1, LARGE_INTEGER *li); extern int Message_SmallerEqualReplayCounter(LARGE_INTEGER li1, int a2); @@ -1402,7 +1402,7 @@ extern void rtw_txframes_update_attrib_vcs_info(_adapter *padapter, struct xmit_ extern int rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib); extern int32_t rtw_put_snap(uint8_t *data, int h_proto); extern void rtw_update_protection(_adapter *padapter, uint8_t *ie, unsigned int ie_len); -extern void rtw_count_tx_stats(PADAPTER padapter, struct xmit_frame *pxmitframe, __int64 sz); +extern void rtw_count_tx_stats(PADAPTER padapter, struct xmit_frame *pxmitframe, uint64_t sz); extern int32_t rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf, int a3); extern struct list_head *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv, _irqL a2); extern int32_t rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe); diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h index d8bab59..4922122 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h @@ -412,7 +412,7 @@ typedef struct { unsigned char mac[6]; } Rltk_wlan_t; -#define netdev_priv(dev) dev->priv +#define netdev_priv(dev) dev->priv extern struct net_device *alloc_etherdev(int sizeof_priv); void free_netdev(struct net_device *dev); diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wireless.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wireless.h index 19495ce..c3865a6 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wireless.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wireless.h @@ -412,7 +412,7 @@ typedef long long __i64; #define IWEVTXDROP 0x8C00 /* Packet dropped to excessive retry */ #define IWEVQUAL 0x8C01 /* Quality part of statistics (scan) */ #define IWEVCUSTOM 0x8C02 /* Driver specific ascii string */ -#define IWEVREGISTERED 0x8C03 /* Discovered a new node (AP mode) */ +#define IWEVREGISTERED 0x8C03 /* Discovered a new node (AP mode) */ #define IWEVEXPIRED 0x8C04 /* Expired a node (AP mode) */ #define IWEVGENIE 0x8C05 /* Generic IE (WPA, RSN, WMM, ..) * (scan results); This includes id and diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wlan_intf.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wlan_intf.h index c8d6368..7e461b0 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wlan_intf.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wlan_intf.h @@ -37,6 +37,9 @@ struct sk_buff { */ /************************************************************/ +// #include "wrapper.h" +extern struct net_device *rltk_wlan_info; + //----- ------------------------------------------------------------------ // Wlan Interface opened for upper layer //----- ------------------------------------------------------------------ @@ -55,7 +58,6 @@ int rltk_wlan_set_wps_phase(unsigned char is_trigger_wps); int rtw_ps_enable(int enable); int rltk_wlan_is_connected_to_ap(void); - #ifdef __cplusplus } #endif diff --git a/RTL00_SDKV35a/component/common/example/uart_atcmd/example_uart_atcmd.c b/RTL00_SDKV35a/component/common/example/uart_atcmd/example_uart_atcmd.c index 5c05bc9..4ce302f 100644 --- a/RTL00_SDKV35a/component/common/example/uart_atcmd/example_uart_atcmd.c +++ b/RTL00_SDKV35a/component/common/example/uart_atcmd/example_uart_atcmd.c @@ -301,6 +301,11 @@ void gpio_uart_at_rx_irq_callback (uint32_t id, gpio_irq_event event) void uart_at_rx_wakeup() { gpio_irq_t gpio_rx_wake; +#ifdef RTL8711AM +#if (UART_AT_RX_WAKE!=PA_0)||(UART_AT_RX_WAKE!=PE_3) +#error "Set pin rx_wakeup!" +#endif +#endif gpio_irq_init(&gpio_rx_wake, UART_AT_RX_WAKE, gpio_uart_at_rx_irq_callback, 0); gpio_irq_set(&gpio_rx_wake, IRQ_FALL, 1); // Falling Edge Trigger gpio_irq_enable(&gpio_rx_wake); diff --git a/RTL00_SDKV35a/component/common/example/uart_atcmd/example_uart_atcmd.h b/RTL00_SDKV35a/component/common/example/uart_atcmd/example_uart_atcmd.h index 901a288..2320f72 100644 --- a/RTL00_SDKV35a/component/common/example/uart_atcmd/example_uart_atcmd.h +++ b/RTL00_SDKV35a/component/common/example/uart_atcmd/example_uart_atcmd.h @@ -13,27 +13,34 @@ #include "osdep_api.h" -#if 0// defined(RTL8710AF) +#if defined(RTL8710AF) // RTL8710AF -#define UART_TX PA_4 // PC_3 -#define UART_RX PA_0 // PC_0 +#define UART_TX PA_4 // PC_3 +#define UART_RX PA_0 // PC_0 #define UART_RTS PA_2 // PC_2 #define UART_CTS PA_1 // PC_1 -#elif defined(RTL8711AM) +#elif 0 // defined(RTL8711AM) // RTL8711AM -#define UART_TX PA_7 -#define UART_RX PA_6 +#define UART_TX PA_7 +#define UART_RX PA_6 // no Interrupt! #define UART_RTS PA_3 #define UART_CTS PA_5 -#else +#elif 0 // else // RTL8711AM + RTL8710AF -#define UART_TX PC_3 -#define UART_RX PC_0 +#define UART_TX PC_3 +#define UART_RX PC_0 // no Interrupt! #define UART_RTS PC_2 #define UART_CTS PC_1 +#elif defined(RTL8711AM) +// RTL8711AM + RTL8710AF +#define UART_TX PE_0 +#define UART_RX PE_3 +#define UART_RTS PE_1 +#define UART_CTS PE_2 + #endif #define KEY_ENTER 0xd diff --git a/RTL00_SDKV35a/component/common/file_system/fatfs/disk_if/src/sdcard.c b/RTL00_SDKV35a/component/common/file_system/fatfs/disk_if/src/sdcard.c index 0878bd1..f7ee687 100644 --- a/RTL00_SDKV35a/component/common/file_system/fatfs/disk_if/src/sdcard.c +++ b/RTL00_SDKV35a/component/common/file_system/fatfs/disk_if/src/sdcard.c @@ -55,7 +55,6 @@ DRESULT SD_disk_read(BYTE *buff, DWORD sector, UINT count){ #if _USE_WRITE == 1 DRESULT SD_disk_write(const BYTE *buff, DWORD sector, UINT count){ SD_RESULT res; - res = SD_WriteBlocks(sector, buff, count); return interpret_sd_result(res); diff --git a/RTL00_SDKV35a/component/common/file_system/fatfs/r0.10c/include/ffconf.h b/RTL00_SDKV35a/component/common/file_system/fatfs/r0.10c/include/ffconf.h index c03dba8..85f3005 100644 --- a/RTL00_SDKV35a/component/common/file_system/fatfs/r0.10c/include/ffconf.h +++ b/RTL00_SDKV35a/component/common/file_system/fatfs/r0.10c/include/ffconf.h @@ -45,7 +45,7 @@ /* To enable fast seek feature, set _USE_FASTSEEK to 1. */ -#define _USE_LABEL 0 /* 0:Disable or 1:Enable */ +#define _USE_LABEL 1 /* 0:Disable or 1:Enable */ /* To enable volume label functions, set _USE_LAVEL to 1 */ @@ -57,7 +57,7 @@ / Locale and Namespace Configurations /---------------------------------------------------------------------------*/ -#define _CODE_PAGE 437 +#define _CODE_PAGE 866 // 437 /* The _CODE_PAGE specifies the OEM code page to be used on the target system. / Incorrect setting of the code page can cause a file open failure. / diff --git a/RTL00_SDKV35a/component/common/file_system/fatfs/r0.10c/src/ff.c b/RTL00_SDKV35a/component/common/file_system/fatfs/r0.10c/src/ff.c index a6e3a9d..7096067 100644 --- a/RTL00_SDKV35a/component/common/file_system/fatfs/r0.10c/src/ff.c +++ b/RTL00_SDKV35a/component/common/file_system/fatfs/r0.10c/src/ff.c @@ -2568,7 +2568,6 @@ FRESULT f_read ( UINT rcnt, cc; BYTE csect, *rbuff = (BYTE*)buff; - *br = 0; /* Clear read byte counter */ res = validate(fp); /* Check validity */ @@ -2670,9 +2669,10 @@ FRESULT f_write ( const BYTE *wbuff = (const BYTE*)buff; BYTE csect; - *bw = 0; /* Clear write byte counter */ +// rtl_printf("f_write(%p, %p, %d) = %d\n", fp, buff, btw); + res = validate(fp); /* Check validity */ if (res != FR_OK) LEAVE_FF(fp->fs, res); if (fp->err) /* Check error */ @@ -2773,8 +2773,6 @@ FRESULT f_write ( } - - /*-----------------------------------------------------------------------*/ /* Synchronize the File */ /*-----------------------------------------------------------------------*/ diff --git a/RTL00_SDKV35a/component/os/freertos/freertos_pmu.c b/RTL00_SDKV35a/component/os/freertos/freertos_pmu.c index c7e4c78..a9efd4b 100644 --- a/RTL00_SDKV35a/component/os/freertos/freertos_pmu.c +++ b/RTL00_SDKV35a/component/os/freertos/freertos_pmu.c @@ -75,8 +75,6 @@ void freertos_pre_sleep_processing(unsigned int *expected_idle_time) { uint32_t tick_after_sleep; uint32_t tick_passed; uint32_t backup_systick_reg; - unsigned char IsDramOn = 1; - unsigned char suspend_sdram = 1; #if (configGENERATE_RUN_TIME_STATS == 1) uint32_t kernel_tick_before_sleep; @@ -101,20 +99,6 @@ void freertos_pre_sleep_processing(unsigned int *expected_idle_time) { // Store gtimer timestamp before sleep tick_before_sleep = us_ticker_read(); - if ( sys_is_sdram_power_on() == 0 ) { - IsDramOn = 0; - } - - if (IsDramOn) { -#if defined(FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM) && (FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM==0) - // sdram is turned on, and we don't want suspend sdram - suspend_sdram = 0; -#endif - } else { - // sdram didn't turned on, we should not suspend it - suspend_sdram = 0; - } - #if (FREERTOS_PMU_DISABLE_LOGUART_IN_TICKLESS) // config gpio on log uart tx for pull ctrl HAL_GPIO_PIN gpio_log_uart_tx; @@ -129,8 +113,16 @@ void freertos_pre_sleep_processing(unsigned int *expected_idle_time) { backup_systick_reg = portNVIC_SYSTICK_CURRENT_VALUE_REG; +#ifdef CONFIG_SDR_EN // sleep - sleep_ex_selective(wakeup_event, stime, reserve_pll, suspend_sdram); +#if defined(FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM) && (FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM!=0) + sleep_ex_selective(wakeup_event, stime, reserve_pll, IsSdrPowerOn()); +#else + sleep_ex_selective(wakeup_event, stime, reserve_pll, 0); +#endif +#else + sleep_ex_selective(wakeup_event, stime, reserve_pll, 0); +#endif // CONFIG_SDR_EN portNVIC_SYSTICK_CURRENT_VALUE_REG = backup_systick_reg; diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/core_cmFunc.h b/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/core_cmFunc.h index 0a18faf..21cce31 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/core_cmFunc.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/core_cmFunc.h @@ -309,7 +309,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ -#include +// #include #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/core_cmInstr.h b/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/core_cmInstr.h index d213f0e..9bf01e6 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/core_cmInstr.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/core_cmInstr.h @@ -295,7 +295,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ -#include +// #include #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/rtl_stdlib.h b/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/rtl_stdlib.h index 637fe7a..36c0d67 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/rtl_stdlib.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/rtl_stdlib.h @@ -21,14 +21,14 @@ #define strcmp(str1, str2) prvStrCmp((const u8*)str1, (const u8*)str2) #define sscanf(src, format...) //TODO #define strtok(str, delim) prvStrTok(str, delim) -#define strcpy(dst, src) prvStrCpy((u8 *)dst, (const u8*)src) +#define strcpy(dst, src) prvStrCpy((u8 *)dst, (const u8*)src) #define atoi(str) prvAtoi(str) -#define strstr(str1, str2) prvStrStr(str1, str2) +#define strstr(str1, str2) prvStrStr(str1, str2) // // standard i/o // -#define snprintf DiagSnPrintf +#define snprintf DiagSnPrintf #define sprintf prvDiagSPrintf #define printf prvDiagPrintf diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/strproc.h b/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/strproc.h index ab1a37f..49c66f6 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/strproc.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/strproc.h @@ -79,7 +79,7 @@ extern _LONG_CALL_ROM_ const char * prvStrStr( IN const char * str2 ); - +#ifndef __GNUC__ /* * Fast implementation of tolower() for internal usage. Do not use in your * code. @@ -88,6 +88,7 @@ static inline char _tolower(const char c) { return c | 0x20; } +#endif /* Fast check for octal digit */ static inline int isodigit(const char c) diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/system_8195a.c b/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/system_8195a.c index 49b38c1..fff8d15 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/system_8195a.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/system_8195a.c @@ -49,7 +49,7 @@ #define __SYSTEM_CLOCK (200000000UL/6*5) // PLATFORM_CLOCK // extern unsigned int rand_x; -extern u32 HalGetCpuClk(VOID); +//extern u32 HalGetCpuClk(VOID); #ifdef CONFIG_CHIP_A_CUT const u32 SysCpkClkTbl[]= { diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_gdma.h b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_gdma.h index d7294e6..6807363 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_gdma.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_gdma.h @@ -58,17 +58,17 @@ typedef struct _HAL_GDMA_ADAPTER_ { struct GDMA_CH_LLI *pLlix; struct BLOCK_SIZE_LIST *pBlockSizeList; - PGDMA_CH_LLI_ELE pLli; - u32 NextPlli; + PGDMA_CH_LLI_ELE pLli; + u32 NextPlli; u8 TestItem; - u8 ChNum; - u8 GdmaIndex; - u8 IsrCtrl:1; - u8 GdmaOnOff:1; - u8 Llpctrl:1; - u8 Lli0:1; - u8 Rsvd4to7:4; - u8 GdmaIsrType; + u8 ChNum; + u8 GdmaIndex; + u8 IsrCtrl:1; + u8 GdmaOnOff:1; + u8 Llpctrl:1; + u8 Lli0:1; + u8 Rsvd4to7:4; + u8 GdmaIsrType; }HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER; typedef struct _HAL_GDMA_CHNL_ { diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_gpio.h b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_gpio.h index e89e368..4be5edc 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_gpio.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_gpio.h @@ -244,7 +244,7 @@ HAL_GPIO_IP_DeInit( -extern u16 GPIOState[_PORT_MAX-1]; // побитно 16 бит для каждого порта (A..K), бит=номер задействованного пина в порту на переферию. +extern u16 GPIOState[_PORT_MAX-1]; // побитно 16 бит для каждого порта (A..K), бит=номер задействованного пина в порту на периферию. #endif // end of "#define _HAL_GPIO_H_" diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_misc.h b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_misc.h index 477d322..b8516ea 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_misc.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_misc.h @@ -31,11 +31,12 @@ enum _HAL_RESET_REASON{ typedef u32 HAL_RESET_REASON; #ifdef CONFIG_TIMER_MODULE -extern _LONG_CALL_ u32 HalDelayUs(u32 us); +extern _LONG_CALL_ unsigned int HalDelayUs(unsigned int us); #endif -extern _LONG_CALL_ u32 HalGetCpuClk(VOID); -extern _LONG_CALL_ u8 HalGetRomInfo(VOID); +extern _LONG_CALL_ unsigned int HalGetCpuClk(VOID); +extern _LONG_CALL_ unsigned char HalGetRomInfo(VOID); +extern u8 HalGetChipId(void); extern _LONG_CALL_ROM_ void *_memset( void *s, int c, SIZE_T n ); extern _LONG_CALL_ROM_ void *_memcpy( void *s1, const void *s2, SIZE_T n ); diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_sdio_host.h b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_sdio_host.h index 378a757..c6dc0ae 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_sdio_host.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_sdio_host.h @@ -14,11 +14,9 @@ #include "rtl8195a_sdio_host.h" - #define SDIO_HOST_WAIT_FOREVER 0xFFFFFFFF - typedef struct _HAL_SDIO_HOST_OP_ { HAL_Status (*HalSdioHostInitHost) (VOID *Data); HAL_Status (*HalSdioHostInitCard) (VOID *Data); @@ -48,20 +46,20 @@ typedef enum _SDIO_XFER_TYPE_{ }SDIO_XFER_TYPE; typedef struct _HAL_SDIO_HOST_ADAPTER_{ - IRQ_HANDLE IrqHandle; // Irq Handler - ADMA2_DESC_FMT *AdmaDescTbl; - u32 Response[4]; - u32 CardOCR; - u32 CardStatus; - u32 IsWriteProtect; - u8 SdStatus[SD_STATUS_LEN]; - u8 Csd[CSD_REG_LEN]; + IRQ_HANDLE IrqHandle; //+0..6(u32) Irq Handler + ADMA2_DESC_FMT *AdmaDescTbl; //+7(u32) + u32 Response[4]; //+8..11(u32) + u32 CardOCR; //+12 + u32 CardStatus; //+13 + u32 IsWriteProtect; //+14 + u8 SdStatus[SD_STATUS_LEN]; //+15.. + u8 Csd[CSD_REG_LEN]; //+31 volatile u8 CmdCompleteFlg; volatile u8 XferCompleteFlg; volatile u8 ErrIntFlg; volatile u8 CardCurState; u8 IsSdhc; - u8 CurrSdClk; + u8 CurrSdClk; //+133? u16 RCA; u16 SdSpecVer; SDIO_ERR_TYPE errType; @@ -76,6 +74,7 @@ typedef struct _HAL_SDIO_HOST_ADAPTER_{ VOID *CardRemoveCbPara; }HAL_SDIO_HOST_ADAPTER, *PHAL_SDIO_HOST_ADAPTER; +extern HAL_SDIO_HOST_ADAPTER SdioHostAdapter; extern HAL_Status HalSdioHostInit( @@ -102,6 +101,5 @@ HalSdioHostOpInit( IN VOID *Data ); - #endif diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_spi_flash.h b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_spi_flash.h index 0fc5ec4..1af9278 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_spi_flash.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_spi_flash.h @@ -55,6 +55,7 @@ enum _SPIC_BIT_MODE_ { SpicOneBitMode = 0, SpicDualBitMode = 1, SpicQuadBitMode = 2, + SpicMaxMode = 3 }; //====================================================== @@ -98,20 +99,22 @@ enum _SPIC_BIT_MODE_ { #define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down /*Micron Special command*/ -#define FLASH_CMD_DE 0xC4 -#define FLASH_CMD_4PP2 0x12 -#define FLASH_CMD_RFSR 0x70 -#define FLASH_CMD_CFSR 0x50 -#define FLASH_CMD_RNCR 0xB5 -#define FLASH_CMD_WNCR 0xB1 -#define FLASH_CMD_RVCR 0x85 -#define FLASH_CMD_WVCR 0x81 -#define FLASH_CMD_REVCR 0x65 -#define FLASH_CMD_WEVCR 0x61 -#define FLASH_CMD_REAR 0xC8 -#define FLASH_CMD_WEAR 0xC5 -#define FLASH_CMD_ENQUAD 0x35 -#define FLASH_CMD_EXQUAD 0xF5 +#define FLASH_CMD_DE 0xC4 // DIE ERASE +#define FLASH_CMD_4PP2 0x12 // 4-BYTE PAGE PROGRAM +#define FLASH_CMD_RFSR 0x70 // READ FLAG STATUS REGISTER +#define FLASH_CMD_CFSR 0x50 // CLEAR FLAG STATUS REGISTER +#define FLASH_CMD_RNCR 0xB5 // READ NONVOLATILE CONFIGURATION REGISTER +#define FLASH_CMD_WNCR 0xB1 // WRITE NONVOLATILE CONFIGURATION REGISTER +#define FLASH_CMD_RVCR 0x85 // READ VOLATILE CONFIGURATION REGISTER +#define FLASH_CMD_WVCR 0x81 // WRITE VOLATILE CONFIGURATION REGISTER +#define FLASH_CMD_REVCR 0x65 // READ ENHANCED VOLATILE CONFIGURATION REGISTER +#define FLASH_CMD_WEVCR 0x61 // WRITE ENHANCED VOLATILE CONFIGURATION REGISTER +#define FLASH_CMD_REAR 0xC8 // READ EXTENDED ADDRESS REGISTER +#define FLASH_CMD_WEAR 0xC5 // WRITE EXTENDED ADDRESS REGISTER +#define FLASH_CMD_ENQUAD 0x35 // ENTER QUAD +#define FLASH_CMD_EXQUAD 0xF5 // EXIT QUAD +#define FLASH_CMD_ROTPA 0x4B // READ OTP ARRAY +#define FLASH_CMD_POTPA 0x42 // PROGRAM OTP ARRAY /*MXIC Special command*/ #define FLASH_CMD_RDCR 0x15 //read configurate register @@ -120,7 +123,10 @@ enum _SPIC_BIT_MODE_ { #define FLASH_CMD_ENSO 0xB1 // enter secured OTP #define FLASH_CMD_EXSO 0xC1 // exit secured OTP #define FLASH_CMD_RDSCUR 0x2B // read security register -#define FLASH_CMD_WRSCUR 0x2F // write security register +#define FLASH_CMD_WRSCUR 0x2F // write security register + +/* EON Special command*/ +#define FLASH_CMD_EOTPM 0x3A // Enter OTP Mode (3Ah) //#endif #if 0 diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c index 9e7a5a2..867e3be 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c @@ -202,7 +202,6 @@ void __attribute__((section(".hal.ram.text"))) RtlBootToSram(void) { SpicInitRtl8195A(1, 1); // InitBaudRate 1, SpicBitMode 1 SpicFlashInitRtl8195A(1); // SpicBitMode 1 - DBG_8195A("===== Enter Image 1.5 ====\nImg2 Sign: %s, InfaStart @ 0x%08x\n", &__image2_validate_code__, __image2_entry_func__); if (strcmp((const char * )&__image2_validate_code__, "RTKWin")) { @@ -313,7 +312,7 @@ void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(void) { HalDelayUs(1000); int sdr_enable = 0; #ifdef CONFIG_SDR_EN - if ((chip_id + 5) > 2) { + if (chip_id > CHIP_ID_8711AF) { SdrCtrlInit(); sdr_enable = 1; } @@ -335,7 +334,9 @@ void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(void) { SpicReadIDRtl8195A(); SpicFlashInitRtl8195A(SpicDualBitMode); // SpicBitMode 1 } -// if (sdr_enable) SdrControllerInit(); +#ifdef CONFIG_SDR_EN + if (sdr_enable) SdrControllerInit(); +#endif if (flash_enable) { u32 img1size = (*(u16 *) (SPI_FLASH_BASE + 0x18)) << 10; // size in 1024 bytes if (img1size == 0 || img1size >= 0x3FFFC00) diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio.h b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio.h index 76b2c66..500fe7c 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio.h @@ -945,7 +945,7 @@ enum SDIO_RPWM2_BITS { RPWM2_PIN_C7_LV_BIT = BIT8, // GPIO C7 wakeup level RPWM2_PIN_D5_LV_BIT = BIT9, // GPIO D5 wakeup level RPWM2_PIN_E3_LV_BIT = BIT10, // GPIO E3 wakeup level - RPWM2_CG_BIT = BIT11, // Clock Gated + RPWM2_CG_BIT = BIT11, // Clock Gated RPWM2_ACK_BIT = BIT14, // Acknowledge RPWM2_TOGGLE_BIT = BIT15, // Toggle bit }; diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio_host.h b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio_host.h index be3cd4d..7b3039e 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio_host.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio_host.h @@ -273,15 +273,15 @@ typedef enum /* 0x2C */ typedef enum { - BASE_CLK = 0x00, - BASE_CLK_DIVIDED_BY_2 = 0x01, - BASE_CLK_DIVIDED_BY_4 = 0x02, - BASE_CLK_DIVIDED_BY_8 = 0x04, - BASE_CLK_DIVIDED_BY_16 = 0x08, - BASE_CLK_DIVIDED_BY_32 = 0x10, - BASE_CLK_DIVIDED_BY_64 = 0x20, - BASE_CLK_DIVIDED_BY_128 = 0x40, - BASE_CLK_DIVIDED_BY_256 = 0x80 + BASE_CLK = 0x00, // 41.6 MHz + BASE_CLK_DIVIDED_BY_2 = 0x01, // 20.8 MHz + BASE_CLK_DIVIDED_BY_4 = 0x02, // 10.4 MHz + BASE_CLK_DIVIDED_BY_8 = 0x04, // 5.2 MHZ + BASE_CLK_DIVIDED_BY_16 = 0x08, // 2.6 MHz + BASE_CLK_DIVIDED_BY_32 = 0x10, // 1.3 MHz + BASE_CLK_DIVIDED_BY_64 = 0x20, // 650 kHz + BASE_CLK_DIVIDED_BY_128 = 0x40, // 325 kHz + BASE_CLK_DIVIDED_BY_256 = 0x80 // 162 kHz }SD_CLK_DIVISOR; typedef enum diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c index 7c2fddb..b7cc2b3 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c @@ -41,7 +41,7 @@ HalGdmaChBlockSetingRtl8195a_Patch( //4 1) Check chanel is avaliable if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) { //4 Disable Channel - DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n"); + DBG_GDMA_WARN("Channel had used; Disable Channel!\n"); HalGdmaChDisRtl8195a(Data); diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pcm.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pcm.c index ad14043..0b0197f 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pcm.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pcm.c @@ -221,7 +221,7 @@ HalPcmIsrEnAndDisRtl8195a ( IN VOID *Data ) { -/* +#ifdef CONFIG_PCM_EN PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data; u32 IsrMask, Addr, IsrCtrl; u8 IsrTypeIndex = 0; @@ -243,7 +243,7 @@ HalPcmIsrEnAndDisRtl8195a ( } } -*/ +#endif return _TRUE; } @@ -254,14 +254,14 @@ HalPcmDumpRegRtl8195a ( IN VOID *Data ) { -/* +#ifdef CONFIG_PCM_EN PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data; HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN, (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)| (pHalGdmaAdapter->ChEn)) ); -*/ +#endif return _TRUE; } @@ -270,16 +270,18 @@ HalPcmRtl8195a ( IN VOID *Data ) { -/* PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data; +#ifdef CONFIG_PCM_EN + PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data; HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN, (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)& ~(pHalGdmaAdapter->ChEn)) ); -*/ +#endif return _TRUE; } -/* + +#ifdef CONFIG_PCM_EN u8 HalGdmaChIsrCleanRtl8195a ( IN VOID *Data @@ -354,6 +356,6 @@ HalGdmaChCleanAutoDstRtl8195a ( HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF))); } -*/ +#endif // CONFIG_PCM_EN diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_sdio_host.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_sdio_host.c index edf1a5c..7930120 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_sdio_host.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_sdio_host.c @@ -1,41 +1,41 @@ /* -*/ + */ #include "rtl8195a.h" #include "rtl8195a_sdio_host.h" //------------------------------------------------------------------------- // Function declarations /* -signed int SdioHostIsTimeout(uint32_t StartCount, uint32_t TimeoutCnt); -void SdioHostSendCmd(SDIO_HOST_CMD *Cmd); -signed int SdioHostGetResponse(void *Data, int RspType); -void SdioHostSdBusPwrCtrl(uint8_t En, int a2); -int SdioHostSdClkCtrl(void *Data, int En, int Divisor); -int SdioHostChkDataLineActive(uint32_t Timeout); -int SdioHostChkCmdInhibitCMD(uint32_t Timeout); -int SdioHostChkCmdInhibitDAT(uint32_t Timeout); -uint32_t SdioHostIsrHandle(void *Data); -int HalSdioHostDeInitRtl8195a(void *Data); -int HalSdioHostEnableRtl8195a(void *Data); -int HalSdioHostDisableRtl8195a(void *Data); -signed int HalSdioHostIrqInitRtl8195a(void *Data); -signed int HalSdioHostInitHostRtl8195a(void *Data); -int HalSdioHostStopTransferRtl8195a(void *Data, uint32_t a2); -signed int SdioHostErrIntRecovery(void *Data, int a2, signed int a3); -signed int SdioHostChkXferComplete(void *Data, uint32_t Timeout, signed int a3); -signed int SdioHostChkCmdComplete(void *Data, uint32_t Timeout); -int SdioHostCardSelection(void *Data, int Select, int a3); -int SdioHostGetCSD(void *Data, uint32_t a2); -int HalSdioHostReadBlocksDmaRtl8195a(int result, uint32_t a2, int64 a3, uint32_t BlockCnta); -int HalSdioHostWriteBlocksDmaRtl8195a(int result, uint32_t a2, int64 a3, uint32_t BlockCnta); -int SdioHostSwitchFunction(void *Data, int Mode, int Fn2Sel, int Fn1Sel, uint8_t *StatusBuf); -int HalSdioHostGetCardStatusRtl8195a(void *Data, uint32_t a2, int a3); -signed int HalSdioHostInitCardRtl8195a(void *Data, int a2, int a3); -int HalSdioHostGetSdStatusRtl8195a(void *Data, uint32_t a2, int a3); -signed int HalSdioHostChangeSdClockRtl8195a(void *Data, int Frequency); -int HalSdioHostEraseRtl8195a(uint64_t EndAddr, int64 a2, int64 EndAddra); -signed int HalSdioHostGetWriteProtectRtl8195a(void *Data, uint32_t a2, int a3); -int HalSdioHostSetWriteProtectRtl8195a(void *Data, int Setting); -*/ + signed int SdioHostIsTimeout(uint32_t StartCount, uint32_t TimeoutCnt); + void SdioHostSendCmd(SDIO_HOST_CMD *Cmd); + signed int SdioHostGetResponse(void *Data, int RspType); + void SdioHostSdBusPwrCtrl(uint8_t En, int a2); + int SdioHostSdClkCtrl(void *Data, int En, int Divisor); + int SdioHostChkDataLineActive(uint32_t Timeout); + int SdioHostChkCmdInhibitCMD(uint32_t Timeout); + int SdioHostChkCmdInhibitDAT(uint32_t Timeout); + uint32_t SdioHostIsrHandle(void *Data); + int HalSdioHostDeInitRtl8195a(void *Data); + int HalSdioHostEnableRtl8195a(void *Data); + int HalSdioHostDisableRtl8195a(void *Data); + signed int HalSdioHostIrqInitRtl8195a(void *Data); + signed int HalSdioHostInitHostRtl8195a(void *Data); + int HalSdioHostStopTransferRtl8195a(void *Data, uint32_t a2); + signed int SdioHostErrIntRecovery(void *Data, int a2, signed int a3); + signed int SdioHostChkXferComplete(void *Data, uint32_t Timeout, signed int a3); + signed int SdioHostChkCmdComplete(void *Data, uint32_t Timeout); + int SdioHostCardSelection(void *Data, int Select, int a3); + int SdioHostGetCSD(void *Data, uint32_t a2); + int HalSdioHostReadBlocksDmaRtl8195a(int result, uint32_t a2, int64 a3, uint32_t BlockCnta); + int HalSdioHostWriteBlocksDmaRtl8195a(int result, uint32_t a2, int64 a3, uint32_t BlockCnta); + int SdioHostSwitchFunction(void *Data, int Mode, int Fn2Sel, int Fn1Sel, uint8_t *StatusBuf); + int HalSdioHostGetCardStatusRtl8195a(void *Data, uint32_t a2, int a3); + signed int HalSdioHostInitCardRtl8195a(void *Data, int a2, int a3); + int HalSdioHostGetSdStatusRtl8195a(void *Data, uint32_t a2, int a3); + signed int HalSdioHostChangeSdClockRtl8195a(void *Data, int Frequency); + int HalSdioHostEraseRtl8195a(uint64_t EndAddr, int64 a2, int64 EndAddra); + signed int HalSdioHostGetWriteProtectRtl8195a(void *Data, uint32_t a2, int a3); + int HalSdioHostSetWriteProtectRtl8195a(void *Data, int Setting); + */ // int DiagPrintf(const char *, ...); weak // int VectorIrqDisRtl8195A(u32); weak // int VectorIrqUnRegisterRtl8195A(u32); weak @@ -43,309 +43,256 @@ int HalSdioHostSetWriteProtectRtl8195a(void *Data, int Setting); // int VectorIrqRegisterRtl8195A(void); weak // int VectorIrqEnRtl8195A(u32); weak // int HalDelayUs(u32); weak - //------------------------------------------------------------------------- // Data declarations +//------------------------------------------------------------------------- +//-----SdioHostIsTimeout(StartCount, TimeoutCnt) +HAL_Status SdioHostIsTimeout(u32 StartCount, u32 TimeoutCnt) { + u32 t1, t2; + HAL_Status result; -// extern _UNKNOWN HalTimerOp; weak -// extern _UNKNOWN ConfigDebugInfo; weak -// extern _UNKNOWN ConfigDebugErr; weak + t1 = HalTimerOp.HalTimerReadCount(1); + t2 = StartCount - t1; + if (StartCount < t1) + t2--; + if (TimeoutCnt >= t2) + result = HAL_OK; + else + result = HAL_TIMEOUT; + return result; +} - -//----- -int SdioHostIsTimeout(uint32_t StartCount, uint32_t TimeoutCnt) -{ - u32 t1, t2; - int result; - - t1 = HalTimerOp.HalTimerReadCount(1); - t2 = StartCount - t1; - if(StartCount < t1) t2--; - if (TimeoutCnt >= t2 ) result = 0; - else result = 2; - return result; +//----- SdioHostSendCmd(PSDIO_HOST_CMD) +void SdioHostSendCmd(PSDIO_HOST_CMD Cmd) { + u16 reg_cmd = ((*(u8 *) &Cmd->CmdFmt & 0x3B) | (*(u8 *) &Cmd->CmdFmt & 0xC0) + | ((*((u8 *) &Cmd->CmdFmt + 1) & 0x3F) << 8)); + HAL_SDIO_HOST_WRITE32(REG_SDIO_HOST_ARG, Cmd->Arg); // 40058008 = Cmd->Arg + HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_CMD, reg_cmd); // 4005800E = reg_cmd } //----- -void SdioHostSendCmd(SDIO_HOST_CMD *Cmd) -{ - int v1; +HAL_Status SdioHostGetResponse(void *Data, int RspType) { + HAL_Status result; - v1 = *(u8 *)&Cmd->CmdFmt & 0x3B | *(u8 *)&Cmd->CmdFmt & 0xC0 | ((*((u8 *)&Cmd->CmdFmt + 1) & 0x3F) << 8); - v40058008 = Cmd->Arg; - v4005800E = v1; + if (Data) { + *((u32 *) Data + 5) = HAL_SDIO_HOST_READ32(REG_SDIO_HOST_RSP0); // 40058010; + *((u32 *) Data + 6) = HAL_SDIO_HOST_READ32(REG_SDIO_HOST_RSP2); + if (RspType == 1) { + *((u32 *) Data + 7) = HAL_SDIO_HOST_READ32(REG_SDIO_HOST_RSP4); + *((u32 *) Data + 8) = HAL_SDIO_HOST_READ32(REG_SDIO_HOST_RSP6); + } + result = HAL_OK; + } else + result = HAL_ERR_PARA; + return result; } //----- -signed int SdioHostGetResponse(void *Data, int RspType) -{ - signed int result; +void SdioHostSdBusPwrCtrl(uint8_t En) { + u8 reg_pwr; - if ( Data ) - { - *((u32 *)Data + 5) = v40058010; - *((u32 *)Data + 6) = v40058014; - if ( RspType == 1 ) - { - *((u32 *)Data + 7) = v40058018; - *((u32 *)Data + 8) = v4005801C; - } - result = 0; - } - else - { - result = 3; - } - return result; + HAL_SDIO_HOST_WRITE8(REG_SDIO_HOST_PWR_CTRL, + HAL_SDIO_HOST_READ8(REG_SDIO_HOST_PWR_CTRL) & (~ PWR_CTRL_SD_BUS_PWR)); + if (HAL_SDIO_HOST_READ32(REG_SDIO_HOST_CAPABILITIES) & CAPA_VOLT_SUPPORT_33V) { + DBG_SDIO_WARN("Supply SD bus voltage: 3.3V\n"); + reg_pwr = VOLT_30V << 1; + goto set_pwr; + } + if (HAL_SDIO_HOST_READ32(REG_SDIO_HOST_CAPABILITIES) & CAPA_VOLT_SUPPORT_30V) { + DBG_SDIO_WARN("Supply SD bus voltage: 3.0V\n"); + reg_pwr = VOLT_30V << 1; + goto set_pwr; + } + if (HAL_SDIO_HOST_READ32(REG_SDIO_HOST_CAPABILITIES) & CAPA_VOLT_SUPPORT_18V) { + DBG_SDIO_WARN("Supply SD bus voltage: 1.8V\n"); + reg_pwr = VOLT_18V << 1; + goto set_pwr; + } + DBG_SDIO_ERR("No supported voltage\n"); + goto exit_; + set_pwr: + HAL_SDIO_HOST_WRITE8(REG_SDIO_HOST_PWR_CTRL, reg_pwr); + exit_: + HAL_SDIO_HOST_WRITE8(REG_SDIO_HOST_PWR_CTRL, + HAL_SDIO_HOST_READ8(REG_SDIO_HOST_PWR_CTRL) | PWR_CTRL_SD_BUS_PWR); } //----- -void SdioHostSdBusPwrCtrl(uint8_t En, int a2) -{ - char v2; // r3@4 +HAL_Status SdioHostSdClkCtrl(void *Data, int En, int Divisor) { // SD_CLK_DIVISOR + u8 *v3; // r3@1 + HAL_Status result; + char v5; // r2@7 - v40058029 &= 0xFEu; - if ( v40058040 & 0x1000000 ) - { - DBG_SDIO_WARN("Supply SD bus voltage: 3.3V\n", ConfigDebugInfo << 21); - v2 = 14; -LABEL_9: - v40058029 = v2; - goto LABEL_16; - } - if ( v40058040 & 0x2000000 ) - { - DBG_SDIO_WARN("Supply SD bus voltage: 3.0V\n", a2, v40058040 << 6); - v2 = 12; - goto LABEL_9; - } - if ( v40058040 & 0x4000000 ) - { - DBG_SDIO_WARN("Supply SD bus voltage: 1.8V\n", 32 * v40058040, ConfigDebugInfo << 21); - v2 = 10; - goto LABEL_9; - } - DBG_SDIO_ERR("No supported voltage\n", 32 * v40058040, v40058040 << 6); -LABEL_16: - v40058029 |= 1u; + v3 = Data; + result = HAL_SDIO_HOST_READ32(REG_SDIO_HOST_PRESENT_STATE) + & (PRES_STATE_CMD_INHIBIT_CMD | PRES_STATE_CMD_INHIBIT_DAT); // v40058024 & 3; + if (HAL_SDIO_HOST_READ32(REG_SDIO_HOST_PRESENT_STATE) + & (PRES_STATE_CMD_INHIBIT_CMD | PRES_STATE_CMD_INHIBIT_DAT) != 0) { + result = HAL_BUSY; + } else { + if (!En) { + v4005802C &= 0xFFFBu; + return 0; + } + v4005802C &= 0xFFFBu; + v4005802C = v4005802C | (u16) ((u16) Divisor << 8); + v4005802C |= 4u; + if (Divisor == 8) { // BASE_CLK_DIVIDED_BY_16 + v5 = 4; + goto LABEL_23; + } + if ((unsigned int) Divisor > 8) { + if (Divisor == 32) { // BASE_CLK_DIVIDED_BY_64 + v5 = 2; + goto LABEL_23; + } + if ((unsigned int) Divisor > 0x20) { // BASE_CLK_DIVIDED_BY_64 + if (Divisor == 64) { // BASE_CLK_DIVIDED_BY_128 + v5 = 1; + goto LABEL_23; + } + if (Divisor == 128) { // BASE_CLK_DIVIDED_BY_256 + v3[133] = 0; + return result; + } + } else if (Divisor == 16) { + v5 = 3; + goto LABEL_23; + } + } else { + if (Divisor == 1) { // BASE_CLK_DIVIDED_BY_2 + v5 = 7; + goto LABEL_23; + } + if ((unsigned int) Divisor < 1) { // BASE_CLK < BASE_CLK_DIVIDED_BY_2 + v5 = 8; + LABEL_23: v3[133] = v5; + return result; + } + if (Divisor == 2) { // BASE_CLK_DIVIDED_BY_4 + v5 = 6; + goto LABEL_23; + } + if (Divisor == 4) { // BASE_CLK_DIVIDED_BY_8 + v5 = 5; + goto LABEL_23; + } + } + + DBG_SDIO_ERR("Unsupported SDCLK divisor !!\n"); + return 0; + } + return result; } - -//----- -int SdioHostSdClkCtrl(void *Data, int En, int Divisor) -{ - u8 *v3; // r3@1 - int result; // r0@1 - char v5; // r2@7 - - v3 = Data; - result = v40058024 & 3; - if ( v40058024 & 3 ) - { - result = 1; - } - else - { - if ( !En ) - { - v4005802C &= 0xFFFBu; - return 0; - } - v4005802C &= 0xFFFBu; - v4005802C = v4005802C | (u16)((u16)Divisor << 8); - v4005802C |= 4u; - if ( Divisor == 8 ) - { - v5 = 4; - goto LABEL_23; - } - if ( (unsigned int)Divisor > 8 ) - { - if ( Divisor == 32 ) - { - v5 = 2; - goto LABEL_23; - } - if ( (unsigned int)Divisor > 0x20 ) - { - if ( Divisor == 64 ) - { - v5 = 1; - goto LABEL_23; - } - if ( Divisor == 128 ) - { - v3[133] = 0; - return result; - } - } - else if ( Divisor == 16 ) - { - v5 = 3; - goto LABEL_23; - } - } - else - { - if ( Divisor == 1 ) - { - v5 = 7; - goto LABEL_23; - } - if ( (unsigned int)Divisor < 1 ) - { - v5 = 8; -LABEL_23: - v3[133] = v5; - return result; - } - if ( Divisor == 2 ) - { - v5 = 6; - goto LABEL_23; - } - if ( Divisor == 4 ) - { - v5 = 5; - goto LABEL_23; - } - } - - DBG_SDIO_ERR("Unsupported SDCLK divisor !!\n"); - return 0; - } - } - return result; -} -// 23D4: using guessed type int DiagPrintf(const char *, ...); - -//----- (000001E4) -------------------------------------------------------- -int SdioHostChkDataLineActive(uint32_t Timeout) -{ - uint32_t v1; // r4@1 - int result; // r0@2 - - v1 = (*((int ( **)(u32))&HalTimerOp + 2))(1); - do - { - result = v40058024 & 4; - if ( !(v40058024 & 4) ) break; - result = SdioHostIsTimeout(v1, 3225); - } - while ( result != 2 ); - return result; +//----- SdioHostChkDataLineActive(uint32_t Timeout) +HAL_Status SdioHostChkDataLineActive(uint32_t Timeout) { + HAL_Status result; + u32 t1 = HalTimerOp.HalTimerReadCount(1); + do { + if ((HAL_SDIO_HOST_READ32(REG_SDIO_HOST_PRESENT_STATE) + & PRES_STATE_DAT_LINE_ACTIVE) == 0) + break; + result = SdioHostIsTimeout(t1, 3225); + } while (result != HAL_TIMEOUT); + return result; } -//----- (0000021C) -------------------------------------------------------- -int SdioHostChkCmdInhibitCMD(uint32_t Timeout) -{ - uint32_t v1; // r4@1 - int result; // r0@2 - - v1 = (*((int ( **)(u32))&HalTimerOp + 2))(1); - do - { - result = v40058024 & 1; - if ( !(v40058024 & 1) ) - break; - result = SdioHostIsTimeout(v1, 3225); - } - while ( result != 2 ); - return result; +//----- SdioHostChkCmdInhibitCMD(uint32_t Timeout) +HAL_Status SdioHostChkCmdInhibitCMD(uint32_t Timeout) { + HAL_Status result; + u32 t1 = HalTimerOp.HalTimerReadCount(1); + do { + if ((HAL_SDIO_HOST_READ32(REG_SDIO_HOST_PRESENT_STATE) + & PRES_STATE_CMD_INHIBIT_CMD) == 0) + break; + result = SdioHostIsTimeout(t1, 3225); + } while (result != HAL_TIMEOUT); + return result; } -//----- (00000254) -------------------------------------------------------- -int SdioHostChkCmdInhibitDAT(uint32_t Timeout) -{ - uint32_t v1; // r4@1 - int result; // r0@2 - - v1 = (*((int ( **)(u32))&HalTimerOp + 2))(1); - do - { - result = v40058024 & 2; - if ( !(v40058024 & 2) ) - break; - result = SdioHostIsTimeout(v1, 3225); - } - while ( result != 2 ); - return result; +//----- SdioHostChkCmdInhibitDAT(uint32_t Timeout) +int SdioHostChkCmdInhibitDAT(uint32_t Timeout) { + HAL_Status result; + u32 t1 = HalTimerOp.HalTimerReadCount(1); + do { + if ((HAL_SDIO_HOST_READ32(REG_SDIO_HOST_PRESENT_STATE) + & PRES_STATE_CMD_INHIBIT_DAT) == 0) + break; + result = SdioHostIsTimeout(t1, 3225); + } while (result != HAL_TIMEOUT); + return result; } //----- (0000028C) -------------------------------------------------------- -uint32_t SdioHostIsrHandle(void *Data) -{ - int v1; // r5@1 - u32 *v2; // r4@1 - uint8_t v3; // r0@7 - int v4; // r1@7 - void ( *v5)(u32); // r3@7 - void ( *v6)(u32); // r3@10 - uint32_t result; // r0@14 +void SdioHostIsrHandle(void *Data) { + int v1; // r5@1 + u32 *v2; // r4@1 + uint8_t v3; // r0@7 + int v4; // r1@7 + void (*v5)(u32); // r3@7 + void (*v6)(u32); // r3@10 +// uint32_t result; // r0@14 - v1 = v40058030; - v40058038 = 0; - v2 = Data; - if ( v40058030 ) { - if ( v40058030 << 31 < 0 ) - *((u8 *)Data + 128) = 1; - if ( v1 << 30 < 0 ) - *((u8 *)Data + 129) = 1; - if ( v1 & NOR_INT_STAT_CARD_INSERT) // 0x40 - { - v3 = SdioHostSdClkCtrl(Data, 1, 64); - SdioHostSdBusPwrCtrl(v3, v4); - v5 = (void ( *)(u32))v2[35]; - if ( v5 ) v5(v2[37]); - } - if ( v1 & NOR_INT_STAT_CARD_REMOVAL) // 0x80 - { - v40058029 &= 0xFEu; - SdioHostSdClkCtrl(v2, 0, 0); - v6 = (void ( *)(u32))v2[36]; - if ( v6 ) - v6(v2[38]); - } - if ( v1 & NOR_INT_STAT_ERR_INT) // 0x8000 ) - { - v4005803A = 0; - *((u8 *)v2 + 130) = 1; - } - } - v40058034 = 195; - result = 0; - v40058038 = 195; - return result; + v1 = v40058030; + v40058038 = 0; + v2 = Data; + if (v1) { + if (v1 << 31 < 0) + *((u8 *) Data + 128) = 1; + if (v1 << 30 < 0) + *((u8 *) Data + 129) = 1; + if (v1 & NOR_INT_STAT_CARD_INSERT) // 0x40 + { + v3 = SdioHostSdClkCtrl(Data, 1, BASE_CLK_DIVIDED_BY_128); // BASE_CLK_DIVIDED_BY_128 + SdioHostSdBusPwrCtrl(v3, v4); + v5 = (void (*)(u32)) v2[35]; + if (v5) + v5(v2[37]); + } + if (v1 & NOR_INT_STAT_CARD_REMOVAL) // 0x80 + { + v40058029 &= 0xFEu; + SdioHostSdClkCtrl(v2, 0, BASE_CLK); // BASE_CLK + v6 = (void (*)(u32)) v2[36]; + if (v6) + v6(v2[38]); + } + if (v1 & NOR_INT_STAT_ERR_INT) // 0x8000 ) + { + v4005803A = 0; + *((u8 *) v2 + 130) = 1; + } + } + v40058034 = 195; +// result = 0; + v40058038 = 195; +// return 0; } //----- (00000328) -------------------------------------------------------- -HAL_Status HalSdioHostDeInitRtl8195a(IN VOID *Data) -{ - void *v1; // r5@1 - int v2; // r4@1 +HAL_Status HalSdioHostDeInitRtl8195a(IN VOID *Data) { + void *v1; // r5@1 + int v2; // r4@1 - PHAL_SDIO_HOST_ADAPTER v1 = Data; - v40058029 &= 0xFEu; - v2 = SdioHostSdClkCtrl(Data, 0, 0); - if ( !v2 ) - { - if ( v1 ) - { - VectorIrqDisRtl8195A(v1); - VectorIrqUnRegisterRtl8195A(v1); - v4005802C &= 0xFFFEu; - v40059000 &= 0xFFFFFBFF; - v40000214 &= 0xFFFFFFFB; - HalPinCtrlRtl8195A(65, 0, 0); - v40000240 &= 0xFFFFFFF7; - v40000240 &= 0xFFFFFFFB; - } - else - { - v2 = 3; - } - } - return v2; + PHAL_SDIO_HOST_ADAPTER v1 = Data; + v40058029 &= 0xFEu; + v2 = SdioHostSdClkCtrl(Data, 0, BASE_CLK); + if (!v2) { + if (v1) { + VectorIrqDisRtl8195A(v1); + VectorIrqUnRegisterRtl8195A(v1); + v4005802C &= 0xFFFEu; + v40059000 &= 0xFFFFFBFF; + v40000214 &= 0xFFFFFFFB; + HalPinCtrlRtl8195A(65, 0, 0); + v40000240 &= 0xFFFFFFF7; + v40000240 &= 0xFFFFFFFB; + } else { + v2 = 3; + } + } + return v2; } // 23DC: using guessed type int VectorIrqDisRtl8195A(u32); // 23E0: using guessed type int VectorIrqUnRegisterRtl8195A(u32); @@ -354,27 +301,25 @@ HAL_Status HalSdioHostDeInitRtl8195a(IN VOID *Data) //----- (000003C0) -------------------------------------------------------- HAL_Status HalSdioHostEnableRtl8195a(IN VOID *Data) // // PHAL_SDIO_HOST_ADAPTER Data { - v40000240 |= 4u; - v40000240 |= 8u; - v4005802C |= 1u; - while ( !(v4005802C & 2) ) - ; - return SdioHostSdClkCtrl(Data, 1, 1); + v40000240 |= 4u; + v40000240 |= 8u; + v4005802C |= 1u; + while (!(v4005802C & 2)) + ; + return SdioHostSdClkCtrl(Data, 1, BASE_CLK_DIVIDED_BY_2); } //----- (000003F8) -------------------------------------------------------- -HAL_Status HalSdioHostDisableRtl8195a(IN VOID *Data) -{ - int result; // r0@1 +HAL_Status HalSdioHostDisableRtl8195a(IN VOID *Data) { + int result; // r0@1 - result = SdioHostSdClkCtrl(Data, 0, 0); - if ( !result ) - { - v4005802C &= 0xFFFEu; - v40000240 &= 0xFFFFFFF7; - v40000240 &= 0xFFFFFFFB; - } - return result; + result = SdioHostSdClkCtrl(Data, 0, BASE_CLK); + if (!result) { + v4005802C &= 0xFFFEu; + v40000240 &= 0xFFFFFFF7; + v40000240 &= 0xFFFFFFFB; + } + return result; } //----- HalSdioHostIrqInitRtl8195a @@ -382,1811 +327,1615 @@ HAL_Status HalSdioHostIrqInitRtl8195a(IN VOID *Data) // PIRQ_HANDLE Data { HAL_Status result; PIRQ_HANDLE v1 = Data; - if (v1) { + if (v1) { v1->Data = Data; v1->IrqNum = SDIO_HOST_IRQ; v1->IrqFun = SdioHostIsrHandle; v1->Priority = 6; - VectorIrqRegisterRtl8195A(); + VectorIrqRegisterRtl8195A((PIRQ_HANDLE) v1); VectorIrqEnRtl8195A((PIRQ_HANDLE) v1); result = HAL_OK; - } - else result = HAL_ERR_PARA; - return result; + } else + result = HAL_ERR_PARA; + return result; } //----- HalSdioHostInitHostRtl8195a -HAL_Status HalSdioHostInitHostRtl8195a(IN VOID *Data) -{ - HAL_WRITE32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0, - HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0) & (~BIT_SOC_ACTCK_SDIO_DEV_EN)); - HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, - HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN) & (~BIT_SOC_HCI_SDIOD_ON_EN)); +HAL_Status HalSdioHostInitHostRtl8195a(IN VOID *Data) { + HAL_WRITE32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0, + HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0) & (~BIT_SOC_ACTCK_SDIO_DEV_EN)); + HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, + HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN) & (~BIT_SOC_HCI_SDIOD_ON_EN)); - HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, - HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN) & (~BIT_SOC_HCI_SDIOD_OFF_EN)); + HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, + HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN) & (~BIT_SOC_HCI_SDIOD_OFF_EN)); - HAL_WRITE32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL, - HAL_READ32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL) & (~BIT_HCI_SDIOD_PIN_EN)); + HAL_WRITE32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL, + HAL_READ32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL) & (~BIT_HCI_SDIOD_PIN_EN)); - HAL_WRITE32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0, - HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0) | BIT_SOC_ACTCK_SDIO_HST_EN); - HAL_WRITE32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0, - HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0) | BIT_SOC_SLPCK_SDIO_HST_EN); - HalPinCtrlRtl8195A(SDIOH, 0, 1); - HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, - HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN) | BIT_SOC_HCI_SDIOH_EN); - HAL_SDIO_HOST_WRITE8(REG_SDIO_HOST_SW_RESET, - HAL_SDIO_HOST_READ8(REG_SDIO_HOST_SW_RESET) | 1); //4005802F |= 1; - int x = 1000; - while(HAL_SDIO_HOST_READ8(REG_SDIO_HOST_SW_RESET) & 1 ) { - if(x-- == 0) { + HAL_WRITE32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0, + HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0) | BIT_SOC_ACTCK_SDIO_HST_EN); + HAL_WRITE32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0, + HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0) | BIT_SOC_SLPCK_SDIO_HST_EN); + HalPinCtrlRtl8195A(SDIOH, 0, 1); + HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, + HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN) | BIT_SOC_HCI_SDIOH_EN); + HAL_SDIO_HOST_WRITE8(REG_SDIO_HOST_SW_RESET, + HAL_SDIO_HOST_READ8(REG_SDIO_HOST_SW_RESET) | 1); //4005802F |= 1; + int x = 1000; + while (HAL_SDIO_HOST_READ8(REG_SDIO_HOST_SW_RESET) & 1) { + if (x-- == 0) { DBG_SDIO_ERR("SD host initialization FAIL !!\n"); - return HAL_TIMEOUT; - } - } - HalSdioHostIrqInitRtl8195a(Data); - HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_ERROR_INT_STATUS_EN, 195);// 40058034 = 195; - HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_NORMAL_INT_SIG_EN, 195);// 40058038 = 195; - HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_ERROR_INT_STATUS_EN, 127);// 40058036 = 127; - HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_ERROR_INT_SIG_EN, 127);// 4005803A = 127; - HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_CLK_CTRL, - HAL_SDIO_HOST_READ16(REG_SDIO_HOST_CLK_CTRL) | 1);// 4005802C |= 1; - x = 1000; - while ( !(HAL_SDIO_HOST_READ16(REG_SDIO_HOST_CLK_CTRL) & 2) ) { - if(x-- == 0) { + return HAL_TIMEOUT; + } + } + HalSdioHostIrqInitRtl8195a(Data); + HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_ERROR_INT_STATUS_EN, 195); // 40058034 = 195; + HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_NORMAL_INT_SIG_EN, 195); // 40058038 = 195; + HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_ERROR_INT_STATUS_EN, 127); // 40058036 = 127; + HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_ERROR_INT_SIG_EN, 127); // 4005803A = 127; + HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_CLK_CTRL, + HAL_SDIO_HOST_READ16(REG_SDIO_HOST_CLK_CTRL) | CLK_CTRL_INTERAL_CLK_EN); // 4005802C |= 1; + x = 1000; + while (!(HAL_SDIO_HOST_READ16(REG_SDIO_HOST_CLK_CTRL) + & CLK_CTRL_INTERAL_CLK_STABLE)) { + if (x-- == 0) { DBG_SDIO_ERR("SD host initialization FAIL !!\n"); - return HAL_TIMEOUT; - } - } - HAL_WRITE32(SYSTEM_CTRL_BASE, 0x59000, - HAL_READ32(SYSTEM_CTRL_BASE, 0x59000) | 0x400); // 40059000 |= 0x400; - if (HAL_SDIO_HOST_READ32(REG_SDIO_HOST_CAPABILITIES) & 0x80000 ) - HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_HOST_CTRL, 16); //40058028 = 16; - HAL_SDIO_HOST_WRITE8(REG_SDIO_HOST_TIMEOUT_CTRL, 14); //4005802E = 14; - return 0; + return HAL_TIMEOUT; + } + } + HAL_WRITE32(SYSTEM_CTRL_BASE, 0x59000, + HAL_READ32(SYSTEM_CTRL_BASE, 0x59000) | 0x400); // 40059000 |= 0x400; + if (HAL_SDIO_HOST_READ32(REG_SDIO_HOST_CAPABILITIES) & 0x80000) + HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_HOST_CTRL, 16); //40058028 = 16; + HAL_SDIO_HOST_WRITE8(REG_SDIO_HOST_TIMEOUT_CTRL, 14); //4005802E = 14; + return 0; } //----- (00000578) -------------------------------------------------------- -HAL_Status HalSdioHostStopTransferRtl8195a(IN VOID *Data) -{ - u8 *v2; // r4@1 - int result; // r0@2 - char v4; // r2@4 - uint32_t v5; // r1@4 - signed int v6; // r2@4 - SDIO_HOST_CMD Cmd; // [sp+0h] [bp-10h]@1 +HAL_Status HalSdioHostStopTransferRtl8195a(IN VOID *Data) { + u8 *v2; // r4@1 + int result; // r0@2 + char v4; // r2@4 + uint32_t v5; // r1@4 + signed int v6; // r2@4 + SDIO_HOST_CMD Cmd; // [sp+0h] [bp-10h]@1 - *(u32 *)&Cmd.CmdFmt = Data; - Cmd.Arg = a2; - v2 = Data; - if ( Data ) - { - result = SdioHostChkCmdInhibitCMD((uint32_t)Data); - if ( !result ) - { - result = SdioHostChkCmdInhibitDAT(0); - if ( !result ) - { - Cmd.CmdFmt = (SDIO_HOST_CMD_FMT)((*(u8 *)&Cmd.CmdFmt | 0x1B) & 0xDF | 0xC0); - v4 = *((u8 *)&Cmd.CmdFmt + 1); - v2[128] = 0; - v2[129] = 0; - Cmd.Arg = 0; - *((u8 *)&Cmd.CmdFmt + 1) = v4 & 0xC0 | 0xC; - SdioHostSendCmd(&Cmd); - result = SdioHostChkCmdComplete(v2, v5); - if ( !result ) - result = SdioHostChkXferComplete(v2, 0x1388u, v6); - } - } - } - else - { - result = 3; - } - return result; + *(u32 *) &Cmd.CmdFmt = Data; + Cmd.Arg = a2; + v2 = Data; + if (Data) { + result = SdioHostChkCmdInhibitCMD((uint32_t) Data); + if (!result) { + result = SdioHostChkCmdInhibitDAT(0); + if (!result) { + Cmd.CmdFmt = (SDIO_HOST_CMD_FMT) ((*(u8 *) &Cmd.CmdFmt | 0x1B) + & 0xDF | 0xC0); + v4 = *((u8 *) &Cmd.CmdFmt + 1); + v2[128] = 0; + v2[129] = 0; + Cmd.Arg = 0; + *((u8 *) &Cmd.CmdFmt + 1) = v4 & 0xC0 | 0xC; + SdioHostSendCmd(&Cmd); + result = SdioHostChkCmdComplete(v2, v5); + if (!result) + result = SdioHostChkXferComplete(v2, 0x1388u, v6); + } + } + } else { + result = 3; + } + return result; } //----- (000005D8) -------------------------------------------------------- -signed int SdioHostErrIntRecovery(void *Data, int a2, signed int a3) -{ - u8 *v3; // r6@1 - __int16 v4; // r5@4 - int v5; // r3@5 - const char *v6; // r0@11 - signed int result; // r0@13 - int v8; // r3@15 - int v9; // r0@24 - const char *v10; // r0@32 +signed int SdioHostErrIntRecovery(void *Data, int a2, signed int a3) { + u8 *v3; // r6@1 + __int16 v4; // r5@4 + int v5; // r3@5 + const char *v6; // r0@11 + signed int result; // r0@13 + int v8; // r3@15 + int v9; // r0@24 + const char *v10; // r0@32 - v3 = Data; - if ( !Data ) - return 3; - DBG_SDIO_ERR("Recovering error interrupt...\n", a2, a3); - v4 = v40058032; - if ( v40058032 << 28 ) - { - v4005802F |= 2u; - v5 = 0; - while ( 1 ) - { - ++v5; - a2 = v4005802F << 30; - if ( !(v4005802F & 2) ) break; - a2 = 1001; - if ( v5 == 1001 ) - goto LABEL_14; - } - if ( v5 == 1000 ) - { - DBG_SDIO_ERR("CMD line reset timeout !!\n"); - return 2; - } - } -LABEL_14: - if ( v40058032 & 0x70 ) - { - v4005802F |= 4u; - v8 = 0; - while ( 1 ) - { - ++v8; - a2 = v4005802F << 29; - if ( !(v4005802F & 4) ) - break; - a2 = 1001; - if ( v8 == 1001 ) - goto LABEL_22; - } - if ( v8 == 1000 ) - { - DBG_SDIO_ERR("DAT line reset timeout !!\n"); - return 2; - } - } -LABEL_22: + v3 = Data; + if (!Data) + return 3; + DBG_SDIO_ERR("Recovering error interrupt...\n", a2, a3); + v4 = v40058032; + if (v40058032 << 28) { + v4005802F |= 2u; + v5 = 0; + while (1) { + ++v5; + a2 = v4005802F << 30; + if (!(v4005802F & 2)) + break; + a2 = 1001; + if (v5 == 1001) + goto LABEL_14; + } + if (v5 == 1000) { + DBG_SDIO_ERR("CMD line reset timeout !!\n"); + return 2; + } + } + LABEL_14: if (v40058032 & 0x70) { + v4005802F |= 4u; + v8 = 0; + while (1) { + ++v8; + a2 = v4005802F << 29; + if (!(v4005802F & 4)) + break; + a2 = 1001; + if (v8 == 1001) + goto LABEL_22; + } + if (v8 == 1000) { + DBG_SDIO_ERR("DAT line reset timeout !!\n"); + return 2; + } + } + LABEL_22: DBG_SDIO_ERR("Error interrupt status: 0x%04X\n", v40058032); - v40058032 = v4; - v3[130] = 0; - v9 = HalSdioHostStopTransferRtl8195a(v3, a2); - if ( !v9 ) - { - while ( 1 ) - { - ++v9; - if ( !(v40058024 & 3) ) - break; - if ( v9 == 1001 ) - goto LABEL_30; - } - if ( v9 == 1000 ) - return 2; -LABEL_30: - if ( v40058032 << 28 ) - { - DBG_SDIO_ERR("Non-recoverable error(1) !!\n"); -LABEL_33: - DiagPrintf(v10); - goto LABEL_34; - } - } - else - { - if ( v40058032 & 0x10 ) - { - DBG_SDIO_ERR("Non-recoverable error(2) !!\n"); - goto LABEL_34; - } - HalDelayUs(50); - if ( (v40058024 & 0xF00000) == 15728640 ) - { - DBG_SDIO_ERR("Recoverable error...\n"); - result = 16; - goto LABEL_44; - } - DBG_SDIO_ERR("Non-recoverable error(3) !!\n"); - goto LABEL_34; - } - } -LABEL_34: - result = 238; -LABEL_44: - v4005803A = 127; - return result; - } + v40058032 = v4; + v3[130] = 0; + v9 = HalSdioHostStopTransferRtl8195a(v3, a2); + if (!v9) { + while (1) { + ++v9; + if (!(v40058024 & 3)) + break; + if (v9 == 1001) + goto LABEL_30; + } + if (v9 == 1000) + return 2; + LABEL_30: if (v40058032 << 28) { + DBG_SDIO_ERR("Non-recoverable error(1) !!\n"); + LABEL_33: DiagPrintf(v10); + goto LABEL_34; + } + } else { + if (v40058032 & 0x10) { + DBG_SDIO_ERR("Non-recoverable error(2) !!\n"); + goto LABEL_34; + } + HalDelayUs(50); + if ((v40058024 & 0xF00000) == 15728640) { + DBG_SDIO_ERR("Recoverable error...\n"); + result = 16; + goto LABEL_44; + } + DBG_SDIO_ERR("Non-recoverable error(3) !!\n"); + goto LABEL_34; + } + + LABEL_34: result = 238; + LABEL_44: v4005803A = 127; + return result; + DBG_SDIO_ERR("Stop transmission error !!\n"); - return 238; + return 238; } // 23D4: using guessed type int DiagPrintf(const char *, ...); // 23F0: using guessed type int HalDelayUs(u32); //----- (00000748) -------------------------------------------------------- -signed int SdioHostChkXferComplete(void *Data, uint32_t Timeout, signed int a3) -{ - uint32_t v3; // r6@1 - u8 *v4; // r4@1 - uint32_t v5; // r5@3 - uint32_t v6; // r7@3 - signed int result; // r0@9 +signed int SdioHostChkXferComplete(void *Data, uint32_t Timeout, signed int a3) { + uint32_t v3; // r6@1 + u8 *v4; // r4@1 + uint32_t v5; // r5@3 + uint32_t v6; // r7@3 + signed int result; // r0@9 - v3 = Timeout; - v4 = Data; - if ( Data ) - { - if ( Timeout - 1 > 0xFFFFFFFD ) - { - v6 = 0; - v5 = 0; - } - else - { - v5 = 1000 * Timeout / 0x1F; - v6 = (*((int ( **)(u32))&HalTimerOp + 2))(1); - } - do - { - while ( 1 ) - { - if ( v4[129] && v40058024 & 0x100000 ) - return 0; - if ( v4[130] ) - return SdioHostErrIntRecovery(v4, Timeout, a3); - if ( !v5 ) - break; - result = SdioHostIsTimeout(v6, v5); - if ( result == 2 ) - return result; - } - } - while ( v3 ); - result = 1; - } - else - { - result = 3; - } - return result; + v3 = Timeout; + v4 = Data; + if (Data) { + if (Timeout - 1 > 0xFFFFFFFD) { + v6 = 0; + v5 = 0; + } else { + v5 = 1000 * Timeout / 0x1F; + v6 = (*((int (**)(u32)) &HalTimerOp + 2))(1); + } + do { + while (1) { + if (v4[129] && v40058024 & 0x100000) + return 0; + if (v4[130]) + return SdioHostErrIntRecovery(v4, Timeout, a3); + if (!v5) + break; + result = SdioHostIsTimeout(v6, v5); + if (result == 2) + return result; + } + } while (v3); + result = 1; + } else { + result = 3; + } + return result; } //----- (000007C4) -------------------------------------------------------- -signed int SdioHostChkCmdComplete(void *Data, uint32_t Timeout) -{ - void *v2; // r4@1 - int v3; // r1@2 - signed int v4; // r2@2 - uint32_t v5; // r5@2 - signed int result; // r0@5 +signed int SdioHostChkCmdComplete(void *Data, uint32_t Timeout) { + void *v2; // r4@1 + int v3; // r1@2 + signed int v4; // r2@2 + uint32_t v5; // r5@2 + signed int result; // r0@5 - v2 = Data; - if ( Data ) - { - v5 = (*((int ( **)(u32, u32))&HalTimerOp + 2))(1, Timeout); - while ( !*((u8 *)v2 + 128) ) - { - if ( *((u8 *)v2 + 130) ) - return SdioHostErrIntRecovery(v2, v3, v4); - result = SdioHostIsTimeout(v5, 1612); - if ( result == 2 ) - return result; - } - result = 0; - } - else - { - result = 3; - } - return result; + v2 = Data; + if (Data) { + v5 = (*((int (**)(u32, u32)) &HalTimerOp + 2))(1, Timeout); + while (!*((u8 *) v2 + 128)) { + if (*((u8 *) v2 + 130)) + return SdioHostErrIntRecovery(v2, v3, v4); + result = SdioHostIsTimeout(v5, 1612); + if (result == 2) + return result; + } + result = 0; + } else + result = 3; + + return result; } //----- (0000080C) -------------------------------------------------------- -int SdioHostCardSelection(void *Data, int Select, int a3) -{ - u8 *v3; // r4@1 - int result; // r0@3 - char v5; // r3@5 - int v6; // r3@5 - uint32_t v7; // r1@5 - signed int v8; // r2@5 - signed int v9; // r5@6 - char v10; // r3@11 - uint32_t v11; // r1@11 - SDIO_HOST_CMD Cmd; // [sp+0h] [bp-18h]@1 - int v13; // [sp+8h] [bp-10h]@1 +int SdioHostCardSelection(void *Data, int Select, int a3) { + u8 *v3; // r4@1 + int result; // r0@3 + char v5; // r3@5 + int v6; // r3@5 + uint32_t v7; // r1@5 + signed int v8; // r2@5 + signed int v9; // r5@6 + char v10; // r3@11 + uint32_t v11; // r1@11 + SDIO_HOST_CMD Cmd; // [sp+0h] [bp-18h]@1 + int v13; // [sp+8h] [bp-10h]@1 - *(u32 *)&Cmd.CmdFmt = Data; - Cmd.Arg = Select; - v13 = a3; - v3 = Data; - if ( Data ) - { - if ( Select == 1 ) - { - result = SdioHostChkCmdInhibitCMD((uint32_t)Data); - if ( !result ) - { - result = SdioHostChkCmdInhibitDAT(0); - if ( !result ) - { - Cmd.CmdFmt = (SDIO_HOST_CMD_FMT)((*(u8 *)&Cmd.CmdFmt | 0x1B) & 0x1F); - v5 = *((u8 *)&Cmd.CmdFmt + 1); - v3[128] = 0; - *((u8 *)&Cmd.CmdFmt + 1) = v5 & 0xC0 | 7; - v6 = *((u16 *)v3 + 67); - v3[129] = 0; - Cmd.Arg = v6 << 16; - SdioHostSendCmd(&Cmd); - result = SdioHostChkCmdComplete(v3, v7); - if ( !result ) - { - v9 = SdioHostChkXferComplete(v3, 0x1388u, v8); - if ( v9 || (SdioHostGetResponse(v3, *(u8 *)&Cmd.CmdFmt & 3), v3[24] == 7) ) - { - result = v9; - } - else - { - DBG_SDIO_ERR("Command index error !!\n"); - result = 238; - } - } - } - } - } - else - { - result = SdioHostChkCmdInhibitCMD((uint32_t)Data); - if ( !result ) - { - *(u8 *)&Cmd.CmdFmt &= 4u; - v10 = *((u8 *)&Cmd.CmdFmt + 1); - v3[128] = 0; - Cmd.Arg = 0; - *((u8 *)&Cmd.CmdFmt + 1) = v10 & 0xC0 | 7; - SdioHostSendCmd(&Cmd); - result = SdioHostChkCmdComplete(v3, v11); - } - } - } - else - { - result = 3; - } - return result; + *(u32 *) &Cmd.CmdFmt = Data; + Cmd.Arg = Select; + v13 = a3; + v3 = Data; + if (Data) { + if (Select == 1) { + result = SdioHostChkCmdInhibitCMD((uint32_t) Data); + if (!result) { + result = SdioHostChkCmdInhibitDAT(0); + if (!result) { + Cmd.CmdFmt = (SDIO_HOST_CMD_FMT) ((*(u8 *) &Cmd.CmdFmt + | 0x1B) & 0x1F); + v5 = *((u8 *) &Cmd.CmdFmt + 1); + v3[128] = 0; + *((u8 *) &Cmd.CmdFmt + 1) = v5 & 0xC0 | 7; + v6 = *((u16 *) v3 + 67); + v3[129] = 0; + Cmd.Arg = v6 << 16; + SdioHostSendCmd(&Cmd); + result = SdioHostChkCmdComplete(v3, v7); + if (!result) { + v9 = SdioHostChkXferComplete(v3, 0x1388u, v8); + if (v9 + || (SdioHostGetResponse(v3, + *(u8 *) &Cmd.CmdFmt & 3), v3[24] == 7)) { + result = v9; + } else { + DBG_SDIO_ERR("Command index error !!\n"); + result = 238; + } + } + } + } + } else { + result = SdioHostChkCmdInhibitCMD((uint32_t) Data); + if (!result) { + *(u8 *) &Cmd.CmdFmt &= 4u; + v10 = *((u8 *) &Cmd.CmdFmt + 1); + v3[128] = 0; + Cmd.Arg = 0; + *((u8 *) &Cmd.CmdFmt + 1) = v10 & 0xC0 | 7; + SdioHostSendCmd(&Cmd); + result = SdioHostChkCmdComplete(v3, v11); + } + } + } else { + result = 3; + } + return result; } // 23D4: using guessed type int DiagPrintf(const char *, ...); //----- (000008FC) -------------------------------------------------------- -int SdioHostGetCSD(void *Data, uint32_t a2) -{ - void *v2; // r4@1 - int result; // r0@2 - int v4; // r3@3 - uint32_t v5; // r1@3 - signed int v6; // r6@3 - unsigned int v7; // r3@4 - unsigned int v8; // r2@4 - unsigned int v9; // r3@4 - unsigned int v10; // r2@4 - unsigned int v11; // r3@4 - unsigned int v12; // r2@4 - unsigned int v13; // r3@4 - SDIO_HOST_CMD Cmd; // [sp+0h] [bp-18h]@1 +int SdioHostGetCSD(void *Data, uint32_t a2) { + void *v2; // r4@1 + int result; // r0@2 + int v4; // r3@3 + uint32_t v5; // r1@3 + signed int v6; // r6@3 + unsigned int v7; // r3@4 + unsigned int v8; // r2@4 + unsigned int v9; // r3@4 + unsigned int v10; // r2@4 + unsigned int v11; // r3@4 + unsigned int v12; // r2@4 + unsigned int v13; // r3@4 + SDIO_HOST_CMD Cmd; // [sp+0h] [bp-18h]@1 - *(u32 *)&Cmd.CmdFmt = Data; - Cmd.Arg = a2; - v2 = Data; - if ( Data ) - { - result = SdioHostChkCmdInhibitCMD((uint32_t)Data); - if ( !result ) - { - Cmd.CmdFmt = (SDIO_HOST_CMD_FMT)((*(u8 *)&Cmd.CmdFmt & 0xFC | 9) & 0xF); - *((u8 *)&Cmd.CmdFmt + 1) = *((u8 *)&Cmd.CmdFmt + 1) & 0xC0 | 9; - v4 = *((u16 *)v2 + 67); - *((u8 *)v2 + 128) = 0; - Cmd.Arg = v4 << 16; - SdioHostSendCmd(&Cmd); - v6 = SdioHostChkCmdComplete(v2, v5); - if ( !v6 ) - { - SdioHostGetResponse(v2, *(u8 *)&Cmd.CmdFmt & 3); - v7 = *((u32 *)v2 + 8); - *((u8 *)v2 + 127) = 1; - *((u8 *)v2 + 112) = v7 >> 16; - *((u8 *)v2 + 114) = v7; - v8 = v7 >> 8; - v9 = *((u32 *)v2 + 7); - *((u8 *)v2 + 113) = v8; - *((u8 *)v2 + 115) = BYTE3(v9); - *((u8 *)v2 + 116) = v9 >> 16; - *((u8 *)v2 + 118) = v9; - v10 = v9 >> 8; - v11 = *((u32 *)v2 + 6); - *((u8 *)v2 + 117) = v10; - *((u8 *)v2 + 119) = BYTE3(v11); - *((u8 *)v2 + 120) = v11 >> 16; - *((u8 *)v2 + 122) = v11; - v12 = v11 >> 8; - v13 = *((u32 *)v2 + 5); - *((u8 *)v2 + 121) = v12; - *((u8 *)v2 + 123) = BYTE3(v13); - *((u8 *)v2 + 124) = v13 >> 16; - *((u8 *)v2 + 125) = BYTE1(v13); - *((u8 *)v2 + 126) = v13; - } - result = v6; - } - } - else - { - result = 3; - } - return result; + *(u32 *) &Cmd.CmdFmt = Data; + Cmd.Arg = a2; + v2 = Data; + if (Data) { + result = SdioHostChkCmdInhibitCMD((uint32_t) Data); + if (!result) { + Cmd.CmdFmt = (SDIO_HOST_CMD_FMT) ((*(u8 *) &Cmd.CmdFmt & 0xFC | 9) + & 0xF); + *((u8 *) &Cmd.CmdFmt + 1) = *((u8 *) &Cmd.CmdFmt + 1) & 0xC0 | 9; + v4 = *((u16 *) v2 + 67); + *((u8 *) v2 + 128) = 0; + Cmd.Arg = v4 << 16; + SdioHostSendCmd(&Cmd); + v6 = SdioHostChkCmdComplete(v2, v5); + if (!v6) { + SdioHostGetResponse(v2, *(u8 *) &Cmd.CmdFmt & 3); + v7 = *((u32 *) v2 + 8); + *((u8 *) v2 + 127) = 1; + *((u8 *) v2 + 112) = v7 >> 16; + *((u8 *) v2 + 114) = v7; + v8 = v7 >> 8; + v9 = *((u32 *) v2 + 7); + *((u8 *) v2 + 113) = v8; + *((u8 *) v2 + 115) = BYTE3(v9); + *((u8 *) v2 + 116) = v9 >> 16; + *((u8 *) v2 + 118) = v9; + v10 = v9 >> 8; + v11 = *((u32 *) v2 + 6); + *((u8 *) v2 + 117) = v10; + *((u8 *) v2 + 119) = BYTE3(v11); + *((u8 *) v2 + 120) = v11 >> 16; + *((u8 *) v2 + 122) = v11; + v12 = v11 >> 8; + v13 = *((u32 *) v2 + 5); + *((u8 *) v2 + 121) = v12; + *((u8 *) v2 + 123) = BYTE3(v13); + *((u8 *) v2 + 124) = v13 >> 16; + *((u8 *) v2 + 125) = BYTE1(v13); + *((u8 *) v2 + 126) = v13; + } + result = v6; + } else + result = 3; + return result; + } } - //----- (000009CC) -------------------------------------------------------- -HAL_Status HalSdioHostReadBlocksDmaRtl8195a(IN VOID *Data, IN u64 ReadAddr, IN u32 BlockCnt) -{ - int64 v4; // r4@1 - int v5; // r6@1 - int v6; // r7@3 - char v7; // r3@12 - uint32_t v8; // r1@12 - signed int v9; // r2@13 - int v10; // r1@16 - const char *v11; // r0@17 - char v12; // r3@20 - uint32_t v13; // r1@20 - signed int v14; // r2@23 - uint32_t v15; // r1@23 - SDIO_HOST_CMD Cmd; // [sp+0h] [bp-20h]@1 +HAL_Status HalSdioHostReadBlocksDmaRtl8195a(IN VOID *Data, IN u64 ReadAddr, +IN u32 BlockCnt) { + int64 v4; // r4@1 + int v5; // r6@1 + int v6; // r7@3 + char v7; // r3@12 + uint32_t v8; // r1@12 + signed int v9; // r2@13 + int v10; // r1@16 + const char *v11; // r0@17 + char v12; // r3@20 + uint32_t v13; // r1@20 + signed int v14; // r2@23 + uint32_t v15; // r1@23 + SDIO_HOST_CMD Cmd; // [sp+0h] [bp-20h]@1 - *(u32 *)&Cmd.CmdFmt = result; - Cmd.Arg = a2; - v4 = a3; - v5 = result; - if ( !result ) - return 3; - if ( BlockCnta >= 0x10000 ) - return 3; - v6 = *(u32 *)(result + 16); - if ( v6 << 30 || *(u32 *)(*(u32 *)(result + 16) + 4) << 30 ) - return 3; - if ( *(u8 *)(result + 132) ) - LODWORD(v4) = a3 >> 9; - while ( 1 ) - { - while ( 1 ) - { - v40058058 = v6; - v40058004 = 512; - if ( BlockCnta != 1 ) - break; - v4005800C = 17; -LABEL_18: - result = SdioHostChkCmdInhibitCMD(result); - if ( result ) - return result; - result = SdioHostChkDataLineActive(0); - if ( result ) - return result; - Cmd.CmdFmt = (SDIO_HOST_CMD_FMT)((*(u8 *)&Cmd.CmdFmt & 0xF4 | 0x3A) & 0x3F); - v12 = *((u8 *)&Cmd.CmdFmt + 1); - *(u8 *)(v5 + 128) = 0; - *(u8 *)(v5 + 129) = 0; - *((u8 *)&Cmd.CmdFmt + 1) = v12 & 0xC0 | 0x11; - Cmd.Arg = v4; - SdioHostSendCmd(&Cmd); - result = SdioHostChkCmdComplete((void *)v5, v13); - if ( result ) - goto LABEL_21; - SdioHostGetResponse((void *)v5, *(u8 *)&Cmd.CmdFmt & 3); - result = SdioHostChkXferComplete((void *)v5, 0x1388u, v14); - if ( !result ) - return 0; - if ( result != 16 ) - { - if ( v40058032 & 0x200 ) - { - v40058032 = 512; - if ( HalSdioHostStopTransferRtl8195a((void *)v5, v15) ) - { - if ( ConfigDebugErr & 0x400 ) - { - v11 = "\r[SDIO Err]Stop transmission error!\n"; - goto LABEL_29; - } - } - } - return 238; - } - } - v40058006 = BlockCnta; - v4005800C = 55; - if ( BlockCnta <= 1 ) - goto LABEL_18; - result = SdioHostChkCmdInhibitCMD(result); - if ( result ) - return result; - result = SdioHostChkDataLineActive(0); - if ( result ) - return result; - Cmd.CmdFmt = (SDIO_HOST_CMD_FMT)((*(u8 *)&Cmd.CmdFmt & 0xF4 | 0x3A) & 0x3F); - v7 = *((u8 *)&Cmd.CmdFmt + 1); - *(u8 *)(v5 + 128) = 0; - *(u8 *)(v5 + 129) = 0; - *(u8 *)(v5 + 130) = 0; - *((u8 *)&Cmd.CmdFmt + 1) = v7 & 0xC0 | 0x12; - Cmd.Arg = v4; - SdioHostSendCmd(&Cmd); - result = SdioHostChkCmdComplete((void *)v5, v8); - if ( !result ) - { - SdioHostGetResponse((void *)v5, *(u8 *)&Cmd.CmdFmt & 3); - result = SdioHostChkXferComplete((void *)v5, 0x1388u, v9); - if ( !result ) - break; - } -LABEL_21: - if ( result != 16 ) - return result; - } - if ( !(v40058032 & 0x20) ) - return 0; - v10 = ConfigDebugErr << 21; - if ( ConfigDebugErr & 0x400 ) - { - v11 = "\r[SDIO Err]Data CRC error!\n"; -LABEL_29: - DiagPrintf(v11, v10); - } - return 238; + HAL_Status result; + + *(u32 *) &Cmd.CmdFmt = result; + Cmd.Arg = a2; + v4 = a3; + v5 = result; + if (!result) + return 3; + if (BlockCnt >= 0x10000) + return HAL_ERR_PARA; + v6 = *(u32 *) (result + 16); + if (v6 << 30 || *(u32 *) (*(u32 *) (result + 16) + 4) << 30) + return 3; + if (*(u8 *) (result + 132)) + LODWORD (v4) = a3 >> 9; + while (1) { + while (1) { + HAL_SDIO_HOST_WRITE32(REG_SDIO_HOST_ADMA_SYS_ADDR, v6); // 40058058 = v6; + v40058004 = DATA_BLK_LEN; + if (BlockCnt != 1) + break; + v4005800C = 17; + LABEL_18: result = SdioHostChkCmdInhibitCMD(result); + if (result) + return result; + result = SdioHostChkDataLineActive(0); + if (result) + return result; + Cmd.CmdFmt = + (SDIO_HOST_CMD_FMT) ((*(u8 *) &Cmd.CmdFmt & 0xF4 | 0x3A) + & 0x3F); + v12 = *((u8 *) &Cmd.CmdFmt + 1); + *(u8 *) (v5 + 128) = 0; + *(u8 *) (v5 + 129) = 0; + *((u8 *) &Cmd.CmdFmt + 1) = v12 & 0xC0 | 0x11; + Cmd.Arg = v4; + SdioHostSendCmd(&Cmd); + result = SdioHostChkCmdComplete((void *) v5, v13); + if (result) + goto LABEL_21; + SdioHostGetResponse((void *) v5, *(u8 *) &Cmd.CmdFmt & 3); + result = SdioHostChkXferComplete((void *) v5, 0x1388u, v14); + if (!result) + return 0; + if (result != 16) { + if (v40058032 & 0x200) { + v40058032 = 512; + if (HalSdioHostStopTransferRtl8195a((void *) v5, v15)) { + if (ConfigDebugErr & 0x400) { + v11 = "\r[SDIO Err]Stop transmission error!\n"; + goto LABEL_29; + } + } + } + return 238; + } + } + v40058006 = BlockCnta; + v4005800C = 55; + if (BlockCnta <= 1) + goto LABEL_18; + result = SdioHostChkCmdInhibitCMD(result); + if (result) + return result; + result = SdioHostChkDataLineActive(0); + if (result) + return result; + Cmd.CmdFmt = (SDIO_HOST_CMD_FMT) ((*(u8 *) &Cmd.CmdFmt & 0xF4 | 0x3A) + & 0x3F); + v7 = *((u8 *) &Cmd.CmdFmt + 1); + *(u8 *) (v5 + 128) = 0; + *(u8 *) (v5 + 129) = 0; + *(u8 *) (v5 + 130) = 0; + *((u8 *) &Cmd.CmdFmt + 1) = v7 & 0xC0 | 0x12; + Cmd.Arg = v4; + SdioHostSendCmd(&Cmd); + result = SdioHostChkCmdComplete((void *) v5, v8); + if (!result) { + SdioHostGetResponse((void *) v5, *(u8 *) &Cmd.CmdFmt & 3); + result = SdioHostChkXferComplete((void *) v5, 0x1388u, v9); + if (!result) + break; + } + LABEL_21: if (result != 16) + return result; + } + if (!(v40058032 & 0x20)) + return 0; + v10 = ConfigDebugErr << 21; + if (ConfigDebugErr & 0x400) { + v11 = "\r[SDIO Err]Data CRC error!\n"; + LABEL_29: DiagPrintf(v11, v10); + } + return 238; } // 23D4: using guessed type int DiagPrintf(const char *, ...); //----- (00000B78) -------------------------------------------------------- -HAL_Status -HalSdioHostWriteBlocksDmaRtl8195a(IN VOID *Data, IN u64 WriteAddr, IN u32 BlockCnt) -{ - uint32_t v4; // r4@1 - int v5; // r6@1 - int v6; // r8@3 - char v7; // r3@12 - uint32_t v8; // r1@12 - signed int v9; // r2@13 - char v10; // r3@25 - uint32_t v11; // r1@25 - signed int v12; // r2@28 - uint32_t v13; // r1@29 - SDIO_HOST_CMD Cmd; // [sp+0h] [bp-20h]@1 +HAL_Status HalSdioHostWriteBlocksDmaRtl8195a(IN VOID *Data, +IN u64 WriteAddr, +IN u32 BlockCnt) { - *(u32 *)&Cmd.CmdFmt = result; - Cmd.Arg = a2; - v4 = a3; - v5 = result; - if ( !result ) - return 3; - if ( BlockCnta >= 0x10000 ) - return 3; - v6 = *(u32 *)(result + 16); - if ( v6 & 3 || *(u32 *)(*(u32 *)(result + 16) + 4) << 30 ) - return 3; - if ( *(u8 *)(result + 132) ) - v4 = a3 >> 9; - while ( 1 ) - { - while ( 1 ) - { - v40058058 = v6; - v40058004 = 512; - if ( BlockCnta == 1 ) - { - v4005800C = 1; - goto LABEL_23; - } - v40058006 = BlockCnta; - v4005800C = 39; - if ( BlockCnta > 1 ) - break; -LABEL_23: - result = SdioHostChkCmdInhibitCMD(result); - if ( result ) - return result; - result = SdioHostChkDataLineActive(0); - if ( result ) - return result; - Cmd.CmdFmt = (SDIO_HOST_CMD_FMT)((*(u8 *)&Cmd.CmdFmt & 0xF4 | 0x3A) & 0x3F); - v10 = *((u8 *)&Cmd.CmdFmt + 1); - *(u8 *)(v5 + 128) = 0; - *(u8 *)(v5 + 129) = 0; - *((u8 *)&Cmd.CmdFmt + 1) = v10 & 0xC0 | 0x18; - Cmd.Arg = v4; - SdioHostSendCmd(&Cmd); - result = SdioHostChkCmdComplete((void *)v5, v11); - if ( result ) - goto LABEL_26; - SdioHostGetResponse((void *)v5, *(u8 *)&Cmd.CmdFmt & 3); - if ( *(u32 *)(v5 + 20) & 0x4000000 ) - { -LABEL_14: - if ( ConfigDebugErr & 0x400 ) - DiagPrintf("\r[SDIO Err]Write protect violation !!\n"); - return 3; - } - result = SdioHostChkXferComplete((void *)v5, 0x1388u, v12); - if ( !result ) - return result; - if ( result != 16 ) - { - if ( v40058032 & 0x200 ) - { - v40058032 = 512; - if ( HalSdioHostStopTransferRtl8195a((void *)v5, v13) ) - { - if ( ConfigDebugErr & 0x400 ) - DiagPrintf("\r[SDIO Err]Stop transmission error!\n"); - } - } - return 238; - } - } - result = SdioHostChkCmdInhibitCMD(result); - if ( result ) - return result; - result = SdioHostChkDataLineActive(0); - if ( result ) - return result; - Cmd.CmdFmt = (SDIO_HOST_CMD_FMT)((*(u8 *)&Cmd.CmdFmt & 0xF4 | 0x3A) & 0x3F); - v7 = *((u8 *)&Cmd.CmdFmt + 1); - *(u8 *)(v5 + 128) = 0; - *(u8 *)(v5 + 129) = 0; - *(u8 *)(v5 + 130) = 0; - *((u8 *)&Cmd.CmdFmt + 1) = v7 & 0xC0 | 0x19; - Cmd.Arg = v4; - SdioHostSendCmd(&Cmd); - result = SdioHostChkCmdComplete((void *)v5, v8); - if ( !result ) - { - SdioHostGetResponse((void *)v5, *(u8 *)&Cmd.CmdFmt & 3); - if ( *(u32 *)(v5 + 20) & 0x4000000 ) - goto LABEL_14; - result = SdioHostChkXferComplete((void *)v5, 0x1F40u, v9); - if ( !result ) - break; - } -LABEL_26: - if ( result != 16 ) - return result; - } - if ( v40058032 & 0x20 ) - return 238; - if ( v40058032 & 0x10 ) - result = 2; - else - result = 0; - return result; + PHAL_SDIO_HOST_ADAPTER pSdioHostAdapter = (PHAL_SDIO_HOST_ADAPTER) Data; //int v5; // r6@1 + uint32_t sec_count; // v4; // r4@1 + +//int v6; // r8@3 + char v7; // r3@12 + uint32_t v8; // r1@12 + signed int v9; // r2@13 + char v10; // r3@25 + uint32_t v11; // r1@25 + signed int v12; // r2@28 + uint32_t v13; // r1@29 + SDIO_HOST_CMD Cmd; // [sp+0h] [bp-20h]@1 + HAL_Status result; + + *(u32 *) &Cmd.CmdFmt = ?; + Cmd.Arg = a2; + v4 = WriteAddr; +//v5 = result; //pSdioHostAdapter + if (BlockCnt == 0) + return HAL_ERR_PARA; + if (BlockCnt >= 0x10000) + return HAL_ERR_PARA; + ADMA2_DESC_FMT AdmaDescTbl = pSdioHostAdapter->AdmaDescTbl; + if (((u32) AdmaDescTbl & 3) || (AdmaDescTbl.Addr1 & 3)) + return HAL_ERR_PARA; + if (*(u8 *) (Data + 132)) + sec_count = WriteAddr >> 9; // + while (!(HAL_SDIO_HOST_READ32(REG_SDIO_HOST_PRESENT_STATE) & 0x100000)) { + result = SdioHostIsTimeout(v8, 0x3F01u); + if (result == HAL_TIMEOUT) { + DBG_SDIO_ERR("card busy TIMEOUT\n"); + return result; + } + } + + while (1) { + + while (1) { + HAL_SDIO_HOST_WRITE32(REG_SDIO_HOST_ADMA_SYS_ADDR, + (u32)AdmaDescTbl); //40058058 = v6; + HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_BLK_SIZE, DATA_BLK_LEN); // 40058004 = 512; + if (BlockCnt == 1) { + HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_BLK_CNT, 1); // 4005800C = 1; + goto LABEL_23; + } + HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_BLK_CNT, BlockCnt); // 40058006 = BlockCnta; + HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_XFER_MODE, + XFER_MODE_DMA_EN | XFER_MODE_BLK_CNT_EN | XFER_MODE_AUTO_CMD12_EN | XFER_MODE_MULT_SINGLE_BLK); //4005800C = 0x27; + if (BlockCnt > 1) + break; + + LABEL_23: result = SdioHostChkCmdInhibitCMD(result); + if (result != HAL_OK) + return result; + result = SdioHostChkDataLineActive(0); + if (result != HAL_OK) + return result; + Cmd.CmdFmt = + (SDIO_HOST_CMD_FMT) ((*(u8 *) &Cmd.CmdFmt & 0xF4 | 0x3A) + & 0x3F); + v10 = *((u8 *) &Cmd.CmdFmt + 1); + *(u8 *) (pSdioHostAdapter + 128) = 0; + *(u8 *) (pSdioHostAdapter + 129) = 0; + *((u8 *) &Cmd.CmdFmt + 1) = v10 & 0xC0 | 0x18; + Cmd.Arg = sec_count; + SdioHostSendCmd(&Cmd); + result = SdioHostChkCmdComplete((void *) v5, v11); + if (result) + goto LABEL_26; + SdioHostGetResponse((void *) pSdioHostAdapter, + *(u8 *) &Cmd.CmdFmt & 3); + if (*(u32 *) (pSdioHostAdapter + 20) & 0x4000000) { + LABEL_14: + DBG_SDIO_ERR("Write protect violation !!\n"); + return HAL_ERR_PARA; + } + result = SdioHostChkXferComplete((void *) pSdioHostAdapter, 0x1388u, + v12); + if (result != HAL_OK) + return result; + if (result != 16) { + if (HAL_SDIO_HOST_READ16( + REG_SDIO_HOST_ERROR_INT_STATUS) & ERR_INT_STAT_ADMA) { + HAL_SDIO_HOST_WRITE16(REG_SDIO_HOST_ERROR_INT_STATUS, + ERR_INT_STAT_ADMA); // 40058032 = 512; + if (HalSdioHostStopTransferRtl8195a( + (void *) pSdioHostAdapter, v13)) { + DBG_SDIO_ERR("Stop transmission error!\n"); + } + } + return 238; + } + } + result = SdioHostChkCmdInhibitCMD(result); + if (result != HAL_OK) + return result; + result = SdioHostChkDataLineActive(0); + if (result != HAL_OK) + return result; + Cmd.CmdFmt = (SDIO_HOST_CMD_FMT) ((*(u8 *) &Cmd.CmdFmt & 0xF4 | 0x3A) + & 0x3F); + v7 = *((u8 *) &Cmd.CmdFmt + 1); + *(u8 *) (pSdioHostAdapter + 128) = 0; + *(u8 *) (pSdioHostAdapter + 129) = 0; + *(u8 *) (pSdioHostAdapter + 130) = 0; + *((u8 *) &Cmd.CmdFmt + 1) = v7 & 0xC0 | 0x19; + Cmd.Arg = sec_count; + SdioHostSendCmd(&Cmd); + result = SdioHostChkCmdComplete((void *) v5, v8); + if (!result) { + SdioHostGetResponse((void *) pSdioHostAdapter, + *(u8 *) &Cmd.CmdFmt & 3); + if (*(u32 *) (pSdioHostAdapter + 20) & 0x4000000) + goto LABEL_14; + result = SdioHostChkXferComplete((void *) pSdioHostAdapter, 0x1F40u, + v9); + if (result != HAL_OK) + break; + } + LABEL_26: if (result != 16) + return result; + } + if (HAL_SDIO_HOST_READ16( + REG_SDIO_HOST_ERROR_INT_STATUS) & ERR_INT_STAT_DATA_CRC) // 40058032 & 0x20) + return HAL_ERR_UNKNOWN; + if (HAL_SDIO_HOST_READ16( + REG_SDIO_HOST_ERROR_INT_STATUS) & ERR_INT_STAT_DATA_TIMEOUT) + result = HAL_TIMEOUT; + else + result = HAL_OK; + return result; } // 23D4: using guessed type int DiagPrintf(const char *, ...); //----- (00000D34) -------------------------------------------------------- -int SdioHostSwitchFunction(void *Data, int Mode, int Fn2Sel, int Fn1Sel, uint8_t *StatusBuf) -{ - u8 *v5; // r4@1 - uint32_t v6; // r0@1 - int v7; // r5@1 - int v8; // r6@1 - char v9; // r7@3 - int result; // r0@3 - char v11; // r3@5 - uint32_t v12; // r1@5 - signed int v13; // r2@6 - uint32_t v14; // r1@6 - SDIO_HOST_CMD Cmd; // [sp+0h] [bp-20h]@1 - int v16; // [sp+8h] [bp-18h]@1 +int SdioHostSwitchFunction(void *Data, int Mode, int Fn2Sel, int Fn1Sel, + uint8_t *StatusBuf) { + u8 *v5; // r4@1 + uint32_t v6; // r0@1 + int v7; // r5@1 + int v8; // r6@1 + char v9; // r7@3 + int result; // r0@3 + char v11; // r3@5 + uint32_t v12; // r1@5 + signed int v13; // r2@6 + uint32_t v14; // r1@6 + SDIO_HOST_CMD Cmd; // [sp+0h] [bp-20h]@1 + int v16; // [sp+8h] [bp-18h]@1 - *(u32 *)&Cmd.CmdFmt = Data; - Cmd.Arg = Mode; - v16 = Fn2Sel; - v5 = Data; - v6 = *((u32 *)Data + 4); - v7 = Mode; - v8 = Fn2Sel; - if ( !v6 || ((u8)Fn1Sel | (u8)v6) & 3 ) - { - result = 3; - } - else - { - v40058058 = v6; - v40058004 = 64; - v4005800C = 17; - v9 = *(u8 *)v6; - *(u16 *)(v6 + 2) = 64; - *(u8 *)v6 = ((v9 | 3) & 0xFB | 4 * ((Fn1Sel | v6) & 1)) & 0xEF | 16 * ((Fn1Sel | v6) & 1) | 0x20; - *(u32 *)(v6 + 4) = Fn1Sel; - result = SdioHostChkCmdInhibitCMD(v6); - if ( !result ) - { - result = SdioHostChkDataLineActive(0); - if ( !result ) - { - Cmd.CmdFmt = (SDIO_HOST_CMD_FMT)((*(u8 *)&Cmd.CmdFmt & 0xF4 | 0x3A) & 0x3F); - v11 = *((u8 *)&Cmd.CmdFmt + 1); - v5[128] = 0; - *((u8 *)&Cmd.CmdFmt + 1) = v11 & 0xC0 | 6; - v5[129] = 0; - Cmd.Arg = v8 | 0xFFFFF0 | (v7 << 31); - SdioHostSendCmd(&Cmd); - result = SdioHostChkCmdComplete(v5, v12); - if ( !result ) - { - SdioHostGetResponse(v5, *(u8 *)&Cmd.CmdFmt & 3); - result = SdioHostChkXferComplete(v5, 0x1388u, v13); - if ( result ) - { - if ( result != 16 ) - { - if ( v40058032 & 0x200 ) - { - v40058032 = 512; - if ( HalSdioHostStopTransferRtl8195a(v5, v14) ) - { - DBG_SDIO_ERR("Stop transmission error!\n"); - } - } - } - result = 238; - } - } - } - } - } - return result; + *(u32 *) &Cmd.CmdFmt = Data; + Cmd.Arg = Mode; + v16 = Fn2Sel; + v5 = Data; + v6 = *((u32 *) Data + 4); + v7 = Mode; + v8 = Fn2Sel; + if (!v6 || ((u8) Fn1Sel | (u8) v6) & 3) { + result = 3; + } else { + v40058058 = v6; + v40058004 = 64; + v4005800C = 17; + v9 = *(u8 *) v6; + *(u16 *) (v6 + 2) = 64; + *(u8 *) v6 = ((v9 | 3) & 0xFB | 4 * ((Fn1Sel | v6) & 1)) & 0xEF + | 16 * ((Fn1Sel | v6) & 1) | 0x20; + *(u32 *) (v6 + 4) = Fn1Sel; + result = SdioHostChkCmdInhibitCMD(v6); + if (!result) { + result = SdioHostChkDataLineActive(0); + if (!result) { + Cmd.CmdFmt = (SDIO_HOST_CMD_FMT) ((*(u8 *) &Cmd.CmdFmt & 0xF4 + | 0x3A) & 0x3F); + v11 = *((u8 *) &Cmd.CmdFmt + 1); + v5[128] = 0; + *((u8 *) &Cmd.CmdFmt + 1) = v11 & 0xC0 | 6; + v5[129] = 0; + Cmd.Arg = v8 | 0xFFFFF0 | (v7 << 31); + SdioHostSendCmd(&Cmd); + result = SdioHostChkCmdComplete(v5, v12); + if (!result) { + SdioHostGetResponse(v5, *(u8 *) &Cmd.CmdFmt & 3); + result = SdioHostChkXferComplete(v5, 0x1388u, v13); + if (result) { + if (result != 16) { + if (v40058032 & 0x200) { + v40058032 = 512; + if (HalSdioHostStopTransferRtl8195a(v5, v14)) { + DBG_SDIO_ERR("Stop transmission error!\n"); + } + } + } + result = 238; + } + } + } + } + } + return result; } // 23D4: using guessed type int DiagPrintf(const char *, ...); //----- (00000E34) -------------------------------------------------------- -HAL_Status HalSdioHostGetCardStatusRtl8195a(IN VOID *Data) -{ - void *v3; // r4@1 - int result; // r0@2 - char v5; // r3@3 - uint32_t v6; // r1@3 - signed int v7; // r5@3 - unsigned int v8; // r3@7 - SDIO_HOST_CMD Cmd; // [sp+0h] [bp-18h]@1 - int v10; // [sp+8h] [bp-10h]@1 +HAL_Status HalSdioHostGetCardStatusRtl8195a(IN VOID *Data) { + void *v3; // r4@1 + int result; // r0@2 + char v5; // r3@3 + uint32_t v6; // r1@3 + signed int v7; // r5@3 + unsigned int v8; // r3@7 + SDIO_HOST_CMD Cmd; // [sp+0h] [bp-18h]@1 + int v10; // [sp+8h] [bp-10h]@1 - *(u32 *)&Cmd.CmdFmt = Data; - Cmd.Arg = a2; - v10 = a3; - v3 = Data; - if ( !Data ) - return 3; - result = SdioHostChkCmdInhibitCMD((uint32_t)Data); - if ( result ) return result; - Cmd.CmdFmt = (SDIO_HOST_CMD_FMT)((*(u8 *)&Cmd.CmdFmt & 0xF4 | 0x1A) & 0x1F); - v5 = *((u8 *)&Cmd.CmdFmt + 1); - *((u8 *)v3 + 128) = 0; - *((u8 *)&Cmd.CmdFmt + 1) = v5 & 0xC0 | 0xD; - Cmd.Arg = *((u16 *)v3 + 67) << 16; - SdioHostSendCmd(&Cmd); - v7 = SdioHostChkCmdComplete(v3, v6); - if ( v7 ) return v7; - SdioHostGetResponse(v3, *(u8 *)&Cmd.CmdFmt & 3); - if ( *((u8 *)v3 + 24) == 13 ) - { - v8 = *((u32 *)v3 + 5); - *((u32 *)v3 + 10) = v8; - *((u8 *)v3 + 131) = (v8 >> 9) & 0xF; - return v7; - } - DBG_SDIO_ERR("Command index error !!\n"); - return 238; + *(u32 *) &Cmd.CmdFmt = Data; + Cmd.Arg = a2; + v10 = a3; + v3 = Data; + if (!Data) + return 3; + result = SdioHostChkCmdInhibitCMD((uint32_t) Data); + if (result) + return result; + Cmd.CmdFmt = + (SDIO_HOST_CMD_FMT) ((*(u8 *) &Cmd.CmdFmt & 0xF4 | 0x1A) & 0x1F); + v5 = *((u8 *) &Cmd.CmdFmt + 1); + *((u8 *) v3 + 128) = 0; + *((u8 *) &Cmd.CmdFmt + 1) = v5 & 0xC0 | 0xD; + Cmd.Arg = *((u16 *) v3 + 67) << 16; + SdioHostSendCmd(&Cmd); + v7 = SdioHostChkCmdComplete(v3, v6); + if (v7) + return v7; + SdioHostGetResponse(v3, *(u8 *) &Cmd.CmdFmt & 3); + if (*((u8 *) v3 + 24) == 13) { + v8 = *((u32 *) v3 + 5); + *((u32 *) v3 + 10) = v8; + *((u8 *) v3 + 131) = (v8 >> 9) & 0xF; + return v7; + } + DBG_SDIO_ERR("Command index error !!\n"); + return 238; } // 23D4: using guessed type int DiagPrintf(const char *, ...); //----- (00000ED0) -------------------------------------------------------- -HAL_Status HalSdioHostInitCardRtl8195a(IN VOID *Data) -{ - u8 *v3; // r5@1 - int v4; // r0@2 - char v5; // r3@3 - uint32_t v6; // r1@3 - signed int v7; // r4@4 - const char *v8; // r0@6 - int v9; // r0@7 - uint32_t v10; // r1@8 - const char *v11; // r0@11 - int v12; // r3@12 - int v13; // r0@24 - char v14; // r3@25 - uint32_t v15; // r1@25 - signed int v16; // r0@26 - const char *v17; // r0@28 - char v18; // r3@34 - uint32_t v19; // r1@34 - signed int v20; // r0@35 - signed int v21; // r6@35 - u8 v22; // cf@36 - char v23; // r3@39 - uint32_t v24; // r1@39 - signed int v25; // r0@40 - const char *v26; // r0@42 - char v27; // r3@48 - uint32_t v28; // r1@48 - const char *v29; // r0@53 - uint32_t v30; // r0@64 - int v31; // r0@64 - char v32; // r3@65 - uint32_t v33; // r1@65 - int v34; // r0@70 - char v35; // r3@71 - uint32_t v36; // r1@71 - uint32_t v37; // r1@81 - int v38; // r2@81 - int v39; // r6@81 - int v40; // r1@82 - const char *v41; // r0@83 - int v42; // r0@87 - uint32_t v43; // r1@87 - int v44; // r2@87 - int v45; // r3@88 - uint32_t v46; // r1@88 - signed int v47; // r0@89 - const char *v48; // r0@91 - char v49; // r3@98 - uint32_t v50; // r1@98 - void *v52; // [sp+0h] [bp-20h]@1 - int v53; // [sp+4h] [bp-1Ch]@1 - int v54; // [sp+8h] [bp-18h]@1 +HAL_Status HalSdioHostInitCardRtl8195a(IN VOID *Data) { + u8 *v3; // r5@1 + int v4; // r0@2 + char v5; // r3@3 + uint32_t v6; // r1@3 + signed int v7; // r4@4 + const char *v8; // r0@6 + int v9; // r0@7 + uint32_t v10; // r1@8 + const char *v11; // r0@11 + int v12; // r3@12 + int v13; // r0@24 + char v14; // r3@25 + uint32_t v15; // r1@25 + signed int v16; // r0@26 + const char *v17; // r0@28 + char v18; // r3@34 + uint32_t v19; // r1@34 + signed int v20; // r0@35 + signed int v21; // r6@35 + u8 v22; // cf@36 + char v23; // r3@39 + uint32_t v24; // r1@39 + signed int v25; // r0@40 + const char *v26; // r0@42 + char v27; // r3@48 + uint32_t v28; // r1@48 + const char *v29; // r0@53 + uint32_t v30; // r0@64 + int v31; // r0@64 + char v32; // r3@65 + uint32_t v33; // r1@65 + int v34; // r0@70 + char v35; // r3@71 + uint32_t v36; // r1@71 + uint32_t v37; // r1@81 + int v38; // r2@81 + int v39; // r6@81 + int v40; // r1@82 + const char *v41; // r0@83 + int v42; // r0@87 + uint32_t v43; // r1@87 + int v44; // r2@87 + int v45; // r3@88 + uint32_t v46; // r1@88 + signed int v47; // r0@89 + const char *v48; // r0@91 + char v49; // r3@98 + uint32_t v50; // r1@98 + void *v52; // [sp+0h] [bp-20h]@1 + int v53; // [sp+4h] [bp-1Ch]@1 + int v54; // [sp+8h] [bp-18h]@1 - v52 = Data; - v53 = a2; - v54 = a3; - v3 = Data; - if ( !Data ) - { - v7 = 3; - goto LABEL_115; - } - v4 = SdioHostChkCmdInhibitCMD((uint32_t)Data); - if ( !v4 ) - { - v5 = (char)v52; - v3[128] = 0; - LOBYTE(v52) = v5 & 4; - v53 = 0; - BYTE1(v52) &= 0xC0u; - SdioHostSendCmd((SDIO_HOST_CMD *)&v52); - v4 = SdioHostChkCmdComplete(v3, v6); - } - v7 = v4; - if ( v4 ) - { - DBG_SDIO_ERR("Reset sd card fail !!\n"); - goto LABEL_104; - } - goto LABEL_115; - } - v9 = SdioHostChkCmdInhibitCMD(0); - if ( v9 - || (LOBYTE(v52) = (((u8)v52 & 0xF4 | 0x1A) & 0xDF | 32 * (v7 & 1)) & 0x3F | ((v7 & 3) << 6), - BYTE1(v52) = BYTE1(v52) & 0xC0 | 8, - v3[128] = v7, - v53 = 426, - SdioHostSendCmd((SDIO_HOST_CMD *)&v52), - (v9 = SdioHostChkCmdComplete(v3, v10)) != 0) ) - { - v7 = v9; - if ( v9 ) - goto LABEL_22; - } - else - { - SdioHostGetResponse(v3, (u8)v52 & 3); - if ( v3[24] != 8 ) - { - if ( ConfigDebugErr & 0x400 ) - { - v11 = "\r[SDIO Err]Command index error !!\n"); // DBG_SDIO_ERR(" -LABEL_18: - DiagPrintf(v11); - goto LABEL_21; - } - goto LABEL_21; - } - v12 = *((u32 *)v3 + 5); - if ( (u8)v12 != 170 ) - { - DBG_SDIO_ERR("Echo-back of check pattern: %X\n"); - goto LABEL_21; - } - v9 = v12 << 23; - if ( !(v12 & 0x100) ) - { - if ( ConfigDebugErr & 0x400 ) - { - v11 = "\r[SDIO Err]Voltage accepted error!\n"; - goto LABEL_18; - } -LABEL_21: - v7 = 238; -LABEL_22: - if ( ConfigDebugErr & 0x400 ) - { - v8 = "\r[SDIO Err]Voltage check fail !!\n"; - goto LABEL_104; - } - goto LABEL_115; - } - } - v13 = SdioHostChkCmdInhibitCMD(v9); - if ( v13 ) - goto LABEL_63; - LOBYTE(v52) = ((u8)v52 & 0xFC | 0x1A) & 0x1F; - v14 = BYTE1(v52) & 0xC0 | 0x37; - v3[128] = v7; - BYTE1(v52) = v14; - v53 = v7; - SdioHostSendCmd((SDIO_HOST_CMD *)&v52); - v13 = SdioHostChkCmdComplete(v3, v15); - if ( v13 ) - goto LABEL_63; - v16 = SdioHostGetResponse(v3, (u8)v52 & 3); - if ( v3[24] != 55 ) - { - if ( ConfigDebugErr & 0x400 ) // DBG_SDIO_ERR(" - { - v17 = "\r[SDIO Err]Command index error !!\n"; -LABEL_32: - DiagPrintf(v17); - goto LABEL_57; - } - goto LABEL_57; - } - if ( !(*((u32 *)v3 + 5) & 0x20) ) - { - if ( ConfigDebugErr & 0x400 ) - { - v17 = "\r[SDIO Err]ACMD isn't expected!\n"; - goto LABEL_32; - } -LABEL_57: - v7 = 238; - goto LABEL_60; - } - v13 = SdioHostChkCmdInhibitCMD(v16); - if ( v13 - || (LOBYTE(v52) = ((u8)v52 & 0xFC | 2) & 7, - v18 = BYTE1(v52) & 0xC0 | 0x29, - v3[128] = v7, - BYTE1(v52) = v18, - v53 = v7, - SdioHostSendCmd((SDIO_HOST_CMD *)&v52), - (v13 = SdioHostChkCmdComplete(v3, v19)) != 0) ) - { -LABEL_63: - v7 = v13; - if ( !v13 ) - goto LABEL_64; -LABEL_60: - if ( ConfigDebugErr & 0x400 ) - { - v8 = "\r[SDIO Err]Get OCR fail !!\n"; - goto LABEL_104; - } - goto LABEL_115; - } - v20 = SdioHostGetResponse(v3, (u8)v52 & 3); - v21 = 100; - *((u32 *)v3 + 9) = *((u32 *)v3 + 5) & 0xFFFFFF; - while ( 1 ) - { - v22 = __CFADD__(v21--, -1); - if ( !v22 ) - goto LABEL_51; - v13 = SdioHostChkCmdInhibitCMD(v20); - if ( v13 ) - goto LABEL_63; - LOBYTE(v52) = ((u8)v52 & 0xFC | 0x1A) & 0x1F; - v23 = BYTE1(v52); - v3[128] = 0; - v53 = 0; - BYTE1(v52) = v23 & 0xC0 | 0x37; - SdioHostSendCmd((SDIO_HOST_CMD *)&v52); - v13 = SdioHostChkCmdComplete(v3, v24); - if ( v13 ) - goto LABEL_63; - v25 = SdioHostGetResponse(v3, (u8)v52 & 3); - if ( v3[24] != 55 ) - { - if ( ConfigDebugErr & 0x400 ) - { - v26 = "\r[SDIO Err]Command index error !!\n"; -LABEL_46: - DiagPrintf(v26); - goto LABEL_62; - } - goto LABEL_62; - } - if ( !(*((u32 *)v3 + 5) & 0x20) ) - { - if ( ConfigDebugErr & 0x400 ) - { - v26 = "\r[SDIO Err]ACMD isn't expected!\n"; - goto LABEL_46; - } -LABEL_62: - v13 = 238; - goto LABEL_63; - } - v13 = SdioHostChkCmdInhibitCMD(v25); - if ( v13 ) - goto LABEL_63; - LOBYTE(v52) = ((u8)v52 & 0xFC | 2) & 7; - v27 = BYTE1(v52); - v3[128] = 0; - BYTE1(v52) = v27 & 0xC0 | 0x29; - v53 = 1077673984; - SdioHostSendCmd((SDIO_HOST_CMD *)&v52); - v13 = SdioHostChkCmdComplete(v3, v28); - if ( v13 ) - goto LABEL_63; - SdioHostGetResponse(v3, (u8)v52 & 3); - if ( *((u32 *)v3 + 5) < 0 ) - break; - v20 = HalDelayUs(10000); - } - if ( !v21 ) - { - v7 = 2; - goto LABEL_60; - } -LABEL_51: - if ( *((u32 *)v3 + 5) & 0x40000000 ) - { - v3[132] = 1; - if ( !(ConfigDebugInfo & 0x400) ) - goto LABEL_64; - v29 = "\r[SDIO Inf]This is a SDHC card\n"; - } - else - { - v3[132] = 0; - if ( !(ConfigDebugInfo & 0x400) ) - goto LABEL_64; - v29 = "\r[SDIO Inf]This is a SDSC card\n"; - } - DiagPrintf(v29); -LABEL_64: - v30 = HalDelayUs(20); - v31 = SdioHostChkCmdInhibitCMD(v30); - if ( v31 - || (LOBYTE(v52) = ((u8)v52 & 0xF4 | 9) & 0xF, - v32 = BYTE1(v52) & 0xC0 | 2, - v3[128] = v7, - BYTE1(v52) = v32, - v53 = v7, - SdioHostSendCmd((SDIO_HOST_CMD *)&v52), - (v31 = SdioHostChkCmdComplete(v3, v33)) != 0) ) - { - v7 = v31; - if ( !v31 ) - goto LABEL_70; - if ( ConfigDebugErr & 0x400 ) - { - v8 = "\r[SDIO Err]Get CID fail !!\n"; - goto LABEL_104; - } - goto LABEL_115; - } - v31 = SdioHostGetResponse(v3, (u8)v52 & 3); -LABEL_70: - v34 = SdioHostChkCmdInhibitCMD(v31); - if ( v34 - || (LOBYTE(v52) = ((u8)v52 & 0xF4 | 0x1A) & 0x1F, - v35 = BYTE1(v52) & 0xC0 | 3, - v3[128] = v7, - BYTE1(v52) = v35, - v53 = v7, - SdioHostSendCmd((SDIO_HOST_CMD *)&v52), - (v34 = SdioHostChkCmdComplete(v3, v36)) != 0) ) - { - v7 = v34; - if ( v34 ) - goto LABEL_79; - } - else - { - SdioHostGetResponse(v3, (u8)v52 & 3); - if ( v3[24] != 3 ) - { - if ( ConfigDebugErr & 0x400 ) - DiagPrintf("\r[SDIO Err]Command index error !!\n"); - v7 = 238; -LABEL_79: - if ( ConfigDebugErr & 0x400 ) - { - v8 = "\r[SDIO Err]Get RCA fail !!\n"; - goto LABEL_104; - } - goto LABEL_115; - } - *((u16 *)v3 + 67) = *((u16 *)v3 + 11); - } - SdioHostSdClkCtrl(v3, 1, 1); - v39 = SdioHostGetCSD(v3, v37); - if ( v39 ) - { - v40 = ConfigDebugErr << 21; - if ( ConfigDebugErr & 0x400 ) - { - v41 = "\r[SDIO Err]Get CSD fail !!\n"; - goto LABEL_108; - } -LABEL_113: - v7 = v39; - goto LABEL_115; - } - v39 = SdioHostCardSelection(v3, 1, v38); - if ( v39 ) - { - if ( !(ConfigDebugErr & 0x400) ) - goto LABEL_113; - v41 = "\r[SDIO Err]Select sd card fail !!\n"; -LABEL_108: - DiagPrintf(v41, v40); - goto LABEL_113; - } - v42 = SdioHostChkCmdInhibitCMD(0); - if ( v42 ) - goto LABEL_120; - LOBYTE(v52) = ((u8)v52 & 0xFC | 0x1A) & 0x1F; - BYTE1(v52) = BYTE1(v52) & 0xC0 | 0x37; - v45 = *((u16 *)v3 + 67) << 16; - v3[128] = v7; - v53 = v45; - SdioHostSendCmd((SDIO_HOST_CMD *)&v52); - v42 = SdioHostChkCmdComplete(v3, v46); - if ( v42 ) - goto LABEL_120; - v47 = SdioHostGetResponse(v3, (u8)v52 & 3); - if ( v3[24] != 55 ) - goto LABEL_90; - if ( !(*((u32 *)v3 + 5) & 0x20) ) - { - if ( ConfigDebugErr & 0x400 ) - { - v48 = "\r[SDIO Err]ACMD isn't expected!\n"; -LABEL_95: - DiagPrintf(v48); - } - goto LABEL_96; - } - v42 = SdioHostChkCmdInhibitCMD(v47); - if ( v42 - || (LOBYTE(v52) = ((u8)v52 & 0xFC | 0x1A) & 0x1F, - v49 = BYTE1(v52) & 0xC0 | 6, - v3[128] = v7, - BYTE1(v52) = v49, - v53 = 2, - SdioHostSendCmd((SDIO_HOST_CMD *)&v52), - (v42 = SdioHostChkCmdComplete(v3, v50)) != 0) ) - { -LABEL_120: - v7 = v42; - if ( v42 ) - goto LABEL_102; -LABEL_105: - v39 = HalSdioHostGetCardStatusRtl8195a(v3, v43, v44); - if ( v39 ) - { - v40 = ConfigDebugErr << 21; - if ( !(ConfigDebugErr & 0x400) ) - goto LABEL_113; - v41 = "\r[SDIO Err]Get sd card current state fail !!\n"; - goto LABEL_108; - } - if ( v3[131] != 4 ) - { - DBG_SDIO_ERR("The card isn't in TRANSFER state !! (Current state: %d)\n", - v3[131], - ConfigDebugErr << 21); - v7 = 238; - goto LABEL_115; - } - } - else - { - SdioHostGetResponse(v3, (u8)v52 & 3); - if ( v3[24] == 6 ) - { - v44 = v40058028 | 2; - v40058028 |= 2u; - goto LABEL_105; - } -LABEL_90: - if ( ConfigDebugErr & 0x400 ) - { - v48 = "\r[SDIO Err]Command index error !!\n"; - goto LABEL_95; - } -LABEL_96: - v7 = 238; -LABEL_102: - if ( ConfigDebugErr & 0x400 ) - { - v8 = "\r[SDIO Err]Set bus width fail !!\n"; -LABEL_104: - DiagPrintf(v8); - } -LABEL_115: - DBG_SDIO_ERR"SD card initialization FAIL !!\n"); - } - return v7; + v52 = Data; + v53 = a2; + v54 = a3; + v3 = Data; + if (!Data) { + v7 = 3; + goto LABEL_115; + }; + v4 = SdioHostChkCmdInhibitCMD((uint32_t) Data); + if (!v4) { + v5 = (char) v52; + v3[128] = 0; + LOBYTE (v52) = v5 & 4; + v53 = 0; + BYTE1(v52) &= 0xC0u; + SdioHostSendCmd((SDIO_HOST_CMD *) &v52); + v4 = SdioHostChkCmdComplete(v3, v6); + }; + v7 = v4; + if (v4) { + DBG_SDIO_ERR("Reset sd card fail !!\n"); + goto LABEL_104; + }; + goto LABEL_115; + + v9 = SdioHostChkCmdInhibitCMD(0); + if (v9 + || (LOBYTE(v52) = (((u8) v52 & 0xF4 | 0x1A) & 0xDF | 32 * (v7 & 1)) + & 0x3F | ((v7 & 3) << 6), BYTE1(v52) = BYTE1(v52) & 0xC0 + | 8, v3[128] = v7, v53 = 426, SdioHostSendCmd( + (SDIO_HOST_CMD *) &v52), (v9 = SdioHostChkCmdComplete(v3, + v10)) != 0)) { + v7 = v9; + if (v9) + goto LABEL_22; + } else { + SdioHostGetResponse(v3, (u8) v52 & 3); + if (v3[24] != 8) { + if (ConfigDebugErr & 0x400) { + v11 = "\r[SDIO Err]Command index error !!\n" + ); // DBG_SDIO_ERR(" + LABEL_18: DiagPrintf(v11); + goto LABEL_21; + } + goto LABEL_21; + } + v12 = *((u32 *) v3 + 5); + if ((u8) v12 != 170) { + DBG_SDIO_ERR("Echo-back of check pattern: %X\n"); + goto LABEL_21; + } + v9 = v12 << 23; + if (!(v12 & 0x100)) { + if (ConfigDebugErr & 0x400) { + v11 = "\r[SDIO Err]Voltage accepted error!\n"; + goto LABEL_18; + } + LABEL_21: v7 = 238; + LABEL_22: if (ConfigDebugErr & 0x400) { + v8 = "\r[SDIO Err]Voltage check fail !!\n"; + goto LABEL_104; + } + goto LABEL_115; + } + } + v13 = SdioHostChkCmdInhibitCMD(v9); + if (v13) + goto LABEL_63; + LOBYTE (v52) = ((u8) v52 & 0xFC | 0x1A) & 0x1F; + v14 = BYTE1(v52) & 0xC0 | 0x37; + v3[128] = v7; + BYTE1 (v52) = v14; + v53 = v7; + SdioHostSendCmd((SDIO_HOST_CMD *) &v52); + v13 = SdioHostChkCmdComplete(v3, v15); + if (v13) + goto LABEL_63; + v16 = SdioHostGetResponse(v3, (u8) v52 & 3); + if (v3[24] != 55) { + if (ConfigDebugErr & 0x400) // DBG_SDIO_ERR(" + { + v17 = "\r[SDIO Err]Command index error !!\n"; + LABEL_32: DiagPrintf(v17); + goto LABEL_57; + } + goto LABEL_57; + }; + if (!(*((u32 *) v3 + 5) & 0x20)) { + if (ConfigDebugErr & 0x400) { + v17 = "\r[SDIO Err]ACMD isn't expected!\n"; + goto LABEL_32; + } + LABEL_57: v7 = 238; + goto LABEL_60; + }; + v13 = SdioHostChkCmdInhibitCMD(v16); + if (v13 + || (LOBYTE(v52) = ((u8) v52 & 0xFC | 2) & 7, v18 = BYTE1(v52) & 0xC0 + | 0x29, v3[128] = v7, BYTE1(v52) = v18, v53 = v7, SdioHostSendCmd( + (SDIO_HOST_CMD *) &v52), (v13 = SdioHostChkCmdComplete(v3, + v19)) != 0)) { + LABEL_63: v7 = v13; + if (!v13) + goto LABEL_64; + LABEL_60: if (ConfigDebugErr & 0x400) { + v8 = "\r[SDIO Err]Get OCR fail !!\n"; + goto LABEL_104; + } + goto LABEL_115; + } + v20 = SdioHostGetResponse(v3, (u8) v52 & 3); + v21 = 100; + *((u32 *) v3 + 9) = *((u32 *) v3 + 5) & 0xFFFFFF; + while (1) { + v22 = __CFADD__(v21--, -1); + if (!v22) + goto LABEL_51; + v13 = SdioHostChkCmdInhibitCMD(v20); + if (v13) + goto LABEL_63; + LOBYTE (v52) = ((u8) v52 & 0xFC | 0x1A) & 0x1F; + v23 = BYTE1(v52); + v3[128] = 0; + v53 = 0; + BYTE1 (v52) = v23 & 0xC0 | 0x37; + SdioHostSendCmd((SDIO_HOST_CMD *) &v52); + v13 = SdioHostChkCmdComplete(v3, v24); + if (v13) + goto LABEL_63; + v25 = SdioHostGetResponse(v3, (u8) v52 & 3); + if (v3[24] != 55) { + if (ConfigDebugErr & 0x400) { + v26 = "\r[SDIO Err]Command index error !!\n"; + LABEL_46: DiagPrintf(v26); + goto LABEL_62; + } + goto LABEL_62; + } + if (!(*((u32 *) v3 + 5) & 0x20)) { + if (ConfigDebugErr & 0x400) { + v26 = "\r[SDIO Err]ACMD isn't expected!\n"; + goto LABEL_46; + } + LABEL_62: v13 = 238; + goto LABEL_63; + } + v13 = SdioHostChkCmdInhibitCMD(v25); + if (v13) + goto LABEL_63; + LOBYTE (v52) = ((u8) v52 & 0xFC | 2) & 7; + v27 = BYTE1(v52); + v3[128] = 0; + BYTE1 (v52) = v27 & 0xC0 | 0x29; + v53 = 1077673984; + SdioHostSendCmd((SDIO_HOST_CMD *) &v52); + v13 = SdioHostChkCmdComplete(v3, v28); + if (v13) + goto LABEL_63; + SdioHostGetResponse(v3, (u8) v52 & 3); + if (*((u32 *) v3 + 5) < 0) + break; + v20 = HalDelayUs(10000); + }; + if (!v21) { + v7 = 2; + goto LABEL_60; + }; + LABEL_51: if (*((u32 *) v3 + 5) & 0x40000000) { + v3[132] = 1; + if (!(ConfigDebugInfo & 0x400)) + goto LABEL_64; + v29 = "\r[SDIO Inf]This is a SDHC card\n"; + } else { + v3[132] = 0; + if (!(ConfigDebugInfo & 0x400)) + goto LABEL_64; + v29 = "\r[SDIO Inf]This is a SDSC card\n"; + } + DiagPrintf(v29); + LABEL_64: v30 = HalDelayUs(20); + v31 = SdioHostChkCmdInhibitCMD(v30); + if (v31 + || (LOBYTE(v52) = ((u8) v52 & 0xF4 | 9) & 0xF, v32 = BYTE1(v52) + & 0xC0 | 2, v3[128] = v7, BYTE1(v52) = v32, v53 = v7, SdioHostSendCmd( + (SDIO_HOST_CMD *) &v52), (v31 = SdioHostChkCmdComplete(v3, + v33)) != 0)) { + v7 = v31; + if (!v31) + goto LABEL_70; + if (ConfigDebugErr & 0x400) { + v8 = "\r[SDIO Err]Get CID fail !!\n"; + goto LABEL_104; + } + goto LABEL_115; + } + v31 = SdioHostGetResponse(v3, (u8) v52 & 3); + LABEL_70: v34 = SdioHostChkCmdInhibitCMD(v31); + if (v34 + || (LOBYTE(v52) = ((u8) v52 & 0xF4 | 0x1A) & 0x1F, v35 = BYTE1(v52) + & 0xC0 | 3, v3[128] = v7, BYTE1(v52) = v35, v53 = v7, SdioHostSendCmd( + (SDIO_HOST_CMD *) &v52), (v34 = SdioHostChkCmdComplete(v3, + v36)) != 0)) { + v7 = v34; + if (v34) + goto LABEL_79; + } else { + SdioHostGetResponse(v3, (u8) v52 & 3); + if (v3[24] != 3) { + if (ConfigDebugErr & 0x400) + DiagPrintf("\r[SDIO Err]Command index error !!\n"); + v7 = 238; + LABEL_79: if (ConfigDebugErr & 0x400) { + v8 = "\r[SDIO Err]Get RCA fail !!\n"; + goto LABEL_104; + } + goto LABEL_115; + } + *((u16 *) v3 + 67) = *((u16 *) v3 + 11); + } + SdioHostSdClkCtrl(v3, 1, BASE_CLK_DIVIDED_BY_2); + v39 = SdioHostGetCSD(v3, v37); + if (v39) { + v40 = ConfigDebugErr << 21; + if (ConfigDebugErr & 0x400) { + v41 = "\r[SDIO Err]Get CSD fail !!\n"; + goto LABEL_108; + } + LABEL_113: v7 = v39; + goto LABEL_115; + } + v39 = SdioHostCardSelection(v3, 1, v38); + if (v39) { + if (!(ConfigDebugErr & 0x400)) + goto LABEL_113; + v41 = "\r[SDIO Err]Select sd card fail !!\n"; + LABEL_108: DiagPrintf(v41, v40); + goto LABEL_113; + } + v42 = SdioHostChkCmdInhibitCMD(0); + if (v42) + goto LABEL_120; + LOBYTE (v52) = ((u8) v52 & 0xFC | 0x1A) & 0x1F; + BYTE1 (v52) = BYTE1(v52) & 0xC0 | 0x37; + v45 = *((u16 *) v3 + 67) << 16; + v3[128] = v7; + v53 = v45; + SdioHostSendCmd((SDIO_HOST_CMD *) &v52); + v42 = SdioHostChkCmdComplete(v3, v46); + if (v42) + goto LABEL_120; + v47 = SdioHostGetResponse(v3, (u8) v52 & 3); + if (v3[24] != 55) + goto LABEL_90; + if (!(*((u32 *) v3 + 5) & 0x20)) { + if (ConfigDebugErr & 0x400) { + v48 = "\r[SDIO Err]ACMD isn't expected!\n"; + LABEL_95: DiagPrintf(v48); + } + goto LABEL_96; + } + v42 = SdioHostChkCmdInhibitCMD(v47); + if (v42 + || (LOBYTE(v52) = ((u8) v52 & 0xFC | 0x1A) & 0x1F, v49 = BYTE1(v52) + & 0xC0 | 6, v3[128] = v7, BYTE1(v52) = v49, v53 = 2, SdioHostSendCmd( + (SDIO_HOST_CMD *) &v52), (v42 = SdioHostChkCmdComplete(v3, + v50)) != 0)) { + LABEL_120: v7 = v42; + if (v42) + goto LABEL_102; + LABEL_105: v39 = HalSdioHostGetCardStatusRtl8195a(v3, v43, v44); + if (v39) { + v40 = ConfigDebugErr << 21; + if (!(ConfigDebugErr & 0x400)) + goto LABEL_113; + v41 = "\r[SDIO Err]Get sd card current state fail !!\n"; + goto LABEL_108; + } + if (v3[131] != 4) { + DBG_SDIO_ERR( + "The card isn't in TRANSFER state !! (Current state: %d)\n", + v3[131], ConfigDebugErr << 21); + v7 = 238; + goto LABEL_115; + } + } else { + SdioHostGetResponse(v3, (u8) v52 & 3); + if (v3[24] == 6) { + v44 = v40058028 | 2; + v40058028 |= 2u; + goto LABEL_105; + } + LABEL_90: if (ConfigDebugErr & 0x400) { + v48 = "\r[SDIO Err]Command index error !!\n"; + goto LABEL_95; + } + LABEL_96: v7 = 238; + LABEL_102: if (ConfigDebugErr & 0x400) { + v8 = "\r[SDIO Err]Set bus width fail !!\n"; + LABEL_104: DiagPrintf(v8); + } + LABEL_115: + DBG_SDIO_ERR("SD card initialization FAIL !!\n"); + } + return v7; } // 23D4: using guessed type int DiagPrintf(const char *, ...); // 23F0: using guessed type int HalDelayUs(u32); //----- (000014E8) -------------------------------------------------------- -HAL_Status HalSdioHostGetSdStatusRtl8195a(IN VOID *Data) -{ - int v3; // r3@1 - char *v4; // r4@1 - char v5; // r0@3 - int v6; // r0@3 - int result; // r0@3 - int v8; // r3@4 - uint32_t v9; // r1@4 - const char *v10; // r0@7 - int v11; // r3@8 - char v12; // r3@13 - uint32_t v13; // r1@13 - signed int v14; // r2@14 - signed int v15; // r0@14 - uint32_t v16; // r1@14 - SDIO_HOST_CMD Cmd; // [sp+0h] [bp-18h]@1 - int v18; // [sp+8h] [bp-10h]@1 +HAL_Status HalSdioHostGetSdStatusRtl8195a(IN VOID *Data) { + int v3; // r3@1 + char *v4; // r4@1 + char v5; // r0@3 + int v6; // r0@3 + int result; // r0@3 + int v8; // r3@4 + uint32_t v9; // r1@4 + const char *v10; // r0@7 + int v11; // r3@8 + char v12; // r3@13 + uint32_t v13; // r1@13 + signed int v14; // r2@14 + signed int v15; // r0@14 + uint32_t v16; // r1@14 + SDIO_HOST_CMD Cmd; // [sp+0h] [bp-18h]@1 + int v18; // [sp+8h] [bp-10h]@1 - v3 = *((u32 *)Data + 4); - *(u32 *)&Cmd.CmdFmt = Data; - Cmd.Arg = a2; - v18 = a3; - v4 = (char *)Data; - if ( !v3 || v3 & 3 ) - { - result = 3; - } - else - { - v40058058 = v3; - v40058004 = 64; - v4005800C = 17; - v5 = *(u8 *)v3; - *(u16 *)(v3 + 2) = 64; - v6 = (u8)((v5 | 3) & 0xEB) | 0x20; - *(u8 *)v3 = v6; - *(u32 *)(v3 + 4) = v4 + 48; - result = SdioHostChkCmdInhibitCMD(v6); - if ( !result ) - { - Cmd.CmdFmt = (SDIO_HOST_CMD_FMT)((*(u8 *)&Cmd.CmdFmt & 0xFC | 0x1A) & 0x1F); - *((u8 *)&Cmd.CmdFmt + 1) = *((u8 *)&Cmd.CmdFmt + 1) & 0xC0 | 0x37; - v8 = *((u16 *)v4 + 67); - v4[128] = 0; - Cmd.Arg = v8 << 16; - SdioHostSendCmd(&Cmd); - result = SdioHostChkCmdComplete(v4, v9); - if ( !result ) - { - SdioHostGetResponse(v4, *(u8 *)&Cmd.CmdFmt & 3); - if ( v4[24] != 55 ) - { - if ( ConfigDebugErr & 0x400 ) - { - v10 = "\r[SDIO Err]Command index error !!\n"; -LABEL_20: - DiagPrintf(v10); - return 238; - } - return 238; - } - v11 = *((u32 *)v4 + 5); - if ( !(v11 & 0x20) ) - { - if ( ConfigDebugErr & 0x400 ) - { - v10 = "\r[SDIO Err]ACMD isn't expected!\n"; - goto LABEL_20; - } - return 238; - } - result = SdioHostChkCmdInhibitCMD(*((u32 *)v4 + 5) << 26); - if ( !result ) - { - result = SdioHostChkDataLineActive(0); - if ( !result ) - { - Cmd.CmdFmt = (SDIO_HOST_CMD_FMT)((*(u8 *)&Cmd.CmdFmt & 0xFC | 0x3A) & 0x3F); - v12 = *((u8 *)&Cmd.CmdFmt + 1); - v4[128] = 0; - v4[129] = 0; - Cmd.Arg = 0; - *((u8 *)&Cmd.CmdFmt + 1) = v12 & 0xC0 | 0xD; - SdioHostSendCmd(&Cmd); - result = SdioHostChkCmdComplete(v4, v13); - if ( !result ) - { - SdioHostGetResponse(v4, *(u8 *)&Cmd.CmdFmt & 3); - v15 = SdioHostChkXferComplete(v4, 0x1388u, v14); - if ( v15 ) - { - if ( v15 == 16 ) - return 238; - if ( !(v40058032 & 0x200) ) - return 238; - v40058032 = 512; - if ( !HalSdioHostStopTransferRtl8195a(v4, v16) || !(ConfigDebugErr & 0x400) ) - return 238; - v10 = "\r[SDIO Err]Stop transmission error!\n"; - goto LABEL_20; - } - result = 0; - } - } - } - } - } - } - return result; + v3 = *((u32 *) Data + 4); + *(u32 *) &Cmd.CmdFmt = Data; + Cmd.Arg = a2; + v18 = a3; + v4 = (char *) Data; + if (!v3 || v3 & 3) { + result = 3; + } else { + v40058058 = v3; + v40058004 = 64; + v4005800C = 17; + v5 = *(u8 *) v3; + *(u16 *) (v3 + 2) = 64; + v6 = (u8) ((v5 | 3) & 0xEB) | 0x20; + *(u8 *) v3 = v6; + *(u32 *) (v3 + 4) = v4 + 48; + result = SdioHostChkCmdInhibitCMD(v6); + if (!result) { + Cmd.CmdFmt = + (SDIO_HOST_CMD_FMT) ((*(u8 *) &Cmd.CmdFmt & 0xFC | 0x1A) + & 0x1F); + *((u8 *) &Cmd.CmdFmt + 1) = *((u8 *) &Cmd.CmdFmt + 1) & 0xC0 | 0x37; + v8 = *((u16 *) v4 + 67); + v4[128] = 0; + Cmd.Arg = v8 << 16; + SdioHostSendCmd(&Cmd); + result = SdioHostChkCmdComplete(v4, v9); + if (!result) { + SdioHostGetResponse(v4, *(u8 *) &Cmd.CmdFmt & 3); + if (v4[24] != 55) { + if (ConfigDebugErr & 0x400) { + v10 = "\r[SDIO Err]Command index error !!\n"; + LABEL_20: DiagPrintf(v10); + return 238; + } + return 238; + } + v11 = *((u32 *) v4 + 5); + if (!(v11 & 0x20)) { + if (ConfigDebugErr & 0x400) { + v10 = "\r[SDIO Err]ACMD isn't expected!\n"; + goto LABEL_20; + } + return 238; + } + result = SdioHostChkCmdInhibitCMD(*((u32 *) v4 + 5) << 26); + if (!result) { + result = SdioHostChkDataLineActive(0); + if (!result) { + Cmd.CmdFmt = (SDIO_HOST_CMD_FMT) ((*(u8 *) &Cmd.CmdFmt + & 0xFC | 0x3A) & 0x3F); + v12 = *((u8 *) &Cmd.CmdFmt + 1); + v4[128] = 0; + v4[129] = 0; + Cmd.Arg = 0; + *((u8 *) &Cmd.CmdFmt + 1) = v12 & 0xC0 | 0xD; + SdioHostSendCmd(&Cmd); + result = SdioHostChkCmdComplete(v4, v13); + if (!result) { + SdioHostGetResponse(v4, *(u8 *) &Cmd.CmdFmt & 3); + v15 = SdioHostChkXferComplete(v4, 0x1388u, v14); + if (v15) { + if (v15 == 16) + return 238; + if (!(v40058032 & 0x200)) + return 238; + v40058032 = 512; + if (!HalSdioHostStopTransferRtl8195a(v4, v16) + || !(ConfigDebugErr & 0x400)) + return 238; + v10 = "\r[SDIO Err]Stop transmission error!\n"; + goto LABEL_20; + } + result = 0; + } + } + } + } + } + } + return result; } // 23D4: using guessed type int DiagPrintf(const char *, ...); //----- (00001668) -------------------------------------------------------- -HAL_Status HalSdioHostChangeSdClockRtl8195a(IN VOID *Data, IN u8 Frequency) -{ - u8 *v2; // r5@1 - int v3; // r4@6 - int v4; // r2@8 - int v5; // r0@10 - int v6; // r0@10 - char v7; // r3@11 - uint32_t v8; // r1@11 - signed int v9; // r0@12 - const char *v10; // r0@14 - char v11; // r3@22 - uint32_t v12; // r1@22 - signed int v13; // r2@23 - signed int v14; // r0@23 - uint32_t v15; // r1@25 - int v16; // r0@32 - int v17; // r0@34 - int v18; // r0@36 - const char *v19; // r0@40 - int v20; // r2@52 - char v22; // [sp+0h] [bp-58h]@11 - char v23; // [sp+1h] [bp-57h]@11 - int v24; // [sp+4h] [bp-54h]@11 - uint8_t StatusData[64]; // [sp+8h] [bp-50h]@8 +HAL_Status HalSdioHostChangeSdClockRtl8195a(IN VOID *Data, IN u8 Frequency) { + PHAL_SDIO_HOST_ADAPTER v2 /*pSdioHostAdapter*/= + (PHAL_SDIO_HOST_ADAPTER) Data; + u8 * v2; // r5@1 + int v3; // r4@6 + int v4; // r2@8 + int v5; // r0@10 + int v6; // r0@10 + char v7; // r3@11 + uint32_t v8; // r1@11 + signed int v9; // r0@12 + const char *v10; // r0@14 + char v11; // r3@22 + uint32_t v12; // r1@22 + signed int v13; // r2@23 + signed int v14; // r0@23 + uint32_t v15; // r1@25 + int v16; // r0@32 + int v17; // r0@34 + int v18; // r0@36 + const char *v19; // r0@40 + int v20; // r2@52 + char v22; // [sp+0h] [bp-58h]@11 + char v23; // [sp+1h] [bp-57h]@11 + int v24; // [sp+4h] [bp-54h]@11 + uint8_t StatusData[64]; // [sp+8h] [bp-50h]@8 - v2 = Data; - if ( !Data || (unsigned int)(Frequency - 5) > 3 ) - return 3; - if ( *((u8 *)Data + 133) == Frequency ) - { - DBG_SDIO_WARN("Current SDCLK frequency is already the specified value...\n"); - return 0; - } - if ( Frequency != 8 ) - { - if ( Frequency == 6 ) - { - v20 = 2; - } - else if ( Frequency == 7 ) - { - v20 = 1; - } - else - { - if ( Frequency != 5 ) - { - DBG_SDIO_ERR("Unsupported SDCLK frequency !!\n"); - v3 = 3; - goto LABEL_60; - } - v20 = 4; - } - v3 = SdioHostSdClkCtrl(Data, 1, v20); - if ( !v3 ) - return 0; -LABEL_60: - if ( !(ConfigDebugErr & 0x400) ) - return v3; - v19 = "\r[SDIO Err]Host changes clock fail !!\n"; // DBG_SDIO_ERR(" - goto LABEL_62; - } - v4 = *((u32 *)Data + 4); - *(u32 *)StatusData = 0; - *(u32 *)&StatusData[4] = 0; - if ( !v4 || v4 & 3 ) - return 3; - v40058058 = v4; - v40058004 = 8; - v4005800C = 17; - v5 = (u8)((*(u8 *)v4 | 3) & 0xEB) | 0x20; - *(u8 *)v4 = v5; - *(u16 *)(v4 + 2) = 8; - *(u32 *)(v4 + 4) = StatusData; - v6 = SdioHostChkCmdInhibitCMD(v5); - if ( v6 ) - goto LABEL_70; - v22 = (v22 & 0xF4 | 0x1A) & 0x1F; - v7 = v23; - v2[128] = 0; - v23 = v7 & 0xC0 | 0x37; - v24 = *((u16 *)v2 + 67) << 16; - SdioHostSendCmd((SDIO_HOST_CMD *)&v22); - v6 = SdioHostChkCmdComplete(v2, v8); - if ( v6 ) - goto LABEL_70; - v9 = SdioHostGetResponse(v2, v22 & 3); - if ( v2[24] != 55 ) - { - if ( !(ConfigDebugErr & 0x400) ) - return 238; - v10 = "\r[SDIO Err]Command index error !!\n"; -LABEL_15: - DiagPrintf(v10); - return 238; - } - if ( !(*((u32 *)v2 + 5) & 0x20) ) - { - if ( !(ConfigDebugErr & 0x400) ) - return 238; - v10 = "\r[SDIO Err]ACMD isn't expected!\n"; - goto LABEL_15; - } - v6 = SdioHostChkCmdInhibitCMD(v9); - if ( v6 - || (v6 = SdioHostChkDataLineActive(0)) != 0 - || (v22 = (v22 & 0xF4 | 0x3A) & 0x3F, - v11 = v23, - v2[128] = 0, - v2[129] = 0, - v24 = 0, - v23 = v11 & 0xC0 | 0x33, - SdioHostSendCmd((SDIO_HOST_CMD *)&v22), - (v6 = SdioHostChkCmdComplete(v2, v12)) != 0) ) - { -LABEL_70: - v3 = v6; - if ( v6 ) - return v3; - } - else - { - SdioHostGetResponse(v2, v22 & 3); - v14 = SdioHostChkXferComplete(v2, 0x1388u, v13); - if ( v14 ) - { - if ( v14 == 16 ) - return 238; - v15 = v40058032 << 22; - if ( !(v40058032 & 0x200) ) - return 238; - v40058032 = 512; - if ( !HalSdioHostStopTransferRtl8195a(v2, v15) || !(ConfigDebugErr & 0x400) ) - return 238; - v10 = "\r[SDIO Err]Stop transmission error!\n"; - goto LABEL_15; - } - v3 = 0; - *((u16 *)v2 + 68) = StatusData[0] & 0xF; - } - if ( *((u16 *)v2 + 68) ) - { - v16 = SdioHostSwitchFunction(v2, 0, 15, (int)StatusData, *(uint8_t **)&v22); - if ( v16 ) - return v16; - if ( StatusData[13] & 2 ) - { - v17 = SdioHostSwitchFunction(v2, v16, 1, (int)StatusData, *(uint8_t **)&v22); - if ( v17 ) - return v17; - if ( (StatusData[16] & 0xF) != 1 ) - { - if ( !(ConfigDebugErr & 0x400) ) - return 238; - v10 = "\r[SDIO Err]\"High-Speed\" can't be switched !!\n"; - goto LABEL_15; - } - v18 = SdioHostSwitchFunction(v2, 1, 1, (int)StatusData, *(uint8_t **)&v22); - if ( v18 ) - return v18; - if ( (StatusData[16] & 0xF) != 1 ) - { - if ( !(ConfigDebugErr & 0x400) ) - return 238; - v10 = "\r[SDIO Err]Card changes to High-Speed fail !!\n"; - goto LABEL_15; - } - v3 = SdioHostSdClkCtrl(v2, 1, v18); - if ( v3 ) - { - if ( !(ConfigDebugErr & 0x400) ) - return v3; - v19 = "\r[SDIO Err]Host changes to High-Speed fail !!\n"; -LABEL_62: - DiagPrintf(v19); - return v3; - } - } - else if ( ConfigDebugInfo & 0x400 ) - { - // DBG_SDIO_WARN(" - v19 = "\r[SDIO Inf]This card doesn't support \"High-Speed Function\" and can't change to high-speed...\n"; - goto LABEL_62; - } - } - else if ( ConfigDebugInfo & 0x400 ) - { - v19 = "\r[SDIO Inf]This card doesn't support CMD6 and can't change to high-speed...\n"; - goto LABEL_62; - } - return 0; + v2 = Data; + if (!Data || (unsigned int) (Frequency - 5) > 3) + return 3; + if (v2.CurrSdClk == Frequency) { + DBG_SDIO_WARN( + "Current SDCLK frequency is already the specified value...\n"); + return 0; + } + if (Frequency != SD_CLK_41_6MHZ) { // SD_CLK_41_6MHZ + if (Frequency == SD_CLK_10_4MHZ) // SD_CLK_10_4MHZ + v20 = BASE_CLK_DIVIDED_BY_4; + else if (Frequency == SD_CLK_20_8MHZ) // SD_CLK_20_8MHZ + v20 = BASE_CLK_DIVIDED_BY_2; + else if (Frequency != SD_CLK_5_2MHZ) { // SD_CLK_5_2MHZ + DBG_SDIO_ERR("Unsupported SDCLK frequency !!\n"); + v3 = 3; + goto LABEL_60; + } + v20 = BASE_CLK_DIVIDED_BY_8; + } + v3 = SdioHostSdClkCtrl(Data, 1, v20); + if (!v3) + return 0; + LABEL_60: if (!(ConfigDebugErr & 0x400)) { + return v3; + v19 = "\r[SDIO Err]Host changes clock fail !!\n"; // DBG_SDIO_ERR(" + goto LABEL_62; + } + v4 = *((u32 *) Data + 4); + *(u32 *) StatusData = 0; + *(u32 *) &StatusData[4] = 0; + if (!v4 || v4 & 3) + return 3; + v40058058 = v4; + v40058004 = 8; + v4005800C = 17; + v5 = (u8) ((*(u8 *) v4 | 3) & 0xEB) | 0x20; + *(u8 *) v4 = v5; + *(u16 *) (v4 + 2) = 8; + *(u32 *) (v4 + 4) = StatusData; + v6 = SdioHostChkCmdInhibitCMD(v5); + if (v6) + goto LABEL_70; + v22 = (v22 & 0xF4 | 0x1A) & 0x1F; + v7 = v23; + v2[128] = 0; + v23 = v7 & 0xC0 | 0x37; + v24 = *((u16 *) v2 + 67) << 16; + SdioHostSendCmd((SDIO_HOST_CMD *) &v22); + v6 = SdioHostChkCmdComplete(v2, v8); + if (v6) + goto LABEL_70; + v9 = SdioHostGetResponse(v2, v22 & 3); + if (v2[24] != 55) { + if (!(ConfigDebugErr & 0x400)) + return 238; + v10 = "\r[SDIO Err]Command index error !!\n"; + LABEL_15: DiagPrintf(v10); + return 238; + } + if (!(*((u32 *) v2 + 5) & 0x20)) { + if (!(ConfigDebugErr & 0x400)) + return 238; + v10 = "\r[SDIO Err]ACMD isn't expected!\n"; + goto LABEL_15; + } + v6 = SdioHostChkCmdInhibitCMD(v9); + if (v6 || (v6 = SdioHostChkDataLineActive(0)) != 0 + || (v22 = (v22 & 0xF4 | 0x3A) & 0x3F, v11 = v23, v2[128] = 0, v2[129] = + 0, v24 = 0, v23 = v11 & 0xC0 | 0x33, SdioHostSendCmd( + (SDIO_HOST_CMD *) &v22), (v6 = SdioHostChkCmdComplete(v2, + v12)) != 0)) { + LABEL_70: v3 = v6; + if (v6) + return v3; + } else { + SdioHostGetResponse(v2, v22 & 3); + v14 = SdioHostChkXferComplete(v2, 0x1388u, v13); + if (v14) { + if (v14 == 16) + return 238; + v15 = v40058032 << 22; + if (!(v40058032 & 0x200)) + return 238; + v40058032 = 512; + if (!HalSdioHostStopTransferRtl8195a(v2, v15) + || !(ConfigDebugErr & 0x400)) + return 238; + v10 = "\r[SDIO Err]Stop transmission error!\n"; + goto LABEL_15; + } + v3 = 0; + *((u16 *) v2 + 68) = StatusData[0] & 0xF; + } + if (*((u16 *) v2 + 68)) { + v16 = SdioHostSwitchFunction(v2, 0, 15, (int) StatusData, + *(uint8_t **) &v22); + if (v16) + return v16; + if (StatusData[13] & 2) { + v17 = SdioHostSwitchFunction(v2, v16, 1, (int) StatusData, + *(uint8_t **) &v22); + if (v17) + return v17; + if ((StatusData[16] & 0xF) != 1) { + if (!(ConfigDebugErr & 0x400)) + return 238; + v10 = "\r[SDIO Err]\"High-Speed\" can't be switched !!\n"; + goto LABEL_15; + } + v18 = SdioHostSwitchFunction(v2, 1, 1, (int) StatusData, + *(uint8_t **) &v22); + if (v18) + return v18; + if ((StatusData[16] & 0xF) != 1) { + if (!(ConfigDebugErr & 0x400)) + return 238; + v10 = "\r[SDIO Err]Card changes to High-Speed fail !!\n"; + goto LABEL_15; + } + v3 = SdioHostSdClkCtrl(v2, 1, v18); + if (v3) { + if (!(ConfigDebugErr & 0x400)) + return v3; + v19 = "\r[SDIO Err]Host changes to High-Speed fail !!\n"; + LABEL_62: DiagPrintf(v19); + return v3; + } + } else if (ConfigDebugInfo & 0x400) { +// DBG_SDIO_WARN(" + v19 = + "\r[SDIO Inf]This card doesn't support \"High-Speed Function\" and can't change to high-speed...\n"; + goto LABEL_62; + } + } else if (ConfigDebugInfo & 0x400) { + v19 = + "\r[SDIO Inf]This card doesn't support CMD6 and can't change to high-speed...\n"; + goto LABEL_62; + } + return 0; } // 23D4: using guessed type int DiagPrintf(const char *, ...); //----- (0000194C) -------------------------------------------------------- -HAL_Status HalSdioHostEraseRtl8195a(IN VOID *Data, IN u64 StartAddr, IN u64 EndAddr) -{ - uint32_t v3; // r4@1 - uint32_t v4; // r6@1 - int v5; // r8@1 - int result; // r0@4 - char v7; // r3@5 - uint32_t v8; // r1@5 - signed int v9; // r0@6 - char v10; // r3@11 - uint32_t v11; // r1@11 - signed int v12; // r0@12 - char v13; // r3@15 - uint32_t v14; // r1@15 - signed int v15; // r2@15 - SDIO_HOST_CMD v16; // [sp+0h] [bp-20h]@1 +HAL_Status HalSdioHostEraseRtl8195a(IN VOID *Data, IN u64 StartAddr, +IN u64 EndAddr) { + uint32_t v3; // r4@1 + uint32_t v4; // r6@1 + int v5; // r8@1 + int result; // r0@4 + char v7; // r3@5 + uint32_t v8; // r1@5 + signed int v9; // r0@6 + char v10; // r3@11 + uint32_t v11; // r1@11 + signed int v12; // r0@12 + char v13; // r3@15 + uint32_t v14; // r1@15 + signed int v15; // r2@15 + SDIO_HOST_CMD v16; // [sp+0h] [bp-20h]@1 - v16 = (SDIO_HOST_CMD)EndAddr; - v3 = EndAddra; - v4 = a2; - v5 = EndAddr; - if ( !(u32)EndAddr ) - return 3; - if ( *(u8 *)(EndAddr + 132) ) - { - v4 = a2 >> 9; - v3 = EndAddra >> 9; - } - result = SdioHostChkCmdInhibitCMD(EndAddr); - if ( !result ) - { - v16.CmdFmt = (SDIO_HOST_CMD_FMT)((*(u8 *)&v16.CmdFmt & 0xFC | 0x1A) & 0x1F); - v7 = *((u8 *)&v16.CmdFmt + 1); - *(u8 *)(v5 + 128) = 0; - *((u8 *)&v16.CmdFmt + 1) = v7 & 0xC0 | 0x20; - v16.Arg = v4; - SdioHostSendCmd(&v16); - result = SdioHostChkCmdComplete((void *)v5, v8); - if ( !result ) - { - v9 = SdioHostGetResponse((void *)v5, *(u8 *)&v16.CmdFmt & 3); - if ( *(u8 *)(v5 + 24) != 32 ) - goto LABEL_20; - result = SdioHostChkCmdInhibitCMD(v9); - if ( result ) - return result; - v16.CmdFmt = (SDIO_HOST_CMD_FMT)((*(u8 *)&v16.CmdFmt & 0xFC | 0x1A) & 0x1F); - v10 = *((u8 *)&v16.CmdFmt + 1); - *(u8 *)(v5 + 128) = 0; - *((u8 *)&v16.CmdFmt + 1) = v10 & 0xC0 | 0x21; - v16.Arg = v3; - SdioHostSendCmd(&v16); - result = SdioHostChkCmdComplete((void *)v5, v11); - if ( result ) - return result; - v12 = SdioHostGetResponse((void *)v5, *(u8 *)&v16.CmdFmt & 3); - if ( *(u8 *)(v5 + 24) != 33 ) - { -LABEL_20: - DBG_SDIO_ERR("Command index error !!\n"); - result = 238; - } - else - { - result = SdioHostChkCmdInhibitCMD(v12); - if ( !result ) - { - result = SdioHostChkCmdInhibitDAT(0); - if ( !result ) - { - v16.CmdFmt = (SDIO_HOST_CMD_FMT)((*(u8 *)&v16.CmdFmt | 0x1B) & 0x1F); - v13 = *((u8 *)&v16.CmdFmt + 1); - *(u8 *)(v5 + 128) = 0; - *(u8 *)(v5 + 129) = 0; - v16.Arg = 0; - *((u8 *)&v16.CmdFmt + 1) = v13 & 0xC0 | 0x26; - SdioHostSendCmd(&v16); - result = SdioHostChkCmdComplete((void *)v5, v14); - if ( !result ) - result = SdioHostChkXferComplete((void *)v5, 0x1388u, v15); - } - } - } - } - } - return result; + v16 = (SDIO_HOST_CMD) EndAddr; + v3 = EndAddra; + v4 = a2; + v5 = EndAddr; + if (!(u32) EndAddr) + return 3; + if (*(u8 *) (EndAddr + 132)) { + v4 = a2 >> 9; + v3 = EndAddra >> 9; + } + result = SdioHostChkCmdInhibitCMD(EndAddr); + if (!result) { + v16.CmdFmt = (SDIO_HOST_CMD_FMT) ((*(u8 *) &v16.CmdFmt & 0xFC | 0x1A) + & 0x1F); + v7 = *((u8 *) &v16.CmdFmt + 1); + *(u8 *) (v5 + 128) = 0; + *((u8 *) &v16.CmdFmt + 1) = v7 & 0xC0 | 0x20; + v16.Arg = v4; + SdioHostSendCmd(&v16); + result = SdioHostChkCmdComplete((void *) v5, v8); + if (!result) { + v9 = SdioHostGetResponse((void *) v5, *(u8 *) &v16.CmdFmt & 3); + if (*(u8 *) (v5 + 24) != 32) + goto LABEL_20; + result = SdioHostChkCmdInhibitCMD(v9); + if (result) + return result; + v16.CmdFmt = + (SDIO_HOST_CMD_FMT) ((*(u8 *) &v16.CmdFmt & 0xFC | 0x1A) + & 0x1F); + v10 = *((u8 *) &v16.CmdFmt + 1); + *(u8 *) (v5 + 128) = 0; + *((u8 *) &v16.CmdFmt + 1) = v10 & 0xC0 | 0x21; + v16.Arg = v3; + SdioHostSendCmd(&v16); + result = SdioHostChkCmdComplete((void *) v5, v11); + if (result) + return result; + v12 = SdioHostGetResponse((void *) v5, *(u8 *) &v16.CmdFmt & 3); + if (*(u8 *) (v5 + 24) != 33) { + LABEL_20: + DBG_SDIO_ERR("Command index error !!\n"); + result = 238; + } else { + result = SdioHostChkCmdInhibitCMD(v12); + if (!result) { + result = SdioHostChkCmdInhibitDAT(0); + if (!result) { + v16.CmdFmt = (SDIO_HOST_CMD_FMT) ((*(u8 *) &v16.CmdFmt + | 0x1B) & 0x1F); + v13 = *((u8 *) &v16.CmdFmt + 1); + *(u8 *) (v5 + 128) = 0; + *(u8 *) (v5 + 129) = 0; + v16.Arg = 0; + *((u8 *) &v16.CmdFmt + 1) = v13 & 0xC0 | 0x26; + SdioHostSendCmd(&v16); + result = SdioHostChkCmdComplete((void *) v5, v14); + if (!result) + result = SdioHostChkXferComplete((void *) v5, + 0x1388u, v15); + } + } + } + } + } + return result; } // 23D4: using guessed type int DiagPrintf(const char *, ...); //----- (00001AA8) -------------------------------------------------------- -HAL_Status HalSdioHostGetWriteProtectRtl8195a(IN VOID *Data); -{ - void *v3; // r4@1 - uint32_t v4; // r1@2 - int v5; // r2@2 - int v6; // r5@2 - signed int result; // r0@6 - int v8; // r2@10 - const char *v9; // r0@13 +HAL_Status HalSdioHostGetWriteProtectRtl8195a(IN VOID *Data) { + void *v3; // r4@1 + uint32_t v4; // r1@2 + int v5; // r2@2 + int v6; // r5@2 + signed int result; // r0@6 + int v8; // r2@10 + const char *v9; // r0@13 - v3 = Data; - if ( !Data ) - return 3; - v6 = HalSdioHostGetCardStatusRtl8195a(Data, a2, a3); - if ( v6 ) - { - if ( !(ConfigDebugErr & 0x400) ) - return v6; - v9 = "\r[SDIO Err]Get card status fail !!\n"; -LABEL_16: - DiagPrintf(v9); - return v6; - } - if ( *((u8 *)v3 + 131) == 3 ) - { -LABEL_10: - v6 = SdioHostGetCSD(v3, v4); - if ( !v6 ) - { - *((u32 *)v3 + 11) = ((unsigned int)*((u8 *)v3 + 126) >> 4) & 1; - return SdioHostCardSelection(v3, 1, v8); - } - if ( !(ConfigDebugErr & 0x400) ) - return v6; - v9 = "\r[SDIO Err]Get CSD fail !!\n"; - goto LABEL_16; - } - if ( *((u8 *)v3 + 131) == 4 || *((u8 *)v3 + 131) == 5 ) - { - result = SdioHostCardSelection(v3, 0, v5); - if ( result ) - return result; - goto LABEL_10; - } - if ( ConfigDebugErr & 0x400 ) - DiagPrintf("\r[SDIO Err]Wrong card state !!\n", ConfigDebugErr << 21); - return 238; + v3 = Data; + if (!Data) + return 3; + v6 = HalSdioHostGetCardStatusRtl8195a(Data, a2, a3); + if (v6) { + if (!(ConfigDebugErr & 0x400)) + return v6; + v9 = "\r[SDIO Err]Get card status fail !!\n"; + LABEL_16: DiagPrintf(v9); + return v6; + } + if (*((u8 *) v3 + 131) == 3) { + LABEL_10: v6 = SdioHostGetCSD(v3, v4); + if (!v6) { + *((u32 *) v3 + 11) = ((unsigned int) *((u8 *) v3 + 126) >> 4) & 1; + return SdioHostCardSelection(v3, 1, v8); + } + if (!(ConfigDebugErr & 0x400)) + return v6; + v9 = "\r[SDIO Err]Get CSD fail !!\n"; + goto LABEL_16; + } + if (*((u8 *) v3 + 131) == 4 || *((u8 *) v3 + 131) == 5) { + result = SdioHostCardSelection(v3, 0, v5); + if (result) + return result; + goto LABEL_10; + } + if (ConfigDebugErr & 0x400) + DiagPrintf("\r[SDIO Err]Wrong card state !!\n", ConfigDebugErr << 21); + return 238; } // 23D4: using guessed type int DiagPrintf(const char *, ...); //----- (00001B48) -------------------------------------------------------- -HAL_Status HalSdioHostSetWriteProtectRtl8195a(IN VOID *Data, IN u8 Setting) -{ - int v2; // r3@1 - u8 *v3; // r4@1 - int v4; // r2@2 - uint8_t v5; // r2@5 - int v6; // r1@7 - unsigned int v7; // r2@7 - signed int v8; // r0@8 - u8 v9; // cf@11 - char v10; // r1@13 - int result; // r0@13 - char v12; // r3@15 - uint32_t v13; // r1@15 - signed int v14; // r2@16 - uint32_t v15; // r1@20 - char v16; // [sp+0h] [bp-30h]@15 - char v17; // [sp+1h] [bp-2Fh]@15 - HAL_Status ret; // [sp+4h] [bp-2Ch]@15 - uint8_t tmp[16]; // [sp+8h] [bp-28h]@3 +HAL_Status HalSdioHostSetWriteProtectRtl8195a(IN VOID *Data, IN u8 Setting) { + int v2; // r3@1 + u8 *v3; // r4@1 + int v4; // r2@2 + uint8_t v5; // r2@5 + int v6; // r1@7 + unsigned int v7; // r2@7 + signed int v8; // r0@8 + u8 v9; // cf@11 + char v10; // r1@13 + int result; // r0@13 + char v12; // r3@15 + uint32_t v13; // r1@15 + signed int v14; // r2@16 + uint32_t v15; // r1@20 + char v16; // [sp+0h] [bp-30h]@15 + char v17; // [sp+1h] [bp-2Fh]@15 + HAL_Status ret; // [sp+4h] [bp-2Ch]@15 + uint8_t tmp[16]; // [sp+8h] [bp-28h]@3 - v2 = *((u32 *)Data + 4); - v3 = Data; - if ( !v2 ) - return 3; - v4 = *((u32 *)Data + 4) & 3; - if ( v2 & 3 ) - return 3; - do - { - tmp[v4] = *((u8 *)Data + v4 + 112); - ++v4; - } - while ( v4 != 15 ); - if ( Setting == 1 ) - v5 = tmp[14] | 0x10; - else - v5 = tmp[14] & 0xEF; - v6 = 0; - tmp[14] = v5; - LOBYTE(v7) = 0; - do - { - v8 = 7; - do - { - v7 = (u8)(2 * v7); - if ( (((signed int)tmp[v6] >> v8) & 1) != v7 >> 7 ) - LOBYTE(v7) = v7 ^ 0x89; - v9 = __CFADD__(v8--, -1); - } - while ( v9 ); - ++v6; - } - while ( v6 != 15 ); - tmp[15] = 2 * v7 | 1; - v40058058 = v2; - v40058004 = 16; - v4005800C = 1; - v10 = *(u8 *)v2; - *(u16 *)(v2 + 2) = 16; - *(u8 *)v2 = v10 & 0xC8 | 0x23; - *(u32 *)(v2 + 4) = tmp; - result = SdioHostChkCmdInhibitCMD(1u); - if ( !result ) - { - result = SdioHostChkDataLineActive(0); - if ( !result ) - { - v16 = (v16 & 0xF4 | 0x3A) & 0x3F; - v12 = v17; - v3[128] = 0; - v3[129] = 0; - ret = 0; - v17 = v12 & 0xC0 | 0x1B; - SdioHostSendCmd((SDIO_HOST_CMD *)&v16); - result = SdioHostChkCmdComplete(v3, v13); - if ( !result ) - { - SdioHostGetResponse(v3, v16 & 3); - if ( *((u32 *)v3 + 5) & 0x4000000 ) - { - DBG_SDIO_ERR("Write protect violation !!\n", ConfigDebugErr << 21); - return 3; - } - result = SdioHostChkXferComplete(v3, 0x1388u, v14); - if ( result ) - { - if ( result != 16 ) - { - if ( v40058032 & 0x200 ) - { - v40058032 = 512; - if ( HalSdioHostStopTransferRtl8195a(v3, v15) ) - { - DBG_SDIO_ERR("Stop transmission error!\n"); - } - } - } - result = 238; - } - } - } - } - return result; + v2 = *((u32 *) Data + 4); + v3 = Data; + if (!v2) + return 3; + v4 = *((u32 *) Data + 4) & 3; + if (v2 & 3) + return 3; + do { + tmp[v4] = *((u8 *) Data + v4 + 112); + ++v4; + } while (v4 != 15); + if (Setting == 1) + v5 = tmp[14] | 0x10; + else + v5 = tmp[14] & 0xEF; + v6 = 0; + tmp[14] = v5; + LOBYTE (v7) = 0; + do { + v8 = 7; + do { + v7 = (u8) (2 * v7); + if ((((signed int) tmp[v6] >> v8) & 1) != v7 >> 7) + LOBYTE (v7) = v7 ^ 0x89; + v9 = __CFADD__(v8--, -1); + } while (v9); + ++v6; + } while (v6 != 15); + tmp[15] = 2 * v7 | 1; + v40058058 = v2; + v40058004 = 16; + v4005800C = 1; + v10 = *(u8 *) v2; + *(u16 *) (v2 + 2) = 16; + *(u8 *) v2 = v10 & 0xC8 | 0x23; + *(u32 *) (v2 + 4) = tmp; + result = SdioHostChkCmdInhibitCMD(1u); + if (!result) { + result = SdioHostChkDataLineActive(0); + if (!result) { + v16 = (v16 & 0xF4 | 0x3A) & 0x3F; + v12 = v17; + v3[128] = 0; + v3[129] = 0; + ret = 0; + v17 = v12 & 0xC0 | 0x1B; + SdioHostSendCmd((SDIO_HOST_CMD *) &v16); + result = SdioHostChkCmdComplete(v3, v13); + if (!result) { + SdioHostGetResponse(v3, v16 & 3); + if (*((u32 *) v3 + 5) & 0x4000000) { + DBG_SDIO_ERR("Write protect violation !!\n", + ConfigDebugErr << 21); + return 3; + } + result = SdioHostChkXferComplete(v3, 0x1388u, v14); + if (result) { + if (result != 16) { + if (v40058032 & 0x200) { + v40058032 = 512; + if (HalSdioHostStopTransferRtl8195a(v3, v15)) { + DBG_SDIO_ERR("Stop transmission error!\n"); + } + } + } + result = 238; + } + } + } + } + return result; } - diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c index 9d33059..99e5568 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c @@ -14,8 +14,7 @@ extern _LONG_CALL_ HAL_Status HalSsiInitRtl8195a(VOID *Adaptor); -extern _LONG_CALL_ -u32 HalGetCpuClk(VOID); +//extern _LONG_CALL_ u32 HalGetCpuClk(VOID); VOID _SsiReadInterruptRtl8195a(VOID *Adapter) diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_adc.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_adc.c index a5e4294..a91b7ab 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_adc.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_adc.c @@ -1228,10 +1228,7 @@ RtkADCReceive( return _EXIT_FAILURE; } -extern u32 -HalDelayUs( - IN u32 us -); +//extern u32 HalDelayUs(IN u32 us); u32 RtkADCReceiveBuf( diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_misc.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_misc.c index 0403c23..dc26766 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_misc.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_misc.c @@ -56,4 +56,14 @@ HAL_RESET_REASON HalGetResetCause(void) return HAL_PERI_ON_READ32(REG_SYS_DSLP_TIM_CTRL); } +u8 HalGetChipId(void) { + u8 chip_id = CHIP_ID_8195AM; +#if CONFIG_DEBUG_LOG > 3 + if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8, &chip_id, L25EOUTVOLTAGE) != 1) + DBG_MISC_INFO("Get Chip ID Failed\r"); +#else + HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8, &chip_id, L25EOUTVOLTAGE); +#endif + return chip_id; +} diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_pcm.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_pcm.c index 265a857..e3a09e6 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_pcm.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_pcm.c @@ -8,6 +8,7 @@ */ +#include "platform_autoconf.h" #include "hal_pcm.h" #ifdef CONFIG_PCM_EN diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_pinmux.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_pinmux.c index 820d1fb..2bcf6cd 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_pinmux.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_pinmux.c @@ -30,6 +30,7 @@ void HalJtagPinOff(void) HalPinCtrlRtl8195A(JTAG, 0, 0); } + #if RTL8710_DEF_PIN_ON //----- GpioIcFunChk @@ -45,7 +46,7 @@ u8 GpioIcFunChk(IN u32 chip_pin, IN u8 Operation) if (tst & 0xEF) result = 1; else { result = tst & 0x10; - if(tst & 0x10) { // RTL8710AF ? + if(result) { // RTL8710AF ? if (chip_pin - 1 <= 2) result = 0; // PA_1, PA_2, PA_3 else { result = chip_pin - PC_5; // PC_5 diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdio_host.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdio_host.c index e911904..45ba0c6 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdio_host.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdio_host.c @@ -4,12 +4,17 @@ * RTL8710/11 pvvx 12/2016 */ #include "rtl8195a.h" +#ifdef CONFIG_SDIO_HOST_EN #include "sd.h" #include "sdio_host.h" #include "hal_sdio_host.h" #include "rtl8195a_sdio_host.h" #include "hal_pinmux.h" - +//#ifdef RTL8710AF + #include "hal_gpio.h" + #include "PinNames.h" + #include "hal_gpio.h" +//#endif //------------------------------------------------------------------------- // Function declarations @@ -107,4 +112,17 @@ void HalSdioHostOpInit(void *Data) { phsha->HalSdioHostErase = &HalSdioHostEraseRtl8195a; phsha->HalSdioHostGetWriteProtect = &HalSdioHostGetWriteProtectRtl8195a; phsha->HalSdioHostSetWriteProtect = &HalSdioHostSetWriteProtectRtl8195a; +//#ifdef RTL8710AF + if(HalGetChipId() != CHIP_ID_8195AM) { + GPIOState[0] &= ~((1 << 8) - 1); + { + for (int i = 0; i <= 6; i++) + HAL_GPIO_PullCtrl(i, PullNone); + HAL_GPIO_PullCtrl(PA_6, PullDown); + HAL_GPIO_PullCtrl(PA_7, PullDown); + } + } +//#endif } + +#endif // CONFIG_SDIO_HOST_EN diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c index 58c7859..3bc2b26 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c @@ -1047,7 +1047,7 @@ MemTest( } // MemTest -#if defined ( __ICCARM__ ) +//#if defined ( __ICCARM__ ) u8 IsSdrPowerOn( VOID ) @@ -1058,7 +1058,7 @@ u8 IsSdrPowerOn( return 1; } } -#endif +//#endif #else // ifndef CONFIG_SDR_EN diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c index 24cb3d9..1c0b5ed 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c @@ -22,8 +22,8 @@ extern void xPortPendSVHandler( void ) __attribute__ (( naked )); #endif extern void xPortSysTickHandler( void ); extern void vPortSVCHandler( void ); -extern u32 HalGetCpuClk(VOID); -extern _LONG_CALL_ u32 HalDelayUs(u32 us); +//extern unsigned int HalGetCpuClk(void); +//extern _LONG_CALL_ u32 HalDelayUs(u32 us); extern COMMAND_TABLE UartLogRomCmdTable[]; extern HAL_TIMER_OP HalTimerOp; diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_spi_flash_ram.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_spi_flash_ram.c index a1871f0..6d3f101 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_spi_flash_ram.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_spi_flash_ram.c @@ -14,900 +14,867 @@ #define SPI_CTRL_BASE 0x1FFEF000 -#define SPI_DLY_CTRL_ADDR 0x40000300 // [7:0] +#define SPI_DLY_CTRL_ADDR 0x40000300 // [7:0] #define MIN_BAUDRATE 0x01 #define MAX_BAUDRATE 0x04 #define MAX_AUTOLEN 0x14 #define MAX_DLYLINE 99 #define GOLD_ID_NO_RAM 0xC220 -#define WR_DATA(addr, data) (*((volatile u32*)(addr)) = (data)) +#define WR_DATA(addr, data) (*((volatile u32*)(addr)) = (data)) #define RD_DATA(addr) (*((volatile u32*)(addr))) -BOOLEAN SpicFlashInitRtl8195A( u8 SpicBitMode ); -u32 SpicCalibrationRtl8195A( u8 SpicBitMode, u32 DefRdDummyCycle ); // spi-flash calibration +BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode); +u32 SpicCalibrationRtl8195A(u8 SpicBitMode, u32 DefRdDummyCycle); // spi-flash calibration -VOID SpicSetFlashStatusRefinedRtl8195A( u32 data, SPIC_INIT_PARA SpicInitPara ); +VOID SpicSetFlashStatusRefinedRtl8195A(u32 data, SPIC_INIT_PARA SpicInitPara); -VOID SpicConfigAutoModeRtl8195A( u8 SpicBitMode ); // config spi-flash controller to auto mode -VOID SpicReadIDRtl8195A( VOID ); +VOID SpicConfigAutoModeRtl8195A(u8 SpicBitMode); // config spi-flash controller to auto mode +VOID SpicReadIDRtl8195A(VOID); _LONG_CALL_ -extern VOID SpicInitRtl8195A( u8 InitBaudRate, - u8 SpicBitMode ); // spi-flash controller initialization +extern VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode); // spi-flash controller initialization _LONG_CALL_ -extern VOID SpicRxCmdRtl8195A( u8 ); // recieve command +extern VOID SpicRxCmdRtl8195A(u8); // recieve command _LONG_CALL_ -extern VOID SpicSetFlashStatusRtl8195A( u32 data, - SPIC_INIT_PARA SpicInitPara ); // WRSR, write spi-flash status register +extern VOID SpicSetFlashStatusRtl8195A(u32 data, SPIC_INIT_PARA SpicInitPara); // WRSR, write spi-flash status register _LONG_CALL_ -extern VOID SpicWaitBusyDoneRtl8195A( VOID ); // wait sr[0] = 0, wait transmission done +extern VOID SpicWaitBusyDoneRtl8195A(VOID); // wait sr[0] = 0, wait transmission done _LONG_CALL_ -extern VOID SpicWaitWipDoneRtl8195A( SPIC_INIT_PARA - SpicInitPara ); // wait spi-flash status register[0] = 0 +extern VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara); // wait spi-flash status register[0] = 0 _LONG_CALL_ -extern VOID SpicEraseFlashRtl8195A( VOID ); // CE, flash chip erase +extern VOID SpicEraseFlashRtl8195A(VOID); // CE, flash chip erase _LONG_CALL_ -extern u32 SpicCmpDataForCalibrationRtl8195A( void ); // compare read_data and golden_data -#ifdef CONFIG_FPGA +extern u32 SpicCmpDataForCalibrationRtl8195A(void); // compare read_data and golden_data +#ifdef CONFIG_FPGA _LONG_CALL_ -extern VOID SpicProgFlashForCalibrationRtl8195A( SPIC_INIT_PARA - SpicInitPara ); // program spi-flash +extern VOID SpicProgFlashForCalibrationRtl8195A(SPIC_INIT_PARA SpicInitPara); // program spi-flash #endif _LONG_CALL_ -extern VOID SpicLoadInitParaFromClockRtl8195A( u8 CpuClkMode, u8 BaudRate, - PSPIC_INIT_PARA pSpicInitPara ); +extern VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara); + +_LONG_CALL_ +extern u8 SpicGetFlashStatusRtl8195A(SPIC_INIT_PARA SpicInitPara); _LONG_CALL_ -extern u8 SpicGetFlashStatusRtl8195A( SPIC_INIT_PARA SpicInitPara ); +extern VOID SpicTxCmdRtl8195A(u8 cmd, SPIC_INIT_PARA SpicInitPara); -_LONG_CALL_ -extern VOID SpicTxCmdRtl8195A( u8 cmd, SPIC_INIT_PARA SpicInitPara ); - -struct ava_window -{ - u16 baud_rate; - u16 auto_length; - u32 dly_line_sp; - u32 dly_line_ep; +struct ava_window { + u16 baud_rate; + u16 auto_length; + u32 dly_line_sp; + u32 dly_line_ep; }; #ifdef CONFIG_FPGA HAL_ROM_DATA_SECTION -SPIC_INIT_PARA FPGASpicInitPara = {1, 1, 0, 0}; +SPIC_INIT_PARA FPGASpicInitPara = {1,1,0,0}; #endif #if 0 HAL_FLASH_DATA_ -SECTION SPIC_INIT_PARA SpicInitParaAllClk[CPU_CLK_TYPE_NO] = {{0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0}, -}; +SECTION SPIC_INIT_PARA SpicInitParaAllClk[CPU_CLK_TYPE_NO] = {{0,0,0,0}, + {0,0,0,0}, + {0,0,0,0}, + {0,0,0,0}, + {0,0,0,0}, + {0,0,0,0},}; #else -HAL_FLASH_DATA_SECTION -SPIC_INIT_PARA SpicInitParaAllClk[3][CPU_CLK_TYPE_NO]; +HAL_FLASH_DATA_SECTION +SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; #endif extern SPIC_INIT_PARA SpicInitCPUCLK[4]; /* Send Flash Instruction with Data Phase */ HAL_FLASH_TEXT_SECTION -VOID +VOID SpicTxCmdWithDataRtl8195A ( - IN u8 cmd, - IN u8 DataPhaseLen, - IN u8 * pData, - IN SPIC_INIT_PARA SpicInitPara + IN u8 cmd, + IN u8 DataPhaseLen, + IN u8* pData, + IN SPIC_INIT_PARA SpicInitPara ) { - u8 i; - DBG_SPIF_INFO( "%s(0x%x, 0x%x, 0x%x, 0x%x)\n", __func__, cmd, DataPhaseLen, pData, SpicInitPara ); - // Disable SPI_FLASH User Mode - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); + u8 i; +#if CONFIG_DEBUG_LOG > 4 + DBG_SPIF_INFO("%s(0x%x, 0x%x, 0x%x, 0x%x)\n",__func__, cmd, DataPhaseLen, pData, SpicInitPara); +#endif + // Disable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); - if ( DataPhaseLen > 15 ) - { - DBG_SPIF_WARN( "SpicTxInstRtl8195A: Data Phase Leng too Big(%d)\n", DataPhaseLen ); - DataPhaseLen = 15; - } + if (DataPhaseLen > 15) { + DBG_SPIF_WARN("SpicTxInstRtl8195A: Data Phase Leng too Big(%d)\n",DataPhaseLen); + DataPhaseLen = 15; + } + + HAL_SPI_WRITE32(REG_SPIC_ADDR_LENGTH, DataPhaseLen); - HAL_SPI_WRITE32( REG_SPIC_ADDR_LENGTH, DataPhaseLen ); - // set ctrlr0: TX mode - HAL_SPI_WRITE32( REG_SPIC_CTRLR0, - ( HAL_SPI_READ32( REG_SPIC_CTRLR0 ) & 0xFFF0FCFF ) ); - // set flash_cmd: wren to fifo - HAL_SPI_WRITE8( REG_SPIC_DR0, cmd ); + // set ctrlr0: TX mode + HAL_SPI_WRITE32(REG_SPIC_CTRLR0, + (HAL_SPI_READ32(REG_SPIC_CTRLR0)& 0xFFF0FCFF)); - //fill addr - for ( i = 0; i < DataPhaseLen; i++ ) - { - HAL_SPI_WRITE8( REG_SPIC_DR0, ( u8 ) * ( pData + i ) ); - } + // set flash_cmd: wren to fifo + HAL_SPI_WRITE8(REG_SPIC_DR0, cmd); + + //fill addr + for (i=0;i> 4 ) >= 2 ) ) - { - SPI_FLASH_PIN_FCTRL( ON ); - // Wait for flash busy done - SpicWaitWipDoneRefinedRtl8195A( SpicInitPara ); + if ((HAL_READ32(SYSTEM_CTRL_BASE,REG_SYS_EFUSE_SYSCFG6) & BIT(25))&& + ((((u8)HAL_READ32(SYSTEM_CTRL_BASE,REG_SYS_SYSTEM_CFG0))>>4)>= 2)){ - while( ( SpicGetFlashStatusRefinedRtl8195A( SpicInitPara ) & 0x02 ) == 0 ) - { - // Set flash_cmd: WREN to FIFO - //SpicTxCmdRtl8195A(FLASH_CMD_WREN, SpicInitPara); - SpicTxCmdWithDataRtl8195A( FLASH_CMD_WREN, 0, 0, SpicInitPara ); + SPI_FLASH_PIN_FCTRL(ON); + + // Wait for flash busy done + SpicWaitWipDoneRefinedRtl8195A(SpicInitPara); + + while((SpicGetFlashStatusRefinedRtl8195A(SpicInitPara) & 0x02)==0) { + // Set flash_cmd: WREN to FIFO + //SpicTxCmdRtl8195A(FLASH_CMD_WREN, SpicInitPara); + SpicTxCmdWithDataRtl8195A(FLASH_CMD_WREN, 0, 0, SpicInitPara); + } + + DBG_8195A("Deep power down\n"); + + // Set flash_cmd: Chip_erase to FIFO + //SpicTxCmdRtl8195A(FLASH_CMD_CE, SpicInitPara); + SpicTxCmdWithDataRtl8195A(FLASH_CMD_DP, 0, 0, SpicInitPara); + + // polling WEL + do { + } while((SpicGetFlashStatusRefinedRtl8195A(SpicInitPara) & 0x02)!=0); } - - DBG_8195A( "Deep power down\n" ); - // Set flash_cmd: Chip_erase to FIFO - //SpicTxCmdRtl8195A(FLASH_CMD_CE, SpicInitPara); - SpicTxCmdWithDataRtl8195A( FLASH_CMD_DP, 0, 0, SpicInitPara ); - - // polling WEL - do - { - } - while( ( SpicGetFlashStatusRefinedRtl8195A( SpicInitPara ) & 0x02 ) != 0 ); - } } //This funciton is only valid for Micron Flash HAL_FLASH_TEXT_SECTION -VOID +VOID SpicDieEraseFlashRtl8195A( - IN u32 Address + IN u32 Address ) { - u8 Addr[3]; - Addr[0] = ( Address >> 16 ) & 0xFF; - Addr[1] = ( Address >> 8 ) & 0xFF; - Addr[2] = Address & 0xFF; - SpicTxFlashInstRtl8195A( 0xC4, 3, Addr ); + u8 Addr[3]; + + Addr[0] = (Address >> 16) & 0xFF; + Addr[1] = (Address >> 8) & 0xFF; + Addr[2] = Address & 0xFF; + SpicTxFlashInstRtl8195A(0xC4, 3, Addr); } HAL_FLASH_TEXT_SECTION -VOID +VOID SpicBlockEraseFlashRtl8195A( - IN u32 Address + IN u32 Address ) { - u8 Addr[3]; - DBG_8195A( "Erase Cmd Set\n" ); - // Set flash_cmd: Chip_erase to FIFO - Addr[0] = ( Address >> 16 ) & 0xFF; - Addr[1] = ( Address >> 8 ) & 0xFF; - Addr[2] = Address & 0xFF; - SpicTxFlashInstRtl8195A( FLASH_CMD_BE, 3, Addr ); + u8 Addr[3]; + + DBG_8195A("Erase Cmd Set\n"); + // Set flash_cmd: Chip_erase to FIFO + Addr[0] = (Address >> 16) & 0xFF; + Addr[1] = (Address >> 8) & 0xFF; + Addr[2] = Address & 0xFF; + SpicTxFlashInstRtl8195A(FLASH_CMD_BE, 3, Addr); } HAL_FLASH_TEXT_SECTION -VOID +VOID SpicSectorEraseFlashRtl8195A( - IN u32 Address + IN u32 Address ) { - u8 Addr[3]; - Addr[0] = ( Address >> 16 ) & 0xFF; - Addr[1] = ( Address >> 8 ) & 0xFF; - Addr[2] = Address & 0xFF; - SpicTxFlashInstRtl8195A( FLASH_CMD_SE, 3, Addr ); + u8 Addr[3]; + + Addr[0] = (Address >> 16) & 0xFF; + Addr[1] = (Address >> 8) & 0xFF; + Addr[2] = Address & 0xFF; + SpicTxFlashInstRtl8195A(FLASH_CMD_SE, 3, Addr); } HAL_FLASH_TEXT_SECTION -VOID +VOID SpicWriteStatusFlashRtl8195A( - IN u32 Status + IN u32 Status ) { - u8 Buf[3]; - Buf[0] = Status & 0xFF; - Buf[1] = ( Status >> 8 ) & 0xFF; - //1 For MXIC, Status Register is 8-bit width; for Winbond, Status Reguster is 16-bit width - SpicTxFlashInstRtl8195A( FLASH_CMD_WRSR, 1, Buf ); + u8 Buf[3]; + + Buf[0] = Status & 0xFF; + Buf[1] = (Status >> 8) & 0xFF; + //1 For MXIC, Status Register is 8-bit width; for Winbond, Status Reguster is 16-bit width + SpicTxFlashInstRtl8195A(FLASH_CMD_WRSR, 1, Buf); } HAL_FLASH_TEXT_SECTION -VOID +VOID SpicWriteProtectFlashRtl8195A( - IN u32 Protect + IN u32 Protect ) { - SPIC_INIT_PARA SpicInitPara; - u8 Status; - Status = SpicGetFlashStatusRefinedRtl8195A( SpicInitPara ); - - if ( Protect ) - { - Status |= 0x1c; // protect whole chip - } - else - { - Status &= ~0x1c; // Protect none - } - - SpicWriteStatusFlashRtl8195A( Status ); + SPIC_INIT_PARA SpicInitPara; + u8 Status; + + Status = SpicGetFlashStatusRefinedRtl8195A(SpicInitPara); + if (Protect) { + Status |= 0x1c; // protect whole chip + } + else { + Status &= ~0x1c; // Protect none + } + SpicWriteStatusFlashRtl8195A(Status); } HAL_FLASH_TEXT_SECTION BOOLEAN SpicFlashInitRtl8195A( - IN u8 SpicBitMode + IN u8 SpicBitMode ) { - u32 DefRdDummyCycle = 0; - SPIC_INIT_PARA SpicInitPara; + u32 DefRdDummyCycle = 0; + SPIC_INIT_PARA SpicInitPara; + #ifdef CONFIG_FPGA - SpicInitPara.BaudRate = FPGASpicInitPara.BaudRate; - SpicInitPara.RdDummyCyle = FPGASpicInitPara.RdDummyCyle; - SpicInitPara.DelayLine = FPGASpicInitPara.DelayLine; + SpicInitPara.BaudRate = FPGASpicInitPara.BaudRate; + SpicInitPara.RdDummyCyle = FPGASpicInitPara.RdDummyCyle; + SpicInitPara.DelayLine = FPGASpicInitPara.DelayLine; #endif - switch ( SpicBitMode ) - { - case SpicOneBitMode: - // DBG_8195A("Initial Spic One bit mode\n"); - // wait for flash busy done - SpicWaitWipDoneRefinedRtl8195A( SpicInitPara ); - // set auto mode - SpicConfigAutoModeRtl8195A( SpicBitMode ); - /* MXIC spec */ - DefRdDummyCycle = 0; - break; - - case SpicDualBitMode: - // DBG_8195A("Initial Spic Two bit mode\n"); -#ifdef CONFIG_FPGA - // program golden_data to golden_address and store golden_data in sram - SpicProgFlashForCalibrationRtl8195A( SpicInitPara ); + switch (SpicBitMode) { + case SpicOneBitMode: +#if CONFIG_DEBUG_LOG > 4 + DBG_8195A("Initial Spic One bit mode\n"); #endif - // set auto mode - SpicConfigAutoModeRtl8195A( SpicBitMode ); - /* MXIC spec */ -#if FLASH_RD_2IO_EN - DefRdDummyCycle = FLASH_DM_CYCLE_2IO; -#endif -#if FLASH_RD_2O_EN - DefRdDummyCycle = FLASH_DM_CYCLE_2O; -#endif - break; + // wait for flash busy done + SpicWaitWipDoneRefinedRtl8195A(SpicInitPara); - case SpicQuadBitMode: - DBG_8195A( "Initial Spic Four bit mode\n" ); -#ifdef CONFIG_FPGA - // program golden_data to golden_address and store golden_data in sram - SpicProgFlashForCalibrationRtl8195A( SpicInitPara ); + // set auto mode + SpicConfigAutoModeRtl8195A(SpicBitMode); + + /* MXIC spec */ + DefRdDummyCycle = 0; + break; + case SpicDualBitMode: +#if CONFIG_DEBUG_LOG > 4 + DBG_8195A("Initial Spic Two bit mode\n"); #endif - // set auto mode - SpicConfigAutoModeRtl8195A( SpicBitMode ); - // set 4bit-mode - SpicSetFlashStatusRefinedRtl8195A( 0x40, SpicInitPara ); - /* MXIC spec */ -#if FLASH_RD_4IO_EN - DefRdDummyCycle = FLASH_DM_CYCLE_4IO; +#ifdef CONFIG_FPGA + // program golden_data to golden_address and store golden_data in sram + SpicProgFlashForCalibrationRtl8195A(SpicInitPara); +#endif + // set auto mode + SpicConfigAutoModeRtl8195A(SpicBitMode); + + /* MXIC spec */ + #if FLASH_RD_2IO_EN + DefRdDummyCycle = FLASH_DM_CYCLE_2IO; + #endif + #if FLASH_RD_2O_EN + DefRdDummyCycle = FLASH_DM_CYCLE_2O; + #endif + + break; + case SpicQuadBitMode: +#if CONFIG_DEBUG_LOG > 4 + DBG_8195A("Initial Spic Four bit mode\n"); #endif -#if FLASH_RD_4O_EN - DefRdDummyCycle = FLASH_DM_CYCLE_4O; +#ifdef CONFIG_FPGA + // program golden_data to golden_address and store golden_data in sram + SpicProgFlashForCalibrationRtl8195A(SpicInitPara); #endif - break; + // set auto mode + SpicConfigAutoModeRtl8195A(SpicBitMode); - default: - DBG_8195A( "No Support SPI Mode!!!!!!!!\n" ); - break; - } + // set 4bit-mode + SpicSetFlashStatusRefinedRtl8195A(0x40, SpicInitPara); - SpicReadIDRtl8195A(); + /* MXIC spec */ + #if FLASH_RD_4IO_EN + DefRdDummyCycle = FLASH_DM_CYCLE_4IO; + #endif + #if FLASH_RD_4O_EN + DefRdDummyCycle = FLASH_DM_CYCLE_4O; + #endif + break; + default: + DBG_8195A("No Support SPI Mode!!!!!!!!\n"); + break; + + } + SpicReadIDRtl8195A(); - if ( !SpicCalibrationRtl8195A( SpicBitMode, DefRdDummyCycle ) ) - { - DBG_8195A( "SPI calibration fail and recover one bit mode\n" ); - SpicLoadInitParaFromClockRtl8195A( 0, 0, &SpicInitPara ); - SpicInitRefinedRtl8195A( SpicInitPara.BaudRate, SpicOneBitMode ); - SpicConfigAutoModeRtl8195A( SpicOneBitMode ); - return _FALSE; - } + if (!SpicCalibrationRtl8195A(SpicBitMode, DefRdDummyCycle)) { - return _TRUE; + DBG_8195A("SPI calibration fail and recover one bit mode\n"); + SpicLoadInitParaFromClockRtl8195A(0, 0, &SpicInitPara); + + SpicInitRefinedRtl8195A(SpicInitPara.BaudRate, SpicOneBitMode); + SpicConfigAutoModeRtl8195A(SpicOneBitMode); + + return _FALSE; + } + + return _TRUE; } HAL_FLASH_TEXT_SECTION -VOID +VOID SpicUserProgramRtl8195A ( - //IN flash_t *obj, - IN u8 * data, - IN SPIC_INIT_PARA SpicInitPara, - IN u32 addr, - IN u32 * LengthInfo + //IN flash_t *obj, + IN u8 *data, + IN SPIC_INIT_PARA SpicInitPara, + IN u32 addr, + IN u32* LengthInfo ) { - u32 Info; - u32 Length = ( u32 ) * LengthInfo; - u32 OccuSize; - u32 writeword; - u32 lastwriteword; - u32 ProgramLength; - u32 instruction; - u32 PageSize; - u8 addrbyte[3]; - u8 UnalignOffset; - u8 lastunalignoffset; - u8 index; - u8 * ptr; - u8 * buff; - UnalignOffset = 0; - lastunalignoffset = 0; - writeword = 0; - lastwriteword = 0; - ProgramLength = 0; - buff = data; - PageSize = 256; - OccuSize = addr & 0xFF; - if( OccuSize ) - { - if( ( Length >= PageSize ) || ( ( OccuSize + Length ) >= PageSize ) ) - ProgramLength = PageSize - OccuSize; - else - ProgramLength = Length; - } - else //program from the beginning of the page - { - if( Length >= PageSize ) - ProgramLength = PageSize; - else - ProgramLength = Length; - } + u32 Info; + u32 Length = (u32) *LengthInfo; + u32 OccuSize; + u32 writeword; + u32 lastwriteword; + u32 ProgramLength; + u32 instruction; + u32 PageSize; + u8 addrbyte[3]; + u8 UnalignOffset; + u8 lastunalignoffset; + u8 index; + u8 *ptr; + u8 *buff; - *LengthInfo -= ProgramLength; - - if( addr & 0x03 ) - { - UnalignOffset = ( addr & 0x03 ); - addr -= UnalignOffset; - writeword = HAL_READ32( SPI_FLASH_BASE, addr ); - ptr = ( u8 * ) &writeword + UnalignOffset; - UnalignOffset = 4 - UnalignOffset; - - for( index = 0; index < UnalignOffset ; index++ ) - { - *ptr = *buff; - buff++; - ptr++; - ProgramLength--; - - if( ProgramLength == 0 ) - break; + + UnalignOffset = 0; + lastunalignoffset = 0; + writeword = 0; + lastwriteword = 0; + ProgramLength = 0; + buff = data; + PageSize = 256; + + OccuSize = addr & 0xFF; + if(OccuSize){ + if((Length >= PageSize) ||((OccuSize + Length) >= PageSize)) + ProgramLength= PageSize - OccuSize; + else + ProgramLength = Length; } - } - else - { - if( ProgramLength >= 4 ) - { - writeword = ( u32 )( *buff ) | ( u32 )( ( *( buff + 1 ) ) << 8 ) | ( u32 )( ( * - ( buff + 2 ) ) << 16 ) | ( u32 )( ( *( buff + 3 ) ) << 24 ); - } - } - - //address already align - if( ProgramLength & 0x3 ) - { - lastunalignoffset = ProgramLength & 0x3; - - if( UnalignOffset ) - lastwriteword = HAL_READ32( SPI_FLASH_BASE, ( addr + 4 ) + ProgramLength - lastunalignoffset ); - else - lastwriteword = HAL_READ32( SPI_FLASH_BASE, addr + ProgramLength - lastunalignoffset ); - - buff += ( ProgramLength - lastunalignoffset ); - ptr = ( u8 * ) &lastwriteword; - - for( index = 0; index < lastunalignoffset; index++ ) - { - *ptr = *buff; - buff++; - ptr++; + else{//program from the beginning of the page + if(Length >= PageSize) + ProgramLength = PageSize; + else + ProgramLength = Length; } - if( UnalignOffset == 0 ) - if( ProgramLength < 4 ) - { - writeword = lastwriteword; - ProgramLength = 0; - } - } + *LengthInfo -= ProgramLength; - addrbyte[2] = ( addr & 0xFF0000 ) >> 16; - addrbyte[1] = ( addr & 0xFF00 ) >> 8; - addrbyte[0] = addr & 0xFF; - instruction = FLASH_CMD_PP | ( addrbyte[2] << 8 ) | ( addrbyte[1] << 16 ) | ( addrbyte[0] << 24 ); - Info = HAL_SPI_READ32( REG_SPIC_ADDR_LENGTH ); - //Store current setting of Address length - // Set flash_cmd: WREN to FIFO - SpicTxCmdRtl8195A( FLASH_CMD_WREN, SpicInitPara ); - // Disable SPI_FLASH - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - // set ctrlr0: TX mode - HAL_SPI_WRITE32( REG_SPIC_CTRLR0, - ( HAL_SPI_READ32( REG_SPIC_CTRLR0 ) & ( ~ BIT_TMOD( 3 ) ) ) ); - HAL_SPI_WRITE32( REG_SPIC_ADDR_LENGTH, BIT_ADDR_PHASE_LENGTH( 1 ) ); - HAL_SPI_WRITE32( REG_SPIC_DR0, instruction ); - HAL_SPI_WRITE32( REG_SPIC_DR0, writeword ); - - if( UnalignOffset == 0 ) - { - if( ProgramLength >= 4 ) - { - buff = data + 4; - ProgramLength -= 4; + if(addr & 0x03){ + UnalignOffset = (addr & 0x03); + addr -= UnalignOffset; + writeword = HAL_READ32(SPI_FLASH_BASE, addr); + ptr = (u8*) &writeword + UnalignOffset; + UnalignOffset = 4 - UnalignOffset; + for(index = 0; index < UnalignOffset ; index++){ + *ptr = *buff; + buff++; + ptr++; + ProgramLength--; + if(ProgramLength == 0) + break; + } + } + else{ + if(ProgramLength >= 4){ + writeword = (u32)(*buff) | (u32)((*(buff+1)) << 8)|(u32)((*(buff+2)) <<16)|(u32)((*(buff+3))<<24); + } + } +//address already align + if(ProgramLength & 0x3){ + lastunalignoffset = ProgramLength & 0x3; + if(UnalignOffset) + lastwriteword = HAL_READ32(SPI_FLASH_BASE, (addr + 4) + ProgramLength - lastunalignoffset); + else + lastwriteword = HAL_READ32(SPI_FLASH_BASE, addr + ProgramLength - lastunalignoffset); + buff += (ProgramLength - lastunalignoffset); + ptr = (u8*) &lastwriteword; + for(index = 0;index < lastunalignoffset;index++){ + *ptr = *buff; + buff++; + ptr++; + } + if(UnalignOffset == 0) + if(ProgramLength < 4){ + writeword = lastwriteword; + ProgramLength = 0; + } } - } - else - buff = data + UnalignOffset; - //Pre-load data before enabling - index = 0; - while( ProgramLength > 4 ) - { - if( ( u32 )buff & 0x03 ) - { - //while(ProgramLength >= 4){ - writeword = ( u32 )( *buff ) | ( ( u32 )( *( buff + 1 ) ) << 8 ) | ( ( u32 )( * - ( buff + 2 ) ) << 16 ) | ( ( u32 )( *( buff + 3 ) ) << 24 ); - HAL_SPI_WRITE32( REG_SPIC_DR0, writeword ); - ProgramLength -= 4; - buff += 4; - //} + + addrbyte[2] = (addr & 0xFF0000) >>16; + addrbyte[1] = (addr & 0xFF00)>>8; + addrbyte[0] = addr & 0xFF; + + instruction = FLASH_CMD_PP | (addrbyte[2] << 8)|(addrbyte[1] << 16)|(addrbyte[0] << 24); + Info = HAL_SPI_READ32(REG_SPIC_ADDR_LENGTH); + //Store current setting of Address length + // Set flash_cmd: WREN to FIFO + SpicTxCmdRtl8195A(FLASH_CMD_WREN, SpicInitPara); + + // Disable SPI_FLASH + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + + // set ctrlr0: TX mode + HAL_SPI_WRITE32(REG_SPIC_CTRLR0, + (HAL_SPI_READ32(REG_SPIC_CTRLR0) & (~ BIT_TMOD(3)))); + + HAL_SPI_WRITE32(REG_SPIC_ADDR_LENGTH, BIT_ADDR_PHASE_LENGTH(1)); + + HAL_SPI_WRITE32(REG_SPIC_DR0, instruction); + + HAL_SPI_WRITE32(REG_SPIC_DR0, writeword); + + if(UnalignOffset == 0){ + if(ProgramLength >= 4){ + buff = data + 4; + ProgramLength-=4; + } } else - { - //while(ProgramLength >= 4){ - HAL_SPI_WRITE32( REG_SPIC_DR0, ( u32 ) * ( ( u32 * )buff ) ); - ProgramLength -= 4; - buff += 4; - //} + buff = data + UnalignOffset; + //Pre-load data before enabling + index = 0; + while(ProgramLength > 4){ + if((u32)buff & 0x03){ + //while(ProgramLength >= 4){ + writeword = (u32)(*buff) | ((u32)(*(buff+1)) << 8) | ((u32)(*(buff+2)) << 16) | ((u32)(*(buff+3)) << 24); + HAL_SPI_WRITE32(REG_SPIC_DR0, writeword); + ProgramLength -=4; + buff+=4; + //} + } + else{ + //while(ProgramLength >= 4){ + HAL_SPI_WRITE32(REG_SPIC_DR0, (u32)*((u32 *)buff)); + ProgramLength -=4; + buff+=4; + //} + } + index++; + if(index >= 6) + break; } - index++; - - if( index >= 6 ) - break; - } - - // Enable SPI_FLASH User Mode - HAL_SPI_WRITE32( REG_SPIC_SSIENR, BIT_SPIC_EN ); - - if( ( u32 )buff & 0x03 ) - { - while( ProgramLength >= 4 ) - { - writeword = ( u32 )( *buff ) | ( ( u32 )( *( buff + 1 ) ) << 8 ) | ( ( u32 )( * - ( buff + 2 ) ) << 16 ) | ( ( u32 )( *( buff + 3 ) ) << 24 ); - HAL_SPI_WRITE32( REG_SPIC_DR0, writeword ); - ProgramLength -= 4; - buff += 4; + // Enable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN); + + if((u32)buff & 0x03){ + while(ProgramLength >= 4){ + writeword = (u32)(*buff) | ((u32)(*(buff+1)) << 8) | ((u32)(*(buff+2)) << 16) | ((u32)(*(buff+3)) << 24); + HAL_SPI_WRITE32(REG_SPIC_DR0, writeword); + ProgramLength -=4; + buff+=4; + } } - } - else - { - while( ProgramLength >= 4 ) - { - HAL_SPI_WRITE32( REG_SPIC_DR0, ( u32 ) * ( ( u32 * )buff ) ); - ProgramLength -= 4; - buff += 4; + else{ + while(ProgramLength >= 4){ + HAL_SPI_WRITE32(REG_SPIC_DR0, (u32)*((u32 *)buff)); + ProgramLength -=4; + buff+=4; + } } - } - if( ProgramLength > 0 ) - { - HAL_SPI_WRITE32( REG_SPIC_DR0, lastwriteword ); - } + if(ProgramLength > 0){ + HAL_SPI_WRITE32(REG_SPIC_DR0, lastwriteword); + } + - // wait spic busy done - SpicWaitBusyDoneRtl8195A(); + // wait spic busy done + SpicWaitBusyDoneRtl8195A(); + // wait flash busy done (wip=0) + if(SpicInitPara.flashtype == FLASH_MICRON){ + SpicWaitOperationDoneRtl8195A(SpicInitPara); + } + else{ + SpicWaitWipDoneRtl8195A(SpicInitPara); + } + - // wait flash busy done (wip=0) - if( SpicInitPara.flashtype == FLASH_MICRON ) - { - SpicWaitOperationDoneRtl8195A( SpicInitPara ); - } - else - { - SpicWaitWipDoneRtl8195A( SpicInitPara ); - } - // Disable SPI_FLASH User Mode - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - //REG_SPIC_ADDR_LENGTH cannot be programmed if SSIENR is active - //Here to restore the setting of address length - HAL_SPI_WRITE32( REG_SPIC_ADDR_LENGTH, Info ); + // Disable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + //REG_SPIC_ADDR_LENGTH cannot be programmed if SSIENR is active + //Here to restore the setting of address length + HAL_SPI_WRITE32(REG_SPIC_ADDR_LENGTH, Info); } HAL_FLASH_TEXT_SECTION VOID SpicReadIDRtl8195A( - VOID + VOID ) { - u32 RdData; - u32 RetryNum; - SPIC_INIT_PARA SpicInitPara;// = *PSpicInitPara; - u8 i, j; - DBG_SPIF_INFO( "%s(0x%x)\n", __func__, SpicInitPara ); - /* Disable SPI_FLASH User Mode */ - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - /* Set Ctrlr1; 1 byte data frames */ - HAL_SPI_WRITE32( REG_SPIC_CTRLR1, BIT_NDF( 3 ) ); - /* Send flash RX command and read the data */ - SpicRxCmdRefinedRtl8195A( FLASH_CMD_RDID, SpicInitPara ); - RdData = HAL_SPI_READ32( REG_SPIC_DR0 ); - SpicInitPara.id[0] = RdData & 0xFF; - SpicInitPara.id[1] = ( RdData >> 8 ) & 0xFF; - SpicInitPara.id[2] = ( RdData >> 16 ) & 0xFF; + u32 RdData; + u32 RetryNum; + SPIC_INIT_PARA SpicInitPara;// = *PSpicInitPara; + u8 i,j; + + DBG_SPIF_INFO("%s(0x%x)\n", __func__, SpicInitPara); + + /* Disable SPI_FLASH User Mode */ + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + + /* Set Ctrlr1; 1 byte data frames */ + HAL_SPI_WRITE32(REG_SPIC_CTRLR1, BIT_NDF(3)); - for( RetryNum = 0; RetryNum < 3; RetryNum++ ) - { - if( ( SpicInitPara.id[0] != 0 ) && ( SpicInitPara.id[0] != 0xFF ) ) - { - if( SpicInitPara.id[0] == 0x20 ) - SpicInitPara.flashtype = FLASH_MICRON; - else if( SpicInitPara.id[0] == 0xC2 ) - SpicInitPara.flashtype = FLASH_MXIC; - else if( SpicInitPara.id[0] == 0xEF ) - SpicInitPara.flashtype = FLASH_WINBOND; - else - SpicInitPara.flashtype = FLASH_OTHERS; + /* Send flash RX command and read the data */ + SpicRxCmdRefinedRtl8195A(FLASH_CMD_RDID, SpicInitPara); + RdData = HAL_SPI_READ32(REG_SPIC_DR0); - break; + SpicInitPara.id[0] = RdData & 0xFF; + SpicInitPara.id[1] = (RdData>> 8) & 0xFF; + SpicInitPara.id[2] = (RdData>>16) & 0xFF; + for(RetryNum =0; RetryNum < 3; RetryNum++){ + if((SpicInitPara.id[0] != 0) && (SpicInitPara.id[0] != 0xFF)){ + if(SpicInitPara.id[0] == 0x20) + SpicInitPara.flashtype = FLASH_MICRON; + else if(SpicInitPara.id[0] == 0xC2) + SpicInitPara.flashtype = FLASH_MXIC; + else if(SpicInitPara.id[0] == 0xEF) + SpicInitPara.flashtype = FLASH_WINBOND; + else + SpicInitPara.flashtype = FLASH_OTHERS; + break; + } + else{ + if(RetryNum == 2) + DBG_8195A("Invalid ID\n"); + } } - else - { - if( RetryNum == 2 ) - DBG_8195A( "Invalid ID\n" ); + for(i=0;i<3;i++) { + for (j=0; j> 4 ); + + u32 rd_data, /*id_no,*/ baudr, autolen, dly_line; + u32 total_ava_wds=0; + u32 tmp_str_pt, tmp_end_pt, pass, last_pass; + struct ava_window max_wd; + u32 CpuType; + SPIC_INIT_PARA SpicInitPara; + + CpuType = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70)) >> 4); + #if SPIC_CALIBRATION_IN_NVM - - if ( !SpicInitParaAllClk[SpicBitMode][CpuType].Valid ) - { - SpicNVMCalLoad( SpicBitMode, CpuType ); - } - -#endif - - if ( SpicInitParaAllClk[SpicBitMode][CpuType].Valid ) - { - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - HAL_SPI_WRITE32( REG_SPIC_BAUDR, - ( SpicInitParaAllClk[SpicBitMode][CpuType].BaudRate & 0x00000FFF ) ); - rd_data = HAL_SPI_READ32( REG_SPIC_AUTO_LENGTH ); - rd_data = ( rd_data & 0xFFFF0000 ) | ( SpicInitParaAllClk[SpicBitMode][CpuType].RdDummyCyle & - 0x0000FFFF ); - HAL_SPI_WRITE32( REG_SPIC_AUTO_LENGTH, rd_data ); - rd_data = SpicInitParaAllClk[SpicBitMode][CpuType].DelayLine; - WR_DATA( SPI_DLY_CTRL_ADDR, ( ( RD_DATA( SPI_DLY_CTRL_ADDR ) & 0xFFFFFF00 ) | - ( rd_data & 0x000000FF ) ) ); - // Enable SPI_FLASH User Mode - HAL_SPI_WRITE32( REG_SPIC_SSIENR, BIT_SPIC_EN ); - SpicWaitWipDoneRefinedRtl8195A( SpicInitPara ); - pass = SpicCmpDataForCalibrationRtl8195A(); - - if ( pass ) - { - // Check the Magic Pattern OK - return 1; + if (!SpicInitParaAllClk[SpicBitMode][CpuType].Valid) { + SpicNVMCalLoad(SpicBitMode, CpuType); } - } - - // calibration - DBG_8195A( "SPI calibration\n" ); - max_wd.auto_length = 0; - max_wd.baud_rate = 0; - max_wd.dly_line_ep = 0; - max_wd.dly_line_sp = 0; - - for( baudr = MIN_BAUDRATE; baudr < ( MAX_BAUDRATE + 1 ); baudr++ ) - { - // Disable SPI_FLASH User Mode - if( baudr == MIN_BAUDRATE ) - if( SpicBitMode == SpicOneBitMode ) - continue; - - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - HAL_SPI_WRITE32( REG_SPIC_BAUDR, BIT_SCKDV( baudr ) ); - // Enable SPI_FLASH User Mode - HAL_SPI_WRITE32( REG_SPIC_SSIENR, BIT_SPIC_EN ); - //DBG_8195A("(0x14)Baudr: 0x%x\n",HAL_SPI_READ32(REG_SPIC_BAUDR)); - - for( autolen = ( DefRdDummyCycle * 2 * baudr ); - autolen < ( DefRdDummyCycle * 2 * baudr + MAX_AUTOLEN ); autolen++ ) - { - // Disable SPI_FLASH User Mode - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - rd_data = HAL_SPI_READ32( REG_SPIC_AUTO_LENGTH ); - rd_data = ( rd_data & 0xFFFF0000 ) | ( 0x0000FFFF & autolen ); - HAL_SPI_WRITE32( REG_SPIC_AUTO_LENGTH, rd_data ); - // Enable SPI_FLASH User Mode - HAL_SPI_WRITE32( REG_SPIC_SSIENR, BIT_SPIC_EN ); - //DBG_8195A("Auto length: 0x%x\n",autolen); - //DBG_8195A("(0x11C) Auto address length register: 0x%x\n",HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH)); - tmp_str_pt = MAX_DLYLINE; - tmp_end_pt = 0; - last_pass = 0; - - for( dly_line = 0; dly_line <= MAX_DLYLINE; dly_line++ ) - { - rd_data = RD_DATA( SPI_DLY_CTRL_ADDR ); - rd_data = ( rd_data & 0xFFFFFF00 ) | ( dly_line & 0x000000FF ); - WR_DATA( SPI_DLY_CTRL_ADDR, rd_data ); - //DBG_8195A("SPI_DLY_CTRL_ADDR: 0x%x\n",RD_DATA(SPI_DLY_CTRL_ADDR)); +#endif + if (SpicInitParaAllClk[SpicBitMode][CpuType].Valid) { + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + HAL_SPI_WRITE32(REG_SPIC_BAUDR, (SpicInitParaAllClk[SpicBitMode][CpuType].BaudRate & 0x00000FFF)); + rd_data = HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH); + rd_data = (rd_data & 0xFFFF0000) | (SpicInitParaAllClk[SpicBitMode][CpuType].RdDummyCyle & 0x0000FFFF); + HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, rd_data); + rd_data = SpicInitParaAllClk[SpicBitMode][CpuType].DelayLine; + WR_DATA(SPI_DLY_CTRL_ADDR, ((RD_DATA(SPI_DLY_CTRL_ADDR) & 0xFFFFFF00) | (rd_data & 0x000000FF))); + // Enable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN); + SpicWaitWipDoneRefinedRtl8195A(SpicInitPara); pass = SpicCmpDataForCalibrationRtl8195A(); - - if( pass ) // PASS - { - if( last_pass == 0 ) - { - tmp_str_pt = dly_line; - total_ava_wds++; - } - - if( dly_line == MAX_DLYLINE ) - { - tmp_end_pt = dly_line; - - if( total_ava_wds == 1 ) - { - max_wd.baud_rate = baudr; - max_wd.auto_length = autolen; - max_wd.dly_line_sp = tmp_str_pt; - max_wd.dly_line_ep = tmp_end_pt; - } - else - { - if( ( tmp_end_pt - tmp_str_pt ) > ( max_wd.dly_line_ep - max_wd.dly_line_sp ) ) - { - max_wd.baud_rate = baudr; - max_wd.auto_length = autolen; - max_wd.dly_line_sp = tmp_str_pt; - max_wd.dly_line_ep = tmp_end_pt; - } - } - } - - last_pass = 1; + if (pass) { + // Check the Magic Pattern OK + return 1; } - else // FAIL - { - if( last_pass == 1 ) - { - tmp_end_pt = dly_line; - - if( total_ava_wds == 1 ) - { - max_wd.baud_rate = baudr; - max_wd.auto_length = autolen; - max_wd.dly_line_sp = tmp_str_pt; - max_wd.dly_line_ep = tmp_end_pt; - } - else - { - if( ( tmp_end_pt - tmp_str_pt ) > ( max_wd.dly_line_ep - max_wd.dly_line_sp ) ) - { - max_wd.baud_rate = baudr; - max_wd.auto_length = autolen; - max_wd.dly_line_sp = tmp_str_pt; - max_wd.dly_line_ep = tmp_end_pt; - } - } - } - - last_pass = 0; - } - } - - //DBG_8195A("total wds: %d\n",total_ava_wds); - //DBG_8195A("Baud:%x; auto_length:%x; Delay start:%x; Delay end:%x\n",max_wd.baud_rate, max_wd.auto_length,max_wd.dly_line_sp, max_wd.dly_line_ep); } - if ( total_ava_wds ) - { - DBG_8195A( "Find the avaiable window\n" ); - break; - } - } + // calibration + DBG_8195A("SPI calibration\n"); - if( total_ava_wds == 0 ) - { - return 0; - } - else - { - // set baudr, auto_length, and delay_line - DBG_8195A( "Baud:%x; auto_length:%x; Delay start:%x; Delay end:%x\n", max_wd.baud_rate, - max_wd.auto_length, max_wd.dly_line_sp, max_wd.dly_line_ep ); - // Disable SPI_FLASH User Mode - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - HAL_SPI_WRITE32( REG_SPIC_BAUDR, ( max_wd.baud_rate & 0x00000FFF ) ); - SpicInitParaAllClk[SpicBitMode][CpuType].BaudRate = max_wd.baud_rate; - rd_data = HAL_SPI_READ32( REG_SPIC_AUTO_LENGTH ); - rd_data = ( rd_data & 0xFFFF0000 ) | ( max_wd.auto_length & 0x0000FFFF ); - HAL_SPI_WRITE32( REG_SPIC_AUTO_LENGTH, rd_data ); - SpicInitParaAllClk[SpicBitMode][CpuType].RdDummyCyle = max_wd.auto_length; - rd_data = ( ( max_wd.dly_line_sp + max_wd.dly_line_ep ) >> 1 ); - WR_DATA( SPI_DLY_CTRL_ADDR, ( ( RD_DATA( SPI_DLY_CTRL_ADDR ) & 0xFFFFFF00 ) | - ( rd_data & 0x000000FF ) ) ); - SpicInitParaAllClk[SpicBitMode][CpuType].DelayLine = rd_data; - SpicInitParaAllClk[SpicBitMode][CpuType].Valid = 1; - // Enable SPI_FLASH User Mode - HAL_SPI_WRITE32( REG_SPIC_SSIENR, BIT_SPIC_EN ); - SpicWaitWipDoneRefinedRtl8195A( SpicInitPara ); -#if SPIC_CALIBRATION_IN_NVM - SpicNVMCalStore( SpicBitMode, CpuType ); + max_wd.auto_length = 0; + max_wd.baud_rate = 0; + max_wd.dly_line_ep = 0; + max_wd.dly_line_sp = 0; + + for(baudr=MIN_BAUDRATE; baudr < (MAX_BAUDRATE+1); baudr++) { + // Disable SPI_FLASH User Mode + if(baudr == MIN_BAUDRATE) + if(SpicBitMode == SpicOneBitMode) + continue; + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + HAL_SPI_WRITE32(REG_SPIC_BAUDR, BIT_SCKDV(baudr)); + // Enable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN); + //DBG_8195A("(0x14)Baudr: 0x%x\n",HAL_SPI_READ32(REG_SPIC_BAUDR)); + + for(autolen=(DefRdDummyCycle*2*baudr); autolen<(DefRdDummyCycle*2*baudr+MAX_AUTOLEN); autolen++) { + // Disable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + rd_data = HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH); + rd_data = (rd_data & 0xFFFF0000) | (0x0000FFFF & autolen); + HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, rd_data); + // Enable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN); + //DBG_8195A("Auto length: 0x%x\n",autolen); + //DBG_8195A("(0x11C) Auto address length register: 0x%x\n",HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH)); + tmp_str_pt = MAX_DLYLINE; + tmp_end_pt = 0; + last_pass = 0; + + for(dly_line=0; dly_line<=MAX_DLYLINE; dly_line++) { + rd_data = RD_DATA(SPI_DLY_CTRL_ADDR); + rd_data = (rd_data & 0xFFFFFF00) | (dly_line & 0x000000FF); + WR_DATA(SPI_DLY_CTRL_ADDR, rd_data); + //DBG_8195A("SPI_DLY_CTRL_ADDR: 0x%x\n",RD_DATA(SPI_DLY_CTRL_ADDR)); + + pass = SpicCmpDataForCalibrationRtl8195A(); + + + if(pass) { // PASS + if(last_pass==0) { + tmp_str_pt = dly_line; + total_ava_wds++; + } + + if(dly_line==MAX_DLYLINE) { + + tmp_end_pt = dly_line; + + if(total_ava_wds==1) { + max_wd.baud_rate = baudr; + max_wd.auto_length = autolen; + max_wd.dly_line_sp = tmp_str_pt; + max_wd.dly_line_ep = tmp_end_pt; + } + else { + if((tmp_end_pt-tmp_str_pt)>(max_wd.dly_line_ep-max_wd.dly_line_sp)) { + max_wd.baud_rate = baudr; + max_wd.auto_length = autolen; + max_wd.dly_line_sp = tmp_str_pt; + max_wd.dly_line_ep = tmp_end_pt; + } + } + } + last_pass = 1; + } + else { // FAIL + if(last_pass==1) { + tmp_end_pt = dly_line; + if(total_ava_wds == 1) { + max_wd.baud_rate = baudr; + max_wd.auto_length = autolen; + max_wd.dly_line_sp = tmp_str_pt; + max_wd.dly_line_ep = tmp_end_pt; + } + else { + if((tmp_end_pt-tmp_str_pt)>(max_wd.dly_line_ep-max_wd.dly_line_sp)) { + max_wd.baud_rate = baudr; + max_wd.auto_length = autolen; + max_wd.dly_line_sp = tmp_str_pt; + max_wd.dly_line_ep = tmp_end_pt; + } + } + } + last_pass = 0; + } + } +#if CONFIG_DEBUG_LOG > 4 + DBG_8195A("total wds: %d\n",total_ava_wds); + DBG_8195A("Baud:%x; auto_length:%x; Delay start:%x; Delay end:%x\n",max_wd.baud_rate, max_wd.auto_length,max_wd.dly_line_sp, max_wd.dly_line_ep); #endif - return 1; - } + } + if (total_ava_wds) { + DBG_8195A("Find the avaiable window\n"); + break; + } + + } + + + if(total_ava_wds==0) { + return 0; + } + else { + // set baudr, auto_length, and delay_line + DBG_8195A("Baud:%x; auto_length:%x; Delay start:%x; Delay end:%x\n",max_wd.baud_rate, max_wd.auto_length,max_wd.dly_line_sp, max_wd.dly_line_ep); + // Disable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + HAL_SPI_WRITE32(REG_SPIC_BAUDR, (max_wd.baud_rate & 0x00000FFF)); + SpicInitParaAllClk[SpicBitMode][CpuType].BaudRate = max_wd.baud_rate; + rd_data = HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH); + rd_data = (rd_data & 0xFFFF0000) | (max_wd.auto_length & 0x0000FFFF); + HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, rd_data); + SpicInitParaAllClk[SpicBitMode][CpuType].RdDummyCyle = max_wd.auto_length; + rd_data = ((max_wd.dly_line_sp + max_wd.dly_line_ep) >> 1); + WR_DATA(SPI_DLY_CTRL_ADDR, ((RD_DATA(SPI_DLY_CTRL_ADDR) & 0xFFFFFF00) | (rd_data & 0x000000FF))); + SpicInitParaAllClk[SpicBitMode][CpuType].DelayLine = rd_data; + SpicInitParaAllClk[SpicBitMode][CpuType].Valid = 1; + // Enable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN); + SpicWaitWipDoneRefinedRtl8195A(SpicInitPara); +#if SPIC_CALIBRATION_IN_NVM + SpicNVMCalStore(SpicBitMode, CpuType); +#endif + return 1; + } + } HAL_FLASH_TEXT_SECTION -VOID +VOID SpicConfigAutoModeRtl8195A ( - IN u8 SpicBitMode -) + IN u8 SpicBitMode +) { - // Disable SPI_FLASH User Mode - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - if ( SpicOneBitMode == SpicBitMode ) - { - // set write cmd (ppiix4: 0x38) - HAL_SPI_WRITE32( REG_SPIC_WRITE_QUAD_ADDR_DATA, 0x38 ); - // set read cmd (readiox4: 0xEB) - HAL_SPI_WRITE32( REG_SPIC_READ_QUAD_ADDR_DATA, 0xEB ); - HAL_SPI_WRITE32( REG_SPIC_VALID_CMD, - ( HAL_SPI_READ32( REG_SPIC_VALID_CMD ) & ( ~( - BIT_WR_QUAD_II | - BIT_WR_QUAD_I | - BIT_WR_DUAL_II | - BIT_WR_DUAL_I | - BIT_RD_QUAD_IO | - BIT_RD_QUAD_O | - BIT_RD_DUAL_IO | - BIT_RD_DUAL_I ) ) ) ); //Disable all the four and two bit commands. - } - if ( SpicDualBitMode == SpicBitMode ) - { -#if FLASH_RD_2IO_EN - HAL_SPI_WRITE32( REG_SPIC_READ_DUAL_ADDR_DATA, FLASH_CMD_2READ ); -#endif -#if FLASH_RD_2O_EN - HAL_SPI_WRITE32( REG_SPIC_READ_DUAL_DATA, FLASH_CMD_DREAD ); -#endif - HAL_SPI_WRITE32( REG_SPIC_VALID_CMD, - ( HAL_SPI_READ32( REG_SPIC_VALID_CMD ) | ( FLASH_VLD_DUAL_CMDS ) ) ); - } + // Disable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); - if ( SpicQuadBitMode == SpicBitMode ) - { -#if FLASH_WR_4IO_EN - HAL_SPI_WRITE32( REG_SPIC_WRITE_QUAD_ADDR_DATA, FLASH_CMD_4PP ); -#endif -#if FLASH_RD_4IO_EN - HAL_SPI_WRITE32( REG_SPIC_READ_QUAD_ADDR_DATA, FLASH_CMD_4READ ); -#endif -#if FLASH_RD_4O_EN - HAL_SPI_WRITE32( REG_SPIC_READ_QUAD_DATA, FLASH_CMD_QREAD ); -#endif - HAL_SPI_WRITE32( REG_SPIC_VALID_CMD, - ( HAL_SPI_READ32( REG_SPIC_VALID_CMD ) | FLASH_VLD_QUAD_CMDS ) ); - } + if (SpicOneBitMode == SpicBitMode) { + + // set write cmd (ppiix4: 0x38) + HAL_SPI_WRITE32(REG_SPIC_WRITE_QUAD_ADDR_DATA, 0x38); + + // set read cmd (readiox4: 0xEB) + HAL_SPI_WRITE32(REG_SPIC_READ_QUAD_ADDR_DATA, 0xEB); + + HAL_SPI_WRITE32(REG_SPIC_VALID_CMD, + (HAL_SPI_READ32(REG_SPIC_VALID_CMD) & (~( + BIT_WR_QUAD_II | + BIT_WR_QUAD_I | + BIT_WR_DUAL_II | + BIT_WR_DUAL_I | + BIT_RD_QUAD_IO | + BIT_RD_QUAD_O | + BIT_RD_DUAL_IO | + BIT_RD_DUAL_I))));//Disable all the four and two bit commands. + } + + + if (SpicDualBitMode == SpicBitMode) { + #if FLASH_RD_2IO_EN + HAL_SPI_WRITE32(REG_SPIC_READ_DUAL_ADDR_DATA, FLASH_CMD_2READ); + #endif + + #if FLASH_RD_2O_EN + HAL_SPI_WRITE32(REG_SPIC_READ_DUAL_DATA, FLASH_CMD_DREAD); + #endif + + HAL_SPI_WRITE32(REG_SPIC_VALID_CMD, + (HAL_SPI_READ32(REG_SPIC_VALID_CMD)|(FLASH_VLD_DUAL_CMDS))); + + } + + if (SpicQuadBitMode == SpicBitMode) { + #if FLASH_WR_4IO_EN + HAL_SPI_WRITE32(REG_SPIC_WRITE_QUAD_ADDR_DATA, FLASH_CMD_4PP); + #endif + + #if FLASH_RD_4IO_EN + HAL_SPI_WRITE32(REG_SPIC_READ_QUAD_ADDR_DATA, FLASH_CMD_4READ); + #endif + + #if FLASH_RD_4O_EN + HAL_SPI_WRITE32(REG_SPIC_READ_QUAD_DATA, FLASH_CMD_QREAD); + #endif + + HAL_SPI_WRITE32(REG_SPIC_VALID_CMD, + (HAL_SPI_READ32(REG_SPIC_VALID_CMD)|FLASH_VLD_QUAD_CMDS)); + } + + } @@ -918,69 +885,72 @@ SpicConfigAutoModeRtl8195A * * @retval NA */ -HAL_FLASH_TEXT_SECTION -VOID +HAL_FLASH_TEXT_SECTION +VOID SpicWaitWipDoneRefinedRtl8195A( - IN SPIC_INIT_PARA SpicInitPara -) -{ - DBG_SPIF_INFO( "%s(0x%x)\n", __func__, SpicInitPara ); - - do - { - } - while( ( SpicGetFlashStatusRefinedRtl8195A( SpicInitPara ) & 0x01 ) ); + IN SPIC_INIT_PARA SpicInitPara +){ +#if CONFIG_DEBUG_LOG > 4 + DBG_SPIF_INFO("%s(0x%x)\n", __func__, SpicInitPara); +#endif + do { + } while((SpicGetFlashStatusRefinedRtl8195A(SpicInitPara) & 0x01)); } #if 1 HAL_FLASH_TEXT_SECTION -u8 +u8 SpicGetFlashFlagRtl8195A ( - IN SPIC_INIT_PARA SpicInitPara + IN SPIC_INIT_PARA SpicInitPara ) { - u32 RdData; - DBG_SPIF_INFO( "%s(0x%x)\n", __func__, SpicInitPara ); - /* Disable SPI_FLASH User Mode */ - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - /* Set Ctrlr1; 1 byte data frames */ - HAL_SPI_WRITE32( REG_SPIC_CTRLR1, BIT_NDF( 1 ) ); - /* Send flash RX command and read the data */ - SpicRxCmdRefinedRtl8195A( 0x70, SpicInitPara ); - RdData = HAL_SPI_READ8( REG_SPIC_DR0 ); - /* Disable SPI_FLASH User Mode */ - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - if( RdData & 0x2 ) - { - DBG_SPIF_WARN( "Attempts to Program / Erase Protected Area.\n" ); - SpicTxCmdWithDataRtl8195A( 0x50, 0, 0, - SpicInitPara ); //Clear Error Bit & Write Enable of Flag Status Register - } + u32 RdData; + +#if CONFIG_DEBUG_LOG > 4 + DBG_SPIF_INFO("%s(0x%x)\n", __func__, SpicInitPara); +#endif + /* Disable SPI_FLASH User Mode */ + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + + /* Set Ctrlr1; 1 byte data frames */ + HAL_SPI_WRITE32(REG_SPIC_CTRLR1, BIT_NDF(1)); + + /* Send flash RX command and read the data */ + SpicRxCmdRefinedRtl8195A(0x70, SpicInitPara); + RdData = HAL_SPI_READ8(REG_SPIC_DR0); + + /* Disable SPI_FLASH User Mode */ + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + + if(RdData & 0x2){ + DBG_SPIF_WARN("Attempts to Program / Erase Protected Area.\n"); + SpicTxCmdWithDataRtl8195A(0x50, 0, 0, SpicInitPara);//Clear Error Bit & Write Enable of Flag Status Register + } + +return RdData; - return RdData; } HAL_FLASH_TEXT_SECTION -VOID +VOID SpicWaitOperationDoneRtl8195A ( - IN SPIC_INIT_PARA SpicInitPara -) + IN SPIC_INIT_PARA SpicInitPara +) { - DBG_SPIF_INFO( "%s(0x%x)\n", __func__, SpicInitPara ); - - do - { - } - while( !( SpicGetFlashFlagRtl8195A( SpicInitPara ) & 0x80 ) ); +#if CONFIG_DEBUG_LOG > 4 + DBG_SPIF_INFO("%s(0x%x)\n", __func__, SpicInitPara); +#endif + do { + } while(!(SpicGetFlashFlagRtl8195A(SpicInitPara) & 0x80)); } #endif /** - * @brief SpicRxCmdRefinedRtl8195A. To send flash RX command. + * @brief SpicRxCmdRefinedRtl8195A. To send flash RX command. * Timing store/restore is implemented inside. * * @param IN u8 cmd: flash RX command @@ -988,92 +958,101 @@ SpicWaitOperationDoneRtl8195A * @retval NA */ HAL_FLASH_TEXT_SECTION -VOID +VOID SpicRxCmdRefinedRtl8195A( - IN u8 cmd, - IN SPIC_INIT_PARA SpicInitPara -) -{ - u32 RdDummyCycle; - u32 BaudRate; - u32 BaudRate12bit; - u32 DelayLine; - u32 DelayLine8bit; - u32 AutoLength = 0; - u8 CpuClk = ( ( HAL_READ32( SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1 ) & ( 0x70 ) ) >> 4 ); - PSPIC_INIT_PARA PSpicInitParaLocal = NULL; - SPIC_INIT_PARA TmpSpicInitPara; + IN u8 cmd, + IN SPIC_INIT_PARA SpicInitPara +){ + u32 RdDummyCycle; + u32 BaudRate; + u32 BaudRate12bit; + u32 DelayLine; + u32 DelayLine8bit; + + u32 AutoLength = 0; + u8 CpuClk = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70)) >> 4); + PSPIC_INIT_PARA PSpicInitParaLocal = NULL; + SPIC_INIT_PARA TmpSpicInitPara; + #ifdef CONFIG_FPGA - PSpicInitParaLocal = &TmpSpicInitPara; - PSpicInitParaLocal->BaudRate = FPGASpicInitPara.BaudRate; - PSpicInitParaLocal->RdDummyCyle = FPGASpicInitPara.RdDummyCyle; - PSpicInitParaLocal->DelayLine = FPGASpicInitPara.DelayLine; + PSpicInitParaLocal = &TmpSpicInitPara; + PSpicInitParaLocal->BaudRate = FPGASpicInitPara.BaudRate; + PSpicInitParaLocal->RdDummyCyle = FPGASpicInitPara.RdDummyCyle; + PSpicInitParaLocal->DelayLine = FPGASpicInitPara.DelayLine; #else - if ( SpicInitParaAllClk[SpicOneBitMode][CpuClk].Valid ) - { - PSpicInitParaLocal = &( SpicInitParaAllClk[SpicOneBitMode][CpuClk] ); - } - else - { - PSpicInitParaLocal = &TmpSpicInitPara; - SpicLoadInitParaFromClockRtl8195A( CpuClk, 1, PSpicInitParaLocal ); - } + if (SpicInitParaAllClk[SpicOneBitMode][CpuClk].Valid) { + PSpicInitParaLocal = &(SpicInitParaAllClk[SpicOneBitMode][CpuClk]); + } + else { + PSpicInitParaLocal = &TmpSpicInitPara; + SpicLoadInitParaFromClockRtl8195A(CpuClk, 1, PSpicInitParaLocal); + } +#endif +#if CONFIG_DEBUG_LOG > 4 + DBG_8195A("!cpuclk:%x\n",CpuClk); + DBG_8195A("!baud:%x\n",PSpicInitParaLocal->BaudRate); + DBG_8195A("!delay:%x\n",PSpicInitParaLocal->DelayLine); + DBG_8195A("!dummy:%x\n",PSpicInitParaLocal->RdDummyCyle); + + DBG_SPIF_INFO("%s(0x%x, 0x%x)\n", __func__, cmd, PSpicInitParaLocal); #endif -#if 0 - DBG_8195A( "!cpuclk:%x\n", CpuClk ); - DBG_8195A( "!baud:%x\n", PSpicInitParaLocal->BaudRate ); - DBG_8195A( "!delay:%x\n", PSpicInitParaLocal->DelayLine ); - DBG_8195A( "!dummy:%x\n", PSpicInitParaLocal->RdDummyCyle ); -#endif - DBG_SPIF_INFO( "%s(0x%x, 0x%x)\n", __func__, cmd, PSpicInitParaLocal ); - /* Store rd_dummy_cycle */ - AutoLength = HAL_SPI_READ32( REG_SPIC_AUTO_LENGTH ); - RdDummyCycle = AutoLength & BIT_MASK_RD_DUMMY_LENGTH; - HAL_SPI_WRITE32( REG_SPIC_AUTO_LENGTH, - ( ( AutoLength & ( ~BIT_MASK_RD_DUMMY_LENGTH ) ) | ( PSpicInitParaLocal->RdDummyCyle ) ) ); - /* Store baud rate */ - BaudRate = HAL_SPI_READ32( REG_SPIC_BAUDR ); - BaudRate12bit = ( BaudRate & BIT_MASK_SCKDV ); - HAL_SPI_WRITE32( REG_SPIC_BAUDR, - ( ( BaudRate & ( ~BIT_MASK_SCKDV ) ) | ( PSpicInitParaLocal->BaudRate ) ) ); - /* Store delay line */ - DelayLine = HAL_READ32( SYSTEM_CTRL_BASE, REG_PESOC_MEM_CTRL ); - DelayLine8bit = ( DelayLine & BIT_MASK_PESOC_FLASH_DDL_CTRL ); - HAL_WRITE32( SYSTEM_CTRL_BASE, REG_PESOC_MEM_CTRL, - ( ( DelayLine & ( ~BIT_MASK_PESOC_FLASH_DDL_CTRL ) ) | ( PSpicInitParaLocal->DelayLine ) ) ); - //HAL_WRITE32(SYSTEM_CTRL_BASE, REG_PESOC_MEM_CTRL, ((DelayLine & (~BIT_MASK_PESOC_FLASH_DDL_CTRL))|DelayLine8bit)); - /* Disable SPI_FLASH User Mode */ - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - /* set ctrlr0: RX_mode */ - HAL_SPI_WRITE32( REG_SPIC_CTRLR0, - ( ( HAL_SPI_READ32( REG_SPIC_CTRLR0 ) & 0xFFF0FFFF ) | BIT_TMOD( 3 ) ) ); - /* set flash_cmd: write cmd to fifo */ - HAL_SPI_WRITE8( REG_SPIC_DR0, cmd ); - /* Enable SPI_FLASH User Mode */ - HAL_SPI_WRITE32( REG_SPIC_SSIENR, BIT_SPIC_EN ); - /* Wait spic busy done */ - SpicWaitBusyDoneRtl8195A(); - /* Disable SPI_FLASH User Mode */ - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - /* Recover rd_dummy_cycle */ - AutoLength = HAL_SPI_READ32( REG_SPIC_AUTO_LENGTH ); - AutoLength = AutoLength & 0xFFFF0000; - HAL_SPI_WRITE32( REG_SPIC_AUTO_LENGTH, ( AutoLength | RdDummyCycle ) ); - /* Recover baud rate */ - BaudRate = HAL_SPI_READ32( REG_SPIC_BAUDR ); - BaudRate = ( BaudRate & ( ~BIT_MASK_SCKDV ) ); - HAL_SPI_WRITE32( REG_SPIC_BAUDR, ( BaudRate | BaudRate12bit ) ); - /* Recover delay line */ - DelayLine = HAL_READ32( SYSTEM_CTRL_BASE, REG_PESOC_MEM_CTRL ); - DelayLine = ( DelayLine & ( ~BIT_MASK_PESOC_FLASH_DDL_CTRL ) ); - HAL_WRITE32( SYSTEM_CTRL_BASE, REG_PESOC_MEM_CTRL, ( DelayLine | DelayLine8bit ) ); + + /* Store rd_dummy_cycle */ + AutoLength = HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH); + RdDummyCycle = AutoLength & BIT_MASK_RD_DUMMY_LENGTH; + HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, ((AutoLength & (~BIT_MASK_RD_DUMMY_LENGTH))|(PSpicInitParaLocal->RdDummyCyle))); + + /* Store baud rate */ + BaudRate = HAL_SPI_READ32(REG_SPIC_BAUDR); + BaudRate12bit = (BaudRate & BIT_MASK_SCKDV); + HAL_SPI_WRITE32(REG_SPIC_BAUDR,((BaudRate & (~BIT_MASK_SCKDV))|(PSpicInitParaLocal->BaudRate))); + + /* Store delay line */ + DelayLine = HAL_READ32(SYSTEM_CTRL_BASE, REG_PESOC_MEM_CTRL); + DelayLine8bit = (DelayLine & BIT_MASK_PESOC_FLASH_DDL_CTRL); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_PESOC_MEM_CTRL, ((DelayLine & (~BIT_MASK_PESOC_FLASH_DDL_CTRL))|(PSpicInitParaLocal->DelayLine))); + //HAL_WRITE32(SYSTEM_CTRL_BASE, REG_PESOC_MEM_CTRL, ((DelayLine & (~BIT_MASK_PESOC_FLASH_DDL_CTRL))|DelayLine8bit)); + + /* Disable SPI_FLASH User Mode */ + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + + /* set ctrlr0: RX_mode */ + HAL_SPI_WRITE32(REG_SPIC_CTRLR0, + ((HAL_SPI_READ32(REG_SPIC_CTRLR0)&0xFFF0FFFF) | BIT_TMOD(3))); + + /* set flash_cmd: write cmd to fifo */ + HAL_SPI_WRITE8(REG_SPIC_DR0, cmd); + + /* Enable SPI_FLASH User Mode */ + HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN); + + /* Wait spic busy done */ + SpicWaitBusyDoneRtl8195A(); + + /* Disable SPI_FLASH User Mode */ + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + + /* Recover rd_dummy_cycle */ + AutoLength = HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH); + AutoLength = AutoLength & 0xFFFF0000; + HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, (AutoLength | RdDummyCycle)); + + /* Recover baud rate */ + BaudRate = HAL_SPI_READ32(REG_SPIC_BAUDR); + BaudRate = (BaudRate & (~BIT_MASK_SCKDV)); + HAL_SPI_WRITE32(REG_SPIC_BAUDR, (BaudRate|BaudRate12bit)); + + /* Recover delay line */ + DelayLine = HAL_READ32(SYSTEM_CTRL_BASE, REG_PESOC_MEM_CTRL); + DelayLine = (DelayLine & (~BIT_MASK_PESOC_FLASH_DDL_CTRL)); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_PESOC_MEM_CTRL, (DelayLine|DelayLine8bit)); } /** * @brief SpicGetFlashStatusRefinedRtl8195A. For the exchange between one- and two- - * bit mode, the spic timing setting (baud, rd_dummy_cycle (ATUO_LENGTH) + * bit mode, the spic timing setting (baud, rd_dummy_cycle (ATUO_LENGTH) * and delay line) should be changed according to the mode used. * * @param IN SPIC_INIT_PARA SpicInitPara: spic init parameters with timing setting @@ -1081,183 +1060,206 @@ SpicRxCmdRefinedRtl8195A( * @retval u8 flash status register value */ HAL_FLASH_TEXT_SECTION -u8 +u8 SpicGetFlashStatusRefinedRtl8195A( - IN SPIC_INIT_PARA SpicInitPara -) -{ - u32 RdData; - DBG_SPIF_INFO( "%s(0x%x)\n", __func__, SpicInitPara ); - /* Disable SPI_FLASH User Mode */ - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - /* Set Ctrlr1; 1 byte data frames */ - HAL_SPI_WRITE32( REG_SPIC_CTRLR1, BIT_NDF( 1 ) ); - /* Send flash RX command and read the data */ - SpicRxCmdRefinedRtl8195A( FLASH_CMD_RDSR, SpicInitPara ); - RdData = HAL_SPI_READ8( REG_SPIC_DR0 ); - /* Disable SPI_FLASH User Mode */ - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - return RdData; + IN SPIC_INIT_PARA SpicInitPara +){ + + u32 RdData; + + DBG_SPIF_INFO("%s(0x%x)\n", __func__, SpicInitPara); + + /* Disable SPI_FLASH User Mode */ + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + + /* Set Ctrlr1; 1 byte data frames */ + HAL_SPI_WRITE32(REG_SPIC_CTRLR1, BIT_NDF(1)); + + /* Send flash RX command and read the data */ + SpicRxCmdRefinedRtl8195A(FLASH_CMD_RDSR, SpicInitPara); + RdData = HAL_SPI_READ8(REG_SPIC_DR0); + + /* Disable SPI_FLASH User Mode */ + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + + return RdData; } /** - * @brief SpicInitRefinedRtl8195A. + * @brief SpicInitRefinedRtl8195A. * * @param IN u8 InitBaudRate, * IN u8 SpicBitMode * * @retval NA - */ + */ HAL_FLASH_TEXT_SECTION -VOID +VOID SpicInitRefinedRtl8195A( - IN u8 InitBaudRate, - IN u8 SpicBitMode -) -{ - u32 Value32; - SPIC_INIT_PARA SpicInitPara; - PSPIC_INIT_PARA PSpicInitParaLocal; - PSpicInitParaLocal = &SpicInitPara; -#ifdef CONFIG_FPGA - PSpicInitParaLocal->BaudRate = FPGASpicInitPara.BaudRate; - PSpicInitParaLocal->RdDummyCyle = FPGASpicInitPara.RdDummyCyle; - PSpicInitParaLocal->DelayLine = FPGASpicInitPara.DelayLine; -#else - u8 CpuClk; - CpuClk = ( ( ( u8 )( HAL_READ32( SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1 ) & ( 0x70 ) ) ) >> 4 ); + IN u8 InitBaudRate, + IN u8 SpicBitMode +){ - if ( SpicInitParaAllClk[SpicBitMode][CpuClk].Valid ) - { - PSpicInitParaLocal = &( SpicInitParaAllClk[SpicBitMode][CpuClk] ); - } - else - { - SpicLoadInitParaFromClockRtl8195A( CpuClk, 1, PSpicInitParaLocal ); - } + u32 Value32; + SPIC_INIT_PARA SpicInitPara; + PSPIC_INIT_PARA PSpicInitParaLocal; + + PSpicInitParaLocal = &SpicInitPara; +#ifdef CONFIG_FPGA + PSpicInitParaLocal->BaudRate = FPGASpicInitPara.BaudRate; + PSpicInitParaLocal->RdDummyCyle = FPGASpicInitPara.RdDummyCyle; + PSpicInitParaLocal->DelayLine = FPGASpicInitPara.DelayLine; +#else + u8 CpuClk; + + CpuClk = (((u8)(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70))) >> 4); + + if (SpicInitParaAllClk[SpicBitMode][CpuClk].Valid) { + PSpicInitParaLocal = &(SpicInitParaAllClk[SpicBitMode][CpuClk]); + } + else { + SpicLoadInitParaFromClockRtl8195A(CpuClk, 1, PSpicInitParaLocal); + } #endif - // Disable SPI_FLASH User Mode - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - HAL_SPI_WRITE32( REG_SPIC_BAUDR, BIT_SCKDV( InitBaudRate ) ); - HAL_SPI_WRITE32( REG_SPIC_SER, BIT_SER ); - Value32 = HAL_SPI_READ32( REG_SPIC_AUTO_LENGTH ); - HAL_SPI_WRITE32( REG_SPIC_AUTO_LENGTH, - ( ( Value32 & 0xFFFF0000 ) | BIT_RD_DUMMY_LENGTH( PSpicInitParaLocal->RdDummyCyle ) ) ); - HAL_WRITE32( PERI_ON_BASE, REG_PESOC_MEM_CTRL, - ( ( HAL_READ32( PERI_ON_BASE, REG_PESOC_MEM_CTRL ) & 0xFFFFFF00 ) | - PSpicInitParaLocal->DelayLine ) ); - HAL_SPI_WRITE32( REG_SPIC_CTRLR1, BIT_NDF( 4 ) ); - switch ( SpicBitMode ) - { - case SpicOneBitMode: - HAL_SPI_WRITE32( REG_SPIC_CTRLR0, - ( HAL_SPI_READ32( REG_SPIC_CTRLR0 ) & ( ~( BIT_CMD_CH( 3 ) | BIT_ADDR_CH( 3 ) | BIT_DATA_CH( - 3 ) ) ) ) ); - break; + // Disable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); - case SpicDualBitMode: - HAL_SPI_WRITE32( REG_SPIC_CTRLR0, - ( ( HAL_SPI_READ32( REG_SPIC_CTRLR0 ) & ( ~( BIT_CMD_CH( 3 ) | BIT_ADDR_CH( 3 ) | BIT_DATA_CH( - 3 ) ) ) ) | - ( BIT_ADDR_CH( 1 ) | BIT_DATA_CH( 1 ) ) ) ); - break; + HAL_SPI_WRITE32(REG_SPIC_BAUDR, BIT_SCKDV(InitBaudRate)); - case SpicQuadBitMode: - HAL_SPI_WRITE32( REG_SPIC_CTRLR0, - ( ( HAL_SPI_READ32( REG_SPIC_CTRLR0 ) & ( ~( BIT_CMD_CH( 3 ) | BIT_ADDR_CH( 3 ) | BIT_DATA_CH( - 3 ) ) ) ) | - ( BIT_ADDR_CH( 2 ) | BIT_DATA_CH( 2 ) ) ) ); - break; - } + HAL_SPI_WRITE32(REG_SPIC_SER, BIT_SER); + + Value32 = HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH); + HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, + ((Value32 & 0xFFFF0000) | BIT_RD_DUMMY_LENGTH(PSpicInitParaLocal->RdDummyCyle))); + + HAL_WRITE32(PERI_ON_BASE, REG_PESOC_MEM_CTRL, + ((HAL_READ32(PERI_ON_BASE, REG_PESOC_MEM_CTRL)&0xFFFFFF00)| + PSpicInitParaLocal->DelayLine)); + + HAL_SPI_WRITE32(REG_SPIC_CTRLR1, BIT_NDF(4)); + + + switch (SpicBitMode) { + case SpicOneBitMode: + HAL_SPI_WRITE32(REG_SPIC_CTRLR0, + (HAL_SPI_READ32(REG_SPIC_CTRLR0) & (~(BIT_CMD_CH(3)|BIT_ADDR_CH(3)|BIT_DATA_CH(3))))); + break; + + case SpicDualBitMode: + HAL_SPI_WRITE32(REG_SPIC_CTRLR0, + ((HAL_SPI_READ32(REG_SPIC_CTRLR0) & (~(BIT_CMD_CH(3)|BIT_ADDR_CH(3)|BIT_DATA_CH(3)))) | + (BIT_ADDR_CH(1)|BIT_DATA_CH(1)))); + + break; + + case SpicQuadBitMode: + HAL_SPI_WRITE32(REG_SPIC_CTRLR0, + ((HAL_SPI_READ32(REG_SPIC_CTRLR0) & (~(BIT_CMD_CH(3)|BIT_ADDR_CH(3)|BIT_DATA_CH(3)))) | + (BIT_ADDR_CH(2)|BIT_DATA_CH(2)))); + break; + + } } /** - * @brief SpicEraseFlashRefinedRtl8195A. + * @brief SpicEraseFlashRefinedRtl8195A. * * @param NA * * @retval NA */ HAL_FLASH_TEXT_SECTION -VOID -SpicEraseFlashRefinedRtl8195A( VOID ) +VOID +SpicEraseFlashRefinedRtl8195A(VOID) { - SPIC_INIT_PARA SpicInitPara; - // Wait for flash busy done - SpicWaitWipDoneRefinedRtl8195A( SpicInitPara ); - while( ( SpicGetFlashStatusRefinedRtl8195A( SpicInitPara ) & 0x02 ) == 0 ) - { - // Set flash_cmd: WREN to FIFO - //SpicTxCmdRtl8195A(FLASH_CMD_WREN, SpicInitPara); - SpicTxCmdWithDataRtl8195A( FLASH_CMD_WREN, 0, 0, SpicInitPara ); - } + SPIC_INIT_PARA SpicInitPara; - DBG_8195A( "Erase Cmd Set\n" ); - // Set flash_cmd: Chip_erase to FIFO - //SpicTxCmdRtl8195A(FLASH_CMD_CE, SpicInitPara); - SpicTxCmdWithDataRtl8195A( FLASH_CMD_CE, 0, 0, SpicInitPara ); + // Wait for flash busy done + SpicWaitWipDoneRefinedRtl8195A(SpicInitPara); - // polling WEL - do - { - } - while( ( SpicGetFlashStatusRefinedRtl8195A( SpicInitPara ) & 0x02 ) != 0 ); + while((SpicGetFlashStatusRefinedRtl8195A(SpicInitPara) & 0x02)==0) { + // Set flash_cmd: WREN to FIFO + //SpicTxCmdRtl8195A(FLASH_CMD_WREN, SpicInitPara); + SpicTxCmdWithDataRtl8195A(FLASH_CMD_WREN, 0, 0, SpicInitPara); + } + + DBG_8195A("Erase Cmd Set\n"); + + // Set flash_cmd: Chip_erase to FIFO + //SpicTxCmdRtl8195A(FLASH_CMD_CE, SpicInitPara); + SpicTxCmdWithDataRtl8195A(FLASH_CMD_CE, 0, 0, SpicInitPara); + + // polling WEL + do { + } while((SpicGetFlashStatusRefinedRtl8195A(SpicInitPara) & 0x02)!=0); } /** - * @brief SpicSetFlashStatusRefinedRtl8195A. + * @brief SpicSetFlashStatusRefinedRtl8195A. * * @param NA * * @retval NA */ -HAL_FLASH_TEXT_SECTION -VOID +HAL_FLASH_TEXT_SECTION +VOID SpicSetFlashStatusRefinedRtl8195A ( - IN u32 data, - IN SPIC_INIT_PARA SpicInitPara + IN u32 data, + IN SPIC_INIT_PARA SpicInitPara ) { - u32 Info; - Info = HAL_SPI_READ32( REG_SPIC_ADDR_LENGTH ); - // Set flash_cmd: WREN to FIFO - //SpicTxCmdRtl8195A(FLASH_CMD_WREN, SpicInitPara); - SpicTxCmdWithDataRtl8195A( FLASH_CMD_WREN, 0, 0, SpicInitPara ); - // Disable SPI_FLASH - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - // set ctrlr0: TX mode - HAL_SPI_WRITE32( REG_SPIC_CTRLR0, - ( HAL_SPI_READ32( REG_SPIC_CTRLR0 ) & ( ~ BIT_TMOD( 3 ) ) ) ); - HAL_SPI_WRITE32( REG_SPIC_ADDR_LENGTH, BIT_ADDR_PHASE_LENGTH( 1 ) ); - // Set flash_cmd: WRSR to FIFO - HAL_SPI_WRITE8( REG_SPIC_DR0, BIT_DR0( FLASH_CMD_WRSR ) ); - // Set data FIFO - HAL_SPI_WRITE8( REG_SPIC_DR0, BIT_DR0( data ) ); - // Enable SPI_FLASH User Mode - HAL_SPI_WRITE32( REG_SPIC_SSIENR, BIT_SPIC_EN ); - // wait spic busy done - SpicWaitBusyDoneRtl8195A(); + u32 Info; - if( ( SpicInitParaAllClk[0][0].flashtype ) == FLASH_MICRON ) - SpicWaitOperationDoneRtl8195A( SpicInitPara ); - else - SpicWaitWipDoneRefinedRtl8195A( SpicInitPara ); + Info = HAL_SPI_READ32(REG_SPIC_ADDR_LENGTH); + + // Set flash_cmd: WREN to FIFO + //SpicTxCmdRtl8195A(FLASH_CMD_WREN, SpicInitPara); + SpicTxCmdWithDataRtl8195A(FLASH_CMD_WREN, 0, 0, SpicInitPara); + + // Disable SPI_FLASH + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + + // set ctrlr0: TX mode + HAL_SPI_WRITE32(REG_SPIC_CTRLR0, + (HAL_SPI_READ32(REG_SPIC_CTRLR0) & (~ BIT_TMOD(3)))); + + HAL_SPI_WRITE32(REG_SPIC_ADDR_LENGTH, BIT_ADDR_PHASE_LENGTH(1)); + + // Set flash_cmd: WRSR to FIFO + HAL_SPI_WRITE8(REG_SPIC_DR0, BIT_DR0(FLASH_CMD_WRSR)); + + // Set data FIFO + HAL_SPI_WRITE8(REG_SPIC_DR0, BIT_DR0(data)); + + // Enable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN); + + // wait spic busy done + SpicWaitBusyDoneRtl8195A(); + + if((SpicInitParaAllClk[0][0].flashtype) == FLASH_MICRON) + SpicWaitOperationDoneRtl8195A(SpicInitPara); + else + SpicWaitWipDoneRefinedRtl8195A(SpicInitPara); + + // Disable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + + HAL_SPI_WRITE32(REG_SPIC_ADDR_LENGTH, Info); + + // wait flash busy done (wip=0) + SpicWaitWipDoneRefinedRtl8195A(SpicInitPara); - // Disable SPI_FLASH User Mode - HAL_SPI_WRITE32( REG_SPIC_SSIENR, 0 ); - HAL_SPI_WRITE32( REG_SPIC_ADDR_LENGTH, Info ); - // wait flash busy done (wip=0) - SpicWaitWipDoneRefinedRtl8195A( SpicInitPara ); } /** - * @brief SpicWaitWipRtl8195A. + * @brief SpicWaitWipRtl8195A. * * @param NA * @@ -1267,18 +1269,20 @@ SpicSetFlashStatusRefinedRtl8195A HAL_FLASH_TEXT_SECTION u32 SpicWaitWipRtl8195A( - VOID -) -{ - SPIC_INIT_PARA SpicInitPara; - /* Check for flash ready status */ - SpicWaitWipDoneRefinedRtl8195A( SpicInitPara ); - return _TRUE; + VOID +){ + + SPIC_INIT_PARA SpicInitPara; + + /* Check for flash ready status */ + SpicWaitWipDoneRefinedRtl8195A(SpicInitPara); + + return _TRUE; } /** - * @brief SpicSetFlashStatusRefinedRtl8195A. + * @brief SpicSetFlashStatusRefinedRtl8195A. * * @param NA * @@ -1287,30 +1291,31 @@ SpicWaitWipRtl8195A( HAL_FLASH_TEXT_SECTION u32 SpicOneBitCalibrationRtl8195A( - IN u8 SysCpuClk -) -{ - u32 DefRdDummyCycle = 0; - // set auto mode - SpicConfigAutoModeRtl8195A( SpicOneBitMode ); - /* MXIC spec */ - DefRdDummyCycle = 0; + IN u8 SysCpuClk +){ + u32 DefRdDummyCycle = 0; - if ( !SpicCalibrationRtl8195A( SpicOneBitMode, DefRdDummyCycle ) ) - { - return _FALSE; - } -#if 0 - DBG_8195A( "@baud:%x\n", SpicInitParaAllClk[0][SysCpuClk].BaudRate ); - DBG_8195A( "@delay:%x\n", SpicInitParaAllClk[0][SysCpuClk].DelayLine ); - DBG_8195A( "@dummy:%x\n\n", SpicInitParaAllClk[0][SysCpuClk].RdDummyCyle ); -#endif - return _TRUE; + // set auto mode + SpicConfigAutoModeRtl8195A(SpicOneBitMode); + + /* MXIC spec */ + DefRdDummyCycle = 0; + + if (!SpicCalibrationRtl8195A(SpicOneBitMode, DefRdDummyCycle)) { + return _FALSE; + } + +#if CONFIG_DEBUG_LOG > 4 + DBG_8195A("@baud:%x\n",SpicInitParaAllClk[0][SysCpuClk].BaudRate); + DBG_8195A("@delay:%x\n",SpicInitParaAllClk[0][SysCpuClk].DelayLine); + DBG_8195A("@dummy:%x\n\n",SpicInitParaAllClk[0][SysCpuClk].RdDummyCyle); +#endif + return _TRUE; } /** - * @brief SpicDisableRtl8195A. + * @brief SpicDisableRtl8195A. * Disable SPI Flash memory controller. * @param NA * @@ -1318,151 +1323,144 @@ SpicOneBitCalibrationRtl8195A( */ HAL_FLASH_TEXT_SECTION VOID -SpicDisableRtl8195A( VOID ) +SpicDisableRtl8195A(VOID) { - SPI_FLASH_PIN_FCTRL( OFF ); + SPI_FLASH_PIN_FCTRL(OFF); } #if SPIC_CALIBRATION_IN_NVM /** - * @brief SpicNVMCalLoad. + * @brief SpicNVMCalLoad. * Load the SPI Flash Controller Calibration data from NVM * @param NA * * @retval NA */ HAL_FLASH_TEXT_SECTION VOID -SpicNVMCalLoad( u8 BitMode, u8 CpuClk ) +SpicNVMCalLoad(u8 BitMode, u8 CpuClk) { - SPIC_INIT_PARA * pspci_para; - u32 spci_para; - u32 spci_para_inv; - u32 flash_offset; - // DBG_SPIF_INFO("SpicNVMCalLoad==> BitMode=%d CpuClk=%d\r\n", BitMode, CpuClk); - /* each Calibration parameters use 8 bytes, first 4-bytes are the calibration data, - 2nd 4-bytes are the validate data: ~(calibration data) */ - flash_offset = ( CpuClk * 8 ) + ( BitMode * CPU_CLK_TYPE_NO * 8 ); - spci_para = HAL_READ32( SPI_FLASH_BASE, ( FLASH_SPIC_PARA_BASE + flash_offset ) ); + SPIC_INIT_PARA *pspci_para; + u32 spci_para; + u32 spci_para_inv; + u32 flash_offset; - if ( spci_para != 0xFFFFFFFF ) - { - spci_para_inv = HAL_READ32( SPI_FLASH_BASE, ( FLASH_SPIC_PARA_BASE + flash_offset + 4 ) ); - - if ( 0xFFFFFFFF == ( spci_para ^ spci_para_inv ) ) - { - pspci_para = ( SPIC_INIT_PARA * )&spci_para; - SpicInitParaAllClk[BitMode][CpuClk].BaudRate = pspci_para->BaudRate; - SpicInitParaAllClk[BitMode][CpuClk].RdDummyCyle = pspci_para->RdDummyCyle; - SpicInitParaAllClk[BitMode][CpuClk].DelayLine = pspci_para->DelayLine; - SpicInitParaAllClk[BitMode][CpuClk].Valid = pspci_para->Valid; - DBG_SPIF_INFO( "SpicNVMCalLoad: Calibration Loaded(BitMode %d, CPUClk %d): BaudRate=0x%x RdDummyCyle=0x%x DelayLine=0x%x\r\n", - BitMode, CpuClk, - SpicInitParaAllClk[BitMode][CpuClk].BaudRate, - SpicInitParaAllClk[BitMode][CpuClk].RdDummyCyle, - SpicInitParaAllClk[BitMode][CpuClk].DelayLine ); +// DBG_SPIF_INFO("SpicNVMCalLoad==> BitMode=%d CpuClk=%d\r\n", BitMode, CpuClk); + + /* each Calibration parameters use 8 bytes, first 4-bytes are the calibration data, + 2nd 4-bytes are the validate data: ~(calibration data) */ + flash_offset = (CpuClk * 8) + (BitMode * CPU_CLK_TYPE_NO * 8); + spci_para = HAL_READ32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset)); + if (spci_para != 0xFFFFFFFF) { + spci_para_inv = HAL_READ32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset+4)); + if (0xFFFFFFFF == (spci_para ^ spci_para_inv)) { + pspci_para = (SPIC_INIT_PARA*)&spci_para; + SpicInitParaAllClk[BitMode][CpuClk].BaudRate = pspci_para->BaudRate; + SpicInitParaAllClk[BitMode][CpuClk].RdDummyCyle = pspci_para->RdDummyCyle; + SpicInitParaAllClk[BitMode][CpuClk].DelayLine = pspci_para->DelayLine; + SpicInitParaAllClk[BitMode][CpuClk].Valid = pspci_para->Valid; + DBG_SPIF_INFO("SpicNVMCalLoad: Calibration Loaded(BitMode %d, CPUClk %d): BaudRate=0x%x RdDummyCyle=0x%x DelayLine=0x%x\r\n", + BitMode, CpuClk, + SpicInitParaAllClk[BitMode][CpuClk].BaudRate, + SpicInitParaAllClk[BitMode][CpuClk].RdDummyCyle, + SpicInitParaAllClk[BitMode][CpuClk].DelayLine); + } + else { + DBG_SPIF_WARN("SpicNVMCalLoad: Data in Flash(@ 0x%x = 0x%x 0x%x) is Invalid\r\n", + (FLASH_SPIC_PARA_BASE+flash_offset), spci_para, spci_para_inv); + } + } - else - { - DBG_SPIF_WARN( "SpicNVMCalLoad: Data in Flash(@ 0x%x = 0x%x 0x%x) is Invalid\r\n", - ( FLASH_SPIC_PARA_BASE + flash_offset ), spci_para, spci_para_inv ); + else { +// DBG_SPIF_INFO("SpicNVMCalLoad: No Data in Flash(@ 0x%x)\r\n", flash_offset); } - } - else - { - // DBG_SPIF_INFO("SpicNVMCalLoad: No Data in Flash(@ 0x%x)\r\n", flash_offset); - } } /** - * @brief SpicNVMCalLoadAll. + * @brief SpicNVMCalLoadAll. * Load the SPI Flash Controller Calibration data from NVM * @param NA * * @retval NA */ HAL_FLASH_TEXT_SECTION VOID -SpicNVMCalLoadAll( void ) +SpicNVMCalLoadAll(void) { - u8 i, j; - - for( i = 0; i < 3; i++ ) - { - for ( j = 0; j < CPU_CLK_TYPE_NO; j++ ) - { - SpicNVMCalLoad( i, j ); + u8 i,j; + + for(i=0;i<3;i++) { + for (j=0; j BitMode=%d CpuClk=%d\r\n", BitMode, CpuClk ); - /* each Calibration parameters use 8 bytes, first 4-bytes are the calibration data, - 2nd 4-bytes are the validate data: ~(calibration data) */ - flash_offset = ( CpuClk * 8 ) + ( BitMode * CPU_CLK_TYPE_NO * 8 ); - spci_para = HAL_READ32( SPI_FLASH_BASE, ( FLASH_SPIC_PARA_BASE + flash_offset ) ); + SPIC_INIT_PARA *pspci_para; + u32 spci_para; + u32 flash_offset; + SPIC_INIT_PARA SpicInitPara; - if ( spci_para == 0xFFFFFFFF ) - { - // if (1) { - pspci_para = ( SPIC_INIT_PARA * )&spci_para; - pspci_para->BaudRate = SpicInitParaAllClk[BitMode][CpuClk].BaudRate; - pspci_para->RdDummyCyle = SpicInitParaAllClk[BitMode][CpuClk].RdDummyCyle; - pspci_para->DelayLine = SpicInitParaAllClk[BitMode][CpuClk].DelayLine; - pspci_para->Valid = SpicInitParaAllClk[BitMode][CpuClk].Valid; - HAL_WRITE32( SPI_FLASH_BASE, ( FLASH_SPIC_PARA_BASE + flash_offset ), spci_para ); +#if CONFIG_DEBUG_LOG > 4 + DBG_SPIF_INFO("SpicNVMCalStore==> BitMode=%d CpuClk=%d\r\n", BitMode, CpuClk); +#endif + /* each Calibration parameters use 8 bytes, first 4-bytes are the calibration data, + 2nd 4-bytes are the validate data: ~(calibration data) */ + flash_offset = (CpuClk * 8) + (BitMode * CPU_CLK_TYPE_NO * 8); + spci_para = HAL_READ32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset)); + if (spci_para == 0xFFFFFFFF) { +// if (1) { + pspci_para = (SPIC_INIT_PARA*)&spci_para; + pspci_para->BaudRate = SpicInitParaAllClk[BitMode][CpuClk].BaudRate; + pspci_para->RdDummyCyle = SpicInitParaAllClk[BitMode][CpuClk].RdDummyCyle; + pspci_para->DelayLine = SpicInitParaAllClk[BitMode][CpuClk].DelayLine; + pspci_para->Valid = SpicInitParaAllClk[BitMode][CpuClk].Valid; + HAL_WRITE32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset), spci_para); + + if((SpicInitParaAllClk[BitMode][CpuClk].flashtype) == FLASH_MICRON) + SpicWaitOperationDoneRtl8195A(SpicInitPara); + else + SpicWaitWipDoneRefinedRtl8195A(SpicInitPara); + + HAL_WRITE32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset+4), ~spci_para); - if( ( SpicInitParaAllClk[BitMode][CpuClk].flashtype ) == FLASH_MICRON ) - SpicWaitOperationDoneRtl8195A( SpicInitPara ); - else - SpicWaitWipDoneRefinedRtl8195A( SpicInitPara ); + if((SpicInitParaAllClk[BitMode][CpuClk].flashtype) == FLASH_MICRON) + SpicWaitOperationDoneRtl8195A(SpicInitPara); + else + SpicWaitWipDoneRefinedRtl8195A(SpicInitPara); - HAL_WRITE32( SPI_FLASH_BASE, ( FLASH_SPIC_PARA_BASE + flash_offset + 4 ), ~spci_para ); +#if CONFIG_DEBUG_LOG > 4 + DBG_SPIF_INFO("SpicNVMCalStore(BitMode %d, CPUClk %d): Calibration Stored: BaudRate=0x%x RdDummyCyle=0x%x DelayLine=0x%x\r\n", + BitMode, CpuClk, + SpicInitParaAllClk[BitMode][CpuClk].BaudRate, + SpicInitParaAllClk[BitMode][CpuClk].RdDummyCyle, + SpicInitParaAllClk[BitMode][CpuClk].DelayLine); +#endif + // Read back to check + if (HAL_READ32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset)) != spci_para) { + DBG_SPIF_ERR("SpicNVMCalStore Err(Offset=0x%x), Wr=0x%x Rd=0x%x \r\n", + flash_offset, spci_para, HAL_READ32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset))); + } - if( ( SpicInitParaAllClk[BitMode][CpuClk].flashtype ) == FLASH_MICRON ) - SpicWaitOperationDoneRtl8195A( SpicInitPara ); - else - SpicWaitWipDoneRefinedRtl8195A( SpicInitPara ); - - DBG_SPIF_INFO( "SpicNVMCalStore(BitMode %d, CPUClk %d): Calibration Stored: BaudRate=0x%x RdDummyCyle=0x%x DelayLine=0x%x\r\n", - BitMode, CpuClk, - SpicInitParaAllClk[BitMode][CpuClk].BaudRate, - SpicInitParaAllClk[BitMode][CpuClk].RdDummyCyle, - SpicInitParaAllClk[BitMode][CpuClk].DelayLine ); - - // Read back to check - if ( HAL_READ32( SPI_FLASH_BASE, ( FLASH_SPIC_PARA_BASE + flash_offset ) ) != spci_para ) - { - DBG_SPIF_ERR( "SpicNVMCalStore Err(Offset=0x%x), Wr=0x%x Rd=0x%x \r\n", - flash_offset, spci_para, HAL_READ32( SPI_FLASH_BASE, ( FLASH_SPIC_PARA_BASE + flash_offset ) ) ); + if (HAL_READ32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset+4)) != ~spci_para) { + DBG_SPIF_ERR("SpicNVMCalStore Err(Offset=0x%x), Wr=0x%x Rd=0x%x \r\n", + flash_offset+4, ~spci_para, HAL_READ32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset+4))); + } } - - if ( HAL_READ32( SPI_FLASH_BASE, ( FLASH_SPIC_PARA_BASE + flash_offset + 4 ) ) != ~spci_para ) - { - DBG_SPIF_ERR( "SpicNVMCalStore Err(Offset=0x%x), Wr=0x%x Rd=0x%x \r\n", - flash_offset + 4, ~spci_para, HAL_READ32( SPI_FLASH_BASE, - ( FLASH_SPIC_PARA_BASE + flash_offset + 4 ) ) ); + else { + // There is a parameter on the flash memory already + DBG_SPIF_ERR("SpicNVMCalStore: The flash memory(@0x%x = 0x%x) is not able to be write, Erase it first!!\r\n", + (FLASH_SPIC_PARA_BASE+flash_offset), spci_para); } - } - else - { - // There is a parameter on the flash memory already - DBG_SPIF_ERR( "SpicNVMCalStore: The flash memory(@0x%x = 0x%x) is not able to be write, Erase it first!!\r\n", - ( FLASH_SPIC_PARA_BASE + flash_offset ), spci_para ); - } } #endif // #if SPIC_CALIBRATION_IN_NVM diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/lib_platform_new.a b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/lib_platform_new.a index 1814ecd9a93f79e1cb4362b3f8ffc0814b29377b..8812dcf5fc064203aa6da5afddd5d118c1a2965e 100644 GIT binary patch delta 59 zcmaF!hV#uE&IwW+7KRq4W@e_Q8>ZOH)(BYidXH zvb6D9m{wj(MB0)P+U1m`CrPc$JmD=h^|UCB&1JLyzu7=}&iDVm=iAToTl3EQzVpsI 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D:/MCU/SEGGER/JLink_V610a/ +JLINK_PATH ?= D:/MCU/SEGGER/JLink_V612f/ #--------------------------- # Default #---------------------------

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