From 02f846fa9a6e3ba5fb2936a2846d25dae99072b3 Mon Sep 17 00:00:00 2001 From: pvvx Date: Fri, 17 Mar 2017 14:48:21 +0300 Subject: [PATCH] update boot-loader ver 0.2 --- .../8195a/fwlib/ram_lib/rtl_bios_data.c | 8 +- .../realtek/8195a/fwlib/ram_lib/rtl_boot.c | 197 +- .../soc/realtek/8195a/fwlib/ram_lib/startup.c | 17 +- .../common/GCC/rlx8195A-symbol-v04-img2.ld | 2 +- build/bin/ota.bin | Bin 298160 -> 297904 bytes build/bin/ram_1.p.bin | Bin 7732 -> 8252 bytes build/bin/ram_2.bin | Bin 298124 -> 297868 bytes build/bin/ram_2.ns.bin | Bin 298140 -> 297884 bytes build/bin/ram_2.p.bin | Bin 298140 -> 297884 bytes build/bin/ram_all.bin | Bin 343212 -> 342956 bytes build/obj/build.nmap | 4765 ++++++++--------- project/src/driver/i2s_freertos.c | 5 +- 12 files changed, 2552 insertions(+), 2442 deletions(-) diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_bios_data.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_bios_data.c index 9826f15..e9bb21b 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_bios_data.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_bios_data.c @@ -38,8 +38,7 @@ INFRA_RAM_BSS_SECTION u32 _rand_z4, _rand_z3, _rand_z2, _rand_z1, _rand_first; / MON_RAM_BSS_SECTION u8 *ArgvArray[MAX_ARGV]; // 100006AC *ArgvArray[10] ! MON_RAM_BSS_SECTION u8 UartLogHistoryBuf[UART_LOG_HISTORY_LEN][UART_LOG_CMD_BUFLEN]; // 10000430 UartLogHistoryBuf[5][127] ! MON_RAM_BSS_SECTION volatile UART_LOG_CTL UartLogCtl; // 10000408 -/* -= { +/* = { .NewIdx = 0, .SeeIdx = 0, .RevdNo = UART_LOG_HISTORY_LEN, @@ -53,11 +52,10 @@ MON_RAM_BSS_SECTION volatile UART_LOG_CTL UartLogCtl; // 10000408 .pCmdTbl = (PCOMMAND_TABLE) &UartLogRomCmdTable, .CmdTblSz = 6, .CRSTS = 0, - .pHistoryBuf = UartLogHistoryBuf, + .pHistoryBuf = &UartLogHistoryBuf, .TaskRdy = 0 // .Sema -}; -*/ +}; */ MON_RAM_BSS_SECTION UART_LOG_BUF UartLogBuf; // 10000388 MON_RAM_BSS_SECTION volatile UART_LOG_CTL *pUartLogCtl = &UartLogCtl; // 10000384 /* ROM + LIB C */ diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c index 93b9f7f..45fb82a 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c @@ -1,5 +1,5 @@ /* - * BootLoader + * BootLoader Ver 0.2 * Created on: 12/02/2017 * Author: pvvx */ @@ -9,6 +9,8 @@ #include "diag.h" #include "rtl8195a/rtl8195a_sys_on.h" +#include "hal_spi_flash.h" + //------------------------------------------------------------------------- // Data declarations @@ -29,12 +31,6 @@ #endif // DEFAULT_BOOT_CLK_CPU #define BOOT_RAM_TEXT_SECTION // __attribute__((section(".boot.text"))) -//#define BOOT_RAM_RODATA_SECTION __attribute__((section(".boot.rodata"))) -//#define BOOT_RAM_DATA_SECTION __attribute__((section(".boot.data"))) -//#define BOOT_RAM_BSS_SECTION __attribute__((section(".boot.bss"))) - -//extern u32 STACK_TOP; -//extern volatile UART_LOG_CTL * pUartLogCtl; //------------------------------------------------------------------------- typedef struct _seg_header { @@ -61,16 +57,18 @@ LOCAL void RtlBoot1ToSram(void); // image1 LOCAL void RtlBoot2ToSram(void); // image1 LOCAL void RtlBoot3ToSram(void); // image1 LOCAL void RtlBoot4ToSram(void); // image1 -//LOCAL void EnterImage15(void); // image1 -//LOCAL void JtagOn(void); // image1 -//extern _LONG_CALL_ VOID HalCpuClkConfig(unsigned char CpuType); +extern _LONG_CALL_ VOID HalCpuClkConfig(unsigned char CpuType); extern _LONG_CALL_ VOID VectorTableInitRtl8195A(u32 StackP); extern _LONG_CALL_ VOID HalInitPlatformLogUartV02(VOID); extern _LONG_CALL_ VOID HalInitPlatformTimerV02(VOID); //extern _LONG_CALL_ VOID DramInit_rom(IN DRAM_DEVICE_INFO *DramInfo); //extern _LONG_CALL_ u32 SdrCalibration_rom(VOID); extern _LONG_CALL_ int SdrControllerInit_rom(PDRAM_DEVICE_INFO pDramInfo); +extern _LONG_CALL_ u32 SpicCmpDataForCalibrationRtl8195A(void); // compare read_data and golden_data +//extern _LONG_CALL_ VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara); // wait spi-flash status register[0] = 0 +//extern _LONG_CALL_ VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara); +//extern _LONG_CALL_ VOID RtlConsolInit(IN u32 Boot, IN u32 TBLSz, IN VOID *pTBL); //#pragma arm section code = ".boot.text"; //#pragma arm section rodata = ".boot.rodata", rwdata = ".boot.data", zidata = ".boot.bss"; @@ -85,8 +83,6 @@ START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__ = { RtlBoot2ToSram + 1, // PatchFun0(), Run if ( v40000210 & 0x10000000 ) RtlBoot3ToSram + 1, // PatchFun1(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 ) RtlBoot4ToSram + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 ) -//test RtlBootToFlash + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 ) - //------------------------------------------------------------------------- /* Set Debug Flags */ LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() { @@ -150,30 +146,144 @@ LOCAL void INFRA_START_SECTION loguart_wait_tx_fifo_empty(void) { } extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90] -/* - LOCAL uint32 _SpicInitParaAllClk[SpicMaxMode * CPU_CLK_TYPE_NO] = { - 0x01310202, 0x011420C2, - 0x03310002, 0x011420C2, - 0x05310002, 0x011420C2, - 0x07310002, 0x011420C2, - 0x09310002, 0x011420C2, - 0x0B310002, 0x011420C2, +LOCAL uint32 InitTabParaAllClk[3 * CPU_CLK_TYPE_NO] = { + // SIO + 0x01310102, // 72t/byte + 0x03310101, // 0201 - 40t, 0101 - 39t, 0102 - 72t, 0103 - 104t + 0x05310001, // 39t + 0x07310001, + 0x09310001, + 0x0B310001, + // DIO + 0x11311301, // BaudRate = 1, RdDummyCyle = 19, DelayLine = 63, DIO + 0x13311201, // 1201 - 36t + 0x15311101, // 1101 - 35t + 0x17311101, + 0x19311101, + 0x1B311101 + // QIO +/* MXIC Flash only DIO! + 0x21311301, // BaudRate = 1, RdDummyCyle = 19, DelayLine = 63, DIO + 0x23311201, // 1201 - 36t + 0x25311101, // 1101 - 35t + 0x27311101, + 0x29311101, + 0x2B311101 +*/ +}; - 0x11311301, 0x011420C2, - 0x13311201, 0x011420C2, - 0x15311101, 0x011420C2, - 0x17311101, 0x011420C2, - 0x19311101, 0x011420C2, - 0x1B311101, 0x011420C2, +struct spic_table_flash_type { + uint8 cmd[12]; + uint8 strlr2; + uint8 fbaud; + uint8 addrlen; + uint8 fsize; + uint32 contrl; + uint16 validcmd[3]; + uint8 manufacturerid; + uint8 memorytype; +}; + +//PSPIC_INIT_PARA pSpicInitPara; + +struct spic_table_flash_type spic_table_flash = { + { // for FLASH MX25L8006E/1606E + FLASH_CMD_FREAD, // REG_SPIC_READ_FAST_SINGLE 0x400060E0 0x0B + FLASH_CMD_DREAD, // REG_SPIC_READ_DUAL_DATA 0x400060E4 0x3B + FLASH_CMD_DREAD, // REG_SPIC_READ_DUAL_ADDR_DATA 0x400060E8 0x3B ? + FLASH_CMD_QREAD, // REG_SPIC_READ_QUAD_DATA 0x400060EC 0x6B + FLASH_CMD_4READ, // REG_SPIC_READ_QUAD_ADDR_DATA 0x400060F0 0xEB ? + FLASH_CMD_PP, // REG_SPIC_WRITE_SIGNLE 0x400060F4 0x02 + FLASH_CMD_DPP, // REG_SPIC_WRITE_DUAL_DATA 0x400060F8 0xA2 + FLASH_CMD_DPP, // REG_SPIC_WRITE_DUAL_ADDR_DATA 0x400060FC 0xA2 ? + FLASH_CMD_QPP, // REG_SPIC_WRITE_QUAD_DATA 0x40006100 0x32 + FLASH_CMD_4PP, // REG_SPIC_WRITE_QUAD_ADDR_DATA 0x40006104 0x38 + FLASH_CMD_WREN, // REG_SPIC_WRITE_ENABLE 0x40006108 0x06 + FLASH_CMD_RDSR // REG_SPIC_READ_STATUS 0x4000610C 0x05 + }, + BIT_FIFO_ENTRY(5) | BIT_SO_DUM, // REG_SPIC_CTRLR2 0x40006110 0x51 + BIT_FSCKDV(1), // REG_SPIC_FBAUDR 0x40006114 0x01 + BIT_ADDR_PHASE_LENGTH(3), // REG_SPIC_ADDR_LENGTH 0x40006118 0x03 + BIT_FLASE_SIZE(0x0F), // REG_SPIC_FLASE_SIZE 0x40006124 0x0E ? + BIT_CS_H_WR_DUM_LEN(2)| BIT_AUTO_ADDR__LENGTH(3) | BIT_RD_DUMMY_LENGTH(0x0), // REG_SPIC_AUTO_LENGTH 0x4000611C 0x20030001 ? + { + BIT_WR_BLOCKING, // REG_SPIC_VALID_CMD 0x40006120 0x200 SpicOneBitMode + BIT_WR_BLOCKING | BIT_RD_DUAL_I, // REG_SPIC_VALID_CMD 0x40006120 0x200 SpicOneBitMode + BIT_WR_BLOCKING | BIT_RD_QUAD_O, // REG_SPIC_VALID_CMD 0x40006120 0x200 SpicOneBitMode + }, + 0xC2, 0x20 // MX25L8006/MX25L1606 +}; + +LOCAL int BOOT_RAM_TEXT_SECTION SetSpicBitMode(uint8 BitMode) { + PSPIC_INIT_PARA pspic = &SpicInitParaAllClk[BitMode][((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7)]; + if(pspic->Mode.Valid) { + // Disable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + HAL_SPI_WRITE32(REG_SPIC_VALID_CMD, spic_table_flash.validcmd[pspic->Mode.BitMode]); + HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, (HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH) & 0xFFFF0000) | pspic->RdDummyCyle); + HAL_SPI_WRITE32(REG_SPIC_BAUDR, pspic->BaudRate); + FLASH_DDL_FCTRL(pspic->DelayLine); // SPI_DLY_CTRL_ADDR [7:0] + // Enable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN); + } + SPI_FLASH_PIN_FCTRL(ON); + // Test Read Pattern + if(!SpicCmpDataForCalibrationRtl8195A()) { + FLASH_DDL_FCTRL(0x31); // SPI_DLY_CTRL_ADDR [7:0] + for(uint8 i = 1; i < 4; i++) { + for(uint8 x = 0; x < 63; x++) { + // Disable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, (HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH) & 0xFFFF0000) | x); + HAL_SPI_WRITE32(REG_SPIC_BAUDR, i); + // Enable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN); +// HAL_SPI_WRITE32(REG_SPIC_FLUSH_FIFO, 1); + if(SpicCmpDataForCalibrationRtl8195A()) { + DiagPrintf("Spic reinit %d:%d\n", i, x); + pspic->BaudRate = i; + pspic->RdDummyCyle = x; + pspic->DelayLine = 0x31; + pspic->Mode.Valid = 1; + return 1; + }; + }; + }; + return 0; + }; + return 1; +} + +void BOOT_RAM_TEXT_SECTION InitSpicFlashType(struct spic_table_flash_type *ptable_flash) { + u8 * ptrb = &ptable_flash->cmd; + volatile u32 * ptrreg = (volatile u32 *)(SPI_FLASH_CTRL_BASE + REG_SPIC_READ_FAST_SINGLE);// 0x400060E0 + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); // Disable SPI_FLASH User Mode + do { + *ptrreg++ = *ptrb++; + } while(ptrb < (u8 *)(&ptable_flash->fsize)); + ptrreg[0] = ptable_flash->contrl; + ptrreg[1] = ptable_flash->validcmd[SpicOneBitMode]; + ptrreg[2] = ptable_flash->fsize; + HAL_SPI_WRITE32(REG_SPIC_SER, BIT_SER); +} + +LOCAL int BOOT_RAM_TEXT_SECTION InitSpic(uint8 SpicBitMode) { + _memset(SpicInitParaAllClk, 0, sizeof(SpicInitParaAllClk)); + uint32 * ptr = InitTabParaAllClk; + uint8 x; + for(x = 0; x < SpicMaxMode; x++) { + *(uint32 *)&SpicInitParaAllClk[SpicOneBitMode][x].BaudRate = ptr[0]; + *(uint32 *)&SpicInitParaAllClk[SpicDualBitMode][x].BaudRate = ptr[CPU_CLK_TYPE_NO]; + *(uint32 *)&SpicInitParaAllClk[SpicQuadBitMode][x].BaudRate = ptr[CPU_CLK_TYPE_NO]; + ptr++; + } + ACTCK_FLASH_CCTRL(1); + SLPCK_FLASH_CCTRL(1); + HalPinCtrlRtl8195A(SPI_FLASH, 0, 1); + InitSpicFlashType(&spic_table_flash); + return SetSpicBitMode(SpicBitMode); +} - 0x21311301, 0x011420C2, - 0x23311201, 0x011420C2, - 0x25311101, 0x011420C2, - 0x27311101, 0x011420C2, - 0x29311101, 0x011420C2, - 0x2B311101, 0x011420C2 - }; - */ /* SYSPlatformInit */ LOCAL void INFRA_START_SECTION SYSPlatformInit(void) { @@ -422,10 +532,12 @@ LOCAL uint8 BOOT_RAM_TEXT_SECTION IsForceLoadDefaultImg2(void) { // _pHAL_Gpio_Adapter->IrqHandle.IrqFun = NULL; return result; } - /* RTL Console ROM */ LOCAL void BOOT_RAM_TEXT_SECTION RtlConsolRam(void) { // DiagPrintf("\r\nRTL Console ROM\r\n"); +// RtlConsolInit(ROM_STAGE, (u32) 6, (void*) &UartLogRomCmdTable); + pUartLogCtl->RevdNo = UART_LOG_HISTORY_LEN; + pUartLogCtl->BootRdy = 1; pUartLogCtl->pTmpLogBuf->UARTLogBuf[0] = '?'; pUartLogCtl->pTmpLogBuf->BufCount = 1; pUartLogCtl->ExecuteCmd = 1; @@ -445,7 +557,7 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) { else DBG_8195A("\r===== Enter SRAM-Boot %d ====\n", flg); -#if CONFIG_DEBUG_LOG > 2 +#if CONFIG_DEBUG_LOG > 1 DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN)); #endif @@ -462,15 +574,10 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) { (HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x0e)); SDR_PIN_FCTRL(ON); }; - SPI_FLASH_PIN_FCTRL(ON); - *(uint32 *)(&SpicInitParaAllClk[0][0].BaudRate) = 0x1311301; // patch - *(uint32 *)(&SpicInitParaAllClk[1][0].BaudRate) = 0x1311301; // patch - SpicInitRtl8195AV02(CPU_CLK_TYPE_NO - 1 - ((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7), - SpicDualBitMode); - if (!SpicCmpDataForCalibrationRtl8195A()) { - DBG_8195A("Error Init Spic DIO!\n"); + if (!InitSpic(SpicDualBitMode)) { + DBG_8195A("Spic Init Error!\n"); RtlConsolRam(); - } + }; if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // уже загружена? // extern DRAM_DEVICE_INFO SdrDramInfo_rom; // 50 MHz if (!SdrControllerInit_rom(&SdrDramInfo)) { // 100 MHz @@ -500,7 +607,7 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) { if (!flg) loadUserImges(IsForceLoadDefaultImg2() + 1); if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) { - DBG_MISC_ERR("Invalid Image Signature!\n"); + DBG_8195A("Invalid Image Signature!\n"); RtlConsolRam(); } DBG_8195A("Img Sign: %s, Go @ 0x%08x\r\n", &__image2_validate_code__, diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c index 903b310..ee68e4a 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c @@ -75,6 +75,7 @@ void INFRA_START_SECTION SYSPlatformInit(void) { (HAL_SYS_CTRL_READ32(REG_SYS_XTAL_CTRL1) & (~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1))) | BIT_SYS_XTAL_DRV_RF1(1)); // & 0xFFFFFFE7 | 8; +/* if(HalGetCpuClk() != PLATFORM_CLOCK) { //----- CLK CPU loguart_wait_tx_fifo_empty(); // иначе глючит LogUART, если переключение CLK приходится на вывод символов ! @@ -92,6 +93,7 @@ void INFRA_START_SECTION SYSPlatformInit(void) { HalInitPlatformLogUartV02(); // Show ""... :( HalInitPlatformTimerV02(); }; +*/ } //----- SDIO_Device_Off @@ -151,11 +153,15 @@ extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter; #if CONFIG_DEBUG_LOG > 2 DBG_8195A("\rCPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN)); #endif - _memset(SpicInitParaAllClk, 0, sizeof(SpicInitParaAllClk)); - *(uint32 *)(&SpicInitParaAllClk[0][0].BaudRate) = 0x1311301; // patch - *(uint32 *)(&SpicInitParaAllClk[1][0].BaudRate) = 0x1311301; // patch +// _memset(SpicInitParaAllClk, 0, sizeof(SpicInitParaAllClk)); + *(uint32 *)(&SpicInitParaAllClk[0][0].BaudRate) = 0x01310202; // patch + *(uint32 *)(&SpicInitParaAllClk[1][0].BaudRate) = 0x11311301; // patch +// *(uint32 *)(&SpicInitParaAllClk[2][0].BaudRate) = 0x21311301; // patch SPI_FLASH_PIN_FCTRL(ON); - uint8 SpicBaudRate = CPU_CLK_TYPE_NO - 1 - ((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7); +/* +// uint8 SpicBaudRate = CPU_CLK_TYPE_NO - 1 - ((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7); + uint8 SpicBaudRate = 3; // HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7; + DBG_8195A("SpicBaudRate = %d\n", SpicBaudRate); SpicInitRtl8195AV02(SpicBaudRate, SpicDualBitMode); if(!SpicCmpDataForCalibrationRtl8195A()) { DBG_8195A("ReInit Spic to SIO...\n"); @@ -164,7 +170,8 @@ extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter; DBG_8195A("Error Init Spic!\n"); }; }; - SpicFlashInitRtl8195A(SpicDualBitMode); // SpicReadIDRtl8195A(); SpicDualBitMode +*/ +// SpicFlashInitRtl8195A(SpicDualBitMode); // SpicReadIDRtl8195A(); SpicDualBitMode uint8 ChipId = HalGetChipId(); if (ChipId >= CHIP_ID_8195AM) { #ifdef CONFIG_SDR_EN diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img2.ld b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img2.ld index 2edf4c0..02d6016 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img2.ld +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img2.ld @@ -76,7 +76,7 @@ SECTIONS KEEP(*(.hal.flash.data)) KEEP(*(.boot.rodata*)) KEEP(*(.boot.text*)) - KEEP(*(.boot.data)) + KEEP(*(.boot.data*)) __image1_bss_start__ = .; KEEP(*(.boot.bss*)) __image1_bss_end__ = .; diff --git a/build/bin/ota.bin b/build/bin/ota.bin index 895566fe5960481d55a222809e961f074cb80927..ba9de9741f9c1f2eb368934701aea8bfa346bce0 100644 GIT binary patch delta 16589 zcma)j30M_XANTyv%mpq24hYDqfFKBp7f@VqLC}kextsgmf@W$~YHt>9shRsI$9)$U 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T _rtw_free_recv_priv -1002639a T rtw_free_buf_pending_queue -1002639e T recvframe_chkmic -1002649c T decryptor -10026538 T portctrl -100265ae T recv_decache -100265dc T process_pwrbit_data -1002661c T process_wmmps_data -100266a4 T count_rx_stats -10026718 T sta2sta_data_frame -10026854 T ap2sta_data_frame -10026980 T sta2ap_data_frame -10026a08 T validate_recv_ctrl_frame -10026ba2 T validate_recv_data_frame -10026dfc T wlanhdr_to_ethhdr -10026f38 T recvframe_defrag -10026fe2 T recvframe_chk_defrag -10027098 T validate_recv_mgnt_frame -100270d4 T validate_recv_frame -1002719c T recv_indicatepkt_reorder -100271be T process_recv_indicatepkts -10027216 T recv_func_prehandle -1002723e T recv_func_posthandle -100272a2 T recv_func -1002732c T rtw_recv_entry -1002735c T rtw_recv_tasklet -100273b4 T rtw_wep_encrypt -100273fa T rtw_wep_decrypt -10027440 T rtw_tkip_encrypt -100274ac T rtw_tkip_decrypt -10027518 T rtw_aes_encrypt -10027584 T rtw_aes_decrypt -100275e8 T rtw_init_sec_priv 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-10027fa8 T set_channel_bwmode -10027ffe T get_my_bssid -10028002 T get_beacon_interval -10028020 T is_client_associated_to_ap -10028038 T is_client_associated_to_ibss -10028054 T is_IBSS_empty -10028076 T decide_wait_for_beacon_timeout -10028092 T invalidate_cam_all -1002809a T write_cam -10028110 T clear_cam_entry -1002813e T flush_all_cam_entry -1002819c T WMM_param_handler -100281c2 T WMMOnAssocRsp -10028290 T HT_caps_handler -10028330 T HT_info_handler -10028354 T HTOnAssocRsp -1002838c T ERP_IE_handler -100283a8 T VCS_update -100283fa T rtw_check_bcn_info -1002860a T update_beacon_info -10028660 T is_ap_in_tkip -100286d8 T wifirate2_ratetbl_inx -10028744 T update_basic_rate -10028772 T update_supported_rate -1002879c T update_MCS_rate -100287a8 T support_short_GI -100287d6 T get_highest_rate_idx -100287f0 T Update_RA_Entry -100287f8 T set_sta_rate -10028800 T update_tx_basic_rate -10028858 T check_assoc_AP -1002894c T update_IOT_info -100289aa T update_capinfo -10028a28 T update_wireless_mode -10028ac8 T update_bmc_sta_support_rate -10028af0 T update_TSF -10028b02 T correct_TSF -10028b0a t _init_txservq -10028b20 t set_qos -10028b70 T _rtw_init_sta_xmit_priv -10028bb6 T rtw_mfree_xmit_priv_lock -10028c02 T qos_acm -10028c3c T xmitframe_addmic -10028d9a T xmitframe_swencrypt -10028dc6 T rtw_make_wlanhdr -10028fa6 T rtw_txframes_pending -10028fe2 T rtw_txframes_sta_ac_pending -10029018 T rtw_txframes_update_attrib_vcs_info -100290b8 T rtw_put_snap -100290fc T rtw_update_protection -10029142 T rtw_count_tx_stats -10029192 T rtw_free_xmitbuf_ext -100291d4 T rtw_alloc_xmitframe -1002922c T rtw_free_xmitframe -1002927e T rtw_free_xmitframe_queue -100292bc T rtw_get_sta_pending -100292fc T rtw_xmit_classifier -10029362 T rtw_xmitframe_enqueue -10029370 T rtw_alloc_hwxmits -100293ca T rtw_free_hwxmits -100293e0 T _rtw_free_xmit_priv -100294ac T rtw_init_hwxmits -100294c4 T _rtw_init_xmit_priv -1002967c T rtw_get_ff_hwaddr -10029690 T xmitframe_enqueue_for_sleeping_sta -10029850 t dequeue_xmitframes_to_sleeping_queue -100298a6 T stop_sta_xmit -1002998e T wakeup_sta_to_xmit -10029ba4 T xmit_delivery_enabled_frames -10029cc0 T rtw_xmit_tasklet -10029d18 T rtw_xmit_mgnt -10029d1c T rtw_xmit -1002a046 T rtw_sctx_done_err -1002a052 T rtw_alloc_xmitbuf -1002a0ac T rtw_free_xmitbuf -1002a11e T rtw_alloc_xmitbuf_ext -1002a1a4 T rtw_sctx_done -1002a1aa t rtl8195a_free_rx_ring -1002a1b8 t bus_write32 -1002a214 t bus_write16 -1002a270 t bus_write8 -1002a2cc t bus_read32 -1002a326 t bus_read16 -1002a382 t bus_read8 -1002a3de t rtl8195a_free_tx_ring -1002a46c T rtl8195a_init_desc_ring -1002a5ac T rtl8195a_free_desc_ring -1002a5c8 T rtl8195a_reset_desc_ring -1002a65e T InitLxDmaRtl8195a -1002a7c0 T rtl8195a_check_txdesc_closed -1002a838 t rtl8195a_tx_isr -1002a91c T InterruptRecognized8195a -1002a9ac T InitInterrupt8195a -1002a9cc T EnableDMA8195a -1002a9f4 T EnableInterrupt8195a -1002aa34 T DisableDMA8195a -1002aa40 T DisableInterrupt8195a -1002aa58 T UpdateInterruptMask8195a -1002aaba T CheckRxTgRtl8195a -1002aaf4 T rtl8192ee_check_rxdesc_remain -1002ab24 T rtl8195a_recv_tasklet -1002ae38 T rtl8195a_tx_int_handler -1002ae64 T InterruptHandle8195a -1002b0d8 T rtl8195a_xmit_tasklet -1002b100 T lxbus_set_intf_ops -1002b140 t GetTxBufDesc -1002b18a t UpdateFirstTxbdtoXmitBuf.isra.3 -1002b1bc t check_nic_enough_desc.isra.4 -1002b20c T rtl8195ab_init_xmit_priv -1002b21a T rtl8195ab_free_xmit_priv -1002b222 T GetDmaTxbdIdx -1002b23e T rtl8195a_enqueue_xmitbuf -1002b262 T rtl8195a_dequeue_xmitbuf -1002b286 T SetTxbdForLxDMARtl8195ab -1002b306 T UpdateTxbdHostIndex -1002b344 T rtw_dump_xframe -1002b516 T check_tx_desc_resource -1002b550 T rtw_dequeue_xframe -1002b5e4 T rtw_xmitframe_coalesce -1002b898 T rtl8195ab_xmitframe_resume -1002b98e T rtl8195ab_mgnt_xmit -1002b9ca T rtl8195ab_hal_xmit -1002bad8 t Hal_GetEfuseDefinition -1002bb08 t ResumeTxBeacon -1002bb4c T UpdateHalRAMask8195A -1002bce4 T HalLittleWifiMCUThreadRtl8195a -1002bd38 T HalCheckInReqStateThreadRtl8195a -1002bd84 T HalTDMAChangeStateThreadRtl8195a -1002bdd0 t rtl8195a_read_chip_version -1002be44 t Hal_EfuseWordEnableDataWrite -1002c088 t Hal_EfusePowerSwitch -1002c09c t rtl8195a_free_hal_data -1002c0b6 t StopTxBeacon -1002c100 T SetHalODMVar8195A -1002c1b8 T rtl8195a_start_thread -1002c220 T rtl8195a_stop_thread -1002c244 t Hal_ReadEFuse -1002c3b4 T GetHalODMVar8195A -1002c3c8 t rtw_flash_map_update.part.12 -1002c468 t rtw_flash_map_erase -1002c4ac t Hal_EfusePgPacketWrite -1002c728 t Hal_EfuseGetCurrentSize -1002c808 t rtw_flash_map_write -1002c9d6 T rtl8195a_InitBeaconParameters -1002ca46 T _InitBurstPktLen_8195AB -1002ca50 T rtl8195a_set_hal_ops -1002cb30 T rtl8195a_init_default_value -1002cb32 T rtl8195a_InitLLTTable -1002cb7c T Hal_GetChnlGroup8195A -1002cbb8 T rtw_config_map_read -1002cca4 T rtw_config_map_write -1002cd50 T Hal_InitPGData -1002cdae T Hal_EfuseParseIDCode -1002cdc6 T Hal_ReadPowerValueFromPROM_8195A -1002ce64 T Hal_EfuseParseTxPowerInfo_8195A -1002cefc T Hal_EfuseParseEEPROMVer_8195A -1002cf12 T Hal_EfuseParsePackageType_8195A -1002cf7c T Hal_EfuseParseChnlPlan_8195A -1002cfac T Hal_EfuseParseCustomerID_8195A -1002cfc2 T Hal_EfuseParseXtal_8195A -1002cfda T Hal_EfuseParseThermalMeter_8195A -1002d002 T Hal_ReadRFGainOffset -1002d052 T BWMapping_8195A -1002d072 T SCMapping_8195A -1002d09a T rtl8195a_update_txdesc -1002d36a T rtl8195a_fill_fake_txdesc -1002d428 T SetHwReg8195A -1002e0e8 T GetHwReg8195A -1002e17c T SetHalDefVar8195A -1002e25c T GetHalDefVar8195A -1002e280 T PHY_QueryBBReg_8195A_Safe -1002e2ac T PHY_SetBBReg_8195A_Safe -1002e2d8 t phy_RFSerialRead_8195A -1002e38c T PHY_QueryRFReg_8195A -1002e3a4 T PHY_SetRFReg_8195A -1002e3fc T PHY_MACConfig8195A -1002e416 T PHY_BBConfig8195A -1002e526 T PHY_RFConfig8195A -1002e52a T PHY_SetTxPowerIndex_8195A -1002e634 T phy_TxPwrAdjInPercentage -1002e674 T PHY_GetTxPowerIndex_8195A -1002e764 T PHY_SetTxPowerLevel8195A -1002e76a T phy_SpurCalibration_8195A -1002ea22 T phy_SetRegBW_8195A -1002ea60 T phy_PostSetBwMode8195A -1002ebbc T phy_SwChnl8195A -1002ec64 T phy_SwChnlAndSetBwMode8195A -1002ecb4 T PHY_HandleSwChnlAndSetBW8195A -1002ed64 T PHY_SetBWMode8195A -1002ed86 T PHY_SwChnl8195A -1002eda0 T PHY_SetSwChnlBWMode8195A -1002edbe t HalTimerEnable -1002edd0 T InitTDMATimer -1002edf8 T ChangeStateByTDMA -1002ee08 T GetMinRateInRRSR -1002ee3c T CheckInReqState -1002ee4c T InitCheckStateTimer -1002ee7c T InitGTimer1ms -1002eec8 T DeInitGTimer1ms -1002ef10 T ChangeTransmiteRate -1002ef4c T PowerBitSetting -1002efc8 T ChkandChangePS -1002f02c T IssueRsvdPagePacketSetting -1002f0a0 T IssuePSPoll -1002f0cc T WaitTxStateMachineOk -1002f120 T IssueNullData -1002f1b0 T PsCloseRF -1002f1e4 T PsOpenRF -1002f214 T ChkTxQueueIsEmpty -1002f22c T InitPS -1002f29c T ConfigListenBeaconPeriod -1002f2c0 T PS_S2_Condition_Match -1002f2f4 T PS_S4_Condition_Match -1002f370 T PS_32K_Condition_Match -1002f3ac T PS_S2ToS3ToS0State -1002f414 T PS_S2ToS0State -1002f430 T PS_S3ToS2orS0State -1002f460 T PS_S0ToS1ToS2State -1002f4bc T PS_S1ToS0orS2State -1002f4ec T PS_S2ToS4State -1002f538 T PS_S0ToS6State -1002f558 T PS_S6ToS0State -1002f570 T CheckTSFIsStable -1002f5c0 T WaitHWStateReady -1002f5d0 T SysClkDown -1002f640 T SysClkUp -1002f68c T ResetPSParm -1002f700 T PS_S4ToS2State -1002f724 T SleepTo32K -1002f784 T Change_PS_State -1002f930 T Legacy_PS_Setting -1002f9a4 T PSModeSetting -1002fa48 T ChangePSStateByRPWM -1002fa8c T ChangeTDMAState -1002fbac T TDMAChangeStateTask -1002fbd6 T EnterPS -1002fbf8 T SetSmartPSTimer -1002fc34 T GTimer7Handle -1002fc90 T SmartPS2InitTimerAndToGetRxPkt -1002fccc T PS_OnBeacon -1002fd7c T PSBcnEarlyProcess -1002fe38 T PSMtiBcnEarlyProcess -1002fee4 T PSRxBcnProcess -10030034 T TxPktInPSOn -10030072 T PsBcnToProcess -1003012c T GTimer6Handle -10030178 T RPWMProcess -100301b4 T PSSetMode -1003022c T SpeRPT -1003034c T ISR_BcnEarly -100303b8 T ISR_MtiBcnEarly -100303ec T ISR_RxBcn -10030408 T ISR_RxBCMD1 -10030438 T ISR_RxBCMD0 -1003048c T ISR_RxUCMD1 -100304ca T ISR_RxUCMD0 -10030506 T ISR_TxPktIn -10030518 T ISR_TXCCX -1003051c T H2CHDL_SetPwrMode -10030644 T CheckInReqStateTask -1003068a T HalGetNullTxRpt -100306a8 T ISR_TBTT -10030720 T H2CHDL_BcnIgnoreEDCCA -10030730 T PMUInitial -10030780 T PMUTask -1003088c T PHY_RF6052SetBandwidth8195A -100308d0 T PHY_RF6052_Config8195A -10030988 t process_rssi -100309be T rtl8195a_query_rx_desc_status -10030a6e T rtl8195a_query_rx_phy_status -10030bc6 T hal_com_get_channel_plan -10030bfa T HAL_IsLegalChannel -10030c18 T MRateToHwRate -10030c2c T HwRateToMRate -10030c40 T HalSetBrateCfg -10030cec T Hal_MappingOutPipe -10030d08 T hal_init_macaddr -10030d34 T hw_var_port_switch -10030fbc T SetHwReg -10030fc6 T GetHwReg -10030fc8 T switch_power_saving_mode -1003100c T rtw_bb_rf_gain_offset -10031054 T PHY_GetRateValuesOfTxPowerByRate -100311ec T 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gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_TFBGA96_8195A -1004ec6e D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN48_8195A -1004ec8c D .ram.bss$$Base -1004ec8c D __bss_start__ -1004ec8c D __data_end__ -1004ec8c D __ram_image2_text_end__ -1004ec8c d skbdata_list -1004ec94 V skb_data_pool -10052094 d ucIdleTaskHeap -100521ac D HalI2SOpSAL -100521e8 D SYSAdapte -100521ec D PwrAdapter -10052478 D libc_has_init -1005247c d rheap_end -10052480 d event_init.21281 -10052484 D wifi_run_mode -10052488 D wlan_st_netifn -10052489 d sampCntAdd -1005248c d sampCnt -10052490 D mp3_serv -10052512 D tskreader_enable -10052514 D readBuf -10052518 D tskmad_enable -1005251c d bufUnderrunCt -10052520 d oldRate -10052524 d sampDelCnt -10052528 D pbuf_fifo -1005252c D pi2s -10052534 D I2sTxSema -10052538 D eap_method -10052539 D eap_phase -1005253c D rtw_join_status -10052540 D wifi_mode -10052544 d param.21254 -1005255c d join_user_data -10052560 d event_callback_list -100526e0 D paff_array -10052758 D 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wifirate2_ratetbl_inx +100286b4 T update_basic_rate +100286e2 T update_supported_rate +1002870c T update_MCS_rate +10028718 T support_short_GI +10028746 T get_highest_rate_idx +10028760 T Update_RA_Entry +10028768 T set_sta_rate +10028770 T update_tx_basic_rate +100287c8 T check_assoc_AP +100288bc T update_IOT_info +1002891a T update_capinfo +10028998 T update_wireless_mode +10028a38 T update_bmc_sta_support_rate +10028a60 T update_TSF +10028a72 T correct_TSF +10028a7a t _init_txservq +10028a90 t set_qos +10028ae0 T _rtw_init_sta_xmit_priv +10028b26 T rtw_mfree_xmit_priv_lock +10028b72 T qos_acm +10028bac T xmitframe_addmic +10028d0a T xmitframe_swencrypt +10028d36 T rtw_make_wlanhdr +10028f16 T rtw_txframes_pending +10028f52 T rtw_txframes_sta_ac_pending +10028f88 T rtw_txframes_update_attrib_vcs_info +10029028 T rtw_put_snap +1002906c T rtw_update_protection +100290b2 T rtw_count_tx_stats +10029102 T rtw_free_xmitbuf_ext +10029144 T rtw_alloc_xmitframe +1002919c T rtw_free_xmitframe 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wifi_st_dhcp +1004d1fc D wlan_ap_name +1004d204 D wifi_ap_dhcp +1004d214 D feep_tab +1004d244 D wifi_st_cfg +1004d2b0 D wifi_cfg +1004d2b7 D wlan_ap_netifn +1004d2b8 D wifi_ap_cfg +1004d324 D oversampling +1004d328 D SystemCoreClock +1004d32c D error_flag +1004d330 d tcp_port +1004d334 d iss.7348 +1004d338 d udp_port +1004d33a D lwip_host_name +1004d35a d dhcp_server_state_machine +1004d35b d dhcp_recorded_xid +1004d360 d uxCriticalNesting +1004d364 d xNextTaskUnblockTime +1004d368 d seed.11739 +1004d36c d wakeup_event +1004d370 d wakelock +1004d374 d last_wakelock_state +1004d394 D mlme_sta_tbl +1004d404 d PMKID_KDE_TYPE.17744 +1004d40c V nr_xmitbuff +1004d410 V nr_xmitframe +1004d414 d P802_1H_OUI +1004d417 D rtw_adaptivity_mode +1004d418 D g_user_ap_sta_num +1004d41c d rtw_private_handler +1004d460 V max_local_skb_num +1004d464 V max_skb_buf_num +1004d468 D rom_e_rtw_msgp_str_ +1004d644 D ARFB_table +1004d683 D TRYING_NECESSARY_idx +1004d697 D DROPING_NECESSARY +1004d6ab D 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gDeltaSwingTableXtal_MP_P_TxXtalTrack_8195A +1004eb4e D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_TFBGA96_8195A +1004eb6e D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN48_8195A +1004eb8c D .ram.bss$$Base +1004eb8c D __bss_start__ +1004eb8c D __data_end__ +1004eb8c D __ram_image2_text_end__ +1004eb8c d skbdata_list +1004eb94 V skb_data_pool +10051f94 d ucIdleTaskHeap +100520ac D HalI2SOpSAL +100520e8 D SYSAdapte +100520ec D PwrAdapter +10052378 D libc_has_init +1005237c d rheap_end +10052380 d event_init.21281 +10052384 D wifi_run_mode +10052388 D wlan_st_netifn +10052389 d sampCntAdd +1005238c d sampCnt +10052390 D mp3_serv +10052412 D tskreader_enable +10052414 D readBuf +10052418 D tskmad_enable +1005241c d bufUnderrunCt +10052420 d oldRate +10052424 d sampDelCnt +10052428 D pbuf_fifo +1005242c D pi2s +10052434 D I2sTxSema +10052438 D eap_method +10052439 D eap_phase +1005243c D rtw_join_status +10052440 D wifi_mode +10052444 d param.21254 +1005245c d join_user_data +10052460 d event_callback_list +100525e0 D paff_array +10052658 D lwip_init_done +1005265c D xnetif +100526dc d s_aliases.6960 +100526e0 D h_errno +100526e4 d s_hostent.6959 +100526f8 d s_hostent_addr.6961 +100526fc d s_phostent_addr.6962 +10052704 d select_cb_list +10052708 d sockets +100527c8 d select_cb_ctr +100527cc d mbox +100527d0 d tcpip_init_done_arg +100527d4 d tcpip_init_done +100527d8 d allsystems +100527dc d allrouters +100527e0 d igmp_group_list +100527e4 D current_header +100527e8 d ip_id +100527ec D current_iphdr_src +100527f0 D current_iphdr_dest +100527f4 D current_netif +100527f8 d str.6325 +10052808 d reassdatagrams +1005280c d ip_reass_pbufcount +1005280e D dhcp_rx_options_given +10052818 D dhcp_rx_options_val +10052840 d xid.7275 +10052844 d dns_seqno +10052848 d dns_table +10052ca8 d dns_servers +10052cb0 d dns_payload_buffer +10052eb4 d dns_pcb +10052eb8 d dns_payload +10052ebc d tcpip_tcp_timer_active +10052ec0 d next_timeout +10052ec4 D netif_list +10052ec8 D netif_default +10052ecc d netif_num +10052ecd D pbuf_free_ooseq_pending +10052ed0 d raw_pcbs +10052ed4 D tcp_active_pcbs_changed +10052ed8 D tcp_ticks +10052edc d tcp_timer +10052ee0 D tcp_listen_pcbs +10052ee4 D tcp_active_pcbs +10052ee8 d tcp_timer_ctr +10052eec D tcp_tw_pcbs +10052ef0 D tcp_tmp_pcb +10052ef4 D tcp_bound_pcbs +10052ef8 d seqno +10052efc d tcplen +10052f00 d ackno +10052f04 d flags +10052f05 d recv_flags +10052f08 d tcphdr +10052f0c d recv_data +10052f10 d inseg +10052f24 D tcp_input_pcb +10052f28 D udp_pcbs +10052f2c d etharp_cached_entry +10052f30 d arp_table +10052ff8 D lwip_tickless_used +10052ffc d s_timeoutlist +1005302c d s_nextthread +10053030 d dhcps_ip_table_semaphore +10053034 d dhcps_send_broadcast_address +10053038 D dhcps_ip4addr_pool_end +10053039 d dhcp_client_ethernet_address +1005304c d dhcps_subnet_broadcast +10053050 d bound_client_ethernet_address +10053060 d ip_table +10053080 d dhcps_pcb +10053084 d dhcp_message_total_options_lenth +10053088 d dhcps_local_address +1005308c d dhcps_netif +10053090 d client_request_ip +10053094 d dhcps_allocated_client_address +10053098 d dhcps_local_mask +1005309c d dhcps_local_gateway +100530a0 d dhcps_network_id +100530a4 D dhcps_ip4addr_pool_start +100530a8 d dhcp_message_repository +100530ac D ext_upper +100530b0 d xFreeBytesRemaining +100530b4 d ext_free +100530b8 D ext_lower +100530bc d pxEnd +100530c0 d xStart +100530c8 d xMinimumEverFreeBytesRemaining +100530cc d ulTimerCountsForOneTick +100530d0 d ulStoppedTimerCompensation +100530d4 d xMaximumPossibleSuppressedTicks +100530d8 d xPendingReadyList +100530ec d uxTopReadyPriority +100530f0 d uxTasksDeleted +100530f4 d xTickCount +100530f8 d pxReadyTasksLists +100531d4 d pxOverflowDelayedTaskList +100531d8 d xTasksWaitingTermination +100531ec d pxDelayedTaskList +100531f0 d xSchedulerRunning +100531f4 d ulTaskSwitchedInTime +100531f8 D pxCurrentTCB +100531fc d uxPendedTicks +10053200 d xSuspendedTaskList +10053214 d uxCurrentNumberOfTasks +10053218 d ulDeltaTotalRunTime +1005321c d xDelayedTaskList2 +10053230 d xDelayedTaskList1 +10053244 d uxTaskNumber +10053248 d xYieldPending +1005324c d uxSchedulerSuspended +10053250 d xNumOfOverflows +10053254 d pxCurrentTimerList +10053258 d xActiveTimerList1 +1005326c d xActiveTimerList2 +10053280 d xLastTime.5284 +10053284 d xTimerQueue +10053288 d pxOverflowTimerList +1005328c d xTimerTaskHandle +10053290 d device_mutex +1005329c d mutex_init +100532a0 d uxSavedInterruptStatus +100532a4 D min_free_heap_size +100532a8 d g_heap_inited +100532ac d tcm_lock +100532b0 D g_tcm_heap +100532b4 D flashobj +100532c0 D fspic_isinit +100532c4 D WDGAdapter +10053300 d last_acquire_wakelock_time +10053380 D post_sleep_callback +10053400 D pre_sleep_callback +10053480 D reserve_pll +10053484 d sys_sleep_time +10053488 d hold_wakelock_time +10053508 D missing_tick +1005350c D Timer2To7HandlerData +10053524 D auto_reconnect_running +10053528 D p_wlan_autoreconnect_hdl +1005352c D mac_monitor_callback +10053530 D mf_list_head +10053534 d pscan_retry_cnt.21430 +10053538 D promisc_callback_all +1005353c D promisc_sema +10053540 D promisc_callback +10053544 D psk_essid +1005358c D psk_passphrase +1005360e D psk_passphrase64 +1005364f D wpa_global_PSK +1005369f d RFC1042_OUI +100536a4 d rx_ring_pool +10055784 d stop_report_count.20629 +10055785 D bCheckStateTIMER +10055788 d WifiMcuCmdBitMap.20974 +1005578c D p_wlan_init_done_callback +10055790 D rtw_power_percentage_idx +10055794 D p_wlan_uart_adapter_callback +10055798 D rtw_adaptivity_en +1005579c D p_wlan_mgmt_filter +100557a0 D rtw_initmac +100557a4 D rtw_adaptivity_th_l2h_ini +100557a8 d drvpriv +100557bc D skbbuf_used_num +100557c0 V skb_pool +10055978 D skbdata_used_num +1005597c d wrapper_skbbuf_list +10055984 D max_skbdata_used_num +10055988 D max_skbbuf_used_num +1005598c d skb_fail_count +10055990 D timer_table +10055998 D rltk_wlan_info +100559c8 d timer_used_num +100559cc D max_timer_used_num +100559d0 D Noisy_State +100559d4 D pExportWlanIrqSemaphore +100559d8 D gDeltaSwingTableXtal_MP_N_TxXtalTrack_8195A +100559f6 D .ram.bss$$Limit +100559f6 D __bss_end__ +100559f8 B __ram_heap2_start__ 10070000 A __ram_heap2_end__ 1fff0000 D __ram_tcm_start__ 1fff0000 D __tcm_heap_start__ diff --git a/project/src/driver/i2s_freertos.c b/project/src/driver/i2s_freertos.c index 9627877..8fdefdc 100644 --- a/project/src/driver/i2s_freertos.c +++ b/project/src/driver/i2s_freertos.c @@ -187,7 +187,8 @@ char i2sSetRate(int mask, int rate) { //at least the current sample rate. You can also call it quicker: it will suspend the calling //thread if the buffer is full and resume when there's room again. u32 i2sPushPWMSamples(u32 sample) { - for(int i = 0; i < MAX_I2S_OBJS; i++) { + int i; + for(i = 0; i < MAX_I2S_OBJS; i++) { PI2S_OBJS pi2s_cur = pi2s[i]; PHAL_I2S_ADAPTER I2SAdapter = &pi2s_cur->i2s_obj.I2SAdapter; while(pi2s_cur->currDMABuff == NULL){ @@ -242,7 +243,7 @@ u32 i2sPushPWMSamples(u32 sample) { pi2s_cur->currDMABuffPos += 4; } portENTER_CRITICAL(); - for(int i = 0; i < MAX_I2S_OBJS; i++) { + for(i = 0; i < MAX_I2S_OBJS; i++) { PI2S_OBJS pi2s_cur = pi2s[i]; if (pi2s_cur->currDMABuffPos > pi2s_cur->i2s_obj.InitDat.I2SPageSize) { #if USE_RTL_I2S_API