diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_bios_data.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_bios_data.c index 9826f15..e9bb21b 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_bios_data.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_bios_data.c @@ -38,8 +38,7 @@ INFRA_RAM_BSS_SECTION u32 _rand_z4, _rand_z3, _rand_z2, _rand_z1, _rand_first; / MON_RAM_BSS_SECTION u8 *ArgvArray[MAX_ARGV]; // 100006AC *ArgvArray[10] ! MON_RAM_BSS_SECTION u8 UartLogHistoryBuf[UART_LOG_HISTORY_LEN][UART_LOG_CMD_BUFLEN]; // 10000430 UartLogHistoryBuf[5][127] ! MON_RAM_BSS_SECTION volatile UART_LOG_CTL UartLogCtl; // 10000408 -/* -= { +/* = { .NewIdx = 0, .SeeIdx = 0, .RevdNo = UART_LOG_HISTORY_LEN, @@ -53,11 +52,10 @@ MON_RAM_BSS_SECTION volatile UART_LOG_CTL UartLogCtl; // 10000408 .pCmdTbl = (PCOMMAND_TABLE) &UartLogRomCmdTable, .CmdTblSz = 6, .CRSTS = 0, - .pHistoryBuf = UartLogHistoryBuf, + .pHistoryBuf = &UartLogHistoryBuf, .TaskRdy = 0 // .Sema -}; -*/ +}; */ MON_RAM_BSS_SECTION UART_LOG_BUF UartLogBuf; // 10000388 MON_RAM_BSS_SECTION volatile UART_LOG_CTL *pUartLogCtl = &UartLogCtl; // 10000384 /* ROM + LIB C */ diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c index 93b9f7f..45fb82a 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c @@ -1,5 +1,5 @@ /* - * BootLoader + * BootLoader Ver 0.2 * Created on: 12/02/2017 * Author: pvvx */ @@ -9,6 +9,8 @@ #include "diag.h" #include "rtl8195a/rtl8195a_sys_on.h" +#include "hal_spi_flash.h" + //------------------------------------------------------------------------- // Data declarations @@ -29,12 +31,6 @@ #endif // DEFAULT_BOOT_CLK_CPU #define BOOT_RAM_TEXT_SECTION // __attribute__((section(".boot.text"))) -//#define BOOT_RAM_RODATA_SECTION __attribute__((section(".boot.rodata"))) -//#define BOOT_RAM_DATA_SECTION __attribute__((section(".boot.data"))) -//#define BOOT_RAM_BSS_SECTION __attribute__((section(".boot.bss"))) - -//extern u32 STACK_TOP; -//extern volatile UART_LOG_CTL * pUartLogCtl; //------------------------------------------------------------------------- typedef struct _seg_header { @@ -61,16 +57,18 @@ LOCAL void RtlBoot1ToSram(void); // image1 LOCAL void RtlBoot2ToSram(void); // image1 LOCAL void RtlBoot3ToSram(void); // image1 LOCAL void RtlBoot4ToSram(void); // image1 -//LOCAL void EnterImage15(void); // image1 -//LOCAL void JtagOn(void); // image1 -//extern _LONG_CALL_ VOID HalCpuClkConfig(unsigned char CpuType); +extern _LONG_CALL_ VOID HalCpuClkConfig(unsigned char CpuType); extern _LONG_CALL_ VOID VectorTableInitRtl8195A(u32 StackP); extern _LONG_CALL_ VOID HalInitPlatformLogUartV02(VOID); extern _LONG_CALL_ VOID HalInitPlatformTimerV02(VOID); //extern _LONG_CALL_ VOID DramInit_rom(IN DRAM_DEVICE_INFO *DramInfo); //extern _LONG_CALL_ u32 SdrCalibration_rom(VOID); extern _LONG_CALL_ int SdrControllerInit_rom(PDRAM_DEVICE_INFO pDramInfo); +extern _LONG_CALL_ u32 SpicCmpDataForCalibrationRtl8195A(void); // compare read_data and golden_data +//extern _LONG_CALL_ VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara); // wait spi-flash status register[0] = 0 +//extern _LONG_CALL_ VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara); +//extern _LONG_CALL_ VOID RtlConsolInit(IN u32 Boot, IN u32 TBLSz, IN VOID *pTBL); //#pragma arm section code = ".boot.text"; //#pragma arm section rodata = ".boot.rodata", rwdata = ".boot.data", zidata = ".boot.bss"; @@ -85,8 +83,6 @@ START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__ = { RtlBoot2ToSram + 1, // PatchFun0(), Run if ( v40000210 & 0x10000000 ) RtlBoot3ToSram + 1, // PatchFun1(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 ) RtlBoot4ToSram + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 ) -//test RtlBootToFlash + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 ) - //------------------------------------------------------------------------- /* Set Debug Flags */ LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() { @@ -150,30 +146,144 @@ LOCAL void INFRA_START_SECTION loguart_wait_tx_fifo_empty(void) { } extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90] -/* - LOCAL uint32 _SpicInitParaAllClk[SpicMaxMode * CPU_CLK_TYPE_NO] = { - 0x01310202, 0x011420C2, - 0x03310002, 0x011420C2, - 0x05310002, 0x011420C2, - 0x07310002, 0x011420C2, - 0x09310002, 0x011420C2, - 0x0B310002, 0x011420C2, +LOCAL uint32 InitTabParaAllClk[3 * CPU_CLK_TYPE_NO] = { + // SIO + 0x01310102, // 72t/byte + 0x03310101, // 0201 - 40t, 0101 - 39t, 0102 - 72t, 0103 - 104t + 0x05310001, // 39t + 0x07310001, + 0x09310001, + 0x0B310001, + // DIO + 0x11311301, // BaudRate = 1, RdDummyCyle = 19, DelayLine = 63, DIO + 0x13311201, // 1201 - 36t + 0x15311101, // 1101 - 35t + 0x17311101, + 0x19311101, + 0x1B311101 + // QIO +/* MXIC Flash only DIO! + 0x21311301, // BaudRate = 1, RdDummyCyle = 19, DelayLine = 63, DIO + 0x23311201, // 1201 - 36t + 0x25311101, // 1101 - 35t + 0x27311101, + 0x29311101, + 0x2B311101 +*/ +}; - 0x11311301, 0x011420C2, - 0x13311201, 0x011420C2, - 0x15311101, 0x011420C2, - 0x17311101, 0x011420C2, - 0x19311101, 0x011420C2, - 0x1B311101, 0x011420C2, +struct spic_table_flash_type { + uint8 cmd[12]; + uint8 strlr2; + uint8 fbaud; + uint8 addrlen; + uint8 fsize; + uint32 contrl; + uint16 validcmd[3]; + uint8 manufacturerid; + uint8 memorytype; +}; + +//PSPIC_INIT_PARA pSpicInitPara; + +struct spic_table_flash_type spic_table_flash = { + { // for FLASH MX25L8006E/1606E + FLASH_CMD_FREAD, // REG_SPIC_READ_FAST_SINGLE 0x400060E0 0x0B + FLASH_CMD_DREAD, // REG_SPIC_READ_DUAL_DATA 0x400060E4 0x3B + FLASH_CMD_DREAD, // REG_SPIC_READ_DUAL_ADDR_DATA 0x400060E8 0x3B ? + FLASH_CMD_QREAD, // REG_SPIC_READ_QUAD_DATA 0x400060EC 0x6B + FLASH_CMD_4READ, // REG_SPIC_READ_QUAD_ADDR_DATA 0x400060F0 0xEB ? + FLASH_CMD_PP, // REG_SPIC_WRITE_SIGNLE 0x400060F4 0x02 + FLASH_CMD_DPP, // REG_SPIC_WRITE_DUAL_DATA 0x400060F8 0xA2 + FLASH_CMD_DPP, // REG_SPIC_WRITE_DUAL_ADDR_DATA 0x400060FC 0xA2 ? + FLASH_CMD_QPP, // REG_SPIC_WRITE_QUAD_DATA 0x40006100 0x32 + FLASH_CMD_4PP, // REG_SPIC_WRITE_QUAD_ADDR_DATA 0x40006104 0x38 + FLASH_CMD_WREN, // REG_SPIC_WRITE_ENABLE 0x40006108 0x06 + FLASH_CMD_RDSR // REG_SPIC_READ_STATUS 0x4000610C 0x05 + }, + BIT_FIFO_ENTRY(5) | BIT_SO_DUM, // REG_SPIC_CTRLR2 0x40006110 0x51 + BIT_FSCKDV(1), // REG_SPIC_FBAUDR 0x40006114 0x01 + BIT_ADDR_PHASE_LENGTH(3), // REG_SPIC_ADDR_LENGTH 0x40006118 0x03 + BIT_FLASE_SIZE(0x0F), // REG_SPIC_FLASE_SIZE 0x40006124 0x0E ? + BIT_CS_H_WR_DUM_LEN(2)| BIT_AUTO_ADDR__LENGTH(3) | BIT_RD_DUMMY_LENGTH(0x0), // REG_SPIC_AUTO_LENGTH 0x4000611C 0x20030001 ? + { + BIT_WR_BLOCKING, // REG_SPIC_VALID_CMD 0x40006120 0x200 SpicOneBitMode + BIT_WR_BLOCKING | BIT_RD_DUAL_I, // REG_SPIC_VALID_CMD 0x40006120 0x200 SpicOneBitMode + BIT_WR_BLOCKING | BIT_RD_QUAD_O, // REG_SPIC_VALID_CMD 0x40006120 0x200 SpicOneBitMode + }, + 0xC2, 0x20 // MX25L8006/MX25L1606 +}; + +LOCAL int BOOT_RAM_TEXT_SECTION SetSpicBitMode(uint8 BitMode) { + PSPIC_INIT_PARA pspic = &SpicInitParaAllClk[BitMode][((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7)]; + if(pspic->Mode.Valid) { + // Disable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + HAL_SPI_WRITE32(REG_SPIC_VALID_CMD, spic_table_flash.validcmd[pspic->Mode.BitMode]); + HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, (HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH) & 0xFFFF0000) | pspic->RdDummyCyle); + HAL_SPI_WRITE32(REG_SPIC_BAUDR, pspic->BaudRate); + FLASH_DDL_FCTRL(pspic->DelayLine); // SPI_DLY_CTRL_ADDR [7:0] + // Enable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN); + } + SPI_FLASH_PIN_FCTRL(ON); + // Test Read Pattern + if(!SpicCmpDataForCalibrationRtl8195A()) { + FLASH_DDL_FCTRL(0x31); // SPI_DLY_CTRL_ADDR [7:0] + for(uint8 i = 1; i < 4; i++) { + for(uint8 x = 0; x < 63; x++) { + // Disable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); + HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, (HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH) & 0xFFFF0000) | x); + HAL_SPI_WRITE32(REG_SPIC_BAUDR, i); + // Enable SPI_FLASH User Mode + HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN); +// HAL_SPI_WRITE32(REG_SPIC_FLUSH_FIFO, 1); + if(SpicCmpDataForCalibrationRtl8195A()) { + DiagPrintf("Spic reinit %d:%d\n", i, x); + pspic->BaudRate = i; + pspic->RdDummyCyle = x; + pspic->DelayLine = 0x31; + pspic->Mode.Valid = 1; + return 1; + }; + }; + }; + return 0; + }; + return 1; +} + +void BOOT_RAM_TEXT_SECTION InitSpicFlashType(struct spic_table_flash_type *ptable_flash) { + u8 * ptrb = &ptable_flash->cmd; + volatile u32 * ptrreg = (volatile u32 *)(SPI_FLASH_CTRL_BASE + REG_SPIC_READ_FAST_SINGLE);// 0x400060E0 + HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); // Disable SPI_FLASH User Mode + do { + *ptrreg++ = *ptrb++; + } while(ptrb < (u8 *)(&ptable_flash->fsize)); + ptrreg[0] = ptable_flash->contrl; + ptrreg[1] = ptable_flash->validcmd[SpicOneBitMode]; + ptrreg[2] = ptable_flash->fsize; + HAL_SPI_WRITE32(REG_SPIC_SER, BIT_SER); +} + +LOCAL int BOOT_RAM_TEXT_SECTION InitSpic(uint8 SpicBitMode) { + _memset(SpicInitParaAllClk, 0, sizeof(SpicInitParaAllClk)); + uint32 * ptr = InitTabParaAllClk; + uint8 x; + for(x = 0; x < SpicMaxMode; x++) { + *(uint32 *)&SpicInitParaAllClk[SpicOneBitMode][x].BaudRate = ptr[0]; + *(uint32 *)&SpicInitParaAllClk[SpicDualBitMode][x].BaudRate = ptr[CPU_CLK_TYPE_NO]; + *(uint32 *)&SpicInitParaAllClk[SpicQuadBitMode][x].BaudRate = ptr[CPU_CLK_TYPE_NO]; + ptr++; + } + ACTCK_FLASH_CCTRL(1); + SLPCK_FLASH_CCTRL(1); + HalPinCtrlRtl8195A(SPI_FLASH, 0, 1); + InitSpicFlashType(&spic_table_flash); + return SetSpicBitMode(SpicBitMode); +} - 0x21311301, 0x011420C2, - 0x23311201, 0x011420C2, - 0x25311101, 0x011420C2, - 0x27311101, 0x011420C2, - 0x29311101, 0x011420C2, - 0x2B311101, 0x011420C2 - }; - */ /* SYSPlatformInit */ LOCAL void INFRA_START_SECTION SYSPlatformInit(void) { @@ -422,10 +532,12 @@ LOCAL uint8 BOOT_RAM_TEXT_SECTION IsForceLoadDefaultImg2(void) { // _pHAL_Gpio_Adapter->IrqHandle.IrqFun = NULL; return result; } - /* RTL Console ROM */ LOCAL void BOOT_RAM_TEXT_SECTION RtlConsolRam(void) { // DiagPrintf("\r\nRTL Console ROM\r\n"); +// RtlConsolInit(ROM_STAGE, (u32) 6, (void*) &UartLogRomCmdTable); + pUartLogCtl->RevdNo = UART_LOG_HISTORY_LEN; + pUartLogCtl->BootRdy = 1; pUartLogCtl->pTmpLogBuf->UARTLogBuf[0] = '?'; pUartLogCtl->pTmpLogBuf->BufCount = 1; pUartLogCtl->ExecuteCmd = 1; @@ -445,7 +557,7 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) { else DBG_8195A("\r===== Enter SRAM-Boot %d ====\n", flg); -#if CONFIG_DEBUG_LOG > 2 +#if CONFIG_DEBUG_LOG > 1 DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN)); #endif @@ -462,15 +574,10 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) { (HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x0e)); SDR_PIN_FCTRL(ON); }; - SPI_FLASH_PIN_FCTRL(ON); - *(uint32 *)(&SpicInitParaAllClk[0][0].BaudRate) = 0x1311301; // patch - *(uint32 *)(&SpicInitParaAllClk[1][0].BaudRate) = 0x1311301; // patch - SpicInitRtl8195AV02(CPU_CLK_TYPE_NO - 1 - ((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7), - SpicDualBitMode); - if (!SpicCmpDataForCalibrationRtl8195A()) { - DBG_8195A("Error Init Spic DIO!\n"); + if (!InitSpic(SpicDualBitMode)) { + DBG_8195A("Spic Init Error!\n"); RtlConsolRam(); - } + }; if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // уже загружена? // extern DRAM_DEVICE_INFO SdrDramInfo_rom; // 50 MHz if (!SdrControllerInit_rom(&SdrDramInfo)) { // 100 MHz @@ -500,7 +607,7 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) { if (!flg) loadUserImges(IsForceLoadDefaultImg2() + 1); if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) { - DBG_MISC_ERR("Invalid Image Signature!\n"); + DBG_8195A("Invalid Image Signature!\n"); RtlConsolRam(); } DBG_8195A("Img Sign: %s, Go @ 0x%08x\r\n", &__image2_validate_code__, diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c index 903b310..ee68e4a 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c @@ -75,6 +75,7 @@ void INFRA_START_SECTION SYSPlatformInit(void) { (HAL_SYS_CTRL_READ32(REG_SYS_XTAL_CTRL1) & (~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1))) | BIT_SYS_XTAL_DRV_RF1(1)); // & 0xFFFFFFE7 | 8; +/* if(HalGetCpuClk() != PLATFORM_CLOCK) { //----- CLK CPU loguart_wait_tx_fifo_empty(); // иначе глючит LogUART, если переключение CLK приходится на вывод символов ! @@ -92,6 +93,7 @@ void INFRA_START_SECTION SYSPlatformInit(void) { HalInitPlatformLogUartV02(); // Show ""... :( HalInitPlatformTimerV02(); }; +*/ } //----- SDIO_Device_Off @@ -151,11 +153,15 @@ extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter; #if CONFIG_DEBUG_LOG > 2 DBG_8195A("\rCPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN)); #endif - _memset(SpicInitParaAllClk, 0, sizeof(SpicInitParaAllClk)); - *(uint32 *)(&SpicInitParaAllClk[0][0].BaudRate) = 0x1311301; // patch - *(uint32 *)(&SpicInitParaAllClk[1][0].BaudRate) = 0x1311301; // patch +// _memset(SpicInitParaAllClk, 0, sizeof(SpicInitParaAllClk)); + *(uint32 *)(&SpicInitParaAllClk[0][0].BaudRate) = 0x01310202; // patch + *(uint32 *)(&SpicInitParaAllClk[1][0].BaudRate) = 0x11311301; // patch +// *(uint32 *)(&SpicInitParaAllClk[2][0].BaudRate) = 0x21311301; // patch SPI_FLASH_PIN_FCTRL(ON); - uint8 SpicBaudRate = CPU_CLK_TYPE_NO - 1 - ((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7); +/* +// uint8 SpicBaudRate = CPU_CLK_TYPE_NO - 1 - ((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7); + uint8 SpicBaudRate = 3; // HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7; + DBG_8195A("SpicBaudRate = %d\n", SpicBaudRate); SpicInitRtl8195AV02(SpicBaudRate, SpicDualBitMode); if(!SpicCmpDataForCalibrationRtl8195A()) { DBG_8195A("ReInit Spic to SIO...\n"); @@ -164,7 +170,8 @@ extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter; DBG_8195A("Error Init Spic!\n"); }; }; - SpicFlashInitRtl8195A(SpicDualBitMode); // SpicReadIDRtl8195A(); SpicDualBitMode +*/ +// SpicFlashInitRtl8195A(SpicDualBitMode); // SpicReadIDRtl8195A(); SpicDualBitMode uint8 ChipId = HalGetChipId(); if (ChipId >= CHIP_ID_8195AM) { #ifdef CONFIG_SDR_EN diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img2.ld b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img2.ld index 2edf4c0..02d6016 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img2.ld +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img2.ld @@ -76,7 +76,7 @@ SECTIONS KEEP(*(.hal.flash.data)) KEEP(*(.boot.rodata*)) KEEP(*(.boot.text*)) - KEEP(*(.boot.data)) + KEEP(*(.boot.data*)) __image1_bss_start__ = .; KEEP(*(.boot.bss*)) __image1_bss_end__ = .; diff --git a/build/bin/ota.bin b/build/bin/ota.bin index 895566f..ba9de97 100644 Binary files a/build/bin/ota.bin and b/build/bin/ota.bin differ diff --git a/build/bin/ram_1.p.bin b/build/bin/ram_1.p.bin index 85e4a99..99c6d43 100644 Binary files a/build/bin/ram_1.p.bin and b/build/bin/ram_1.p.bin differ diff --git a/build/bin/ram_2.bin b/build/bin/ram_2.bin index 5f68fe4..3322889 100644 Binary files a/build/bin/ram_2.bin and b/build/bin/ram_2.bin differ diff --git a/build/bin/ram_2.ns.bin b/build/bin/ram_2.ns.bin index 0e58328..8dd1524 100644 Binary files a/build/bin/ram_2.ns.bin and b/build/bin/ram_2.ns.bin differ diff --git a/build/bin/ram_2.p.bin b/build/bin/ram_2.p.bin index 5e307a7..bcf8cfc 100644 Binary files a/build/bin/ram_2.p.bin and b/build/bin/ram_2.p.bin differ diff --git a/build/bin/ram_all.bin b/build/bin/ram_all.bin index 674ddd9..3ebfe04 100644 Binary files a/build/bin/ram_all.bin and b/build/bin/ram_all.bin differ diff --git a/build/obj/build.nmap b/build/obj/build.nmap index 28677e0..0f5b9a0 100644 --- a/build/obj/build.nmap +++ b/build/obj/build.nmap @@ -803,21 +803,22 @@ 1000229c t tab_seg_def 10002400 B __rom_heap_start__ 10002400 B end -10002434 t flashcpy -100024d4 t get_seg_id -10002508 t RtlConsolRam -10002528 t EnterImage15 -10002994 t RtlBoot4ToSram -1000299a t RtlBoot3ToSram -100029a0 t RtlBoot2ToSram -100029a6 t RtlBoot1ToSram -100029ac t RtlBootToFlash -100029b8 t __HalCpuClkConfig_veneer -100029c8 t __SpicCmpDataForCalibrationRtl8195A_veneer -100029d8 T SEG_ID -100029d8 T __image1_bss_start__ -100029dc T __image1_bss_end__ -100029dc T __ram_image1_text_end__ +1000245a t flashcpy +100024f8 t get_seg_id +1000252c t RtlConsolRam +10002550 T InitSpicFlashType +10002590 t EnterImage15 +10002b5c t RtlBoot4ToSram +10002b62 t RtlBoot3ToSram +10002b68 t RtlBoot2ToSram +10002b6e t RtlBoot1ToSram +10002b74 t RtlBootToFlash +10002b7c T spic_table_flash +10002b98 t InitTabParaAllClk +10002be0 T SEG_ID +10002be0 T __image1_bss_start__ +10002be4 T __image1_bss_end__ +10002be4 T __ram_image1_text_end__ 10003000 B __ram_heap1_start__ 10003000 B __rom_heap_end__ 10006000 D .image2.start.table1$$Base @@ -829,2375 +830,2371 @@ 10006004 D __image2_validate_code__ 10006018 D cus_sig 10006038 T SYSPlatformInit -100060b0 T SDIO_Device_Off -100060d4 T InfraStart -10006230 T UartLogIrqHandleRam -100062f8 T RtlConsolTaskRam -100063c0 T console_init -1000648c T SpicRxCmdRefinedRtl8195A -10006594 T SpicInitRefinedRtl8195A -10006648 T SpicReadIDRtl8195A -1000674c T SpicConfigAutoModeRtl8195A -100067bc T SpicUserReadRtl8195A -10006930 T SpicUserReadFourByteRtl8195A -10006a4c T SpicGetExtendAddrRtl8195A -10006aa4 T SpicGetConfigRegRtl8195A -10006afc T SpicGetFlashStatusRefinedRtl8195A -10006b54 T SpicWaitWipDoneRefinedRtl8195A -10006b90 T SpicTxCmdWithDataRtl8195A -10006c64 T SpicGetFlashFlagRtl8195A -10006cf0 T SpicWaitOperationDoneRtl8195A -10006d2c T SpicDeepPowerDownFlashRtl8195A -10006db8 T SpicUserProgramRtl8195A -10006fe8 T SpicWaitWipRtl8195A -10006ffc T SpicTxFlashInstRtl8195A -10007090 T SpicEraseFlashRefinedRtl8195A -1000709a T SpicDieEraseFlashRtl8195A -100070bc T SpicBlockEraseFlashRtl8195A -100070de T SpicSectorEraseFlashRtl8195A -10007100 T SpicSetExtendAddrRtl8195A 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-10029370 T rtw_alloc_hwxmits -100293ca T rtw_free_hwxmits -100293e0 T _rtw_free_xmit_priv -100294ac T rtw_init_hwxmits -100294c4 T _rtw_init_xmit_priv -1002967c T rtw_get_ff_hwaddr -10029690 T xmitframe_enqueue_for_sleeping_sta -10029850 t dequeue_xmitframes_to_sleeping_queue -100298a6 T stop_sta_xmit -1002998e T wakeup_sta_to_xmit -10029ba4 T xmit_delivery_enabled_frames -10029cc0 T rtw_xmit_tasklet -10029d18 T rtw_xmit_mgnt -10029d1c T rtw_xmit -1002a046 T rtw_sctx_done_err -1002a052 T rtw_alloc_xmitbuf -1002a0ac T rtw_free_xmitbuf -1002a11e T rtw_alloc_xmitbuf_ext -1002a1a4 T rtw_sctx_done -1002a1aa t rtl8195a_free_rx_ring -1002a1b8 t bus_write32 -1002a214 t bus_write16 -1002a270 t bus_write8 -1002a2cc t bus_read32 -1002a326 t bus_read16 -1002a382 t bus_read8 -1002a3de t rtl8195a_free_tx_ring -1002a46c T rtl8195a_init_desc_ring -1002a5ac T rtl8195a_free_desc_ring -1002a5c8 T rtl8195a_reset_desc_ring -1002a65e T InitLxDmaRtl8195a -1002a7c0 T rtl8195a_check_txdesc_closed -1002a838 t rtl8195a_tx_isr -1002a91c T InterruptRecognized8195a -1002a9ac T InitInterrupt8195a -1002a9cc T EnableDMA8195a -1002a9f4 T EnableInterrupt8195a -1002aa34 T DisableDMA8195a -1002aa40 T DisableInterrupt8195a -1002aa58 T UpdateInterruptMask8195a -1002aaba T CheckRxTgRtl8195a -1002aaf4 T rtl8192ee_check_rxdesc_remain -1002ab24 T rtl8195a_recv_tasklet -1002ae38 T rtl8195a_tx_int_handler -1002ae64 T InterruptHandle8195a -1002b0d8 T rtl8195a_xmit_tasklet -1002b100 T lxbus_set_intf_ops -1002b140 t GetTxBufDesc -1002b18a t UpdateFirstTxbdtoXmitBuf.isra.3 -1002b1bc t check_nic_enough_desc.isra.4 -1002b20c T rtl8195ab_init_xmit_priv -1002b21a T rtl8195ab_free_xmit_priv -1002b222 T GetDmaTxbdIdx -1002b23e T rtl8195a_enqueue_xmitbuf -1002b262 T rtl8195a_dequeue_xmitbuf -1002b286 T SetTxbdForLxDMARtl8195ab -1002b306 T UpdateTxbdHostIndex -1002b344 T rtw_dump_xframe -1002b516 T check_tx_desc_resource -1002b550 T rtw_dequeue_xframe -1002b5e4 T rtw_xmitframe_coalesce -1002b898 T rtl8195ab_xmitframe_resume -1002b98e T rtl8195ab_mgnt_xmit -1002b9ca T rtl8195ab_hal_xmit -1002bad8 t Hal_GetEfuseDefinition -1002bb08 t ResumeTxBeacon -1002bb4c T UpdateHalRAMask8195A -1002bce4 T HalLittleWifiMCUThreadRtl8195a -1002bd38 T HalCheckInReqStateThreadRtl8195a -1002bd84 T HalTDMAChangeStateThreadRtl8195a -1002bdd0 t rtl8195a_read_chip_version -1002be44 t Hal_EfuseWordEnableDataWrite -1002c088 t Hal_EfusePowerSwitch -1002c09c t rtl8195a_free_hal_data -1002c0b6 t StopTxBeacon -1002c100 T SetHalODMVar8195A -1002c1b8 T rtl8195a_start_thread -1002c220 T rtl8195a_stop_thread -1002c244 t Hal_ReadEFuse -1002c3b4 T GetHalODMVar8195A -1002c3c8 t rtw_flash_map_update.part.12 -1002c468 t rtw_flash_map_erase -1002c4ac t Hal_EfusePgPacketWrite -1002c728 t Hal_EfuseGetCurrentSize -1002c808 t rtw_flash_map_write -1002c9d6 T rtl8195a_InitBeaconParameters -1002ca46 T _InitBurstPktLen_8195AB -1002ca50 T rtl8195a_set_hal_ops -1002cb30 T rtl8195a_init_default_value -1002cb32 T rtl8195a_InitLLTTable -1002cb7c T Hal_GetChnlGroup8195A -1002cbb8 T rtw_config_map_read -1002cca4 T rtw_config_map_write -1002cd50 T Hal_InitPGData -1002cdae T Hal_EfuseParseIDCode -1002cdc6 T Hal_ReadPowerValueFromPROM_8195A -1002ce64 T Hal_EfuseParseTxPowerInfo_8195A -1002cefc T Hal_EfuseParseEEPROMVer_8195A -1002cf12 T Hal_EfuseParsePackageType_8195A -1002cf7c T Hal_EfuseParseChnlPlan_8195A -1002cfac T Hal_EfuseParseCustomerID_8195A -1002cfc2 T Hal_EfuseParseXtal_8195A -1002cfda T Hal_EfuseParseThermalMeter_8195A -1002d002 T Hal_ReadRFGainOffset -1002d052 T BWMapping_8195A -1002d072 T SCMapping_8195A -1002d09a T rtl8195a_update_txdesc -1002d36a T rtl8195a_fill_fake_txdesc -1002d428 T SetHwReg8195A -1002e0e8 T GetHwReg8195A -1002e17c T SetHalDefVar8195A -1002e25c T GetHalDefVar8195A -1002e280 T PHY_QueryBBReg_8195A_Safe -1002e2ac T PHY_SetBBReg_8195A_Safe -1002e2d8 t phy_RFSerialRead_8195A -1002e38c T PHY_QueryRFReg_8195A -1002e3a4 T PHY_SetRFReg_8195A -1002e3fc T PHY_MACConfig8195A -1002e416 T PHY_BBConfig8195A -1002e526 T PHY_RFConfig8195A -1002e52a T PHY_SetTxPowerIndex_8195A -1002e634 T phy_TxPwrAdjInPercentage -1002e674 T PHY_GetTxPowerIndex_8195A -1002e764 T PHY_SetTxPowerLevel8195A -1002e76a T phy_SpurCalibration_8195A -1002ea22 T phy_SetRegBW_8195A -1002ea60 T phy_PostSetBwMode8195A -1002ebbc T phy_SwChnl8195A -1002ec64 T phy_SwChnlAndSetBwMode8195A -1002ecb4 T PHY_HandleSwChnlAndSetBW8195A -1002ed64 T PHY_SetBWMode8195A -1002ed86 T PHY_SwChnl8195A -1002eda0 T PHY_SetSwChnlBWMode8195A -1002edbe t HalTimerEnable -1002edd0 T InitTDMATimer -1002edf8 T ChangeStateByTDMA -1002ee08 T GetMinRateInRRSR -1002ee3c T CheckInReqState -1002ee4c T InitCheckStateTimer -1002ee7c T InitGTimer1ms -1002eec8 T DeInitGTimer1ms -1002ef10 T ChangeTransmiteRate -1002ef4c T PowerBitSetting -1002efc8 T ChkandChangePS -1002f02c T IssueRsvdPagePacketSetting -1002f0a0 T IssuePSPoll -1002f0cc T WaitTxStateMachineOk -1002f120 T IssueNullData -1002f1b0 T PsCloseRF -1002f1e4 T PsOpenRF -1002f214 T ChkTxQueueIsEmpty -1002f22c T InitPS -1002f29c T ConfigListenBeaconPeriod -1002f2c0 T PS_S2_Condition_Match -1002f2f4 T PS_S4_Condition_Match -1002f370 T PS_32K_Condition_Match -1002f3ac T PS_S2ToS3ToS0State -1002f414 T PS_S2ToS0State -1002f430 T PS_S3ToS2orS0State -1002f460 T PS_S0ToS1ToS2State -1002f4bc T PS_S1ToS0orS2State -1002f4ec T PS_S2ToS4State -1002f538 T PS_S0ToS6State -1002f558 T PS_S6ToS0State -1002f570 T CheckTSFIsStable -1002f5c0 T WaitHWStateReady -1002f5d0 T SysClkDown -1002f640 T SysClkUp -1002f68c T ResetPSParm -1002f700 T PS_S4ToS2State -1002f724 T SleepTo32K -1002f784 T Change_PS_State -1002f930 T Legacy_PS_Setting -1002f9a4 T PSModeSetting -1002fa48 T ChangePSStateByRPWM -1002fa8c T ChangeTDMAState -1002fbac T TDMAChangeStateTask -1002fbd6 T EnterPS -1002fbf8 T SetSmartPSTimer -1002fc34 T GTimer7Handle -1002fc90 T SmartPS2InitTimerAndToGetRxPkt -1002fccc T PS_OnBeacon -1002fd7c T PSBcnEarlyProcess -1002fe38 T PSMtiBcnEarlyProcess -1002fee4 T PSRxBcnProcess -10030034 T TxPktInPSOn -10030072 T PsBcnToProcess -1003012c T GTimer6Handle -10030178 T RPWMProcess -100301b4 T PSSetMode -1003022c T SpeRPT -1003034c T ISR_BcnEarly -100303b8 T ISR_MtiBcnEarly -100303ec T ISR_RxBcn -10030408 T ISR_RxBCMD1 -10030438 T ISR_RxBCMD0 -1003048c T ISR_RxUCMD1 -100304ca T ISR_RxUCMD0 -10030506 T ISR_TxPktIn -10030518 T ISR_TXCCX -1003051c T H2CHDL_SetPwrMode -10030644 T CheckInReqStateTask -1003068a T HalGetNullTxRpt -100306a8 T ISR_TBTT -10030720 T H2CHDL_BcnIgnoreEDCCA -10030730 T PMUInitial -10030780 T PMUTask -1003088c T PHY_RF6052SetBandwidth8195A -100308d0 T PHY_RF6052_Config8195A -10030988 t process_rssi -100309be T rtl8195a_query_rx_desc_status -10030a6e T rtl8195a_query_rx_phy_status -10030bc6 T hal_com_get_channel_plan -10030bfa T HAL_IsLegalChannel -10030c18 T MRateToHwRate -10030c2c T HwRateToMRate -10030c40 T HalSetBrateCfg -10030cec T Hal_MappingOutPipe -10030d08 T hal_init_macaddr -10030d34 T hw_var_port_switch -10030fbc T SetHwReg -10030fc6 T GetHwReg -10030fc8 T switch_power_saving_mode -1003100c T rtw_bb_rf_gain_offset -10031054 T PHY_GetRateValuesOfTxPowerByRate -100311ec T PHY_StoreTxPowerByRateNew -10031288 T PHY_InitTxPowerByRate -100312a0 T PHY_StoreTxPowerByRate -100312b8 T PHY_GetTxPowerIndexBase -10031358 T PHY_GetTxPowerTrackingOffset -10031384 T PHY_GetRateIndexOfTxPowerByRate -10031398 T PHY_GetTxPowerByRate -100313f8 T phy_StoreTxPowerByRateBase -10031444 T PHY_SetTxPowerByRate -10031480 T phy_ConvertTxPowerByRateInDbmToRelativeValues -10031580 T PHY_TxPowerByRateConfiguration -10031592 T PHY_SetTxPowerIndexByRateArray -100315d0 T PHY_SetTxPowerIndexByRateSection -10031634 T PHY_SetTxPowerLevelByPath -1003166a T phy_GetWorldWideLimit -10031696 T PHY_GetTxPowerLimit -100317c0 T PHY_ConvertTxPowerLimitToPowerIndex -10031910 T PHY_InitTxPowerLimit -10031958 T PHY_SetTxPowerLimit -100319d4 T PHY_GetTxPowerIndex -100319e4 T rtw_hal_chip_configure -100319fa T rtw_hal_read_chip_info -10031a10 T rtw_hal_read_chip_version -10031a26 T rtw_hal_def_value_init -10031a3c T rtw_hal_free_data -10031a52 T rtw_hal_dm_init -10031a68 T rtw_hal_dm_deinit -10031a7e T rtw_hal_init -10031aa8 T rtw_hal_deinit -10031ac2 T rtw_hal_set_hwreg -10031ad0 T rtw_hal_get_hwreg -10031ade T rtw_hal_set_def_var -10031af0 T rtw_hal_get_def_var -10031b02 T rtw_hal_set_odm_var -10031b10 T rtw_hal_get_odm_var -10031b1e T rtw_hal_enable_interrupt -10031b40 T rtw_hal_disable_interrupt -10031b62 T rtw_hal_inirp_init -10031b74 T rtw_hal_inirp_deinit -10031b86 T rtw_hal_irp_reset -10031b94 T rtw_hal_xmit -10031ba6 T rtw_hal_mgnt_xmit -10031bb8 T rtw_hal_init_xmit_priv -10031bca T rtw_hal_free_xmit_priv -10031bd8 T rtw_hal_update_ra_mask -10031c06 T rtw_hal_add_ra_tid -10031c14 T rtw_hal_clone_data -10031c22 T rtw_hal_start_thread -10031c30 T rtw_hal_stop_thread -10031c3e T rtw_hal_read_bbreg -10031c72 T rtw_hal_write_bbreg -10031c9e T rtw_hal_read_rfreg -10031cb0 T rtw_hal_write_rfreg -10031cc4 T rtw_hal_interrupt_handler -10031cd6 T rtw_hal_set_bwmode -10031ce4 T rtw_hal_set_chan -10031cf2 T rtw_hal_set_chnl_bw -10031d08 T rtw_hal_dm_watchdog -10031d1e T rtw_hal_macid_sleep -10031d3e T rtw_hal_macid_wakeup -10031d5e T decide_chip_type_by_device_id -10031d64 t rtw_net_get_stats -10031db4 t netdev_if2_close -10031dd4 t netdev_close -10031e30 t rtw_if1_deinit -10031eca T rtw_os_indicate_connect -10031ece T rtw_os_indicate_scan_done -10031ed2 T rtw_reset_securitypriv -10031fc6 T rtw_os_indicate_disconnect -10032010 T rtw_init_netdev -10032160 T rtw_drv_if2_init -10032368 T rtw_drv_if2_stop -100323be T rtw_drv_if2_free -1003240c T _netdev_open -10032528 T _netdev_if2_open -100325e4 T netdev_if2_open -1003260c T netdev_open -10032634 T rtw_drv_probe -100327b4 T rtw_dev_remove -100327f8 T rtw_drv_entry -10032824 T rtw_drv_halt -10032854 t rtw_wx_set_autoreconnect -10032882 t rtw_wx_get_autoreconnect -10032890 t rtw_forwarding_set -100328b2 t rtw_set_ch_deauth -100328d4 t get_priv_size -100328e8 t rtw_wx_del_custome_ie -10032934 t rtw_wx_set_pscan_freq -100329b6 t rtw_wx_update_custome_ie -10032a28 t rtw_set_tos_value -10032a48 t rtw_get_tx_power -10032b8c t rtw_wx_set_custome_ie -10032c38 t rtw_pm_get -10032c7c t rtw_pm_set -10032d30 t rtw_wx_read32 -10032ddc t rtw_wx_write32 -10032e40 t rtw_wx_set_freq.isra.10 -10032ee8 T rtw_ex_set -10032fa8 T wireless_send_event -10032fb2 T indicate_wx_custom_event -1003300e T indicate_wx_scan_result_present -10033036 T indicate_wx_scan_complete_event -10033060 T rtw_indicate_sta_assoc -100330b0 T rtw_indicate_sta_disassoc -10033108 T rtw_indicate_wx_assoc_event -1003313a T rtw_indicate_wx_disassoc_event -1003316a T rtw_set_wpa_ie -10033280 T strtopsk -100332ec T rtw_wx_get_passphrase -10033338 T rtw_wx_set_ap_essid -10033428 T mac_reg_dump -100334d4 T bb_reg_dump -10033530 T rf_reg_dump -100335a8 t rtw_dbg_port -10033c10 T rtw_set_sta_num -10033c2c T rtw_ex_get_drv_ability -10033cec T rtw_ex_get -10033f84 T rtw_ioctl -10034f10 T rtw_os_recv_resource_init -10034f14 T rtw_os_recv_resource_alloc -10034f1e T rtw_os_recv_resource_free -10034f20 T rtw_tkip_countermeasure -10034fc0 T rtw_handle_tkip_mic_err -10035068 T rtw_recv_indicatepkt -100352b8 T skb_fail_inc -100352d4 T skb_fail_get_and_rst -100352f0 T init_skb_pool -10035348 T init_skb_data_pool -100353a0 T alloc_skb -100354a0 T kfree_skb -10035508 T kfree_skb_chk_key -1003550c T skb_put -10035540 T skb_reserve -1003554e T dev_alloc_skb -1003556a T skb_end_pointer -1003556e T skb_set_tail_pointer -10035576 T skb_pull -1003558e T skb_copy -100355b6 T rtw_remainder_len -100355c2 T _rtw_open_pktfile -100355d4 T _rtw_pktfile_read -10035602 T rtw_set_tx_chksum_offload -10035604 T rtw_os_xmit_resource_alloc -1003560e T rtw_os_xmit_resource_free -10035610 T rtw_os_pkt_complete -10035618 T rtw_os_xmit_complete -1003562a T rtw_os_xmit_schedule -10035666 T rtw_xmit_entry -100356b2 T rtw_alloc_etherdev_with_old_priv -100356c8 T rtw_alloc_etherdev -100356f4 T rtw_free_netdev -10035714 T timer_wrapper -10035768 T alloc_etherdev -100357c4 T free_netdev -100357de T dev_alloc_name -100357e8 T init_timer_wrapper -10035808 T deinit_timer_wrapper -10035854 T init_timer -1003590c T mod_timer -100359ec T cancel_timer_ex -10035a34 T del_timer_sync -10035a98 T rtw_init_timer -10035aa0 T rtw_set_timer -10035aa4 T rtw_cancel_timer -10035aae T rtw_del_timer -10035ab4 T rltk_get_idx_bydev -10035ac4 T rltk_wlan_init -10035b4c T rltk_wlan_deinit -10035c10 T rltk_wlan_start -10035c44 T rltk_wlan_check_isup -10035c54 T rltk_wlan_tx_inc -10035c68 T rltk_wlan_tx_dec -10035c7c T rltk_wlan_get_recv_skb -10035c8c T rltk_wlan_alloc_skb -10035ccc T rltk_wlan_send_skb -10035d00 T rltk_netif_rx -10035dac T rltk_set_sta_num -10035db0 T rltk_set_tx_power_percentage -10035de4 T rltk_wlan_control -10035e78 T rltk_wlan_running -10035e90 T rltk_wlan_handshake_done -10035ec4 T rltk_wlan_is_connected_to_ap -10035f08 T Efuse_PowerSwitch -10035f14 T Efuse_GetCurrentSize -10035f20 T Efuse_CalculateWordCnts -10035f44 T EFUSE_GetEfuseDefinition -10035f58 T efuse_OneByteRead -10035f8c T efuse_OneByteWrite -10035fc0 T Efuse_PgPacketWrite -10035fd4 T efuse_WordEnableDataRead -10036006 T Efuse_WordEnableDataWrite -1003601a T efuse_GetCurrentSize -10036042 T rtw_efuse_map_read -100360a4 T rtw_efuse_map_write -10036224 T rtw_macaddr_cfg -100362e8 T rtw_get_cipher_info -10036362 T rtw_get_bcn_info -10036432 T rtw_init_default_value -100364a0 T rtw_cancel_all_timer -1003650a T rtw_free_drv_sw -10036580 T rtw_reset_drv_sw -100365dc T rtw_init_drv_sw -10036664 T rtw_start_drv_threads -10036720 T rtw_stop_drv_threads -10036754 T rtw_read8 -10036762 T rtw_read16 -10036770 T rtw_read32 -1003677e T rtw_write8 -1003678c T rtw_write16 -1003679a T rtw_write32 -100367a8 T rtw_do_join -1003684c T rtw_set_802_11_bssid -100369d0 T rtw_set_802_11_ssid -10036ad8 T rtw_set_802_11_infrastructure_mode -10036b7a T rtw_set_802_11_bssid_list_scan -10036bca T rtw_set_802_11_authentication_mode -10036bec T rtw_set_802_11_add_wep -10036c4c T ODM_InitRAInfo -10036cec T InitialRateUpdate -10036dec T RateUp_search_RateMask -10036e1e T RateDown_search_RateMask -10036e70 T StartRateByRSSI -10036e9a T RateUpRAM8195A -10036f2e T RateDownTrying -10036f6c T TryDone -10037004 T RateDownStepRAM8195A -100370a4 T RateDecisionRAM8195A -10037188 T ArfrRefresh -10037390 T H2CHDL_Set_MACID_Config -10037454 T PHY_DM_RA_SetRSSI_8195A -10037482 t CheckPositive.isra.0 -10037564 T ODM_ReadAndConfig_MP_8195A_AGC_TAB -100375dc T ODM_ReadAndConfig_MP_8195A_PHY_REG -10037654 T ODM_GetVersion_MP_8195A_PHY_REG -10037658 T ODM_ReadAndConfig_MP_8195A_PHY_REG_PG -1003768c T odm_ConfigRFReg_8195A -100376c4 T odm_ConfigRF_RadioA_8195A -100376d4 T odm_ConfigMAC_8195A -100376d8 T odm_ConfigBB_AGC_8195A -100376e8 T odm_ConfigBB_PHY_REG_PG_8195A -10037716 T odm_ConfigBB_PHY_8195A -1003775e T odm_ConfigBB_TXPWR_LMT_8195A -10037784 T ODM_CmnInfoInit -10037878 T ODM_CmnInfoHook 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console_commands +1004d1e0 d UartLogRamCmdTable_end +1004d1e4 D __data_start__ +1004d1e4 D wlan_st_name +1004d1ec D wifi_st_dhcp +1004d1fc D wlan_ap_name +1004d204 D wifi_ap_dhcp +1004d214 D feep_tab +1004d244 D wifi_st_cfg +1004d2b0 D wifi_cfg +1004d2b7 D wlan_ap_netifn +1004d2b8 D wifi_ap_cfg +1004d324 D oversampling +1004d328 D SystemCoreClock +1004d32c D error_flag +1004d330 d tcp_port +1004d334 d iss.7348 +1004d338 d udp_port +1004d33a D lwip_host_name +1004d35a d dhcp_server_state_machine +1004d35b d dhcp_recorded_xid +1004d360 d uxCriticalNesting +1004d364 d xNextTaskUnblockTime +1004d368 d seed.11739 +1004d36c d wakeup_event +1004d370 d wakelock +1004d374 d last_wakelock_state +1004d394 D mlme_sta_tbl +1004d404 d PMKID_KDE_TYPE.17744 +1004d40c V nr_xmitbuff +1004d410 V nr_xmitframe +1004d414 d P802_1H_OUI +1004d417 D rtw_adaptivity_mode +1004d418 D g_user_ap_sta_num +1004d41c d rtw_private_handler +1004d460 V max_local_skb_num +1004d464 V max_skb_buf_num +1004d468 D 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D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_QFN56_8195A +1004e568 D Array_MP_8195A_RadioA +1004eb30 D gDeltaSwingTableXtal_MP_P_TxXtalTrack_8195A +1004eb4e D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_TFBGA96_8195A +1004eb6e D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN48_8195A +1004eb8c D .ram.bss$$Base +1004eb8c D __bss_start__ +1004eb8c D __data_end__ +1004eb8c D __ram_image2_text_end__ +1004eb8c d skbdata_list +1004eb94 V skb_data_pool +10051f94 d ucIdleTaskHeap +100520ac D HalI2SOpSAL +100520e8 D SYSAdapte +100520ec D PwrAdapter +10052378 D libc_has_init +1005237c d rheap_end +10052380 d event_init.21281 +10052384 D wifi_run_mode +10052388 D wlan_st_netifn +10052389 d sampCntAdd +1005238c d sampCnt +10052390 D mp3_serv +10052412 D tskreader_enable +10052414 D readBuf +10052418 D tskmad_enable +1005241c d bufUnderrunCt +10052420 d oldRate +10052424 d sampDelCnt +10052428 D pbuf_fifo +1005242c D pi2s +10052434 D I2sTxSema +10052438 D eap_method +10052439 D eap_phase +1005243c D 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pxCurrentTCB +100531fc d uxPendedTicks +10053200 d xSuspendedTaskList +10053214 d uxCurrentNumberOfTasks +10053218 d ulDeltaTotalRunTime +1005321c d xDelayedTaskList2 +10053230 d xDelayedTaskList1 +10053244 d uxTaskNumber +10053248 d xYieldPending +1005324c d uxSchedulerSuspended +10053250 d xNumOfOverflows +10053254 d pxCurrentTimerList +10053258 d xActiveTimerList1 +1005326c d xActiveTimerList2 +10053280 d xLastTime.5284 +10053284 d xTimerQueue +10053288 d pxOverflowTimerList +1005328c d xTimerTaskHandle +10053290 d device_mutex +1005329c d mutex_init +100532a0 d uxSavedInterruptStatus +100532a4 D min_free_heap_size +100532a8 d g_heap_inited +100532ac d tcm_lock +100532b0 D g_tcm_heap +100532b4 D flashobj +100532c0 D fspic_isinit +100532c4 D WDGAdapter +10053300 d last_acquire_wakelock_time +10053380 D post_sleep_callback +10053400 D pre_sleep_callback +10053480 D reserve_pll +10053484 d sys_sleep_time +10053488 d hold_wakelock_time +10053508 D missing_tick +1005350c D Timer2To7HandlerData +10053524 D auto_reconnect_running +10053528 D p_wlan_autoreconnect_hdl +1005352c D mac_monitor_callback +10053530 D mf_list_head +10053534 d pscan_retry_cnt.21430 +10053538 D promisc_callback_all +1005353c D promisc_sema +10053540 D promisc_callback +10053544 D psk_essid +1005358c D psk_passphrase +1005360e D psk_passphrase64 +1005364f D wpa_global_PSK +1005369f d RFC1042_OUI +100536a4 d rx_ring_pool +10055784 d stop_report_count.20629 +10055785 D bCheckStateTIMER +10055788 d WifiMcuCmdBitMap.20974 +1005578c D p_wlan_init_done_callback +10055790 D rtw_power_percentage_idx +10055794 D p_wlan_uart_adapter_callback +10055798 D rtw_adaptivity_en +1005579c D p_wlan_mgmt_filter +100557a0 D rtw_initmac +100557a4 D rtw_adaptivity_th_l2h_ini +100557a8 d drvpriv +100557bc D skbbuf_used_num +100557c0 V skb_pool +10055978 D skbdata_used_num +1005597c d wrapper_skbbuf_list +10055984 D max_skbdata_used_num +10055988 D max_skbbuf_used_num +1005598c d skb_fail_count +10055990 D timer_table +10055998 D rltk_wlan_info +100559c8 d timer_used_num +100559cc D max_timer_used_num +100559d0 D Noisy_State +100559d4 D pExportWlanIrqSemaphore +100559d8 D gDeltaSwingTableXtal_MP_N_TxXtalTrack_8195A +100559f6 D .ram.bss$$Limit +100559f6 D __bss_end__ +100559f8 B __ram_heap2_start__ 10070000 A __ram_heap2_end__ 1fff0000 D __ram_tcm_start__ 1fff0000 D __tcm_heap_start__ diff --git a/project/src/driver/i2s_freertos.c b/project/src/driver/i2s_freertos.c index 9627877..8fdefdc 100644 --- a/project/src/driver/i2s_freertos.c +++ b/project/src/driver/i2s_freertos.c @@ -187,7 +187,8 @@ char i2sSetRate(int mask, int rate) { //at least the current sample rate. You can also call it quicker: it will suspend the calling //thread if the buffer is full and resume when there's room again. u32 i2sPushPWMSamples(u32 sample) { - for(int i = 0; i < MAX_I2S_OBJS; i++) { + int i; + for(i = 0; i < MAX_I2S_OBJS; i++) { PI2S_OBJS pi2s_cur = pi2s[i]; PHAL_I2S_ADAPTER I2SAdapter = &pi2s_cur->i2s_obj.I2SAdapter; while(pi2s_cur->currDMABuff == NULL){ @@ -242,7 +243,7 @@ u32 i2sPushPWMSamples(u32 sample) { pi2s_cur->currDMABuffPos += 4; } portENTER_CRITICAL(); - for(int i = 0; i < MAX_I2S_OBJS; i++) { + for(i = 0; i < MAX_I2S_OBJS; i++) { PI2S_OBJS pi2s_cur = pi2s[i]; if (pi2s_cur->currDMABuffPos > pi2s_cur->i2s_obj.InitDat.I2SPageSize) { #if USE_RTL_I2S_API