2016-11-09 00:56:41 +00:00
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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*/
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#ifndef _HAL_8195A_H_
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#define _HAL_8195A_H_
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#include "platform_autoconf.h"
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#include "basic_types.h"
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#include "section_config.h"
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#include "rtl8195a_sys_on.h"
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#include "rtl8195a_peri_on.h"
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#include "hal_platform.h"
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#include "hal_pinmux.h"
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#include "hal_api.h"
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#include "hal_peri_on.h"
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#include "hal_misc.h"
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#include "hal_irqn.h"
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#include "hal_vector_table.h"
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#include "hal_diag.h"
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#include "hal_spi_flash.h"
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#include "rtl8195a_spi_flash.h"
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#include "hal_timer.h"
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#include "hal_util.h"
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#include "hal_efuse.h"
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#include "hal_soc_ps_monitor.h"
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#include "diag.h"
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#include "hal_common.h"
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#include "hal_soc_ps_monitor.h"
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/* ----------------------------------------------------------------------------
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-- Cortex M3 Core Configuration
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
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* @{
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*/
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#define __CM3_REV 0x0200 /**< Core revision r0p0 */
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#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
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#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
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#define __Vendor_SysTickConfig 1 /**< Vendor specific implementation of SysTickConfig is defined */
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#include "core_cm3.h"
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#ifdef CONFIG_TIMER_EN
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#include "hal_timer.h"
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#endif
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#ifdef CONFIG_GDMA_EN
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#include "hal_gdma.h"
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#include "rtl8195a_gdma.h"
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#endif
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#ifdef CONFIG_GPIO_EN
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#include "hal_gpio.h"
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#include "rtl8195a_gpio.h"
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#endif
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#ifdef CONFIG_SPI_COM_EN
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#include "hal_ssi.h"
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#include "rtl8195a_ssi.h"
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#endif
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#ifdef CONFIG_UART_EN
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#include "hal_uart.h"
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#include "rtl8195a_uart.h"
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#endif
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#ifdef CONFIG_I2C_EN
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#include "hal_i2c.h"
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#include "rtl8195a_i2c.h"
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#endif
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#ifdef CONFIG_PCM_EN
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#include "hal_pcm.h"
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#include "rtl8195a_pcm.h"
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#endif
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#ifdef CONFIG_PWM_EN
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#include "hal_pwm.h"
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#include "rtl8195a_pwm.h"
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#endif
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#ifdef CONFIG_I2S_EN
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#include "hal_i2s.h"
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#include "rtl8195a_i2s.h"
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#endif
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#ifdef CONFIG_DAC_EN
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#include "hal_dac.h"
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#include "rtl8195a_dac.h"
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#endif
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#ifdef CONFIG_ADC_EN
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#include "hal_adc.h"
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#include "rtl8195a_adc.h"
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#endif
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#ifdef CONFIG_SDR_EN
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#endif
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#ifdef CONFIG_SPIC_EN
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#endif
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#ifdef CONFIG_SDIO_DEVICE_EN
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#include "hal_sdio.h"
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#endif
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#ifdef CONFIG_NFC_EN
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#include "hal_nfc.h"
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#include "rtl8195a_nfc.h"
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#endif
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#ifdef CONFIG_WDG
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#include "rtl8195a_wdt.h"
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#endif
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#ifdef CONFIG_USB_EN
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#include "hal_usb.h"
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#include "rtl8195a_usb.h"
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#endif
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#include "hal_log_uart.h"
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#ifdef CONFIG_MII_EN
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#include "hal_mii.h"
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#include "rtl8195a_mii.h"
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#endif
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// firmware information, located at the header of Image2
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#define FW_VERSION (0x0100)
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#define FW_SUBVERSION (0x0001)
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#define FW_CHIP_ID (0x8195)
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#define FW_CHIP_VER (0x01)
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#define FW_BUS_TYPE (0x01) // the iNIC firmware type: USB/SDIO
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#define FW_INFO_RSV1 (0x00) // the firmware information reserved
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#define FW_INFO_RSV2 (0x00) // the firmware information reserved
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#define FW_INFO_RSV3 (0x00) // the firmware information reserved
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#define FW_INFO_RSV4 (0x00) // the firmware information reserved
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#define FLASH_RESERVED_DATA_BASE 0x8000 // reserve 32K for Image1
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#define FLASH_SYSTEM_DATA_ADDR 0x9000 // reserve 32K+4K for Image1 + Reserved data
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// Flash Map for Calibration data
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#define FLASH_CAL_DATA_BASE 0xA000
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#define FLASH_CAL_DATA_ADDR(_offset) (FLASH_CAL_DATA_BASE + _offset)
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#define FLASH_CAL_DATA_SIZE 0x1000
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#define FLASH_SECTOR_SIZE 0x1000
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// SPIC Calibration Data
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#define FLASH_SPIC_PARA_OFFSET 0x80
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#define FLASH_SPIC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SPIC_PARA_OFFSET)
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// SDRC Calibration Data
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#define FLASH_SDRC_PARA_OFFSET 0x180
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#define FLASH_SDRC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SDRC_PARA_OFFSET)
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// ADC Calibration Data
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#define FLASH_ADC_PARA_OFFSET 0x200
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#define FLASH_ADC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_ADC_PARA_OFFSET)
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2017-02-04 21:26:09 +00:00
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#define IMG_SIGN_RUN "81958711"
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#define IMG_SIGN_SWP "01958711"
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#define IMG_SIGN1_RUN 0x35393138 // "8195"
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#define IMG_SIGN1_SWP 0x35393130 // "0195"
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#define IMG_SIGN2_RUN 0x31313738 // "8711"
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#define IMG_SIGN2_SWP IMG_SIGN2_RUN // "8711"
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#define IMG2_SIGN_TXT "RTKWin"
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2017-03-14 03:34:44 +00:00
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#define IMG2_SIGN_DW1_TXT 0x574b5452 // "RTKW"
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#define IMG2_SIGN_SW2_TXT 0x6e69 // "in"
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2017-02-04 21:26:09 +00:00
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2017-02-18 00:27:23 +00:00
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typedef struct _RAM_FUNCTION_START_TABLE_ {
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VOID (*RamStartFun) (VOID); // Run for Init console, Run if ( v40000210 & 0x4000000 )
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VOID (*RamWakeupFun) (VOID); // Run if ( v40000210 & 0x20000000 )
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VOID (*RamPatchFun0) (VOID); // Run if ( v40000210 & 0x10000000 )
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VOID (*RamPatchFun1) (VOID); // Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
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VOID (*RamPatchFun2) (VOID); // Run for Init console, if ( v40000210 & 0x4000000 )
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}RAM_FUNCTION_START_TABLE, *PRAM_FUNCTION_START_TABLE;
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// START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__ =
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// {RamStartFun + 1, RamWakeupFun + 1, RamPatchFun0 + 1, RamPatchFun1 + 1, RamPatchFun2 + 1 };
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#define IMG1_VALID_PATTEN_INIT() { 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff }
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// IMAGE1_VALID_PATTEN_SECTION uint8 RAM_IMG1_VALID_PATTEN[8] = IMG1_VALID_PATTEN_INIT();
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typedef struct _RAM_START_FUNCTION_ {
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VOID (*RamStartFun) (VOID);
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}RAM_START_FUNCTION, *PRAM_START_FUNCTION;
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// IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 = { InfraStart + 1 };
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typedef struct __RAM_IMG2_VALID_PATTEN__ {
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char rtkwin[7];
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u8 x[13];
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} _RAM_IMG2_VALID_PATTEN, *_PRAM_IMG2_VALID_PATTEN;
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// IMAGE2_VALID_PATTEN_SECTION _RAM_IMG2_VALID_PATTEN RAM_IMG2_VALID_PATTEN = RAM_IMG2_VALID_PATTEN_INIT();
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#define RAM_IMG2_VALID_PATTEN_INIT() { \
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{ IMG2_SIGN_TXT }, { 0xff, \
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(FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff), \
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(FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff), \
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(FW_CHIP_ID&0xff), ((FW_CHIP_ID >> 8)&0xff), \
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(FW_CHIP_VER), (FW_BUS_TYPE), \
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(FW_INFO_RSV1), (FW_INFO_RSV2), (FW_INFO_RSV3), (FW_INFO_RSV4)}}
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2016-11-09 00:56:41 +00:00
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#endif //_HAL_8195A_H_
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