2016-11-09 00:56:41 +00:00
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef _HAL_PLATFORM_
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#define _HAL_PLATFORM_
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#define ROMVERSION 0x03
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#define ROMINFORMATION (ROMVERSION)
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#define SYSTEM_CLK PLATFORM_CLOCK
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#define PERIPHERAL_IRQ_STATUS 0x04
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#define PERIPHERAL_IRQ_MODE 0x08
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#define PERIPHERAL_IRQ_EN 0x0C
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#define LP_PERI_EXT_IRQ_STATUS 0x24
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#define LP_PERI_EXT_IRQ_MODE 0x28
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#define LP_PERI_EXT_IRQ_EN 0x2C
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#define PERIPHERAL_IRQ_ALL_LEVEL 0
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#define TIMER_CLK 32*1000
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2017-02-19 19:35:23 +00:00
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#define SDR_SDRAM_BASE 0x30000000
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#define SYSTEM_CTRL_BASE 0x40000000
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#define PERI_ON_BASE 0x40000000
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#define SPI_FLASH_BASE 0x98000000
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2016-11-09 00:56:41 +00:00
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//3 Peripheral IP Base Address
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2017-02-19 19:35:23 +00:00
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2016-11-09 00:56:41 +00:00
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#define GPIO_REG_BASE 0x40001000
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#define TIMER_REG_BASE 0x40002000
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2017-02-19 19:35:23 +00:00
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#define VENDOR_REG_BASE 0x40002800
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2016-11-09 00:56:41 +00:00
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#define NFC_INTERFACE_BASE 0x40002400
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#define LOG_UART_REG_BASE 0x40003000
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#define I2C2_REG_BASE 0x40003400
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#define I2C3_REG_BASE 0x40003800
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2017-02-19 19:35:23 +00:00
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#define SDR_CTRL_BASE 0x40005000
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2016-11-09 00:56:41 +00:00
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#define SPI_FLASH_CTRL_BASE 0x40006000
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#define ADC_REG_BASE 0x40010000
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#define DAC_REG_BASE 0x40011000
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#define UART0_REG_BASE 0x40040000
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#define UART1_REG_BASE 0x40040400
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#define UART2_REG_BASE 0x40040800
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#define SPI0_REG_BASE 0x40042000
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#define SPI1_REG_BASE 0x40042400
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#define SPI2_REG_BASE 0x40042800
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#define I2C0_REG_BASE 0x40044000
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#define I2C1_REG_BASE 0x40044400
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#define SDIO_DEVICE_REG_BASE 0x40050000
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#define MII_REG_BASE 0x40050000
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#define SDIO_HOST_REG_BASE 0x40058000
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#define GDMA0_REG_BASE 0x40060000
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#define GDMA1_REG_BASE 0x40061000
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#define I2S0_REG_BASE 0x40062000
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#define I2S1_REG_BASE 0x40063000
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#define PCM0_REG_BASE 0x40064000
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#define PCM1_REG_BASE 0x40065000
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#define CRYPTO_REG_BASE 0x40070000
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#define WIFI_REG_BASE 0x40080000
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#define USB_OTG_REG_BASE 0x400C0000
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#define GDMA1_REG_OFF 0x1000
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#define I2S1_REG_OFF 0x1000
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#define PCM1_REG_OFF 0x1000
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#define SSI_REG_OFF 0x400
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#define RUART_REG_OFF 0x400
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#define CPU_CLK_TYPE_NO 6
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enum _BOOT_TYPE_ {
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BOOT_FROM_FLASH = 0,
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BOOT_FROM_SDIO = 1,
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BOOT_FROM_USB = 2,
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BOOT_FROM_RSVD = 3,
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};
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enum _EFUSE_CPU_CLK_ {
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#if 1
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CLK_200M = 0,
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CLK_100M = 1,
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CLK_50M = 2,
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CLK_25M = 3,
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CLK_12_5M = 4,
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CLK_4M = 5,
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#else
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CLK_25M = 0,
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CLK_200M = 1,
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CLK_100M = 2,
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CLK_50M = 3,
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CLK_12_5M = 4,
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CLK_4M = 5,
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#endif
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};
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#endif //_HAL_PLATFORM_
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