mirror of
https://github.com/drasko/open-ameba.git
synced 2024-11-23 06:24:17 +00:00
348 lines
11 KiB
C
348 lines
11 KiB
C
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef _HAL_I2S_H_
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#define _HAL_I2S_H_
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#include "rtl8195a_i2s.h"
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/* User Define Flags */
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#define I2S_MAX_ID 1 // valid I2S index 0 ~ I2S_MAX_ID
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/**********************************************************************/
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/* I2S HAL initial data structure */
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typedef struct _HAL_I2S_INIT_DAT_ {
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u8 I2SIdx; /*I2S index used*/
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u8 I2SEn; /*I2S module enable tx/rx/tx+rx*/
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u8 I2SMaster; /*I2S Master or Slave mode*/
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u8 I2SWordLen; /*I2S Word length 16 or 24bits*/
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u8 I2SChNum; /*I2S Channel number mono or stereo*/
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u8 I2SPageNum; /*I2S Page Number 2~4*/
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u16 I2SPageSize; /*I2S page Size 1~4096 word*/
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u8 *I2STxData; /*I2S Tx data pointer*/
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u8 *I2SRxData; /*I2S Rx data pointer*/
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u32 I2STxIntrMSK; /*I2S Tx Interrupt Mask*/
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u32 I2STxIntrClr; /*I2S Tx Interrupt register to clear */
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u32 I2SRxIntrMSK; /*I2S Rx Interrupt Mask*/
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u32 I2SRxIntrClr; /*I2S Rx Interrupt register to clear*/
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u16 I2STxIdx; /*I2S TX page index */
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u16 I2SRxIdx; /*I2S RX page index */
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u16 I2SHWTxIdx; /*I2S HW TX page index */
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u16 I2SHWRxIdx; /*I2S HW RX page index */
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u16 I2SRate; /*I2S sample rate*/
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u8 I2STRxAct; /*I2S tx rx act*/
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}HAL_I2S_INIT_DAT, *PHAL_I2S_INIT_DAT;
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/**********************************************************************/
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/* I2S Data Structures */
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/* I2S Module Selection */
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typedef enum _I2S_MODULE_SEL_ {
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I2S0_SEL = 0x0,
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I2S1_SEL = 0x1,
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}I2S_MODULE_SEL,*PI2S_MODULE_SEL;
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/*
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typedef struct _HAL_I2S_ADAPTER_ {
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u32 Enable:1;
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I2S_CTL_REG I2sCtl;
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I2S_SETTING_REG I2sSetting;
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u32 abc;
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u8 I2sIndex;
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}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER;
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*/
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/* I2S HAL Operations */
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typedef struct _HAL_I2S_OP_ {
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RTK_STATUS (*HalI2SInit) (VOID *Data);
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RTK_STATUS (*HalI2SDeInit) (VOID *Data);
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RTK_STATUS (*HalI2STx) (VOID *Data, u8 *pBuff);
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RTK_STATUS (*HalI2SRx) (VOID *Data, u8 *pBuff);
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RTK_STATUS (*HalI2SEnable) (VOID *Data);
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RTK_STATUS (*HalI2SIntrCtrl) (VOID *Data);
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u32 (*HalI2SReadReg) (VOID *Data, u8 I2SReg);
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RTK_STATUS (*HalI2SSetRate) (VOID *Data);
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RTK_STATUS (*HalI2SSetWordLen) (VOID *Data);
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RTK_STATUS (*HalI2SSetChNum) (VOID *Data);
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RTK_STATUS (*HalI2SSetPageNum) (VOID *Data);
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RTK_STATUS (*HalI2SSetPageSize) (VOID *Data);
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RTK_STATUS (*HalI2SClrIntr) (VOID *Data);
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RTK_STATUS (*HalI2SClrAllIntr) (VOID *Data);
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RTK_STATUS (*HalI2SDMACtrl) (VOID *Data);
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/*
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VOID (*HalI2sOnOff)(VOID *Data);
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BOOL (*HalI2sInit)(VOID *Data);
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BOOL (*HalI2sSetting)(VOID *Data);
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BOOL (*HalI2sEn)(VOID *Data);
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BOOL (*HalI2sIsrEnAndDis) (VOID *Data);
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BOOL (*HalI2sDumpReg)(VOID *Data);
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BOOL (*HalI2s)(VOID *Data);
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*/
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}HAL_I2S_OP, *PHAL_I2S_OP;
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/**********************************************************************/
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/* I2S Pinmux Selection */
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#if 0
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typedef enum _I2S0_PINMUX_ {
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I2S0_TO_S0 = 0x0,
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I2S0_TO_S1 = 0x1,
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I2S0_TO_S2 = 0x2,
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}I2S0_PINMUX, *PI2S0_PINMUX;
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typedef enum _I2S1_PINMUX_ {
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I2S1_TO_S0 = 0x0,
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I2S1_TO_S1 = 0x1,
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}I2S1_PINMUX, *PI2S1_PINMUX;
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#endif
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typedef enum _I2S_PINMUX_ {
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I2S_S0 = 0,
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I2S_S1 = 1,
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I2S_S2 = 2,
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I2S_S3 = 3
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}I2S_PINMUX, *PI2S_PINMUX;
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/* I2S Module Status */
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typedef enum _I2S_MODULE_STATUS_ {
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I2S_DISABLE = 0x0,
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I2S_ENABLE = 0x1,
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}I2S_MODULE_STATUS, *PI2S_MODULE_STATUS;
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/* I2S Device Status */
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typedef enum _I2S_Device_STATUS_ {
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I2S_STS_UNINITIAL = 0x00,
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I2S_STS_INITIALIZED = 0x01,
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I2S_STS_IDLE = 0x02,
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I2S_STS_TX_READY = 0x03,
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I2S_STS_TX_ING = 0x04,
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I2S_STS_RX_READY = 0x05,
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I2S_STS_RX_ING = 0x06,
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I2S_STS_TRX_READY = 0x07,
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I2S_STS_TRX_ING = 0x08,
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I2S_STS_ERROR = 0x09,
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}I2S_Device_STATUS, *PI2S_Device_STATUS;
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/* I2S Feature Status */
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typedef enum _I2S_FEATURE_STATUS_{
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I2S_FEATURE_DISABLED = 0,
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I2S_FEATURE_ENABLED = 1,
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}I2S_FEATURE_STATUS,*PI2S_FEATURE_STATUS;
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/* I2S Device Mode */
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typedef enum _I2S_DEV_MODE_ {
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I2S_MASTER_MODE = 0x0,
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I2S_SLAVE_MODE = 0x1
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}I2S_DEV_MODE, *PI2S_DEV_MODE;
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/* I2S Word Length */
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typedef enum _I2S_WORD_LEN_ {
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I2S_WL_16 = 0x0,
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I2S_WL_24 = 0x1,
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}I2S_WORD_LEN, *PI2S_WORD_LEN;
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/* I2S Bus Transmit/Receive */
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typedef enum _I2S_DIRECTION_ {
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I2S_ONLY_RX = 0x0,
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I2S_ONLY_TX = 0x1,
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I2S_TXRX = 0x2
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}I2S_DIRECTION, *PI2S_DIRECTION;
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/* I2S Channel number */
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typedef enum _I2S_CH_NUM_ {
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I2S_CH_STEREO = 0x0,
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I2S_CH_RSVD = 0x1,
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I2S_CH_MONO = 0x2
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}I2S_CH_NUM, *PI2S_CH_NUM;
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/* I2S Page number */
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typedef enum _I2S_PAGE_NUM_ {
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I2S_1PAGE = 0x0,
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I2S_2PAGE = 0x1,
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I2S_3PAGE = 0x2,
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I2S_4PAGE = 0x3
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}I2S_PAGE_NUM, *PI2S_PAGE_NUM;
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/* I2S Sample rate*/
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typedef enum _I2S_SAMPLE_RATE_ {
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I2S_SR_8KHZ = 0x00, // /12
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I2S_SR_16KHZ = 0x01, // /6
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I2S_SR_24KHZ = 0x02, // /4
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I2S_SR_32KHZ = 0x03, // /3
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I2S_SR_48KHZ = 0x05, // /2
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I2S_SR_96KHZ = 0x06, // x1, base 96kHz
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I2S_SR_7p35KHZ = 0x10,
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I2S_SR_11p02KHZ = 0x11,
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I2S_SR_22p05KHZ = 0x12,
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I2S_SR_29p4KHZ = 0x13,
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I2S_SR_44p1KHZ = 0x15,
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I2S_SR_88p2KHZ = 0x16 // x1, base 88200Hz
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}I2S_SAMPLE_RATE, *PI2S_SAMPLE_RATE;
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/* I2S TX interrupt mask/status */
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typedef enum _I2S_TX_IMR_ {
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I2S_TX_INT_PAGE0_OK = (1<<0),
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I2S_TX_INT_PAGE1_OK = (1<<1),
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I2S_TX_INT_PAGE2_OK = (1<<2),
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I2S_TX_INT_PAGE3_OK = (1<<3),
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I2S_TX_INT_FULL = (1<<4),
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I2S_TX_INT_EMPTY = (1<<5)
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} I2S_TX_IMR, *PI2S_TX_IMR;
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/* I2S RX interrupt mask/status */
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typedef enum _I2S_RX_IMR_ {
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I2S_RX_INT_PAGE0_OK = (1<<0),
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I2S_RX_INT_PAGE1_OK = (1<<1),
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I2S_RX_INT_PAGE2_OK = (1<<2),
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I2S_RX_INT_PAGE3_OK = (1<<3),
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I2S_RX_INT_EMPTY = (1<<4),
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I2S_RX_INT_FULL = (1<<5)
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} I2S_RX_IMR, *PI2S_RX_IMR;
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/* I2S User Callbacks */
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typedef struct _SAL_I2S_USER_CB_{
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VOID (*TXCB) (VOID *Data);
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VOID (*TXCCB) (VOID *Data);
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VOID (*RXCB) (VOID *Data);
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VOID (*RXCCB) (VOID *Data);
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VOID (*RDREQCB) (VOID *Data);
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VOID (*ERRCB) (VOID *Data);
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VOID (*GENCALLCB) (VOID *Data);
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}SAL_I2S_USER_CB,*PSAL_I2S_USER_CB;
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typedef struct _I2S_USER_CB_{
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VOID (*TxCCB)(uint32_t id, char *pbuf);
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u32 TxCBId;
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VOID (*RxCCB)(uint32_t id, char *pbuf);
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u32 RxCBId;
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}I2S_USER_CB,*PI2S_USER_CB;
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/* Software API Level I2S Handler */
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typedef struct _HAL_I2S_ADAPTER_{
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u8 DevNum; //I2S device number
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u8 PinMux; //I2S pin mux seletion
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u8 RSVD0; //Reserved
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volatile u8 DevSts; //I2S device status
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u32 RSVD2; //Reserved
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u32 I2SExd; //I2S extended options:
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//bit 0: I2C RESTART supported,
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// 0 for NOT supported,
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// 1 for supported
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//bit 1: I2C General Call supported
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// 0 for NOT supported,
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// 1 for supported
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//bit 2: I2C START Byte supported
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// 0 for NOT supported,
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// 1 for supported
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//bit 3: I2C Slave-No-Ack
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// supported
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// 0 for NOT supported,
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// 1 for supported
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//bit 4: I2C bus loading,
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// 0 for 100pf,
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// 1 for 400pf
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//bit 5: I2C slave ack to General
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// Call
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//bit 6: I2C User register address
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//bit 7: I2C 2-Byte User register
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// address
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//bit 31~bit 8: Reserved
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u32 ErrType; //
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u32 TimeOut; //I2S IO Timeout count
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PHAL_I2S_INIT_DAT pInitDat; //Pointer to I2S initial data struct
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I2S_USER_CB UserCB; //Pointer to I2S User Callback
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IRQ_HANDLE IrqHandle; // Irq Handler
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u32* TxPageList[4]; // The Tx DAM buffer: pointer of each page
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u32* RxPageList[4]; // The Tx DAM buffer: pointer of each page
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}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER;
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typedef struct _HAL_I2S_DEF_SETTING_{
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u8 I2SMaster; // Master or Slave mode
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u8 DevSts; //I2S device status
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u8 I2SChNum; //I2S Channel number mono or stereo
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u8 I2SPageNum; //I2S Page number 2~4
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u8 I2STRxAct; //I2S tx rx act, tx only or rx only or tx+rx
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u8 I2SWordLen; //I2S Word length 16bit or 24bit
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u16 I2SPageSize; //I2S Page size 1~4096 word
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u16 I2SRate; //I2S sample rate 8k ~ 96khz
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u32 I2STxIntrMSK; /*I2S Tx Interrupt Mask*/
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u32 I2SRxIntrMSK; /*I2S Rx Interrupt Mask*/
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}HAL_I2S_DEF_SETTING, *PHAL_I2S_DEF_SETTING;
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/**********************************************************************/
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HAL_Status
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RtkI2SLoadDefault(IN VOID *Adapter, IN VOID *Setting);
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HAL_Status
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RtkI2SInit(IN VOID *Data);
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HAL_Status
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RtkI2SDeInit(IN VOID *Data);
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HAL_Status
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RtkI2SEnable(IN VOID *Data);
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HAL_Status
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RtkI2SDisable(IN VOID *Data);
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extern HAL_Status
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HalI2SInit( IN VOID *Data);
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extern VOID
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HalI2SDeInit( IN VOID *Data);
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extern HAL_Status
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HalI2SDisable( IN VOID *Data);
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extern HAL_Status
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HalI2SEnable( IN VOID *Data);
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/**********************************************************************/
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VOID I2S0ISRHandle(VOID *Data);
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VOID I2S1ISRHandle(VOID *Data);
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/**********************************************************************/
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||
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VOID HalI2SOpInit(
|
||
|
|
IN VOID *Data
|
||
|
|
);
|
||
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|
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||
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||
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#endif
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||
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|