mirror of
https://github.com/drasko/open-ameba.git
synced 2024-11-28 09:10:29 +00:00
362 lines
11 KiB
C
362 lines
11 KiB
C
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#include "FreeRTOS.h"
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#include "task.h"
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#include "diag.h"
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#include "hal_efuse.h"
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#include "efuse_api.h"
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#include "osdep_service.h"
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#include "device_lock.h"
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_LONG_CALL_ROM_ extern u32 HALEFUSEOneByteReadROM(IN u32 CtrlSetting, IN u16 Addr, OUT u8 *Data, IN u8 L25OutVoltage);
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_LONG_CALL_ROM_ extern u32 HALEFUSEOneByteWriteROM(IN u32 CtrlSetting, IN u16 Addr, IN u8 Data, IN u8 L25OutVoltage);
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//====================================================== Start libs
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//-----
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int _HalEFUSEPowerSwitch8195AROM(uint8_t bWrite, uint8_t PwrState, uint8_t L25OutVoltage) {
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if (PwrState == 1) {
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HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_EEPROM_CTRL0, (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EEPROM_CTRL0) & 0xFFFFFF) | 0x69000000); // EFUSE_UNLOCK
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if (!(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN) & BIT_SYS_FEN_EELDR)) // REG_SYS_FUNC_EN BIT_SYS_FEN_EELDR ?
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HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN) | BIT_SYS_FEN_EELDR);
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if (!(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL0) & BIT_SYSON_CK_EELDR_EN)) // REG_SYS_CLK_CTRL0 BIT_SYSON_CK_EELDR_EN ?
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HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL0, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL0) | BIT_SYSON_CK_EELDR_EN);
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if (!(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & BIT_PESOC_EELDR_CK_SEL)) // REG_SYS_CLK_CTRL1 BIT_PESOC_EELDR_CK_SEL ?
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HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) | BIT_PESOC_EELDR_CK_SEL);
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if (bWrite == 1)
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HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_REGU_CTRL0, (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_REGU_CTRL0) & 0xFFFFF0FF) | BIT_SYS_REGU_LDO25E_EN | BIT_SYS_REGU_LDO25E_ADJ(L25OutVoltage));
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}
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else
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{
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HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_EEPROM_CTRL0, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EEPROM_CTRL0) & 0xFFFFFF); // EFUSE_UNLOCK
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if ( bWrite == 1 )
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HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_REGU_CTRL0, (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_REGU_CTRL0) & (~BIT_SYS_REGU_LDO25E_EN)));
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}
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return bWrite;
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}
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//-----
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int _HALEFUSEOneByteReadROM(uint32_t CtrlSetting, uint16_t Addr, uint8_t *Data, uint8_t L25OutVoltage)
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{
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int i = 0, ret = 0;
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if ( (Addr <= 0xFF) || ((CtrlSetting & 0xFFFF) == 0x26AE) ) {
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_HalEFUSEPowerSwitch8195AROM(1, 1, L25OutVoltage);
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HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_TEST, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_TEST) & (~BIT_SYS_EF_FORCE_PGMEN));
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HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_CTRL,
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(CtrlSetting & (~(BIT_SYS_EF_RWFLAG | (BIT_MASK_SYS_EF_ADDR << BIT_SHIFT_SYS_EF_ADDR) | (BIT_MASK_SYS_EF_DATA << BIT_SHIFT_SYS_EF_DATA))))
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| BIT_SYS_EF_ADDR(Addr));
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if(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_CTRL) & BIT_SYS_EF_RWFLAG) {
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*Data = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_CTRL);
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ret = 1;
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}
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else while(1) {
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HalDelayUs(1000);
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if(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_CTRL) & BIT_SYS_EF_RWFLAG) {
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*Data = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_CTRL);
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ret = 1;
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break;
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}
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if (i++ >= 100) {
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*Data = -1;
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ret = 1;
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break;
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};
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};
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_HalEFUSEPowerSwitch8195AROM(1, 0, L25OutVoltage);
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}
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else *Data = -1;
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return ret;
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}
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//-----
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int _HALOTPOneByteReadRAM(uint32_t CtrlSetting, int Addr, uint8_t *Data, uint8_t L25OutVoltage)
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{
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int result;
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if ( (unsigned int)(Addr - 128) > 0x1F )
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result = 1;
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else
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result = _HALEFUSEOneByteReadROM(CtrlSetting, Addr, Data, L25OutVoltage);
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return result;
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}
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//-----
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int _HALEFUSEOneByteReadRAM(uint32_t CtrlSetting, int Addr, uint8_t *Data, uint8_t L25OutVoltage)
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{
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int result;
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if ( (unsigned int)(Addr - 160) > 0x33 )
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{
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result = _HALEFUSEOneByteReadROM(CtrlSetting, Addr, Data, L25OutVoltage);
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}
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else
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{
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*Data = -1;
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result = 1;
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}
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return result;
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}
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//-----
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void _ReadEOTPContant(uint8_t *pContant)
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{
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int i;
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for(i = 0; i < 32; i++ )
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_HALOTPOneByteRead(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_CTRL), i+128, &pContant[i], L25EOUTVOLTAGE);
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}
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//-----
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void _ReadEfuseContant(int UserCode, uint8_t *pContant)
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{
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#define EFUSE_SECTION 11
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uint8_t *pbuf;
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int eFuse_Addr;
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int offset;
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int bcnt;
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int i, j;
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uint8_t DataTemp0;
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uint8_t DataTemp1;
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pbuf = pContant;
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eFuse_Addr = 0;
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do {
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_HALEFUSEOneByteReadRAM(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_CTRL), eFuse_Addr, &DataTemp0, L25EOUTVOLTAGE);
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if ( DataTemp0 == 0x0FF ) break;
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if ( (DataTemp0 & 0x0F) == 0x0F ) {
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_HALEFUSEOneByteReadRAM(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_CTRL), ++eFuse_Addr, &DataTemp1, L25EOUTVOLTAGE);
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offset = ((DataTemp1 & 0x0F0) | (DataTemp0 >> 4)) >> 1;
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bcnt = (~DataTemp1) & 0x0F;
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if (((UserCode + EFUSE_SECTION) << 2) > offset || offset >= ((UserCode + EFUSE_SECTION + 1) << 2)) {
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while (bcnt)
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{
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if (bcnt & 1) eFuse_Addr += 2;
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bcnt >>= 1;
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}
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}
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else
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{
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int base = (offset - ((EFUSE_SECTION + UserCode) << 2)) << 3;
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j = 0;
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while ( bcnt )
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{
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if ( bcnt & 1 )
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{
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_HALEFUSEOneByteReadRAM(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_CTRL), ++eFuse_Addr, &pbuf[base + j], L25EOUTVOLTAGE);
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_HALEFUSEOneByteReadRAM(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_CTRL), ++eFuse_Addr, &pbuf[base + j + 1], L25EOUTVOLTAGE);
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}
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bcnt >>= 1;
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j += 2;
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}
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}
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}
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else
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{
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for (i = (~DataTemp0) & 0x0F; i; i >>= 1 )
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{
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if (i & 1) eFuse_Addr += 2;
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}
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}
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eFuse_Addr++;
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}
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while (eFuse_Addr <= 0x7E);
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}
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//-----
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void _ReadEfuseContant1(uint8_t *pContant)
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{
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_ReadEfuseContant(0, pContant);
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}
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//-----
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void _ReadEfuseContant2(uint8_t *pContant)
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{
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_ReadEfuseContant(1, pContant);
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}
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//-----
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void _ReadEfuseContant3(uint8_t *pContant)
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{
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_ReadEfuseContant(2, pContant);
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}
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int _efuse_otp_read(u8 address, u8 len, u8 *buf)
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{
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u8 content[32]; // the OTP max length is 32
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if((address + len) > 32) return -1;
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_ReadEOTPContant(content);
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_memcpy(buf, content + address, len);
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return 0;
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}
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//====================================================== end libs
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//======================================================
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// OTP : one time programming
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//======================================================
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uint8_t buf[128];
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#define OTP_MAX_LEN 32 // The OTP max length is 32 bytes
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static void efuse_otp_task(void *param)
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{
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int ret;
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u8 i;
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DBG_8195A("\nefuse OTP block: Test Start\n");
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// read OTP content
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device_mutex_lock(RT_DEV_LOCK_EFUSE);
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ret = efuse_otp_read(0, OTP_MAX_LEN, buf);
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device_mutex_unlock(RT_DEV_LOCK_EFUSE);
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if(ret < 0){
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DBG_8195A("efuse OTP block: read address and length error\n");
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goto exit;
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}
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for(i=0; i<OTP_MAX_LEN; i+=8){
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DBG_8195A("[%d]\t%02X %02X %02X %02X %02X %02X %02X %02X\n",
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i, buf[i], buf[i+1], buf[i+2], buf[i+3], buf[i+4], buf[i+5], buf[i+6], buf[i+7]);
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}
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int x = 0;
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while(x < 1024) {
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DBG_8195A("efuse OTP block at %d:\n", x);
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device_mutex_lock(RT_DEV_LOCK_EFUSE);
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for(i = 0; i < sizeof(buf); i++ )
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// _HALEFUSEOneByteReadROM(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_CTRL), i+x, &buf[i], L25EOUTVOLTAGE);
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_HALEFUSEOneByteReadROM(0x26AF, i+x, &buf[i], L25EOUTVOLTAGE);
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device_mutex_unlock(RT_DEV_LOCK_EFUSE);
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for(i = 0; i < sizeof(buf); i+=8){
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DBG_8195A("[%04x]\t%02X %02X %02X %02X %02X %02X %02X %02X\n",
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i+x, buf[i], buf[i+1], buf[i+2], buf[i+3], buf[i+4], buf[i+5], buf[i+6], buf[i+7]);
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}
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x+=sizeof(buf);
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}
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/*
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// write OTP content
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_memset(buf, 0xFF, OTP_MAX_LEN);
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if(0){ // fill your data
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for(i=0; i<OTP_MAX_LEN; i++)
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buf[i] = i;
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}
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if(0){ // write
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device_mutex_lock(RT_DEV_LOCK_EFUSE);
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ret = efuse_otp_write(0, OTP_MAX_LEN, buf);
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device_mutex_unlock(RT_DEV_LOCK_EFUSE);
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if(ret < 0){
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DBG_8195A("efuse OTP block: write address and length error\n");
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goto exit;
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}
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DBG_8195A("\nWrite Done.\n");
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}
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DBG_8195A("\n");
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// read OTP content
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device_mutex_lock(RT_DEV_LOCK_EFUSE);
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ret = efuse_otp_read(0, OTP_MAX_LEN, buf);
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device_mutex_unlock(RT_DEV_LOCK_EFUSE);
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if(ret < 0){
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DBG_8195A("efuse OTP block: read address and length error\n");
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goto exit;
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}
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for(i=0; i<OTP_MAX_LEN; i+=8){
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DBG_8195A("[%d]\t%02X %02X %02X %02X %02X %02X %02X %02X\n",
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i, buf[i], buf[i+1], buf[i+2], buf[i+3], buf[i+4], buf[i+5], buf[i+6], buf[i+7]);
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}
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*/
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DBG_8195A("efuse OTP block: Test Done\n");
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vTaskDelete(NULL);
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exit:
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DBG_8195A("efuse OTP block: Test Fail!\n");
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vTaskDelete(NULL);
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}
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//======================================================
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// MTP : M? time programming
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//======================================================
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#define MTP_MAX_LEN 32 // The MTP max length is 32 bytes
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static void efuse_mtp_task(void *param)
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{
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int ret;
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u8 i;
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DBG_8195A("\nefuse MTP block: Test Start\n");
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// read MTP content
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_memset(buf, 0xFF, MTP_MAX_LEN);
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device_mutex_lock(RT_DEV_LOCK_EFUSE);
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efuse_mtp_read(buf);
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device_mutex_unlock(RT_DEV_LOCK_EFUSE);
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for(i=0; i<MTP_MAX_LEN; i+=8){
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DBG_8195A("[%d]\t%02X %02X %02X %02X %02X %02X %02X %02X\n",
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i, buf[i], buf[i+1], buf[i+2], buf[i+3], buf[i+4], buf[i+5], buf[i+6], buf[i+7]);
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}
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DBG_8195A("\nefuse MTP block: Test Start\n");
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// read MTP content
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_memset(buf, 0xFF, MTP_MAX_LEN);
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device_mutex_lock(RT_DEV_LOCK_EFUSE);
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_ReadEfuseContant1(buf);
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device_mutex_unlock(RT_DEV_LOCK_EFUSE);
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for(i=0; i<MTP_MAX_LEN; i+=8){
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DBG_8195A("[%d]\t%02X %02X %02X %02X %02X %02X %02X %02X\n",
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i, buf[i], buf[i+1], buf[i+2], buf[i+3], buf[i+4], buf[i+5], buf[i+6], buf[i+7]);
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}
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/*
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// write MTP content
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_memset(buf, 0xFF, MTP_MAX_LEN);
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if(0){ // fill your data
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for(i=0; i<MTP_MAX_LEN; i++)
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buf[i] = i;
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}
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if(0){ // write
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device_mutex_lock(RT_DEV_LOCK_EFUSE);
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ret = efuse_mtp_write(buf, MTP_MAX_LEN);
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device_mutex_unlock(RT_DEV_LOCK_EFUSE);
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if(ret < 0){
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DBG_8195A("efuse MTP block: write length error\n");
|
||
|
|
goto exit;
|
||
|
|
}
|
||
|
|
DBG_8195A("\nWrite Done\n");
|
||
|
|
DBG_8195A("Remain %d\n", efuse_get_remaining_length());
|
||
|
|
}
|
||
|
|
DBG_8195A("\n");
|
||
|
|
|
||
|
|
// read MTP content
|
||
|
|
_memset(buf, 0xFF, MTP_MAX_LEN);
|
||
|
|
device_mutex_lock(RT_DEV_LOCK_EFUSE);
|
||
|
|
efuse_mtp_read(buf);
|
||
|
|
device_mutex_unlock(RT_DEV_LOCK_EFUSE);
|
||
|
|
for(i=0; i<MTP_MAX_LEN; i+=8){
|
||
|
|
DBG_8195A("[%d]\t%02X %02X %02X %02X %02X %02X %02X %02X\n",
|
||
|
|
i, buf[i], buf[i+1], buf[i+2], buf[i+3], buf[i+4], buf[i+5], buf[i+6], buf[i+7]);
|
||
|
|
}
|
||
|
|
|
||
|
|
*/
|
||
|
|
DBG_8195A("efuse MTP block: Test Done\n");
|
||
|
|
vTaskDelete(NULL);
|
||
|
|
exit:
|
||
|
|
DBG_8195A("efuse MTP block: Test Fail!\n");
|
||
|
|
vTaskDelete(NULL);
|
||
|
|
}
|
||
|
|
|
||
|
|
void main(void)
|
||
|
|
{
|
||
|
|
ConfigDebugErr = -1; // ~_DBG_GDMA_;
|
||
|
|
ConfigDebugInfo = -1; // ~_DBG_GDMA_;
|
||
|
|
ConfigDebugWarn = -1; // ~_DBG_GDMA_;
|
||
|
|
|
||
|
|
DBG_8195A("EFUSE_CTRL=%08x\n", HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_CTRL));
|
||
|
|
|
||
|
|
if(xTaskCreate(efuse_mtp_task, ((const char*)"efuse_mtp_task"), 512, NULL, tskIDLE_PRIORITY + 1, NULL) != pdPASS)
|
||
|
|
printf("\n\r%s xTaskCreate(efuse_mtp_task) failed", __FUNCTION__);
|
||
|
|
|
||
|
|
if(xTaskCreate(efuse_otp_task, ((const char*)"efuse_otp_task"), 512, NULL, tskIDLE_PRIORITY + 2, NULL) != pdPASS)
|
||
|
|
printf("\n\r%s xTaskCreate(efuse_otp_task) failed", __FUNCTION__);
|
||
|
|
|
||
|
|
/*Enable Schedule, Start Kernel*/
|
||
|
|
if(rtw_get_scheduler_state() == OS_SCHEDULER_NOT_STARTED)
|
||
|
|
vTaskStartScheduler();
|
||
|
|
else
|
||
|
|
vTaskDelete(NULL);
|
||
|
|
}
|