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https://github.com/drasko/open-ameba.git
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95 lines
3.1 KiB
C
95 lines
3.1 KiB
C
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_SPI_EXT_API_H
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#define MBED_SPI_EXT_API_H
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#include "device.h"
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#if DEVICE_SPI
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SPI_DMA_RX_EN (1<<0)
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#define SPI_DMA_TX_EN (1<<1)
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enum {
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SPI_SCLK_IDLE_LOW=0, // the SCLK is Low when SPI is inactive
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SPI_SCLK_IDLE_HIGH=2 // the SCLK is High when SPI is inactive
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};
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// SPI Master mode: for continuous transfer, how the CS toggle:
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enum {
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SPI_CS_TOGGLE_EVERY_FRAME=0, // let SCPH=0 then the CS toggle every frame
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SPI_CS_TOGGLE_START_STOP=1 // let SCPH=1 the CS toggle at start and stop
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};
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enum {
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SPI_SCLK_TOGGLE_MIDDLE=0, // Serial Clk toggle at middle of 1st data bit and latch data at 1st Clk edge
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SPI_SCLK_TOGGLE_START=1 // Serial Clk toggle at start of 1st data bit and latch data at 2nd Clk edge
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};
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typedef enum {
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CS_0 = 0,
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CS_1 = 1,
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CS_2 = 2,
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CS_3 = 3,
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CS_4 = 4,
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CS_5 = 5,
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CS_6 = 6,
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CS_7 = 7
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}ChipSelect;
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#define SPI_STATE_READY 0x00
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#define SPI_STATE_RX_BUSY (1<<1)
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#define SPI_STATE_TX_BUSY (1<<2)
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typedef enum {
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SpiRxIrq,
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SpiTxIrq
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} SpiIrq;
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typedef void (*spi_irq_handler)(uint32_t id, SpiIrq event);
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void spi_irq_hook(spi_t *obj, spi_irq_handler handler, uint32_t id);
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void spi_bus_tx_done_irq_hook(spi_t *obj, spi_irq_handler handler, uint32_t id);
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int32_t spi_slave_read_stream(spi_t *obj, char *rx_buffer, uint32_t length);
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int32_t spi_slave_write_stream(spi_t *obj, char *tx_buffer, uint32_t length);
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int32_t spi_master_read_stream(spi_t *obj, char *rx_buffer, uint32_t length);
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int32_t spi_master_write_stream(spi_t *obj, char *tx_buffer, uint32_t length);
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int32_t spi_master_write_read_stream(spi_t *obj, char *tx_buffer,
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char *rx_buffer, uint32_t length);
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int32_t spi_slave_read_stream_timeout(spi_t *obj, char *rx_buffer, uint32_t length, uint32_t timeout_ms);
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#ifdef CONFIG_GDMA_EN
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int32_t spi_slave_read_stream_dma(spi_t *obj, char *rx_buffer, uint32_t length);
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int32_t spi_slave_write_stream_dma(spi_t *obj, char *tx_buffer, uint32_t length);
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int32_t spi_master_write_read_stream_dma(spi_t * obj, char * tx_buffer, char * rx_buffer, uint32_t length);
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int32_t spi_master_read_stream_dma(spi_t *obj, char *rx_buffer, uint32_t length);
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int32_t spi_master_write_stream_dma(spi_t *obj, char *tx_buffer, uint32_t length);
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int32_t spi_slave_read_stream_dma_timeout(spi_t *obj, char *rx_buffer, uint32_t length, uint32_t timeout_ms);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif
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