Compare commits
2 commits
| Author | SHA1 | Date | |
|---|---|---|---|
| 8209a9a936 | |||
| b10103377d |
16 changed files with 6828 additions and 44728 deletions
|
|
@ -9,13 +9,15 @@ steps:
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- name: submodules
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image: alpine/git
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commands:
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- git submodule update --init --recursive
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- git submodule update --init --recursive --depth 1
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- name: firmware
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image: docker-repo.service.intern.lab.or.it:5000/fiatlux-build-env
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depends_on: [ submodules ]
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commands:
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- export PATH=$(pwd)/modules/sdk/xtensa-lx106-elf/bin:$PATH
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- apt update
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- apt install -y minify
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- make firmware -j$(nproc)
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- name: pcb
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@ -23,7 +25,7 @@ steps:
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commands:
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- apt update
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- apt install -y make zip
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- make pcb -j$(nproc) BOARD=fiatlux
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- make pcb -j$(nproc)
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- name: case
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image: debian:sid
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@ -58,7 +60,7 @@ steps:
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files:
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- firmware/firmware/fiatlux.bin
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- firmware/otaflash.py
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- pcb/fiatlux_pcb.zip
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- pcb/pcb.zip
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checksum:
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- sha512
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- md5
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6
Makefile
6
Makefile
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@ -1,4 +1,3 @@
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.PHONY: firmware flash firmware_docker case pcb
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all: firmware case pcb
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@ -19,6 +18,11 @@ clean:
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+@make -C firmware clean
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+@make -C pcb clean
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flash_docker:
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sh -c "docker build -t fiatlux_firmware_env docker/firmware"
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sh -c "docker run --volume "$$(pwd)"/firmware:/app/firmware --device=/dev/ttyUSB0 fiatlux_firmware_env make -C firmware flash"
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firmware_docker:
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sh -c "docker build -t fiatlux_firmware_env docker/firmware"
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sh -c "docker run --volume "$$(pwd)"/firmware:/app/firmware fiatlux_firmware_env make -C firmware html all"
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@ -2,11 +2,11 @@ PROGRAM=fiatlux
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EXTRA_CFLAGS=-O3 -Ibuild/gen -DLWIP_NETIF_HOSTNAME=1
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EXTRA_COMPONENTS=extras/i2s_dma extras/ws2812_i2s extras/dhcpserver extras/rboot-ota extras/mbedtls extras/httpd extras/sntp extras/cpp_support
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EXTRA_COMPONENTS=extras/i2s_dma extras/ws2812_i2s extras/dhcpserver extras/rboot-ota extras/mbedtls extras/httpd extras/sntp extras/cpp_support extras/paho_mqtt_c
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LIBS = hal m
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FLASH_MODE = dio
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FLASH_MODE = qio
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include ../modules/rtos/common.mk
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@ -15,7 +15,7 @@ html: build/gen/fsdata.c
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build/gen/fsdata.c: webdir/index.html webdir/404.html webdir/css/picnic.min.css webdir/css/style.css webdir/js/smoothie_min.js
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@echo "Generating fsdata.."
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@mkdir -p $(dir $@)
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@./mkwebfs.py --gzip -o $@ $^
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@./mkwebfs.py --gzip --minify -o $@ $^
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test: unittest systest
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@ -2,6 +2,7 @@
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import os
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import gzip
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import argparse
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import subprocess
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parser = argparse.ArgumentParser()
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parser.add_argument('-o', '--output', help='Output file name', default='stdout')
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@ -9,6 +10,9 @@ parser.add_argument('-W', '--webroot', help='Output file name', default='webdir/
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parser.add_argument('--gzip', dest='gzip', action='store_true')
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parser.add_argument('--no-gzip', dest='gzip', action='store_false')
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parser.set_defaults(gzip=False)
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parser.add_argument('--minify', dest='minify', action='store_true')
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parser.add_argument('--no-minify', dest='minify', action='store_false')
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parser.set_defaults(minify=False)
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parser.add_argument('--header', dest='header', action='store_true')
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parser.add_argument('--no-header', dest='header', action='store_false')
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parser.set_defaults(header=True)
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@ -16,6 +20,31 @@ parser.add_argument('input', nargs='+', default=os.getcwd())
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args = parser.parse_args()
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def mimeFromName(name):
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if name.endswith(".html") or name.endswith(".htm") or name.endswith(".shtml") or name.endswith(
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".shtm") or name.endswith(".ssi"):
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return "text/html"
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if name.endswith(".js"):
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return "application/x-javascript"
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if name.endswith(".css"):
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return "text/css"
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if name.endswith(".ico"):
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return "image/x-icon"
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if name.endswith(".gif"):
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return "image/gif"
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if name.endswith(".png"):
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return "image/png"
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if name.endswith(".jpg"):
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return "image/jpeg"
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if name.endswith(".bmp"):
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return "image/bmp"
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if name.endswith(".class"):
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return "application/octet-stream"
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if name.endswith(".ram"):
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return "audio/x-pn-realaudio"
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return "text/plain"
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def dumpBin2CHex(f, b):
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oStr = "\t"
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n = 0
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@ -41,40 +70,28 @@ for file in httpFiles:
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webPath = ("/" + file.removeprefix(args.webroot)).replace("//", "/")
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print("{} > {}".format(file, webPath))
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mimeType = mimeFromName(file)
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if args.header:
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if ("404" in file):
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response = b'HTTP/1.0 404 File not found\r\n'
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else:
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response = b'HTTP/1.0 200 OK\r\n'
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response += b"lwIP/1.4.1 (http://savannah.nongnu.org/projects/lwip)\r\n"
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fext = file.split('.')[-1]
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ctype = b'Content-type: text/plain\r\n'
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if (fext.endswith("html") or fext.endswith("htm") or fext.endswith("shtml") or fext.endswith(
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"shtm") or fext.endswith("ssi")):
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ctype = b'Content-type: text/html\r\n'
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if (fext.endswith("js")):
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ctype = b'Content-type: application/x-javascript\r\n'
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if (fext.endswith("css")):
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ctype = b'Content-type: text/css\r\n'
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if (fext.endswith("ico")):
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ctype = b'Content-type: image/x-icon\r\n'
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if (fext.endswith("gif")):
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ctype = b'Content-type: image/gif\r\n'
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if (fext.endswith("png")):
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ctype = b'Content-type: image/png\r\n'
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if(fext.endswith("jpg")):
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ctype = b'Content-type: image/jpeg\r\n'
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if(fext.endswith("bmp")):
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ctype = b'Content-type: image/bmp\r\n'
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if(fext.endswith("class")):
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ctype = b'Content-type: application/octet-stream\r\n'
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if(fext.endswith("ram")):
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ctype = b'Content-type: audio/x-pn-realaudio\r\n'
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response += ctype
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response += b'Content-type: ' + mimeType.encode() + b'\r\n'
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binFile = open(file, 'rb')
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binData = binFile.read()
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compEff = False
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if args.minify:
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p = subprocess.Popen(["minify", "--html-keep-document-tags", "--mime", mimeType], stdin=subprocess.PIPE,
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stdout=subprocess.PIPE)
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minData = p.communicate(binData)[0]
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if len(minData) < len(binData):
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print("- Minify: {} -> {}".format(len(binData), len(minData)))
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compEff = True
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binData = minData
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if args.gzip:
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compData = gzip.compress(binData, 9)
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if len(compData) < len(binData):
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@ -103,7 +120,8 @@ for file in httpFiles:
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f_fsdata_c.write("};\n\n")
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f_fsdata_c.write("const struct fsdata_file {}[] = {{{{\n {},\n {}, {} + {}, sizeof({}) - {}, 1 }}}};\n\n"
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.format(escFileFile, lastFileStruct, escFileData, escFileData, len(fnameBin), escFileData, len(fnameBin)))
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.format(escFileFile, lastFileStruct, escFileData, escFileData, len(fnameBin), escFileData,
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len(fnameBin)))
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# TODO: The last value is 1 if args.header == True
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lastFileStruct = escFileFile
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@ -1 +1 @@
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Subproject commit a8217311e0d8547127b69b7c4ead62ed3aa87b79
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Subproject commit 7faa16b07ce0d606f9525a316990da5b58e61314
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5
pcb/.gitignore
vendored
5
pcb/.gitignore
vendored
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@ -16,7 +16,6 @@ _autosave-*
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*-save.pro
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*-save.kicad_pcb
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fp-info-cache
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*-backups/
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# Netlist files (exported from Eeschema)
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*.net
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@ -32,6 +31,8 @@ fp-info-cache
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*.wrl
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*.step
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*-bak
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*-backups/
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gen/
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pcb.zip
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report.txt
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58
pcb/Makefile
58
pcb/Makefile
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@ -1,54 +1,52 @@
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.NOTPARALLEL: gen/fab/$(BOARD)-F_Cu.gbr gen/fab/$(BOARD)-B_Cu.gbr gen/fab/$(BOARD)-F_Mask.gbr gen/fab/$(BOARD)-B_Mask.gbr gen/fab/$(BOARD)-F_Paste.gbr gen/fab/$(BOARD)-B_Paste.gbr gen/fab/$(BOARD)-F_SilkS.gbr gen/fab/$(BOARD)-B_SilkS.gbr
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.NOTPARALLEL: gen/fab/fiatlux-F_Cu.gbr gen/fab/fiatlux-B_Cu.gbr gen/fab/fiatlux-F_Mask.gbr gen/fab/fiatlux-B_Mask.gbr gen/fab/fiatlux-F_Paste.gbr gen/fab/fiatlux-B_Paste.gbr gen/fab/fiatlux-F_SilkS.gbr gen/fab/fiatlux-B_SilkS.gbr
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all: test fab doc pcb
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all: test fab doc pcb.zip
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test: gen/$(BOARD)-drc.txt gen/$(BOARD)-erc.txt
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pcb: $(BOARD)_pcb.zip
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doc: gen/$(BOARD).pdf gen/$(BOARD)-front.svg gen/$(BOARD)-back.svg
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fab: test gen/$(BOARD)_fab.zip gen/$(BOARD).csv gen/$(BOARD)-top-pos.csv
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$(BOARD)_pcb.zip: fab doc
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pcb.zip: fab doc
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||||
@mkdir -p gen
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cd gen; zip -r ../$(BOARD)_pcb.zip $(BOARD)_fab.zip $(BOARD).csv $(BOARD)-top-pos.csv $(BOARD)-front.svg $(BOARD)-back.svg $(BOARD).pdf
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cd gen; zip -r ../$(BOARD)_debug.zip .
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@cd gen; zip -r ../pcb.zip fab.zip fiatlux.csv fiatlux-top-pos.csv fiatlux-front.svg fiatlux-back.svg fiatlux.pdf
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@cd gen; zip -r ../debug.zip .
|
||||
|
||||
gen/$(BOARD)_fab.zip: gen/fab/$(BOARD)-F_Cu.gbr gen/fab/$(BOARD)-B_Cu.gbr gen/fab/$(BOARD)-F_Mask.gbr gen/fab/$(BOARD)-B_Mask.gbr
|
||||
gen/$(BOARD)_fab.zip: gen/fab/$(BOARD)-F_Paste.gbr gen/fab/$(BOARD)-B_Paste.gbr gen/fab/$(BOARD)-F_SilkS.gbr gen/fab/$(BOARD)-B_SilkS.gbr
|
||||
test: gen/fiatlux-drc.txt gen/fiatlux-erc.txt
|
||||
|
||||
doc: gen/fiatlux.pdf gen/fiatlux-front.svg gen/fiatlux-back.svg
|
||||
|
||||
fab: test gen/fab.zip gen/fiatlux.csv gen/fiatlux-top-pos.csv
|
||||
|
||||
gen/fab.zip: gen/fab/fiatlux-F_Cu.gbr gen/fab/fiatlux-B_Cu.gbr gen/fab/fiatlux-F_Mask.gbr gen/fab/fiatlux-B_Mask.gbr
|
||||
gen/fab.zip: gen/fab/fiatlux-F_Paste.gbr gen/fab/fiatlux-B_Paste.gbr gen/fab/fiatlux-F_SilkS.gbr gen/fab/fiatlux-B_SilkS.gbr
|
||||
@mkdir -p gen/fab
|
||||
cd gen/fab; zip -r ../$(BOARD)_fab.zip *.gbr
|
||||
@cd gen/fab; zip -r ../fab.zip *.gbr
|
||||
|
||||
gen/$(BOARD)-erc.txt: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
|
||||
gen/fiatlux-erc.txt: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
|
||||
@mkdir -p gen
|
||||
kibot -d gen -c $(BOARD).kiplot.yaml -s update_xml,run_drc -i
|
||||
kibot -d gen -c fiatlux.kiplot.yaml -s update_xml,run_drc -i
|
||||
|
||||
gen/$(BOARD)-drc.txt: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_sch
|
||||
gen/fiatlux-drc.txt: fiatlux.kiplot.yaml fiatlux.pro fiatlux.sch
|
||||
@mkdir -p gen
|
||||
kibot -d gen -c $(BOARD).kiplot.yaml -s update_xml,run_erc -i
|
||||
kibot -d gen -c fiatlux.kiplot.yaml -s update_xml,run_erc -i
|
||||
|
||||
gen/fab/%.gbr: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
|
||||
gen/fab/%.gbr: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
|
||||
@mkdir -p gen
|
||||
kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front gerbers
|
||||
kibot -d gen -c fiatlux.kiplot.yaml -s all print_front gerbers
|
||||
|
||||
gen/$(BOARD)-top-pos.csv: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
|
||||
gen/fiatlux-top-pos.csv: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
|
||||
@mkdir -p gen
|
||||
kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front position
|
||||
kibot -d gen -c fiatlux.kiplot.yaml -s all print_front position
|
||||
|
||||
gen/$(BOARD).csv: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
|
||||
gen/fiatlux.csv: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
|
||||
@mkdir -p gen
|
||||
kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front bom
|
||||
kibot -d gen -c fiatlux.kiplot.yaml -s all print_front bom
|
||||
|
||||
gen/$(BOARD).pdf: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_sch
|
||||
gen/fiatlux.pdf: fiatlux.kiplot.yaml fiatlux.pro fiatlux.sch
|
||||
@mkdir -p gen
|
||||
kibot -d gen -c $(BOARD).kiplot.yaml -s run_drc,run_erc print_sch
|
||||
kibot -d gen -c fiatlux.kiplot.yaml -s run_drc,run_erc print_sch
|
||||
|
||||
gen/$(BOARD)-front.svg: $(BOARD).kicad_pcb
|
||||
gen/fiatlux-front.svg: fiatlux.kicad_pcb
|
||||
@mkdir -p gen
|
||||
pcbdraw --libs default $< $@
|
||||
|
||||
gen/$(BOARD)-back.svg: $(BOARD).kicad_pcb
|
||||
gen/fiatlux-back.svg: fiatlux.kicad_pcb
|
||||
@mkdir -p gen
|
||||
pcbdraw --libs default --back $< $@
|
||||
|
||||
|
|
|
|||
|
|
@ -1,525 +0,0 @@
|
|||
(kicad_sch (version 20211123) (generator eeschema)
|
||||
|
||||
(uuid 0a742bb2-0657-47bc-9dea-e70308e1113a)
|
||||
|
||||
(paper "A4")
|
||||
|
||||
(lib_symbols
|
||||
(symbol "Device:C_Polarized" (pin_numbers hide) (pin_names (offset 0.254)) (in_bom yes) (on_board yes)
|
||||
(property "Reference" "C" (id 0) (at 0.635 2.54 0)
|
||||
(effects (font (size 1.27 1.27)) (justify left))
|
||||
)
|
||||
(property "Value" "C_Polarized" (id 1) (at 0.635 -2.54 0)
|
||||
(effects (font (size 1.27 1.27)) (justify left))
|
||||
)
|
||||
(property "Footprint" "" (id 2) (at 0.9652 -3.81 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "~" (id 3) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "ki_keywords" "cap capacitor" (id 4) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "ki_description" "Polarized capacitor" (id 5) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "ki_fp_filters" "CP_*" (id 6) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(symbol "C_Polarized_0_1"
|
||||
(rectangle (start -2.286 0.508) (end 2.286 1.016)
|
||||
(stroke (width 0) (type default) (color 0 0 0 0))
|
||||
(fill (type none))
|
||||
)
|
||||
(polyline
|
||||
(pts
|
||||
(xy -1.778 2.286)
|
||||
(xy -0.762 2.286)
|
||||
)
|
||||
(stroke (width 0) (type default) (color 0 0 0 0))
|
||||
(fill (type none))
|
||||
)
|
||||
(polyline
|
||||
(pts
|
||||
(xy -1.27 2.794)
|
||||
(xy -1.27 1.778)
|
||||
)
|
||||
(stroke (width 0) (type default) (color 0 0 0 0))
|
||||
(fill (type none))
|
||||
)
|
||||
(rectangle (start 2.286 -0.508) (end -2.286 -1.016)
|
||||
(stroke (width 0) (type default) (color 0 0 0 0))
|
||||
(fill (type outline))
|
||||
)
|
||||
)
|
||||
(symbol "C_Polarized_1_1"
|
||||
(pin passive line (at 0 3.81 270) (length 2.794)
|
||||
(name "~" (effects (font (size 1.27 1.27))))
|
||||
(number "1" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
(pin passive line (at 0 -3.81 90) (length 2.794)
|
||||
(name "~" (effects (font (size 1.27 1.27))))
|
||||
(number "2" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol "MCU_ST_STM8:STM8S003F3U" (in_bom yes) (on_board yes)
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41617
pcb/fiatlux.kicad_pcb
41617
pcb/fiatlux.kicad_pcb
File diff suppressed because it is too large
Load diff
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@ -1,449 +0,0 @@
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"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "fiatlux.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.25,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"net_colors": null
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "fiatlux.net",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"drawing": {
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.25,
|
||||
"pin_symbol_size": 0.0,
|
||||
"text_offset_ratio": 0.08
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "Pcbnew",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"fix_passive_vals": false,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 0,
|
||||
"workbook_filename": ""
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_adjust_passive_values": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"814763c2-92e5-4a2c-941c-9bbd073f6e87",
|
||||
""
|
||||
],
|
||||
[
|
||||
"00000000-0000-0000-0000-00006078273a",
|
||||
"Power"
|
||||
],
|
||||
[
|
||||
"704d02d9-6cb6-48ad-b961-61eafd0de7c6",
|
||||
"Ext-IO"
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
File diff suppressed because it is too large
Load diff
252
pcb/fiatlux.pro
Normal file
252
pcb/fiatlux.pro
Normal file
|
|
@ -0,0 +1,252 @@
|
|||
update=Mo 12 Jul 2021 16:48:53 CEST
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=fiatlux.net
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.2
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.25
|
||||
TrackWidth2=0.25
|
||||
TrackWidth3=0.5
|
||||
TrackWidth4=1
|
||||
TrackWidth5=2
|
||||
ViaDiameter1=0.8
|
||||
ViaDrill1=0.4
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.15
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.09999999999999999
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.127
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.4
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
1340
pcb/fiatlux.sch
Normal file
1340
pcb/fiatlux.sch
Normal file
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
1708
pcb/power.kicad_sch
1708
pcb/power.kicad_sch
File diff suppressed because it is too large
Load diff
3
webapp/.gitignore
vendored
Normal file
3
webapp/.gitignore
vendored
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
node_modules/
|
||||
src/gen/
|
||||
package-lock.json
|
||||
Loading…
Reference in a new issue