add drill files to production file archive

.build.yml

@@ -9,15 +9,13 @@ steps:
 - name: submodules
   image: alpine/git
   commands:
-  - git submodule update --init --recursive --depth 1
+  - git submodule update --init --recursive
 
 - name: firmware
   image: docker-repo.service.intern.lab.or.it:5000/fiatlux-build-env
   depends_on: [ submodules ]
   commands:
   - export PATH=$(pwd)/modules/sdk/xtensa-lx106-elf/bin:$PATH
-  - apt update
-  - apt install -y minify
   - make firmware -j$(nproc)
 
 - name: pcb
@@ -25,7 +23,8 @@ steps:
   commands:
   - apt update
   - apt install -y make zip
-  - make pcb -j$(nproc)
+  - make pcb -j$(nproc) BOARD=fiatlux
+  - make pcb -j$(nproc) BOARD=fiatlux_cc48
 
 - name: case
   image: debian:sid
@@ -60,7 +59,8 @@ steps:
     files: 
       - firmware/firmware/fiatlux.bin
       - firmware/otaflash.py
-      - pcb/pcb.zip
+      - pcb/fiatlux_pcb.zip
+      - pcb/fiatlux_cc48_pcb.zip
     checksum:
       - sha512
       - md5

Makefile

@@ -1,3 +1,4 @@
+
 .PHONY: firmware flash firmware_docker case pcb
 
 all: firmware case pcb
@@ -18,11 +19,6 @@ clean:
 	+@make -C firmware clean
 	+@make -C pcb clean
 
-flash_docker:
-	sh -c "docker build -t fiatlux_firmware_env docker/firmware"
-	sh -c "docker run --volume "$$(pwd)"/firmware:/app/firmware --device=/dev/ttyUSB0 fiatlux_firmware_env make -C firmware flash"
-
-
 firmware_docker:
 	sh -c "docker build -t fiatlux_firmware_env docker/firmware"
 	sh -c "docker run --volume "$$(pwd)"/firmware:/app/firmware fiatlux_firmware_env make -C firmware html all"

firmware/Makefile

@@ -2,11 +2,11 @@ PROGRAM=fiatlux
 
 EXTRA_CFLAGS=-O3 -Ibuild/gen -DLWIP_NETIF_HOSTNAME=1
 
-EXTRA_COMPONENTS=extras/i2s_dma extras/ws2812_i2s extras/dhcpserver extras/rboot-ota extras/mbedtls extras/httpd extras/sntp extras/cpp_support extras/paho_mqtt_c
+EXTRA_COMPONENTS=extras/i2s_dma extras/ws2812_i2s extras/dhcpserver extras/rboot-ota extras/mbedtls extras/httpd extras/sntp extras/cpp_support
 
 LIBS = hal m
 
-FLASH_MODE = qio
+FLASH_MODE = dio
 
 include ../modules/rtos/common.mk
 
@@ -15,7 +15,7 @@ html: build/gen/fsdata.c
 build/gen/fsdata.c: webdir/index.html webdir/404.html webdir/css/picnic.min.css webdir/css/style.css webdir/js/smoothie_min.js
 	@echo "Generating fsdata.."
 	@mkdir -p $(dir $@)
-	@./mkwebfs.py --gzip --minify -o $@ $^
+	@./mkwebfs.py --gzip -o $@ $^
 
 test: unittest systest
 

firmware/mkwebfs.py

@@ -2,7 +2,6 @@
 import os
 import gzip
 import argparse
-import subprocess
 
 parser = argparse.ArgumentParser()
 parser.add_argument('-o', '--output', help='Output file name', default='stdout')
@@ -10,9 +9,6 @@ parser.add_argument('-W', '--webroot', help='Output file name', default='webdir/
 parser.add_argument('--gzip', dest='gzip', action='store_true')
 parser.add_argument('--no-gzip', dest='gzip', action='store_false')
 parser.set_defaults(gzip=False)
-parser.add_argument('--minify', dest='minify', action='store_true')
-parser.add_argument('--no-minify', dest='minify', action='store_false')
-parser.set_defaults(minify=False)
 parser.add_argument('--header', dest='header', action='store_true')
 parser.add_argument('--no-header', dest='header', action='store_false')
 parser.set_defaults(header=True)
@@ -20,31 +16,6 @@ parser.add_argument('input', nargs='+', default=os.getcwd())
 args = parser.parse_args()
 
 
-def mimeFromName(name):
-    if name.endswith(".html") or name.endswith(".htm") or name.endswith(".shtml") or name.endswith(
-            ".shtm") or name.endswith(".ssi"):
-        return "text/html"
-    if name.endswith(".js"):
-        return "application/x-javascript"
-    if name.endswith(".css"):
-        return "text/css"
-    if name.endswith(".ico"):
-        return "image/x-icon"
-    if name.endswith(".gif"):
-        return "image/gif"
-    if name.endswith(".png"):
-        return "image/png"
-    if name.endswith(".jpg"):
-        return "image/jpeg"
-    if name.endswith(".bmp"):
-        return "image/bmp"
-    if name.endswith(".class"):
-        return "application/octet-stream"
-    if name.endswith(".ram"):
-        return "audio/x-pn-realaudio"
-    return "text/plain"
-
-
 def dumpBin2CHex(f, b):
     oStr = "\t"
     n = 0
@@ -70,28 +41,40 @@ for file in httpFiles:
     webPath = ("/" + file.removeprefix(args.webroot)).replace("//", "/")
     print("{} > {}".format(file, webPath))
 
-    mimeType = mimeFromName(file)
-
     if args.header:
         if ("404" in file):
             response = b'HTTP/1.0 404 File not found\r\n'
         else:
             response = b'HTTP/1.0 200 OK\r\n'
         response += b"lwIP/1.4.1 (http://savannah.nongnu.org/projects/lwip)\r\n"
-        response += b'Content-type: ' + mimeType.encode() + b'\r\n'
+        fext = file.split('.')[-1]
+        ctype = b'Content-type: text/plain\r\n'
+        if (fext.endswith("html") or fext.endswith("htm") or fext.endswith("shtml") or fext.endswith(
+                "shtm") or fext.endswith("ssi")):
+            ctype = b'Content-type: text/html\r\n'
+        if (fext.endswith("js")):
+            ctype = b'Content-type: application/x-javascript\r\n'
+        if (fext.endswith("css")):
+            ctype = b'Content-type: text/css\r\n'
+        if (fext.endswith("ico")):
+            ctype = b'Content-type: image/x-icon\r\n'
+        if (fext.endswith("gif")):
+            ctype = b'Content-type: image/gif\r\n'
+        if (fext.endswith("png")):
+            ctype = b'Content-type: image/png\r\n'
+        if(fext.endswith("jpg")):
+            ctype = b'Content-type: image/jpeg\r\n'
+        if(fext.endswith("bmp")):
+            ctype = b'Content-type: image/bmp\r\n'
+        if(fext.endswith("class")):
+            ctype = b'Content-type: application/octet-stream\r\n'
+        if(fext.endswith("ram")):
+            ctype = b'Content-type: audio/x-pn-realaudio\r\n'
+        response += ctype
 
         binFile = open(file, 'rb')
         binData = binFile.read()
         compEff = False
-        if args.minify:
-            p = subprocess.Popen(["minify", "--html-keep-document-tags", "--mime", mimeType], stdin=subprocess.PIPE,
-                                 stdout=subprocess.PIPE)
-            minData = p.communicate(binData)[0]
-            if len(minData) < len(binData):
-                print("- Minify: {} -> {}".format(len(binData), len(minData)))
-                compEff = True
-                binData = minData
-
         if args.gzip:
             compData = gzip.compress(binData, 9)
             if len(compData) < len(binData):
@@ -120,8 +103,7 @@ for file in httpFiles:
         f_fsdata_c.write("};\n\n")
 
         f_fsdata_c.write("const struct fsdata_file {}[] = {{{{\n  {},\n  {}, {} + {}, sizeof({}) - {}, 1 }}}};\n\n"
-                         .format(escFileFile, lastFileStruct, escFileData, escFileData, len(fnameBin), escFileData,
+                .format(escFileFile, lastFileStruct, escFileData, escFileData, len(fnameBin), escFileData, len(fnameBin)))
-                                 len(fnameBin)))
         # TODO: The last value is 1 if args.header == True
         lastFileStruct = escFileFile
 

modules/rtos

@@ -1 +1 @@
-Subproject commit 7faa16b07ce0d606f9525a316990da5b58e61314
+Subproject commit a8217311e0d8547127b69b7c4ead62ed3aa87b79

pcb/.gitignore

@@ -16,6 +16,7 @@ _autosave-*
 *-save.pro
 *-save.kicad_pcb
 fp-info-cache
+*-backups/
 
 # Netlist files (exported from Eeschema)
 *.net
@@ -31,8 +32,6 @@ fp-info-cache
 *.wrl
 *.step
 
-*-backups/
+*-bak
 gen/
 pcb.zip
-
-report.txt

pcb/Makefile

@@ -1,54 +1,61 @@
-.NOTPARALLEL:  gen/fab/fiatlux-F_Cu.gbr gen/fab/fiatlux-B_Cu.gbr gen/fab/fiatlux-F_Mask.gbr gen/fab/fiatlux-B_Mask.gbr  gen/fab/fiatlux-F_Paste.gbr gen/fab/fiatlux-B_Paste.gbr gen/fab/fiatlux-F_SilkS.gbr gen/fab/fiatlux-B_SilkS.gbr
+.NOTPARALLEL:  gen/fab/$(BOARD)-F_Cu.gbr gen/fab/$(BOARD)-B_Cu.gbr gen/fab/$(BOARD)-F_Mask.gbr gen/fab/$(BOARD)-B_Mask.gbr  gen/fab/$(BOARD)-F_Paste.gbr gen/fab/$(BOARD)-B_Paste.gbr gen/fab/$(BOARD)-F_SilkS.gbr gen/fab/$(BOARD)-B_SilkS.gbr
 
-all: test fab doc pcb.zip
+all: test fab doc pcb
 
-pcb.zip: fab doc
+test: gen/$(BOARD)-drc.txt gen/$(BOARD)-erc.txt
+
+pcb: $(BOARD)_pcb.zip
+
+doc: gen/$(BOARD).pdf gen/$(BOARD)-front.svg gen/$(BOARD)-back.svg
+
+fab: test gen/$(BOARD)_fab.zip gen/$(BOARD).csv gen/$(BOARD)-top-pos.csv
+
+$(BOARD)_pcb.zip: fab doc
 	@mkdir -p gen
-	@cd gen; zip -r ../pcb.zip fab.zip fiatlux.csv fiatlux-top-pos.csv fiatlux-front.svg fiatlux-back.svg fiatlux.pdf
+	cd gen; zip -r ../$(BOARD)_pcb.zip $(BOARD)_fab.zip $(BOARD).csv $(BOARD)-top-pos.csv $(BOARD)-front.svg $(BOARD)-back.svg $(BOARD).pdf
-	@cd gen; zip -r ../debug.zip .
+	cd gen; zip -r ../$(BOARD)_debug.zip .
 
-test: gen/fiatlux-drc.txt gen/fiatlux-erc.txt
+gen/$(BOARD)_fab.zip: gen/fab/$(BOARD)-F_Cu.gbr gen/fab/$(BOARD)-B_Cu.gbr gen/fab/$(BOARD)-F_Mask.gbr gen/fab/$(BOARD)-B_Mask.gbr
-
+gen/$(BOARD)_fab.zip: gen/fab/$(BOARD)-F_Paste.gbr gen/fab/$(BOARD)-B_Paste.gbr gen/fab/$(BOARD)-F_SilkS.gbr gen/fab/$(BOARD)-B_SilkS.gbr
-doc: gen/fiatlux.pdf gen/fiatlux-front.svg gen/fiatlux-back.svg
+gen/$(BOARD)_fab.zip: gen/fab/$(BOARD).drl
-
-fab: test gen/fab.zip gen/fiatlux.csv gen/fiatlux-top-pos.csv
-
-gen/fab.zip: gen/fab/fiatlux-F_Cu.gbr gen/fab/fiatlux-B_Cu.gbr gen/fab/fiatlux-F_Mask.gbr gen/fab/fiatlux-B_Mask.gbr
-gen/fab.zip: gen/fab/fiatlux-F_Paste.gbr gen/fab/fiatlux-B_Paste.gbr gen/fab/fiatlux-F_SilkS.gbr gen/fab/fiatlux-B_SilkS.gbr
 	@mkdir -p gen/fab
-	@cd gen/fab; zip -r ../fab.zip *.gbr
+	cd gen/fab; zip -r ../$(BOARD)_fab.zip $(BOARD)*.gbr $(BOARD).drl
 
-gen/fiatlux-erc.txt:  fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
+gen/$(BOARD)-erc.txt:  $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
 	@mkdir -p gen
-	kibot -d gen -c fiatlux.kiplot.yaml -s update_xml,run_drc -i
+	kibot -d gen -c $(BOARD).kiplot.yaml -s update_xml,run_drc -i
 
-gen/fiatlux-drc.txt:  fiatlux.kiplot.yaml fiatlux.pro fiatlux.sch
+gen/$(BOARD)-drc.txt:  $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_sch
 	@mkdir -p gen
-	kibot -d gen -c fiatlux.kiplot.yaml -s update_xml,run_erc -i
+	kibot -d gen -c $(BOARD).kiplot.yaml -s update_xml,run_erc -i
 
-gen/fab/%.gbr: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
+gen/fab/%.gbr: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
 	@mkdir -p gen
-	kibot -d gen -c fiatlux.kiplot.yaml -s all print_front gerbers
+	kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front gerbers
 
-gen/fiatlux-top-pos.csv: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
+gen/fab/$(BOARD).drl: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
 	@mkdir -p gen
-	kibot -d gen -c fiatlux.kiplot.yaml -s all print_front position
+	kibot -d gen -c $(BOARD).kiplot.yaml -s all drill
 
-gen/fiatlux.csv: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
+gen/$(BOARD)-top-pos.csv: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
 	@mkdir -p gen
-	kibot -d gen -c fiatlux.kiplot.yaml -s all print_front bom
+	kibot -d gen -c $(BOARD).kiplot.yaml -s all position
 
-gen/fiatlux.pdf: fiatlux.kiplot.yaml fiatlux.pro fiatlux.sch
+gen/$(BOARD).csv: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
 	@mkdir -p gen
-	kibot -d gen -c fiatlux.kiplot.yaml -s run_drc,run_erc print_sch
+	kibot -d gen -c $(BOARD).kiplot.yaml -s all bom
 
-gen/fiatlux-front.svg: fiatlux.kicad_pcb
+gen/$(BOARD).pdf: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_sch
+	@mkdir -p gen
+	kibot -d gen -c $(BOARD).kiplot.yaml -s run_drc,run_erc print_sch
+
+gen/$(BOARD)-front.svg: $(BOARD).kicad_pcb
 	@mkdir -p gen
 	pcbdraw --libs default $< $@
 
-gen/fiatlux-back.svg: fiatlux.kicad_pcb
+gen/$(BOARD)-back.svg: $(BOARD).kicad_pcb
 	@mkdir -p gen
 	pcbdraw --libs default --back $< $@
 
 clean:
-	@rm -rf gen
+	@rm -rf gen

pcb/fiatlux.kicad_pro

@@ -0,0 +1,431 @@
+{
+  "board": {
+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.09999999999999999,
+        "copper_line_width": 0.19999999999999998,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.09999999999999999,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.09999999999999999,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.65,
+          "height": 0.65,
+          "width": 0.65
+        },
+        "silk_line_width": 0.15,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.508
+        }
+      },
+      "diff_pair_dimensions": [],
+      "drc_exclusions": [],
+      "meta": {
+        "filename": "board_design_settings.json",
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "copper_edge_clearance": "error",
+        "courtyards_overlap": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint_type_mismatch": "error",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zone_has_empty_net": "error",
+        "zones_intersect": "error"
+      },
+      "rule_severitieslegacy_courtyards_overlap": true,
+      "rule_severitieslegacy_no_courtyard_defined": false,
+      "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.0,
+        "min_copper_edge_clearance": 0.049999999999999996,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.25,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_silk_clearance": 0.0,
+        "min_through_hole_diameter": 0.3,
+        "min_track_width": 0.19999999999999998,
+        "min_via_annular_width": 0.049999999999999996,
+        "min_via_diameter": 0.39999999999999997,
+        "use_height_for_length_calcs": true
+      },
+      "track_widths": [
+        0.0,
+        0.25,
+        0.5,
+        1.0,
+        2.0
+      ],
+      "via_dimensions": [],
+      "zones_allow_external_fillets": false,
+      "zones_use_no_outline": true
+    },
+    "layer_presets": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        1,
+        0,
+        1,
+        2
+      ],
+      [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        1,
+        1,
+        2,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        1,
+        1,
+        1,
+        1,
+        1,
+        0,
+        1,
+        1,
+        1,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        2,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_label_syntax": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "extra_units": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "unannotated": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "fiatlux.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12.0,
+        "clearance": 0.127,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6.0
+      }
+    ],
+    "meta": {
+      "version": 2
+    },
+    "net_colors": null
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "fiatlux.net",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "annotate_start_num": 0,
+    "drawing": {
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.25,
+      "pin_symbol_size": 0.0,
+      "text_offset_ratio": 0.08
+    },
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "meta": {
+      "version": 1
+    },
+    "net_format_name": "Pcbnew",
+    "ngspice": {
+      "fix_include_paths": true,
+      "fix_passive_vals": false,
+      "meta": {
+        "version": 0
+      },
+      "model_mode": 0,
+      "workbook_filename": ""
+    },
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "spice_adjust_passive_values": false,
+    "spice_external_command": "spice \"%I\"",
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
+  },
+  "sheets": [
+    [
+      "ab06324e-b31e-4d03-a693-31b71a6eda60",
+      ""
+    ],
+    [
+      "00000000-0000-0000-0000-00006078273a",
+      "Power"
+    ]
+  ],
+  "text_variables": {}
+}

pcb/fiatlux.kiplot.yaml

@@ -38,14 +38,14 @@ outputs:
     type: pdf_sch_print
     dir: .
     options:
-      output: fiatlux.pdf
+      output: '%f.pdf'
 
   - name: 'print_front'
     comment: "Print F.Cu+Dwgs.User"
     type: pdf_pcb_print
     dir: .
     options:
-      output_name: fiatlux-top.pdf
+      output_name: '%f-top.pdf'
     layers:
       - layer: B.Cu
       - layer: F.SilkS
@@ -94,6 +94,15 @@ outputs:
       - layer: Edge.Cuts
         suffix: Edge_Cuts
 
+  - name: 'drill'
+    comment: "Drill Files"
+    type: excellon
+    dir: fab
+    options:
+      output: '%f.drl'
+      metric_units: true
+
+
   - name: 'position'
     comment: "Pick and place file, JLC style"
     type: position

pcb/fiatlux.pro

@@ -1,252 +0,0 @@
-update=Mo 12 Jul 2021 16:48:53 CEST
-version=1
-last_client=kicad
-[general]
-version=1
-RootSch=
-BoardNm=
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=Pcbnew
-SpiceAjustPassiveValues=0
-LabSize=50
-ERC_TestSimilarLabels=1
-[pcbnew]
-version=1
-PageLayoutDescrFile=
-LastNetListRead=fiatlux.net
-CopperLayerCount=2
-BoardThickness=1.6
-AllowMicroVias=0
-AllowBlindVias=0
-RequireCourtyardDefinitions=0
-ProhibitOverlappingCourtyards=1
-MinTrackWidth=0.2
-MinViaDiameter=0.4
-MinViaDrill=0.3
-MinMicroViaDiameter=0.2
-MinMicroViaDrill=0.09999999999999999
-MinHoleToHole=0.25
-TrackWidth1=0.25
-TrackWidth2=0.25
-TrackWidth3=0.5
-TrackWidth4=1
-TrackWidth5=2
-ViaDiameter1=0.8
-ViaDrill1=0.4
-dPairWidth1=0.2
-dPairGap1=0.25
-dPairViaGap1=0.25
-SilkLineWidth=0.15
-SilkTextSizeV=1
-SilkTextSizeH=1
-SilkTextSizeThickness=0.15
-SilkTextItalic=0
-SilkTextUpright=1
-CopperLineWidth=0.2
-CopperTextSizeV=1.5
-CopperTextSizeH=1.5
-CopperTextThickness=0.3
-CopperTextItalic=0
-CopperTextUpright=1
-EdgeCutLineWidth=0.09999999999999999
-CourtyardLineWidth=0.05
-OthersLineWidth=0.15
-OthersTextSizeV=1
-OthersTextSizeH=1
-OthersTextSizeThickness=0.15
-OthersTextItalic=0
-OthersTextUpright=1
-SolderMaskClearance=0
-SolderMaskMinWidth=0
-SolderPasteClearance=0
-SolderPasteRatio=-0
-[pcbnew/Layer.F.Cu]
-Name=F.Cu
-Type=0
-Enabled=1
-[pcbnew/Layer.In1.Cu]
-Name=In1.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In2.Cu]
-Name=In2.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In3.Cu]
-Name=In3.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In4.Cu]
-Name=In4.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In5.Cu]
-Name=In5.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In6.Cu]
-Name=In6.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In7.Cu]
-Name=In7.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In8.Cu]
-Name=In8.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In9.Cu]
-Name=In9.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In10.Cu]
-Name=In10.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In11.Cu]
-Name=In11.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In12.Cu]
-Name=In12.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In13.Cu]
-Name=In13.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In14.Cu]
-Name=In14.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In15.Cu]
-Name=In15.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In16.Cu]
-Name=In16.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In17.Cu]
-Name=In17.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In18.Cu]
-Name=In18.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In19.Cu]
-Name=In19.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In20.Cu]
-Name=In20.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In21.Cu]
-Name=In21.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In22.Cu]
-Name=In22.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In23.Cu]
-Name=In23.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In24.Cu]
-Name=In24.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In25.Cu]
-Name=In25.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In26.Cu]
-Name=In26.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In27.Cu]
-Name=In27.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In28.Cu]
-Name=In28.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In29.Cu]
-Name=In29.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In30.Cu]
-Name=In30.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.B.Cu]
-Name=B.Cu
-Type=0
-Enabled=1
-[pcbnew/Layer.B.Adhes]
-Enabled=1
-[pcbnew/Layer.F.Adhes]
-Enabled=1
-[pcbnew/Layer.B.Paste]
-Enabled=1
-[pcbnew/Layer.F.Paste]
-Enabled=1
-[pcbnew/Layer.B.SilkS]
-Enabled=1
-[pcbnew/Layer.F.SilkS]
-Enabled=1
-[pcbnew/Layer.B.Mask]
-Enabled=1
-[pcbnew/Layer.F.Mask]
-Enabled=1
-[pcbnew/Layer.Dwgs.User]
-Enabled=1
-[pcbnew/Layer.Cmts.User]
-Enabled=1
-[pcbnew/Layer.Eco1.User]
-Enabled=1
-[pcbnew/Layer.Eco2.User]
-Enabled=1
-[pcbnew/Layer.Edge.Cuts]
-Enabled=1
-[pcbnew/Layer.Margin]
-Enabled=1
-[pcbnew/Layer.B.CrtYd]
-Enabled=1
-[pcbnew/Layer.F.CrtYd]
-Enabled=1
-[pcbnew/Layer.B.Fab]
-Enabled=1
-[pcbnew/Layer.F.Fab]
-Enabled=1
-[pcbnew/Layer.Rescue]
-Enabled=0
-[pcbnew/Netclasses]
-[pcbnew/Netclasses/Default]
-Name=Default
-Clearance=0.127
-TrackWidth=0.25
-ViaDiameter=0.8
-ViaDrill=0.4
-uViaDiameter=0.3
-uViaDrill=0.1
-dPairWidth=0.2
-dPairGap=0.25
-dPairViaGap=0.25

pcb/fiatlux_cc48.kicad_pro

@@ -0,0 +1,460 @@
+{
+  "board": {
+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.09999999999999999,
+        "copper_line_width": 0.19999999999999998,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.09999999999999999,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.15,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 1.52,
+          "height": 3.0,
+          "width": 3.0
+        },
+        "silk_line_width": 0.15,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.508
+        }
+      },
+      "diff_pair_dimensions": [
+        {
+          "gap": 0.0,
+          "via_gap": 0.0,
+          "width": 0.0
+        }
+      ],
+      "drc_exclusions": [],
+      "meta": {
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "copper_edge_clearance": "error",
+        "courtyards_overlap": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint_type_mismatch": "error",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zone_has_empty_net": "error",
+        "zones_intersect": "error"
+      },
+      "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.0,
+        "min_copper_edge_clearance": 0.0,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.25,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_silk_clearance": 0.0,
+        "min_through_hole_diameter": 0.3,
+        "min_track_width": 0.19999999999999998,
+        "min_via_annular_width": 0.049999999999999996,
+        "min_via_diameter": 0.39999999999999997,
+        "solder_mask_clearance": 0.0,
+        "solder_mask_min_width": 0.0,
+        "use_height_for_length_calcs": true
+      },
+      "track_widths": [
+        0.0,
+        0.25,
+        1.0,
+        2.0
+      ],
+      "via_dimensions": [
+        {
+          "diameter": 0.0,
+          "drill": 0.0
+        }
+      ],
+      "zones_allow_external_fillets": false,
+      "zones_use_no_outline": true
+    },
+    "layer_presets": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        1,
+        0,
+        1,
+        2
+      ],
+      [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        1,
+        1,
+        2,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        1,
+        1,
+        1,
+        1,
+        1,
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+        1,
+        1,
+        1,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        2,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_label_syntax": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "extra_units": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "unannotated": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "fiatlux_cc48.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12.0,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6.0
+      }
+    ],
+    "meta": {
+      "version": 2
+    },
+    "net_colors": null
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "annotate_start_num": 0,
+    "drawing": {
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.375,
+      "pin_symbol_size": 25.0,
+      "text_offset_ratio": 0.15
+    },
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "meta": {
+      "version": 1
+    },
+    "net_format_name": "",
+    "ngspice": {
+      "fix_include_paths": true,
+      "fix_passive_vals": false,
+      "meta": {
+        "version": 0
+      },
+      "model_mode": 0,
+      "workbook_filename": ""
+    },
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "spice_adjust_passive_values": false,
+    "spice_external_command": "spice \"%I\"",
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
+  },
+  "sheets": [
+    [
+      "9538e4ed-27e6-4c37-b989-9859dc0d49e8",
+      ""
+    ],
+    [
+      "d33c1df4-7e91-4c8a-86ff-6749f0933357",
+      "fiatlux_cc48_channel_driver2"
+    ],
+    [
+      "ec392c76-0785-4274-a56a-aeb995601b34",
+      "fiatlux_cc48_channel_driver1"
+    ],
+    [
+      "0f2c710f-e0cf-4531-985d-317b699b8a1b",
+      "fiatlux_cc48_channel_driver3"
+    ],
+    [
+      "a672b323-13f7-4347-a8ce-0a3f96c45d44",
+      "fiatlux_cc48_channel_driver5"
+    ],
+    [
+      "a5f417c9-09b7-4103-a9bc-767ebcf97650",
+      "fiatlux_cc48_channel_driver4"
+    ],
+    [
+      "41c6dc95-230a-4992-8ca4-7f36f4bdcf94",
+      "fiatlux_cc48_channel_driver6"
+    ]
+  ],
+  "text_variables": {}
+}

pcb/fiatlux_cc48.kiplot.yaml

@@ -0,0 +1,148 @@
+# Example KiPlot config file
+kiplot:
+  version: 1
+
+preflight:
+  run_erc: true
+  update_xml: true
+  run_drc: true
+  check_zone_fills: false
+  ignore_unconnected: false
+
+# global:
+#   kiauto_wait_start: 60
+#   kiauto_time_out_scale: 2
+
+filters:
+  - name: fix_rotation
+    comment: 'Adjust rotation for JLC'
+    type: rot_footprint
+
+  - name: only_jlc_parts
+    comment: 'Only parts with JLC code'
+    type: generic
+    include_only:
+      - column: 'LCSC#'
+        regex: '^C\d+'
+
+variants:
+  - name: rotated
+    comment: 'Just a place holder for the rotation filter'
+    type: kibom
+    variant: rotated
+    pre_transform: fix_rotation
+
+outputs:
+  - name: 'print_sch'
+    comment: "Print schematic (PDF)"
+    type: pdf_sch_print
+    dir: .
+    options:
+      output: '%f.pdf'
+
+  - name: 'print_front'
+    comment: "Print F.Cu+Dwgs.User"
+    type: pdf_pcb_print
+    dir: .
+    options:
+      output_name: '%f-top.pdf'
+    layers:
+      - layer: B.Cu
+      - layer: F.SilkS
+
+  - name: 'gerbers'
+    comment: "Gerbers for the board house"
+    type: gerber
+    dir: fab
+    options:
+      # generic layer options
+      exclude_edge_layer: true
+      exclude_pads_from_silkscreen: false
+      use_aux_axis_as_origin: false
+      plot_sheet_reference: false
+      plot_footprint_refs: true
+      plot_footprint_values: true
+      force_plot_invisible_refs_vals: false
+      tent_vias: true
+
+      # gerber options
+      line_width: 0.1
+      subtract_mask_from_silk: false
+      use_protel_extensions: false
+      gerber_precision: 4.6
+      create_gerber_job_file: true
+      use_gerber_x2_attributes: true
+      use_gerber_net_attributes: true
+
+    layers:
+      - layer: F.Cu
+        suffix: F_Cu
+      - layer: B.Cu
+        suffix: B_Cu
+      - layer: F.SilkS
+        suffix: F_SilkS
+      - layer: B.SilkS
+        suffix: B_SilkS
+      - layer: F.Paste
+        suffix: F_Paste
+      - layer: B.Paste
+        suffix: B_Paste
+      - layer: F.Mask
+        suffix: F_Mask
+      - layer: B.Mask
+        suffix: B_Mask
+      - layer: Edge.Cuts
+        suffix: Edge_Cuts
+
+  - name: 'drill'
+    comment: "Drill Files"
+    type: excellon
+    dir: fab
+    options:
+      output: '%f.drl'
+      metric_units: true
+
+
+  - name: 'position'
+    comment: "Pick and place file, JLC style"
+    type: position
+    options:
+      variant: rotated
+      output: '%f-top-pos.%x'
+      format: CSV
+      units: millimeters
+      separate_files_for_front_and_back: false
+      only_smd: true
+      columns:
+        - id: Ref
+          name: Designator
+        - Val
+        - Package
+        - id: PosX
+          name: "Mid X"
+        - id: PosY
+          name: "Mid Y"
+        - id: Rot
+          name: Rotation
+        - id: Side
+          name: Layer
+
+  - name: 'bom'
+    comment: "BoM for JLC"
+    type: bom
+    options:
+      output: '%f.%x'
+      exclude_filter: 'only_jlc_parts'
+      ref_separator: ','
+      columns:
+        - field: Value
+          name: Comment
+        - field: References
+          name: Designator
+        - Footprint
+        - field: 'LCSC#'
+          name: 'LCSC Part #'
+      csv:
+        hide_pcb_info: true
+        hide_stats_info: true
+        quote_all: true

pcb/fp-lib-table

@@ -0,0 +1,3 @@
+(fp_lib_table
+  (lib (name "fiatlux")(type "KiCad")(uri "${KIPRJMOD}/fiatlux.pretty")(options "")(descr ""))
+)

pcb/library.kicad_sym

@@ -0,0 +1,198 @@
+(kicad_symbol_lib (version 20211014) (generator kicad_symbol_editor)
+  (symbol "BL1551B" (in_bom yes) (on_board yes)
+    (property "Reference" "U" (id 0) (at 0 -1.27 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "BL1551B" (id 1) (at 0 1.27 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (id 2) (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (symbol "BL1551B_0_1"
+      (rectangle (start 6.35 7.62) (end -6.35 -7.62)
+        (stroke (width 0.1524) (type default) (color 0 0 0 0))
+        (fill (type background))
+      )
+      (rectangle (start 10.16 -10.16) (end 10.16 -10.16)
+        (stroke (width 0.1524) (type default) (color 0 0 0 0))
+        (fill (type none))
+      )
+      (rectangle (start 10.16 -10.16) (end 10.16 -10.16)
+        (stroke (width 0.1524) (type default) (color 0 0 0 0))
+        (fill (type none))
+      )
+      (rectangle (start 10.16 -10.16) (end 10.16 -10.16)
+        (stroke (width 0.1524) (type default) (color 0 0 0 0))
+        (fill (type none))
+      )
+    )
+    (symbol "BL1551B_1_1"
+      (pin bidirectional line (at -8.89 3.81 0) (length 2.54)
+        (name "A1" (effects (font (size 1.27 1.27))))
+        (number "1" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 0 -10.16 90) (length 2.54)
+        (name "GND" (effects (font (size 1.27 1.27))))
+        (number "2" (effects (font (size 1.27 1.27))))
+      )
+      (pin bidirectional line (at -8.89 -3.81 0) (length 2.54)
+        (name "A2" (effects (font (size 1.27 1.27))))
+        (number "3" (effects (font (size 1.27 1.27))))
+      )
+      (pin bidirectional line (at 8.89 -3.81 180) (length 2.54)
+        (name "B" (effects (font (size 1.27 1.27))))
+        (number "4" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 0 10.16 270) (length 2.54)
+        (name "VCC" (effects (font (size 1.27 1.27))))
+        (number "5" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at 8.89 3.81 180) (length 2.54)
+        (name "ENB" (effects (font (size 1.27 1.27))))
+        (number "6" (effects (font (size 1.27 1.27))))
+      )
+    )
+  )
+  (symbol "DAC128S085" (in_bom yes) (on_board yes)
+    (property "Reference" "U2" (id 0) (at 2.0194 16.6157 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Value" "DAC128S085" (id 1) (at 2.0194 13.8406 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Footprint" "Package_SO:SSOP-16_3.9x4.9mm_P0.635mm" (id 2) (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "LCSC" "C882851" (id 4) (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (symbol "DAC128S085_0_1"
+      (rectangle (start -12.7 12.7) (end 12.7 -12.7)
+        (stroke (width 0.1524) (type default) (color 0 0 0 0))
+        (fill (type background))
+      )
+    )
+    (symbol "DAC128S085_1_1"
+      (pin input line (at -15.24 5.08 0) (length 2.54)
+        (name "DIN" (effects (font (size 1.27 1.27))))
+        (number "1" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 0 -15.24 90) (length 2.54)
+        (name "GND" (effects (font (size 1.27 1.27))))
+        (number "10" (effects (font (size 1.27 1.27))))
+      )
+      (pin output line (at 15.24 -8.89 180) (length 2.54)
+        (name "VOUTH" (effects (font (size 1.27 1.27))))
+        (number "11" (effects (font (size 1.27 1.27))))
+      )
+      (pin output line (at 15.24 -6.35 180) (length 2.54)
+        (name "VOUTG" (effects (font (size 1.27 1.27))))
+        (number "12" (effects (font (size 1.27 1.27))))
+      )
+      (pin output line (at 15.24 -3.81 180) (length 2.54)
+        (name "VOUTF" (effects (font (size 1.27 1.27))))
+        (number "13" (effects (font (size 1.27 1.27))))
+      )
+      (pin output line (at 15.24 -1.27 180) (length 2.54)
+        (name "VOUTE" (effects (font (size 1.27 1.27))))
+        (number "14" (effects (font (size 1.27 1.27))))
+      )
+      (pin input inverted (at -15.24 10.16 0) (length 2.54)
+        (name "SYNC" (effects (font (size 1.27 1.27))))
+        (number "15" (effects (font (size 1.27 1.27))))
+      )
+      (pin input clock (at -15.24 7.62 0) (length 2.54)
+        (name "SCLK" (effects (font (size 1.27 1.27))))
+        (number "16" (effects (font (size 1.27 1.27))))
+      )
+      (pin output line (at -15.24 2.54 0) (length 2.54)
+        (name "DOUT" (effects (font (size 1.27 1.27))))
+        (number "2" (effects (font (size 1.27 1.27))))
+      )
+      (pin output line (at 15.24 8.89 180) (length 2.54)
+        (name "OUTA" (effects (font (size 1.27 1.27))))
+        (number "3" (effects (font (size 1.27 1.27))))
+      )
+      (pin output line (at 15.24 6.35 180) (length 2.54)
+        (name "OUTB" (effects (font (size 1.27 1.27))))
+        (number "4" (effects (font (size 1.27 1.27))))
+      )
+      (pin output line (at 15.24 3.81 180) (length 2.54)
+        (name "OUTC" (effects (font (size 1.27 1.27))))
+        (number "5" (effects (font (size 1.27 1.27))))
+      )
+      (pin output line (at 15.24 1.27 180) (length 2.54)
+        (name "OUTD" (effects (font (size 1.27 1.27))))
+        (number "6" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 0 15.24 270) (length 2.54)
+        (name "VA" (effects (font (size 1.27 1.27))))
+        (number "7" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -15.24 -7.62 0) (length 2.54)
+        (name "VREF1" (effects (font (size 1.27 1.27))))
+        (number "8" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -15.24 -10.16 0) (length 2.54)
+        (name "VREF2" (effects (font (size 1.27 1.27))))
+        (number "9" (effects (font (size 1.27 1.27))))
+      )
+    )
+  )
+  (symbol "FL7760" (in_bom yes) (on_board yes)
+    (property "Reference" "U5" (id 0) (at 0 0 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "FL7760" (id 1) (at 0 2.54 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "Package_TO_SOT_SMD:SOT-23-6" (id 2) (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "LCSC" "C367387" (id 4) (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (symbol "FL7760_0_1"
+      (rectangle (start -6.35 10.16) (end 6.35 -7.62)
+        (stroke (width 0.1524) (type default) (color 0 0 0 0))
+        (fill (type background))
+      )
+    )
+    (symbol "FL7760_1_1"
+      (pin input line (at 0 12.7 270) (length 2.54)
+        (name "VIN" (effects (font (size 1.27 1.27))))
+        (number "1" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at 0 -10.16 90) (length 2.54)
+        (name "GND" (effects (font (size 1.27 1.27))))
+        (number "2" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -8.89 -3.81 0) (length 2.54)
+        (name "DIM" (effects (font (size 1.27 1.27))))
+        (number "3" (effects (font (size 1.27 1.27))))
+      )
+      (pin output line (at 8.89 -3.81 180) (length 2.54)
+        (name "DRV" (effects (font (size 1.27 1.27))))
+        (number "4" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at -3.81 12.7 270) (length 2.54)
+        (name "VCC" (effects (font (size 1.27 1.27))))
+        (number "5" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at 3.81 12.7 270) (length 2.54)
+        (name "SEN" (effects (font (size 1.27 1.27))))
+        (number "6" (effects (font (size 1.27 1.27))))
+      )
+    )
+  )
+)

pcb/power.sch

@@ -1,643 +0,0 @@
-EESchema Schematic File Version 4
-EELAYER 30 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 2 2
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
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-F 0 "U3" H 5650 2692 50  0000 C CNN
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-F 3 "http://www.advanced-monolithic.com/pdf/ds1117.pdf" H 5750 2200 50  0001 C CNN
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-F 1 "SS14" H 5050 2024 50  0000 C CNN
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pcb/sym-lib-table

@@ -0,0 +1,3 @@
+(sym_lib_table
+  (lib (name "library")(type "KiCad")(uri "${KIPRJMOD}/library.kicad_sym")(options "")(descr ""))
+)

webapp/.gitignore

@@ -1,3 +0,0 @@
-node_modules/
-src/gen/
-package-lock.json