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j3d1:jedi/dev/regallicht
j3d1:jedi/pcbv3
j3d1:jedi/dev/cc48_firmware
j3d1:jedi/dev/wifi
j3d1:jedi/dev/pxelflut
j3d1:jedi/dev/ntp
j3d1:jedi/dev/bus
j3d1:jedi/cc48
j3d1:jedi/dev/cc48
j3d1:jedi/bus
j3d1:jedi/dev/cv24
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j3d1:jedi/dev/http
j3d1:jedi/dev/noctis
j3d1:jedi/dev/test0
j3d1:jedi/dev/lux
j3d1:jedi/dev/ota
j3d1:jedi/dev/syslog
j3d1:eleon/dev/mqtt
j3d1:jedi/dev/mqtt
j3d1:7m9/dev/replace_perl
j3d1:jedi/timed_night_light
j3d1:jedi/dev/case
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j3d1:v0.1
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compare: j3d1:jedi/bus
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j3d1:jedi/dev/cc48_bootloader
j3d1:jedi/dev/regallicht
j3d1:jedi/pcbv3
j3d1:jedi/dev/cc48_firmware
j3d1:jedi/dev/wifi
j3d1:jedi/dev/pxelflut
j3d1:jedi/dev/ntp
j3d1:stable
j3d1:jedi/dev/bus
j3d1:jedi/cc48
j3d1:jedi/dev/cc48
j3d1:jedi/bus
j3d1:jedi/dev/cv24
j3d1:stash
j3d1:jedi/dev/http
j3d1:jedi/dev/noctis
j3d1:jedi/dev/test0
j3d1:jedi/dev/lux
j3d1:jedi/dev/ota
j3d1:jedi/dev/syslog
j3d1:eleon/dev/mqtt
j3d1:jedi/dev/mqtt
j3d1:7m9/dev/replace_perl
j3d1:jedi/timed_night_light
j3d1:jedi/dev/case
j3d1:cc48v1
j3d1:v0.2
j3d1:v0.1

3 commits
stable ... jedi/bus

Author SHA1 Message Date
jedi
9d2594f1d3 stash
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2022-05-23 01:17:00 +02:00
jedi
f8706df9b4 add STM8 to pcb design
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continuous-integration/drone/push Build is passing
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2022-05-23 01:04:21 +02:00
jedi
bcfae05953 update to kicad6
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continuous-integration/drone/push Build is passing
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2022-05-23 00:56:58 +02:00
18 changed files with 44729 additions and 7402 deletions
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8
.build.yml
View file

@ -16,8 +16,6 @@ steps:
depends_on: [ submodules ] depends_on: [ submodules ]
commands: commands:
- export PATH=$(pwd)/modules/sdk/xtensa-lx106-elf/bin:$PATH - export PATH=$(pwd)/modules/sdk/xtensa-lx106-elf/bin:$PATH
- apt update
- apt install -y minify
- make firmware -j$(nproc) - make firmware -j$(nproc)
- name: pcb - name: pcb
@ -25,7 +23,8 @@ steps:
commands: commands:
- apt update - apt update
- apt install -y make zip - apt install -y make zip
- make pcb -j$(nproc) - make pcb -j$(nproc) BOARD=fiatlux
- make pcb -j$(nproc) BOARD=fiatlux_cc48
- name: case - name: case
image: debian:sid image: debian:sid
@ -60,7 +59,8 @@ steps:
files: files:
- firmware/firmware/fiatlux.bin - firmware/firmware/fiatlux.bin
- firmware/otaflash.py - firmware/otaflash.py
- pcb/pcb.zip - pcb/fiatlux_pcb.zip
- pcb/fiatlux_cc48_pcb.zip
checksum: checksum:
- sha512 - sha512
- md5 - md5

6
Makefile
View file

@ -1,3 +1,4 @@
.PHONY: firmware flash firmware_docker case pcb .PHONY: firmware flash firmware_docker case pcb
all: firmware case pcb all: firmware case pcb
@ -18,11 +19,6 @@ clean:
+@make -C firmware clean +@make -C firmware clean
+@make -C pcb clean +@make -C pcb clean
flash_docker:
sh -c "docker build -t fiatlux_firmware_env docker/firmware"
sh -c "docker run --volume "$$(pwd)"/firmware:/app/firmware --device=/dev/ttyUSB0 fiatlux_firmware_env make -C firmware flash"
firmware_docker: firmware_docker:
sh -c "docker build -t fiatlux_firmware_env docker/firmware" sh -c "docker build -t fiatlux_firmware_env docker/firmware"
sh -c "docker run --volume "$$(pwd)"/firmware:/app/firmware fiatlux_firmware_env make -C firmware html all" sh -c "docker run --volume "$$(pwd)"/firmware:/app/firmware fiatlux_firmware_env make -C firmware html all"

6
firmware/Makefile
View file

@ -2,11 +2,11 @@ PROGRAM=fiatlux
EXTRA_CFLAGS=-O3 -Ibuild/gen -DLWIP_NETIF_HOSTNAME=1 EXTRA_CFLAGS=-O3 -Ibuild/gen -DLWIP_NETIF_HOSTNAME=1
EXTRA_COMPONENTS=extras/i2s_dma extras/ws2812_i2s extras/dhcpserver extras/rboot-ota extras/mbedtls extras/httpd extras/sntp extras/cpp_support extras/paho_mqtt_c EXTRA_COMPONENTS=extras/i2s_dma extras/ws2812_i2s extras/dhcpserver extras/rboot-ota extras/mbedtls extras/httpd extras/sntp extras/cpp_support
LIBS = hal m LIBS = hal m
FLASH_MODE = qio FLASH_MODE = dio
include ../modules/rtos/common.mk include ../modules/rtos/common.mk
@ -15,7 +15,7 @@ html: build/gen/fsdata.c
build/gen/fsdata.c: webdir/index.html webdir/404.html webdir/css/picnic.min.css webdir/css/style.css webdir/js/smoothie_min.js build/gen/fsdata.c: webdir/index.html webdir/404.html webdir/css/picnic.min.css webdir/css/style.css webdir/js/smoothie_min.js
@echo "Generating fsdata.." @echo "Generating fsdata.."
@mkdir -p $(dir $@) @mkdir -p $(dir $@)
@./mkwebfs.py --gzip --minify -o $@ $^ @./mkwebfs.py --gzip -o $@ $^
test: unittest systest test: unittest systest

68
firmware/mkwebfs.py
View file

@ -2,7 +2,6 @@
import os import os
import gzip import gzip
import argparse import argparse
import subprocess
parser = argparse.ArgumentParser() parser = argparse.ArgumentParser()
parser.add_argument('-o', '--output', help='Output file name', default='stdout') parser.add_argument('-o', '--output', help='Output file name', default='stdout')
@ -10,9 +9,6 @@ parser.add_argument('-W', '--webroot', help='Output file name', default='webdir/
parser.add_argument('--gzip', dest='gzip', action='store_true') parser.add_argument('--gzip', dest='gzip', action='store_true')
parser.add_argument('--no-gzip', dest='gzip', action='store_false') parser.add_argument('--no-gzip', dest='gzip', action='store_false')
parser.set_defaults(gzip=False) parser.set_defaults(gzip=False)
parser.add_argument('--minify', dest='minify', action='store_true')
parser.add_argument('--no-minify', dest='minify', action='store_false')
parser.set_defaults(minify=False)
parser.add_argument('--header', dest='header', action='store_true') parser.add_argument('--header', dest='header', action='store_true')
parser.add_argument('--no-header', dest='header', action='store_false') parser.add_argument('--no-header', dest='header', action='store_false')
parser.set_defaults(header=True) parser.set_defaults(header=True)
@ -20,31 +16,6 @@ parser.add_argument('input', nargs='+', default=os.getcwd())
args = parser.parse_args() args = parser.parse_args()
def mimeFromName(name):
if name.endswith(".html") or name.endswith(".htm") or name.endswith(".shtml") or name.endswith(
".shtm") or name.endswith(".ssi"):
return "text/html"
if name.endswith(".js"):
return "application/x-javascript"
if name.endswith(".css"):
return "text/css"
if name.endswith(".ico"):
return "image/x-icon"
if name.endswith(".gif"):
return "image/gif"
if name.endswith(".png"):
return "image/png"
if name.endswith(".jpg"):
return "image/jpeg"
if name.endswith(".bmp"):
return "image/bmp"
if name.endswith(".class"):
return "application/octet-stream"
if name.endswith(".ram"):
return "audio/x-pn-realaudio"
return "text/plain"
def dumpBin2CHex(f, b): def dumpBin2CHex(f, b):
oStr = "\t" oStr = "\t"
n = 0 n = 0
@ -70,28 +41,40 @@ for file in httpFiles:
webPath = ("/" + file.removeprefix(args.webroot)).replace("//", "/") webPath = ("/" + file.removeprefix(args.webroot)).replace("//", "/")
print("{} > {}".format(file, webPath)) print("{} > {}".format(file, webPath))
mimeType = mimeFromName(file)
if args.header: if args.header:
if ("404" in file): if ("404" in file):
response = b'HTTP/1.0 404 File not found\r\n' response = b'HTTP/1.0 404 File not found\r\n'
else: else:
response = b'HTTP/1.0 200 OK\r\n' response = b'HTTP/1.0 200 OK\r\n'
response += b"lwIP/1.4.1 (http://savannah.nongnu.org/projects/lwip)\r\n" response += b"lwIP/1.4.1 (http://savannah.nongnu.org/projects/lwip)\r\n"
response += b'Content-type: ' + mimeType.encode() + b'\r\n' fext = file.split('.')[-1]
ctype = b'Content-type: text/plain\r\n'
if (fext.endswith("html") or fext.endswith("htm") or fext.endswith("shtml") or fext.endswith(
"shtm") or fext.endswith("ssi")):
ctype = b'Content-type: text/html\r\n'
if (fext.endswith("js")):
ctype = b'Content-type: application/x-javascript\r\n'
if (fext.endswith("css")):
ctype = b'Content-type: text/css\r\n'
if (fext.endswith("ico")):
ctype = b'Content-type: image/x-icon\r\n'
if (fext.endswith("gif")):
ctype = b'Content-type: image/gif\r\n'
if (fext.endswith("png")):
ctype = b'Content-type: image/png\r\n'
if(fext.endswith("jpg")):
ctype = b'Content-type: image/jpeg\r\n'
if(fext.endswith("bmp")):
ctype = b'Content-type: image/bmp\r\n'
if(fext.endswith("class")):
ctype = b'Content-type: application/octet-stream\r\n'
if(fext.endswith("ram")):
ctype = b'Content-type: audio/x-pn-realaudio\r\n'
response += ctype
binFile = open(file, 'rb') binFile = open(file, 'rb')
binData = binFile.read() binData = binFile.read()
compEff = False compEff = False
if args.minify:
p = subprocess.Popen(["minify", "--html-keep-document-tags", "--mime", mimeType], stdin=subprocess.PIPE,
stdout=subprocess.PIPE)
minData = p.communicate(binData)[0]
if len(minData) < len(binData):
print("- Minify: {} -> {}".format(len(binData), len(minData)))
compEff = True
binData = minData
if args.gzip: if args.gzip:
compData = gzip.compress(binData, 9) compData = gzip.compress(binData, 9)
if len(compData) < len(binData): if len(compData) < len(binData):
@ -120,8 +103,7 @@ for file in httpFiles:
f_fsdata_c.write("};\n\n") f_fsdata_c.write("};\n\n")
f_fsdata_c.write("const struct fsdata_file {}[] = {{{{\n {},\n {}, {} + {}, sizeof({}) - {}, 1 }}}};\n\n" f_fsdata_c.write("const struct fsdata_file {}[] = {{{{\n {},\n {}, {} + {}, sizeof({}) - {}, 1 }}}};\n\n"
.format(escFileFile, lastFileStruct, escFileData, escFileData, len(fnameBin), escFileData, .format(escFileFile, lastFileStruct, escFileData, escFileData, len(fnameBin), escFileData, len(fnameBin)))
len(fnameBin)))
# TODO: The last value is 1 if args.header == True # TODO: The last value is 1 if args.header == True
lastFileStruct = escFileFile lastFileStruct = escFileFile

2
modules/rtos

@ -1 +1 @@
Subproject commit 7faa16b07ce0d606f9525a316990da5b58e61314 Subproject commit a8217311e0d8547127b69b7c4ead62ed3aa87b79

5
pcb/.gitignore vendored
View file

@ -16,6 +16,7 @@ _autosave-*
*-save.pro *-save.pro
*-save.kicad_pcb *-save.kicad_pcb
fp-info-cache fp-info-cache
*-backups/
# Netlist files (exported from Eeschema) # Netlist files (exported from Eeschema)
*.net *.net
@ -31,8 +32,6 @@ fp-info-cache
*.wrl *.wrl
*.step *.step
*-backups/ *-bak
gen/ gen/
pcb.zip pcb.zip
report.txt

58
pcb/Makefile
View file

@ -1,52 +1,54 @@
.NOTPARALLEL: gen/fab/fiatlux-F_Cu.gbr gen/fab/fiatlux-B_Cu.gbr gen/fab/fiatlux-F_Mask.gbr gen/fab/fiatlux-B_Mask.gbr gen/fab/fiatlux-F_Paste.gbr gen/fab/fiatlux-B_Paste.gbr gen/fab/fiatlux-F_SilkS.gbr gen/fab/fiatlux-B_SilkS.gbr .NOTPARALLEL: gen/fab/$(BOARD)-F_Cu.gbr gen/fab/$(BOARD)-B_Cu.gbr gen/fab/$(BOARD)-F_Mask.gbr gen/fab/$(BOARD)-B_Mask.gbr gen/fab/$(BOARD)-F_Paste.gbr gen/fab/$(BOARD)-B_Paste.gbr gen/fab/$(BOARD)-F_SilkS.gbr gen/fab/$(BOARD)-B_SilkS.gbr
all: test fab doc pcb.zip all: test fab doc pcb
pcb.zip: fab doc test: gen/$(BOARD)-drc.txt gen/$(BOARD)-erc.txt
pcb: $(BOARD)_pcb.zip
doc: gen/$(BOARD).pdf gen/$(BOARD)-front.svg gen/$(BOARD)-back.svg
fab: test gen/$(BOARD)_fab.zip gen/$(BOARD).csv gen/$(BOARD)-top-pos.csv
$(BOARD)_pcb.zip: fab doc
@mkdir -p gen @mkdir -p gen
@cd gen; zip -r ../pcb.zip fab.zip fiatlux.csv fiatlux-top-pos.csv fiatlux-front.svg fiatlux-back.svg fiatlux.pdf cd gen; zip -r ../$(BOARD)_pcb.zip $(BOARD)_fab.zip $(BOARD).csv $(BOARD)-top-pos.csv $(BOARD)-front.svg $(BOARD)-back.svg $(BOARD).pdf
@cd gen; zip -r ../debug.zip . cd gen; zip -r ../$(BOARD)_debug.zip .
test: gen/fiatlux-drc.txt gen/fiatlux-erc.txt gen/$(BOARD)_fab.zip: gen/fab/$(BOARD)-F_Cu.gbr gen/fab/$(BOARD)-B_Cu.gbr gen/fab/$(BOARD)-F_Mask.gbr gen/fab/$(BOARD)-B_Mask.gbr
gen/$(BOARD)_fab.zip: gen/fab/$(BOARD)-F_Paste.gbr gen/fab/$(BOARD)-B_Paste.gbr gen/fab/$(BOARD)-F_SilkS.gbr gen/fab/$(BOARD)-B_SilkS.gbr
doc: gen/fiatlux.pdf gen/fiatlux-front.svg gen/fiatlux-back.svg
fab: test gen/fab.zip gen/fiatlux.csv gen/fiatlux-top-pos.csv
gen/fab.zip: gen/fab/fiatlux-F_Cu.gbr gen/fab/fiatlux-B_Cu.gbr gen/fab/fiatlux-F_Mask.gbr gen/fab/fiatlux-B_Mask.gbr
gen/fab.zip: gen/fab/fiatlux-F_Paste.gbr gen/fab/fiatlux-B_Paste.gbr gen/fab/fiatlux-F_SilkS.gbr gen/fab/fiatlux-B_SilkS.gbr
@mkdir -p gen/fab @mkdir -p gen/fab
@cd gen/fab; zip -r ../fab.zip *.gbr cd gen/fab; zip -r ../$(BOARD)_fab.zip *.gbr
gen/fiatlux-erc.txt: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb gen/$(BOARD)-erc.txt: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
@mkdir -p gen @mkdir -p gen
kibot -d gen -c fiatlux.kiplot.yaml -s update_xml,run_drc -i kibot -d gen -c $(BOARD).kiplot.yaml -s update_xml,run_drc -i
gen/fiatlux-drc.txt: fiatlux.kiplot.yaml fiatlux.pro fiatlux.sch gen/$(BOARD)-drc.txt: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_sch
@mkdir -p gen @mkdir -p gen
kibot -d gen -c fiatlux.kiplot.yaml -s update_xml,run_erc -i kibot -d gen -c $(BOARD).kiplot.yaml -s update_xml,run_erc -i
gen/fab/%.gbr: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb gen/fab/%.gbr: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
@mkdir -p gen @mkdir -p gen
kibot -d gen -c fiatlux.kiplot.yaml -s all print_front gerbers kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front gerbers
gen/fiatlux-top-pos.csv: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb gen/$(BOARD)-top-pos.csv: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
@mkdir -p gen @mkdir -p gen
kibot -d gen -c fiatlux.kiplot.yaml -s all print_front position kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front position
gen/fiatlux.csv: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb gen/$(BOARD).csv: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
@mkdir -p gen @mkdir -p gen
kibot -d gen -c fiatlux.kiplot.yaml -s all print_front bom kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front bom
gen/fiatlux.pdf: fiatlux.kiplot.yaml fiatlux.pro fiatlux.sch gen/$(BOARD).pdf: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_sch
@mkdir -p gen @mkdir -p gen
kibot -d gen -c fiatlux.kiplot.yaml -s run_drc,run_erc print_sch kibot -d gen -c $(BOARD).kiplot.yaml -s run_drc,run_erc print_sch
gen/fiatlux-front.svg: fiatlux.kicad_pcb gen/$(BOARD)-front.svg: $(BOARD).kicad_pcb
@mkdir -p gen @mkdir -p gen
pcbdraw --libs default $< $@ pcbdraw --libs default $< $@
gen/fiatlux-back.svg: fiatlux.kicad_pcb gen/$(BOARD)-back.svg: $(BOARD).kicad_pcb
@mkdir -p gen @mkdir -p gen
pcbdraw --libs default --back $< $@ pcbdraw --libs default --back $< $@

525
pcb/bus_node.kicad_sch Normal file
View file

@ -0,0 +1,525 @@
(kicad_sch (version 20211123) (generator eeschema)
(uuid 0a742bb2-0657-47bc-9dea-e70308e1113a)
(paper "A4")
(lib_symbols
(symbol "Device:C_Polarized" (pin_numbers hide) (pin_names (offset 0.254)) (in_bom yes) (on_board yes)
(property "Reference" "C" (id 0) (at 0.635 2.54 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Value" "C_Polarized" (id 1) (at 0.635 -2.54 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Footprint" "" (id 2) (at 0.9652 -3.81 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "ki_keywords" "cap capacitor" (id 4) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "ki_description" "Polarized capacitor" (id 5) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "ki_fp_filters" "CP_*" (id 6) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(symbol "C_Polarized_0_1"
(rectangle (start -2.286 0.508) (end 2.286 1.016)
(stroke (width 0) (type default) (color 0 0 0 0))
(fill (type none))
)
(polyline
(pts
(xy -1.778 2.286)
(xy -0.762 2.286)
)
(stroke (width 0) (type default) (color 0 0 0 0))
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)
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(pts
(xy -1.27 2.794)
(xy -1.27 1.778)
)
(stroke (width 0) (type default) (color 0 0 0 0))
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(rectangle (start 2.286 -0.508) (end -2.286 -1.016)
(stroke (width 0) (type default) (color 0 0 0 0))
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(symbol "C_Polarized_1_1"
(pin passive line (at 0 3.81 270) (length 2.794)
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)
(symbol "MCU_ST_STM8:STM8S003F3U" (in_bom yes) (on_board yes)
(property "Reference" "U" (id 0) (at 1.27 25.4 0)
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)
(property "Value" "STM8S003F3U" (id 1) (at 1.27 22.86 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Footprint" "Package_DFN_QFN:ST_UFQFPN-20_3x3mm_P0.5mm" (id 2) (at 1.27 27.94 0)
(effects (font (size 1.27 1.27)) (justify left) hide)
)
(property "Datasheet" "http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00024550.pdf" (id 3) (at -1.27 -10.16 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "ki_keywords" "STM8S Mainstream Value line 8-bit, 16MHz, 1k RAM, 128 EEPROM" (id 4) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
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(property "ki_description" "16MHz, 8K Flash, 1K RAM, 128 EEPROM, USART, I²C, SPI, UFQFPN-20" (id 5) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "ki_fp_filters" "ST?UFQFPN*3x3mm*P0.5mm*" (id 6) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(symbol "STM8S003F3U_0_1"
(rectangle (start -11.43 21.59) (end 11.43 -21.59)
(stroke (width 0.254) (type default) (color 0 0 0 0))
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)
)
(symbol "STM8S003F3U_1_1"
(pin input line (at -15.24 -15.24 0) (length 3.81)
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41486
pcb/fiatlux.kicad_pcb
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449
pcb/fiatlux.kicad_pro Normal file
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@ -0,0 +1,449 @@
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"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rule_severitieslegacy_courtyards_overlap": true,
"rule_severitieslegacy_no_courtyard_defined": false,
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.01,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_paste_clearance": 0.0,
"solder_paste_margin_ratio": -0.0,
"use_height_for_length_calcs": true
},
"track_widths": [
0.25,
0.25,
0.5,
1.0,
2.0
],
"via_dimensions": [
{
"diameter": 0.8,
"drill": 0.4
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
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],
[
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2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "fiatlux.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "fiatlux.net",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.25,
"pin_symbol_size": 0.0,
"text_offset_ratio": 0.08
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "Pcbnew",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"814763c2-92e5-4a2c-941c-9bbd073f6e87",
""
],
[
"00000000-0000-0000-0000-00006078273a",
"Power"
],
[
"704d02d9-6cb6-48ad-b961-61eafd0de7c6",
"Ext-IO"
]
],
"text_variables": {}
}

3816
pcb/fiatlux.kicad_sch Normal file
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17
pcb/fiatlux.kiplot.yaml
View file

@ -8,6 +8,23 @@ preflight:
run_drc: true run_drc: true
check_zone_fills: false check_zone_fills: false
ignore_unconnected: false ignore_unconnected: false
filters:
- error: 'courtyards_overlap'
regex: '((?s)J4(.*)J13)|((?s)J13(.*)J21)|((?s)J2(.*)J15)|((?s)J2(.*)J4)'
- error: 'courtyards_overlap'
regex: '(?s)J3(.*)J12'
- error: 'clearance'
regex: '(.*)no net(.*) of J1'
global:
filters:
- error: 'courtyards_overlap'
regex: '((?s)J4(.*)J13)|((?s)J13(.*)J21)|((?s)J2(.*)J15)|((?s)J2(.*)J4)'
- error: 'courtyards_overlap'
regex: '(?s)J3(.*)J12'
- error: 'clearance'
regex: '(.*)no net(.*) of J1'
- error: 'silk_overlap'
# global: # global:
# kiauto_wait_start: 60 # kiauto_wait_start: 60

252
pcb/fiatlux.pro
View file

@ -1,252 +0,0 @@
update=Mo 12 Jul 2021 16:48:53 CEST
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=fiatlux.net
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.25
TrackWidth3=0.5
TrackWidth4=1
TrackWidth5=2
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.09999999999999999
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.127
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

1340
pcb/fiatlux.sch
View file

File diff suppressed because it is too large Load diff

1693
pcb/onboard_bus_node.kicad_sch Normal file
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1708
pcb/power.kicad_sch Normal file
View file

File diff suppressed because it is too large Load diff

643
pcb/power.sch
View file

@ -1,643 +0,0 @@
EESchema Schematic File Version 4
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U 1 1 607C2A7C
P 7100 4450
F 0 "#PWR0136" H 7100 4200 50 0001 C CNN
F 1 "GND" H 7105 4277 50 0000 C CNN
F 2 "" H 7100 4450 50 0001 C CNN
F 3 "" H 7100 4450 50 0001 C CNN
1 7100 4450
1 0 0 -1
$EndComp
Wire Wire Line
7100 4450 7100 4350
Wire Wire Line
7900 4250 7900 4350
Wire Wire Line
7900 4350 7100 4350
Connection ~ 7100 4350
Wire Wire Line
7100 4350 7100 4250
Wire Wire Line
7900 3950 7900 3850
Wire Wire Line
7900 3850 7100 3850
Wire Wire Line
7100 3850 7100 3750
Wire Wire Line
7100 3950 7100 3850
Connection ~ 7100 3850
$Comp
L Device:D_Schottky D?
U 1 1 607C7255
P 4450 2150
AR Path="/607C7255" Ref="D?" Part="1"
AR Path="/6078273A/607C7255" Ref="D6" Part="1"
F 0 "D6" H 4450 1933 50 0000 C CNN
F 1 "SS14" H 4450 2024 50 0000 C CNN
F 2 "Diode_SMD:D_SMA" H 4450 2025 50 0001 C CNN
F 3 "~" H 4450 2150 50 0001 C CNN
F 4 "C2480" H 4450 2150 50 0001 C CNN "LCSC"
1 4450 2150
0 -1 -1 0
$EndComp
Wire Wire Line
5650 2750 5650 3050
Wire Wire Line
5050 2850 5050 3050
Wire Wire Line
5050 2300 5050 2450
Connection ~ 5050 2450
Wire Wire Line
4450 2300 4450 2450
Wire Wire Line
4450 2450 5050 2450
$Comp
L power:+12V #PWR0132
U 1 1 608DD823
P 4450 1850
F 0 "#PWR0132" H 4450 1700 50 0001 C CNN
F 1 "+12V" H 4465 2023 50 0000 C CNN
F 2 "" H 4450 1850 50 0001 C CNN
F 3 "" H 4450 1850 50 0001 C CNN
1 4450 1850
1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR0133
U 1 1 608DE102
P 5050 1850
F 0 "#PWR0133" H 5050 1700 50 0001 C CNN
F 1 "+5V" H 5065 2023 50 0000 C CNN
F 2 "" H 5050 1850 50 0001 C CNN
F 3 "" H 5050 1850 50 0001 C CNN
1 5050 1850
1 0 0 -1
$EndComp
Wire Wire Line
4450 1850 4450 2000
Wire Wire Line
5050 1850 5050 2000
$Comp
L power:+5V #PWR0137
U 1 1 608E064A
P 7100 3750
F 0 "#PWR0137" H 7100 3600 50 0001 C CNN
F 1 "+5V" H 7115 3923 50 0000 C CNN
F 2 "" H 7100 3750 50 0001 C CNN
F 3 "" H 7100 3750 50 0001 C CNN
1 7100 3750
1 0 0 -1
$EndComp
$Comp
L Device:D_Zener D7
U 1 1 608E2DA3
P 8700 2700
F 0 "D7" V 8654 2780 50 0000 L CNN
F 1 "Z 5V" V 8745 2780 50 0000 L CNN
F 2 "Diode_SMD:D_MiniMELF" H 8700 2700 50 0001 C CNN
F 3 "~" H 8700 2700 50 0001 C CNN
1 8700 2700
0 1 1 0
$EndComp
$Comp
L Device:D_Zener D8
U 1 1 608E7242
P 9450 2700
F 0 "D8" V 9404 2780 50 0000 L CNN
F 1 "Z 12V" V 9495 2780 50 0000 L CNN
F 2 "Diode_SMD:D_MiniMELF" H 9450 2700 50 0001 C CNN
F 3 "~" H 9450 2700 50 0001 C CNN
1 9450 2700
0 1 1 0
$EndComp
$Comp
L power:+5V #PWR0138
U 1 1 608EA16E
P 8700 2400
F 0 "#PWR0138" H 8700 2250 50 0001 C CNN
F 1 "+5V" H 8715 2573 50 0000 C CNN
F 2 "" H 8700 2400 50 0001 C CNN
F 3 "" H 8700 2400 50 0001 C CNN
1 8700 2400
1 0 0 -1
$EndComp
$Comp
L power:+12V #PWR0139
U 1 1 608EB6FB
P 9450 2400
F 0 "#PWR0139" H 9450 2250 50 0001 C CNN
F 1 "+12V" H 9465 2573 50 0000 C CNN
F 2 "" H 9450 2400 50 0001 C CNN
F 3 "" H 9450 2400 50 0001 C CNN
1 9450 2400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0142
U 1 1 608EC96E
P 8700 3050
F 0 "#PWR0142" H 8700 2800 50 0001 C CNN
F 1 "GND" H 8705 2877 50 0000 C CNN
F 2 "" H 8700 3050 50 0001 C CNN
F 3 "" H 8700 3050 50 0001 C CNN
1 8700 3050
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0143
U 1 1 608ED499
P 9450 3050
F 0 "#PWR0143" H 9450 2800 50 0001 C CNN
F 1 "GND" H 9455 2877 50 0000 C CNN
F 2 "" H 9450 3050 50 0001 C CNN
F 3 "" H 9450 3050 50 0001 C CNN
1 9450 3050
1 0 0 -1
$EndComp
Wire Wire Line
8700 2850 8700 3050
Wire Wire Line
9450 2850 9450 3050
Wire Wire Line
8700 2400 8700 2550
Wire Wire Line
9450 2400 9450 2550
Text Label 4750 2450 0 50 ~ 0
LDO_IN
$Comp
L Connector:Conn_01x01_Female J?
U 1 1 6094781B
P 2700 2200
AR Path="/6094781B" Ref="J?" Part="1"
AR Path="/6078273A/6094781B" Ref="J9" Part="1"
F 0 "J9" H 2728 2226 50 0000 L CNN
F 1 "Testpoint_3V3" H 2728 2135 50 0000 L CNN
F 2 "TestPoint:TestPoint_Pad_D2.0mm" H 2700 2200 50 0001 C CNN
F 3 "~" H 2700 2200 50 0001 C CNN
1 2700 2200
1 0 0 -1
$EndComp
$Comp
L power:+3.3V #PWR?
U 1 1 60947821
P 2500 2200
AR Path="/60947821" Ref="#PWR?" Part="1"
AR Path="/6078273A/60947821" Ref="#PWR0144" Part="1"
F 0 "#PWR0144" H 2500 2050 50 0001 C CNN
F 1 "+3.3V" H 2515 2373 50 0000 C CNN
F 2 "" H 2500 2200 50 0001 C CNN
F 3 "" H 2500 2200 50 0001 C CNN
1 2500 2200
0 -1 -1 0
$EndComp
$Comp
L Connector:Conn_01x01_Female J?
U 1 1 60947827
P 2700 2450
AR Path="/60947827" Ref="J?" Part="1"
AR Path="/6078273A/60947827" Ref="J10" Part="1"
F 0 "J10" H 2728 2476 50 0000 L CNN
F 1 "Testpoint_GND" H 2728 2385 50 0000 L CNN
F 2 "TestPoint:TestPoint_Pad_D2.0mm" H 2700 2450 50 0001 C CNN
F 3 "~" H 2700 2450 50 0001 C CNN
1 2700 2450
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6094782D
P 2500 2450
AR Path="/6094782D" Ref="#PWR?" Part="1"
AR Path="/6078273A/6094782D" Ref="#PWR0145" Part="1"
F 0 "#PWR0145" H 2500 2200 50 0001 C CNN
F 1 "GND" H 2505 2277 50 0000 C CNN
F 2 "" H 2500 2450 50 0001 C CNN
F 3 "" H 2500 2450 50 0001 C CNN
1 2500 2450
0 1 1 0
$EndComp
$Comp
L Connector:Conn_01x01_Female J?
U 1 1 609480A1
P 3900 2450
AR Path="/609480A1" Ref="J?" Part="1"
AR Path="/6078273A/609480A1" Ref="J11" Part="1"
F 0 "J11" H 3792 2225 50 0000 C CNN
F 1 "Testpoint_LDO_IN" H 3792 2316 50 0000 C CNN
F 2 "TestPoint:TestPoint_Pad_D2.0mm" H 3900 2450 50 0001 C CNN
F 3 "~" H 3900 2450 50 0001 C CNN
1 3900 2450
-1 0 0 1
$EndComp
Wire Wire Line
4100 2450 4450 2450
Connection ~ 4450 2450
$Comp
L Device:C C?
U 1 1 609C4CDD
P 6250 2700
AR Path="/609C4CDD" Ref="C?" Part="1"
AR Path="/6078273A/609C4CDD" Ref="C5" Part="1"
F 0 "C5" H 6365 2746 50 0000 L CNN
F 1 "10uF" H 6365 2655 50 0000 L CNN
F 2 "Capacitor_SMD:C_0805_2012Metric" H 6288 2550 50 0001 C CNN
F 3 "~" H 6250 2700 50 0001 C CNN
F 4 "C15850" H 6250 2700 50 0001 C CNN "LCSC"
1 6250 2700
1 0 0 -1
$EndComp
$Comp
L Device:C C?
U 1 1 609C54A2
P 5050 4100
AR Path="/609C54A2" Ref="C?" Part="1"
AR Path="/6078273A/609C54A2" Ref="C2" Part="1"
F 0 "C2" H 5165 4146 50 0000 L CNN
F 1 "10uF" H 5165 4055 50 0000 L CNN
F 2 "Capacitor_SMD:C_0805_2012Metric" H 5088 3950 50 0001 C CNN
F 3 "~" H 5050 4100 50 0001 C CNN
F 4 "C15850" H 5050 4100 50 0001 C CNN "LCSC"
1 5050 4100
1 0 0 -1
$EndComp
$Comp
L Device:C C?
U 1 1 609C5ABB
P 7100 4100
AR Path="/609C5ABB" Ref="C?" Part="1"
AR Path="/6078273A/609C5ABB" Ref="C7" Part="1"
F 0 "C7" H 7215 4146 50 0000 L CNN
F 1 "10uF" H 7215 4055 50 0000 L CNN
F 2 "Capacitor_SMD:C_0805_2012Metric" H 7138 3950 50 0001 C CNN
F 3 "~" H 7100 4100 50 0001 C CNN
F 4 "C15850" H 7100 4100 50 0001 C CNN "LCSC"
1 7100 4100
1 0 0 -1
$EndComp
Wire Wire Line
2300 4100 2300 4200
Wire Wire Line
2400 4100 2300 4100
$Comp
L power:GND #PWR0105
U 1 1 60929622
P 2300 4200
F 0 "#PWR0105" H 2300 3950 50 0001 C CNN
F 1 "GND" H 2305 4027 50 0000 C CNN
F 2 "" H 2300 4200 50 0001 C CNN
F 3 "" H 2300 4200 50 0001 C CNN
1 2300 4200
1 0 0 -1
$EndComp
$Comp
L Connector:Conn_01x03_Male J5
U 1 1 60929628
P 2600 3650
F 0 "J5" H 2572 3582 50 0000 R CNN
F 1 "Conn_01x03_Male" H 2572 3673 50 0000 R CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Horizontal" H 2600 3650 50 0001 C CNN
F 3 "~" H 2600 3650 50 0001 C CNN
1 2600 3650
-1 0 0 1
$EndComp
$Comp
L Connector:Conn_01x02_Male J12
U 1 1 6092962E
P 2600 4100
F 0 "J12" H 2572 3982 50 0000 R CNN
F 1 "Conn_01x02_Male" H 2572 4073 50 0000 R CNN
F 2 "TerminalBlock:TerminalBlock_bornier-2_P5.08mm" H 2600 4100 50 0001 C CNN
F 3 "~" H 2600 4100 50 0001 C CNN
1 2600 4100
-1 0 0 1
$EndComp
Text GLabel 2400 3650 0 50 Input ~ 0
VOUT
$Comp
L power:+12V #PWR0123
U 1 1 60929635
P 2400 4000
F 0 "#PWR0123" H 2400 3850 50 0001 C CNN
F 1 "+12V" V 2415 4128 50 0000 L CNN
F 2 "" H 2400 4000 50 0001 C CNN
F 3 "" H 2400 4000 50 0001 C CNN
1 2400 4000
0 -1 -1 0
$EndComp
$Comp
L power:+12V #PWR0124
U 1 1 6092963B
P 2400 3550
F 0 "#PWR0124" H 2400 3400 50 0001 C CNN
F 1 "+12V" V 2415 3678 50 0000 L CNN
F 2 "" H 2400 3550 50 0001 C CNN
F 3 "" H 2400 3550 50 0001 C CNN
1 2400 3550
0 -1 -1 0
$EndComp
$Comp
L power:+5V #PWR?
U 1 1 60929641
P 2400 3750
AR Path="/60929641" Ref="#PWR?" Part="1"
AR Path="/6078273A/60929641" Ref="#PWR0125" Part="1"
F 0 "#PWR0125" H 2400 3600 50 0001 C CNN
F 1 "+5V" V 2415 3878 50 0000 L CNN
F 2 "" H 2400 3750 50 0001 C CNN
F 3 "" H 2400 3750 50 0001 C CNN
1 2400 3750
0 -1 -1 0
$EndComp
Wire Wire Line
2250 4750 2250 4850
Wire Wire Line
2350 4750 2250 4750
$Comp
L power:GND #PWR0146
U 1 1 60929649
P 2250 4850
F 0 "#PWR0146" H 2250 4600 50 0001 C CNN
F 1 "GND" H 2255 4677 50 0000 C CNN
F 2 "" H 2250 4850 50 0001 C CNN
F 3 "" H 2250 4850 50 0001 C CNN
1 2250 4850
1 0 0 -1
$EndComp
$Comp
L Connector:Conn_01x02_Male J3
U 1 1 6092964F
P 2550 4750
F 0 "J3" H 2522 4632 50 0000 R CNN
F 1 "Conn_01x02_Male" H 2522 4723 50 0000 R CNN
F 2 "TerminalBlock:TerminalBlock_bornier-2_P5.08mm" H 2550 4750 50 0001 C CNN
F 3 "~" H 2550 4750 50 0001 C CNN
1 2550 4750
-1 0 0 1
$EndComp
$Comp
L power:+5V #PWR?
U 1 1 60929655
P 2350 4650
AR Path="/60929655" Ref="#PWR?" Part="1"
AR Path="/6078273A/60929655" Ref="#PWR0147" Part="1"
F 0 "#PWR0147" H 2350 4500 50 0001 C CNN
F 1 "+5V" V 2365 4778 50 0000 L CNN
F 2 "" H 2350 4650 50 0001 C CNN
F 3 "" H 2350 4650 50 0001 C CNN
1 2350 4650
0 -1 -1 0
$EndComp
$Comp
L power:PWR_FLAG #FLG0101
U 1 1 60A9BE5E
P 1050 3800
F 0 "#FLG0101" H 1050 3875 50 0001 C CNN
F 1 "PWR_FLAG" H 1050 3973 50 0000 C CNN
F 2 "" H 1050 3800 50 0001 C CNN
F 3 "~" H 1050 3800 50 0001 C CNN
1 1050 3800
-1 0 0 1
$EndComp
$Comp
L power:+12V #PWR0149
U 1 1 60A9D3DB
P 1050 3800
F 0 "#PWR0149" H 1050 3650 50 0001 C CNN
F 1 "+12V" V 1065 3928 50 0000 L CNN
F 2 "" H 1050 3800 50 0001 C CNN
F 3 "" H 1050 3800 50 0001 C CNN
1 1050 3800
1 0 0 -1
$EndComp
$EndSCHEMATC

3
webapp/.gitignore vendored
View file

@ -1,3 +0,0 @@
node_modules/
src/gen/
package-lock.json