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stable
...
jedi/dev/c
| Author | SHA1 | Date | |
|---|---|---|---|
| c2f80afaa3 | |||
| d26ea01d92 |
15 changed files with 49449 additions and 6701 deletions
|
|
@ -19,11 +19,11 @@ steps:
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||||||
- make firmware -j$(nproc)
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- make firmware -j$(nproc)
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- name: pcb
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- name: pcb
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image: setsoft/kicad_auto
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image: setsoft/kicad_auto:ki6
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commands:
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commands:
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- apt update
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- apt update
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- apt install -y make zip
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- apt install -y make zip
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- make pcb -j$(nproc)
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- make pcb -j$(nproc) BOARD=fiatlux
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- name: case
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- name: case
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image: debian:sid
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image: debian:sid
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@ -58,10 +58,10 @@ steps:
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files:
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files:
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- firmware/firmware/fiatlux.bin
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- firmware/firmware/fiatlux.bin
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- firmware/otaflash.py
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- firmware/otaflash.py
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- pcb/pcb.zip
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- pcb/fiatlux_pcb.zip
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checksum:
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checksum:
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- sha512
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- sha512
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- md5
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- md5
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title: buildtest
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title: fiatlux
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when:
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when:
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event: tag
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event: tag
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1
pcb/.gitignore
vendored
1
pcb/.gitignore
vendored
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@ -16,6 +16,7 @@ _autosave-*
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*-save.pro
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*-save.pro
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*-save.kicad_pcb
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*-save.kicad_pcb
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fp-info-cache
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fp-info-cache
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*-backups/
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# Netlist files (exported from Eeschema)
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# Netlist files (exported from Eeschema)
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*.net
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*.net
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58
pcb/Makefile
58
pcb/Makefile
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@ -1,52 +1,54 @@
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.NOTPARALLEL: gen/fab/fiatlux-F_Cu.gbr gen/fab/fiatlux-B_Cu.gbr gen/fab/fiatlux-F_Mask.gbr gen/fab/fiatlux-B_Mask.gbr gen/fab/fiatlux-F_Paste.gbr gen/fab/fiatlux-B_Paste.gbr gen/fab/fiatlux-F_SilkS.gbr gen/fab/fiatlux-B_SilkS.gbr
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.NOTPARALLEL: gen/fab/$(BOARD)-F_Cu.gbr gen/fab/$(BOARD)-B_Cu.gbr gen/fab/$(BOARD)-F_Mask.gbr gen/fab/$(BOARD)-B_Mask.gbr gen/fab/$(BOARD)-F_Paste.gbr gen/fab/$(BOARD)-B_Paste.gbr gen/fab/$(BOARD)-F_SilkS.gbr gen/fab/$(BOARD)-B_SilkS.gbr
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all: test fab doc pcb.zip
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all: test fab doc pcb
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pcb.zip: fab doc
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test: gen/$(BOARD)-drc.txt gen/$(BOARD)-erc.txt
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pcb: $(BOARD)_pcb.zip
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doc: gen/$(BOARD).pdf gen/$(BOARD)-front.svg gen/$(BOARD)-back.svg
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fab: test gen/$(BOARD)_fab.zip gen/$(BOARD).csv gen/$(BOARD)-top-pos.csv
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$(BOARD)_pcb.zip: fab doc
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@mkdir -p gen
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@mkdir -p gen
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@cd gen; zip -r ../pcb.zip fab.zip fiatlux.csv fiatlux-top-pos.csv fiatlux-front.svg fiatlux-back.svg fiatlux.pdf
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cd gen; zip -r ../$(BOARD)_pcb.zip $(BOARD)_fab.zip $(BOARD).csv $(BOARD)-top-pos.csv $(BOARD)-front.svg $(BOARD)-back.svg $(BOARD).pdf
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@cd gen; zip -r ../debug.zip .
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cd gen; zip -r ../$(BOARD)_debug.zip .
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test: gen/fiatlux-drc.txt gen/fiatlux-erc.txt
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gen/$(BOARD)_fab.zip: gen/fab/$(BOARD)-F_Cu.gbr gen/fab/$(BOARD)-B_Cu.gbr gen/fab/$(BOARD)-F_Mask.gbr gen/fab/$(BOARD)-B_Mask.gbr
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gen/$(BOARD)_fab.zip: gen/fab/$(BOARD)-F_Paste.gbr gen/fab/$(BOARD)-B_Paste.gbr gen/fab/$(BOARD)-F_SilkS.gbr gen/fab/$(BOARD)-B_SilkS.gbr
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doc: gen/fiatlux.pdf gen/fiatlux-front.svg gen/fiatlux-back.svg
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fab: test gen/fab.zip gen/fiatlux.csv gen/fiatlux-top-pos.csv
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gen/fab.zip: gen/fab/fiatlux-F_Cu.gbr gen/fab/fiatlux-B_Cu.gbr gen/fab/fiatlux-F_Mask.gbr gen/fab/fiatlux-B_Mask.gbr
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gen/fab.zip: gen/fab/fiatlux-F_Paste.gbr gen/fab/fiatlux-B_Paste.gbr gen/fab/fiatlux-F_SilkS.gbr gen/fab/fiatlux-B_SilkS.gbr
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@mkdir -p gen/fab
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@mkdir -p gen/fab
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@cd gen/fab; zip -r ../fab.zip *.gbr
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cd gen/fab; zip -r ../$(BOARD)_fab.zip *.gbr
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gen/fiatlux-erc.txt: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
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gen/$(BOARD)-erc.txt: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
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@mkdir -p gen
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@mkdir -p gen
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kibot -d gen -c fiatlux.kiplot.yaml -s update_xml,run_drc -i
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kibot -d gen -c $(BOARD).kiplot.yaml -s update_xml,run_drc -i
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gen/fiatlux-drc.txt: fiatlux.kiplot.yaml fiatlux.pro fiatlux.sch
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gen/$(BOARD)-drc.txt: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_sch
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@mkdir -p gen
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@mkdir -p gen
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kibot -d gen -c fiatlux.kiplot.yaml -s update_xml,run_erc -i
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kibot -d gen -c $(BOARD).kiplot.yaml -s update_xml,run_erc -i
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gen/fab/%.gbr: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
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gen/fab/%.gbr: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
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@mkdir -p gen
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@mkdir -p gen
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kibot -d gen -c fiatlux.kiplot.yaml -s all print_front gerbers
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kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front gerbers
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gen/fiatlux-top-pos.csv: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
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gen/$(BOARD)-top-pos.csv: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
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@mkdir -p gen
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@mkdir -p gen
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kibot -d gen -c fiatlux.kiplot.yaml -s all print_front position
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kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front position
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gen/fiatlux.csv: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
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gen/$(BOARD).csv: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
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@mkdir -p gen
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@mkdir -p gen
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kibot -d gen -c fiatlux.kiplot.yaml -s all print_front bom
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kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front bom
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gen/fiatlux.pdf: fiatlux.kiplot.yaml fiatlux.pro fiatlux.sch
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gen/$(BOARD).pdf: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_sch
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@mkdir -p gen
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@mkdir -p gen
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kibot -d gen -c fiatlux.kiplot.yaml -s run_drc,run_erc print_sch
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kibot -d gen -c $(BOARD).kiplot.yaml -s run_drc,run_erc print_sch
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gen/fiatlux-front.svg: fiatlux.kicad_pcb
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gen/$(BOARD)-front.svg: $(BOARD).kicad_pcb
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@mkdir -p gen
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@mkdir -p gen
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pcbdraw --libs default $< $@
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pcbdraw --libs default $< $@
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gen/fiatlux-back.svg: fiatlux.kicad_pcb
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gen/$(BOARD)-back.svg: $(BOARD).kicad_pcb
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@mkdir -p gen
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@mkdir -p gen
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pcbdraw --libs default --back $< $@
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pcbdraw --libs default --back $< $@
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525
pcb/bus_node.kicad_sch
Normal file
525
pcb/bus_node.kicad_sch
Normal file
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@ -0,0 +1,525 @@
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(kicad_sch (version 20211123) (generator eeschema)
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||||||
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(uuid 0a742bb2-0657-47bc-9dea-e70308e1113a)
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(paper "A4")
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(lib_symbols
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(symbol "Device:C_Polarized" (pin_numbers hide) (pin_names (offset 0.254)) (in_bom yes) (on_board yes)
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(effects (font (size 1.27 1.27)) hide)
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||||||
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(property "ki_description" "Polarized capacitor" (id 5) (at 0 0 0)
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||||||
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(effects (font (size 1.27 1.27)) hide)
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||||||
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||||||
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(property "ki_fp_filters" "CP_*" (id 6) (at 0 0 0)
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(effects (font (size 1.27 1.27)) hide)
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
(property "LCSC" "C35556" (id 4) (at 102.87 87.63 0)
|
||||||
|
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|
||||||
|
)
|
||||||
|
(pin "1" (uuid 0868def6-5403-4cbf-93a7-6389dbc95ce3))
|
||||||
|
(pin "10" (uuid 79e03ae3-04c1-4136-9d11-edbf8450c5e6))
|
||||||
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|
||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
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|
||||||
|
|
||||||
|
(symbol (lib_id "power:GND") (at 85.09 115.57 0) (unit 1)
|
||||||
|
(in_bom yes) (on_board yes)
|
||||||
|
(uuid a2512eb5-1205-4c98-854b-ff2f58d6be51)
|
||||||
|
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||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
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||||||
|
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||||||
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||||||
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|
||||||
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|
||||||
|
|
||||||
|
(symbol (lib_id "Device:C_Polarized") (at 85.09 111.76 0) (unit 1)
|
||||||
|
(in_bom yes) (on_board yes) (fields_autoplaced)
|
||||||
|
(uuid f0975aab-9018-4c2c-83a3-ecbae5bfb12a)
|
||||||
|
(property "Reference" "C3" (id 0) (at 88.011 109.9625 0)
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
)
|
||||||
|
(property "Footprint" "Capacitor_SMD:CP_Elec_3x5.4" (id 2) (at 86.0552 115.57 0)
|
||||||
|
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|
||||||
|
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|
||||||
|
(property "Datasheet" "~" (id 3) (at 85.09 111.76 0)
|
||||||
|
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|
||||||
|
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|
||||||
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||||||
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|
||||||
|
)
|
||||||
|
)
|
||||||
41435
pcb/fiatlux.kicad_pcb
41435
pcb/fiatlux.kicad_pcb
File diff suppressed because it is too large
Load diff
449
pcb/fiatlux.kicad_pro
Normal file
449
pcb/fiatlux.kicad_pro
Normal file
|
|
@ -0,0 +1,449 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"copper_text_size_v": 1.5,
|
||||||
|
"copper_text_thickness": 0.3,
|
||||||
|
"copper_text_upright": true,
|
||||||
|
"courtyard_line_width": 0.049999999999999996,
|
||||||
|
"dimension_precision": 4,
|
||||||
|
"dimension_units": 3,
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
}
|
||||||
|
},
|
||||||
|
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|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
||||||
|
"width": 0.2
|
||||||
|
}
|
||||||
|
],
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
"track_widths": [
|
||||||
|
0.25,
|
||||||
|
0.25,
|
||||||
|
0.5,
|
||||||
|
1.0,
|
||||||
|
2.0
|
||||||
|
],
|
||||||
|
"via_dimensions": [
|
||||||
|
{
|
||||||
|
"diameter": 0.8,
|
||||||
|
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|
||||||
|
}
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
},
|
||||||
|
"boards": [],
|
||||||
|
"cvpcb": {
|
||||||
|
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|
||||||
|
},
|
||||||
|
"erc": {
|
||||||
|
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|
||||||
|
"meta": {
|
||||||
|
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|
||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
2,
|
||||||
|
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|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
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|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"rule_severities": {
|
||||||
|
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|
||||||
|
"bus_entry_needed": "error",
|
||||||
|
"bus_label_syntax": "error",
|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_reference": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"extra_units": "error",
|
||||||
|
"global_label_dangling": "warning",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"multiple_net_names": "warning",
|
||||||
|
"net_not_bus_member": "warning",
|
||||||
|
"no_connect_connected": "warning",
|
||||||
|
"no_connect_dangling": "warning",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "warning",
|
||||||
|
"power_pin_not_driven": "error",
|
||||||
|
"similar_labels": "warning",
|
||||||
|
"unannotated": "error",
|
||||||
|
"unit_value_mismatch": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "fiatlux.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.25,
|
||||||
|
"via_diameter": 0.8,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 2
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "fiatlux.net",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"annotate_start_num": 0,
|
||||||
|
"drawing": {
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_own_page": false,
|
||||||
|
"intersheets_ref_prefix": "",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "",
|
||||||
|
"junction_size_choice": 3,
|
||||||
|
"label_size_ratio": 0.25,
|
||||||
|
"pin_symbol_size": 0.0,
|
||||||
|
"text_offset_ratio": 0.08
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_format_name": "Pcbnew",
|
||||||
|
"ngspice": {
|
||||||
|
"fix_include_paths": true,
|
||||||
|
"fix_passive_vals": false,
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"model_mode": 0,
|
||||||
|
"workbook_filename": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "",
|
||||||
|
"spice_adjust_passive_values": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"814763c2-92e5-4a2c-941c-9bbd073f6e87",
|
||||||
|
""
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"00000000-0000-0000-0000-00006078273a",
|
||||||
|
"Power"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"704d02d9-6cb6-48ad-b961-61eafd0de7c6",
|
||||||
|
"Ext-IO"
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
||||||
3816
pcb/fiatlux.kicad_sch
Normal file
3816
pcb/fiatlux.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
252
pcb/fiatlux.pro
252
pcb/fiatlux.pro
|
|
@ -1,252 +0,0 @@
|
||||||
update=Mo 12 Jul 2021 16:48:53 CEST
|
|
||||||
version=1
|
|
||||||
last_client=kicad
|
|
||||||
[general]
|
|
||||||
version=1
|
|
||||||
RootSch=
|
|
||||||
BoardNm=
|
|
||||||
[cvpcb]
|
|
||||||
version=1
|
|
||||||
NetIExt=net
|
|
||||||
[eeschema]
|
|
||||||
version=1
|
|
||||||
LibDir=
|
|
||||||
[eeschema/libraries]
|
|
||||||
[schematic_editor]
|
|
||||||
version=1
|
|
||||||
PageLayoutDescrFile=
|
|
||||||
PlotDirectoryName=
|
|
||||||
SubpartIdSeparator=0
|
|
||||||
SubpartFirstId=65
|
|
||||||
NetFmtName=Pcbnew
|
|
||||||
SpiceAjustPassiveValues=0
|
|
||||||
LabSize=50
|
|
||||||
ERC_TestSimilarLabels=1
|
|
||||||
[pcbnew]
|
|
||||||
version=1
|
|
||||||
PageLayoutDescrFile=
|
|
||||||
LastNetListRead=fiatlux.net
|
|
||||||
CopperLayerCount=2
|
|
||||||
BoardThickness=1.6
|
|
||||||
AllowMicroVias=0
|
|
||||||
AllowBlindVias=0
|
|
||||||
RequireCourtyardDefinitions=0
|
|
||||||
ProhibitOverlappingCourtyards=1
|
|
||||||
MinTrackWidth=0.2
|
|
||||||
MinViaDiameter=0.4
|
|
||||||
MinViaDrill=0.3
|
|
||||||
MinMicroViaDiameter=0.2
|
|
||||||
MinMicroViaDrill=0.09999999999999999
|
|
||||||
MinHoleToHole=0.25
|
|
||||||
TrackWidth1=0.25
|
|
||||||
TrackWidth2=0.25
|
|
||||||
TrackWidth3=0.5
|
|
||||||
TrackWidth4=1
|
|
||||||
TrackWidth5=2
|
|
||||||
ViaDiameter1=0.8
|
|
||||||
ViaDrill1=0.4
|
|
||||||
dPairWidth1=0.2
|
|
||||||
dPairGap1=0.25
|
|
||||||
dPairViaGap1=0.25
|
|
||||||
SilkLineWidth=0.15
|
|
||||||
SilkTextSizeV=1
|
|
||||||
SilkTextSizeH=1
|
|
||||||
SilkTextSizeThickness=0.15
|
|
||||||
SilkTextItalic=0
|
|
||||||
SilkTextUpright=1
|
|
||||||
CopperLineWidth=0.2
|
|
||||||
CopperTextSizeV=1.5
|
|
||||||
CopperTextSizeH=1.5
|
|
||||||
CopperTextThickness=0.3
|
|
||||||
CopperTextItalic=0
|
|
||||||
CopperTextUpright=1
|
|
||||||
EdgeCutLineWidth=0.09999999999999999
|
|
||||||
CourtyardLineWidth=0.05
|
|
||||||
OthersLineWidth=0.15
|
|
||||||
OthersTextSizeV=1
|
|
||||||
OthersTextSizeH=1
|
|
||||||
OthersTextSizeThickness=0.15
|
|
||||||
OthersTextItalic=0
|
|
||||||
OthersTextUpright=1
|
|
||||||
SolderMaskClearance=0
|
|
||||||
SolderMaskMinWidth=0
|
|
||||||
SolderPasteClearance=0
|
|
||||||
SolderPasteRatio=-0
|
|
||||||
[pcbnew/Layer.F.Cu]
|
|
||||||
Name=F.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.In1.Cu]
|
|
||||||
Name=In1.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In2.Cu]
|
|
||||||
Name=In2.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In3.Cu]
|
|
||||||
Name=In3.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In4.Cu]
|
|
||||||
Name=In4.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In5.Cu]
|
|
||||||
Name=In5.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In6.Cu]
|
|
||||||
Name=In6.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In7.Cu]
|
|
||||||
Name=In7.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In8.Cu]
|
|
||||||
Name=In8.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In9.Cu]
|
|
||||||
Name=In9.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In10.Cu]
|
|
||||||
Name=In10.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In11.Cu]
|
|
||||||
Name=In11.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In12.Cu]
|
|
||||||
Name=In12.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In13.Cu]
|
|
||||||
Name=In13.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In14.Cu]
|
|
||||||
Name=In14.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In15.Cu]
|
|
||||||
Name=In15.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In16.Cu]
|
|
||||||
Name=In16.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In17.Cu]
|
|
||||||
Name=In17.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In18.Cu]
|
|
||||||
Name=In18.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In19.Cu]
|
|
||||||
Name=In19.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In20.Cu]
|
|
||||||
Name=In20.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In21.Cu]
|
|
||||||
Name=In21.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In22.Cu]
|
|
||||||
Name=In22.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In23.Cu]
|
|
||||||
Name=In23.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In24.Cu]
|
|
||||||
Name=In24.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In25.Cu]
|
|
||||||
Name=In25.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In26.Cu]
|
|
||||||
Name=In26.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In27.Cu]
|
|
||||||
Name=In27.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In28.Cu]
|
|
||||||
Name=In28.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In29.Cu]
|
|
||||||
Name=In29.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.In30.Cu]
|
|
||||||
Name=In30.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Layer.B.Cu]
|
|
||||||
Name=B.Cu
|
|
||||||
Type=0
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.B.Adhes]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.F.Adhes]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.B.Paste]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.F.Paste]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.B.SilkS]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.F.SilkS]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.B.Mask]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.F.Mask]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.Dwgs.User]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.Cmts.User]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.Eco1.User]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.Eco2.User]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.Edge.Cuts]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.Margin]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.B.CrtYd]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.F.CrtYd]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.B.Fab]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.F.Fab]
|
|
||||||
Enabled=1
|
|
||||||
[pcbnew/Layer.Rescue]
|
|
||||||
Enabled=0
|
|
||||||
[pcbnew/Netclasses]
|
|
||||||
[pcbnew/Netclasses/Default]
|
|
||||||
Name=Default
|
|
||||||
Clearance=0.127
|
|
||||||
TrackWidth=0.25
|
|
||||||
ViaDiameter=0.8
|
|
||||||
ViaDrill=0.4
|
|
||||||
uViaDiameter=0.3
|
|
||||||
uViaDrill=0.1
|
|
||||||
dPairWidth=0.2
|
|
||||||
dPairGap=0.25
|
|
||||||
dPairViaGap=0.25
|
|
||||||
1340
pcb/fiatlux.sch
1340
pcb/fiatlux.sch
File diff suppressed because it is too large
Load diff
1920
pcb/fiatlux_cv24.kicad_pcb
Normal file
1920
pcb/fiatlux_cv24.kicad_pcb
Normal file
File diff suppressed because it is too large
Load diff
488
pcb/fiatlux_cv24.kicad_pro
Normal file
488
pcb/fiatlux_cv24.kicad_pro
Normal file
|
|
@ -0,0 +1,488 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"board_outline_line_width": 0.09999999999999999,
|
||||||
|
"copper_line_width": 0.19999999999999998,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 1.5,
|
||||||
|
"copper_text_size_v": 1.5,
|
||||||
|
"copper_text_thickness": 0.3,
|
||||||
|
"copper_text_upright": false,
|
||||||
|
"courtyard_line_width": 0.049999999999999996,
|
||||||
|
"dimension_precision": 4,
|
||||||
|
"dimension_units": 3,
|
||||||
|
"dimensions": {
|
||||||
|
"arrow_length": 1270000,
|
||||||
|
"extension_offset": 500000,
|
||||||
|
"keep_text_aligned": true,
|
||||||
|
"suppress_zeroes": false,
|
||||||
|
"text_position": 0,
|
||||||
|
"units_format": 1
|
||||||
|
},
|
||||||
|
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|
||||||
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|
||||||
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|
||||||
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|
||||||
|
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|
||||||
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|
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|
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|
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|
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|
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|
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
}
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"tracks_crossing": "error",
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
4.0
|
||||||
|
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|
||||||
|
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|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
||||||
|
}
|
||||||
|
],
|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
"layer_presets": []
|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
"equivalence_files": []
|
||||||
|
},
|
||||||
|
"erc": {
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
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||||||
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|
||||||
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|
||||||
|
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|
||||||
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|
||||||
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|
||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
|
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|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
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|
||||||
|
0,
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
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|
||||||
|
[
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
]
|
||||||
|
],
|
||||||
|
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|
||||||
|
"bus_definition_conflict": "error",
|
||||||
|
"bus_entry_needed": "error",
|
||||||
|
"bus_label_syntax": "error",
|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_reference": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"extra_units": "error",
|
||||||
|
"global_label_dangling": "warning",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"multiple_net_names": "warning",
|
||||||
|
"net_not_bus_member": "warning",
|
||||||
|
"no_connect_connected": "warning",
|
||||||
|
"no_connect_dangling": "warning",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "warning",
|
||||||
|
"power_pin_not_driven": "error",
|
||||||
|
"similar_labels": "warning",
|
||||||
|
"unannotated": "error",
|
||||||
|
"unit_value_mismatch": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "fiatlux_cv24.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.25,
|
||||||
|
"via_diameter": 0.8,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.127,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Signal-Min",
|
||||||
|
"nets": [
|
||||||
|
"AIN3",
|
||||||
|
"AIN5",
|
||||||
|
"AIN6",
|
||||||
|
"BTN1",
|
||||||
|
"BTN2",
|
||||||
|
"BTN3",
|
||||||
|
"INIT_{IN}",
|
||||||
|
"INIT_{OUT}",
|
||||||
|
"MISO",
|
||||||
|
"MOSI",
|
||||||
|
"SCLK",
|
||||||
|
"SWIM",
|
||||||
|
"~{BUSRST}",
|
||||||
|
"~{INT}"
|
||||||
|
],
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.2,
|
||||||
|
"via_diameter": 0.4,
|
||||||
|
"via_drill": 0.2,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 2
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "fiatlux_cv24.net",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"annotate_start_num": 0,
|
||||||
|
"drawing": {
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_own_page": false,
|
||||||
|
"intersheets_ref_prefix": "",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "",
|
||||||
|
"junction_size_choice": 3,
|
||||||
|
"label_size_ratio": 0.25,
|
||||||
|
"pin_symbol_size": 0.0,
|
||||||
|
"text_offset_ratio": 0.08
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_format_name": "Pcbnew",
|
||||||
|
"ngspice": {
|
||||||
|
"fix_include_paths": true,
|
||||||
|
"fix_passive_vals": false,
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"model_mode": 0,
|
||||||
|
"workbook_filename": ""
|
||||||
|
},
|
||||||
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1865
pcb/fiatlux_cv24.kicad_sch
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1865
pcb/fiatlux_cv24.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
546
pcb/fiatlux_cv24_channel_driver.kicad_sch
Normal file
546
pcb/fiatlux_cv24_channel_driver.kicad_sch
Normal file
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|
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|
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(symbol (lib_id "power:GND") (at 111.76 91.44 0)
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(in_bom yes) (on_board yes) (fields_autoplaced)
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|
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|
||||||
|
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|
||||||
1693
pcb/onboard_bus_node.kicad_sch
Normal file
1693
pcb/onboard_bus_node.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
1708
pcb/power.kicad_sch
Normal file
1708
pcb/power.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue