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57 changed files with 49795 additions and 3 deletions
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/**
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******************************************************************************
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* @file stm32f0xx_ll_bus.h
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* @author MCD Application Team
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* @brief Header file of BUS LL module.
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@verbatim
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##### RCC Limitations #####
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==============================================================================
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[..]
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A delay between an RCC peripheral clock enable and the effective peripheral
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enabling should be taken into account in order to manage the peripheral read/write
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from/to registers.
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(+) This delay depends on the peripheral mapping.
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(++) AHB & APB peripherals, 1 dummy read is necessary
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[..]
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Workarounds:
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(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
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inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F0xx_LL_BUS_H
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#define __STM32F0xx_LL_BUS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f0xx.h"
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/** @addtogroup STM32F0xx_LL_Driver
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* @{
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*/
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#if defined(RCC)
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/** @defgroup BUS_LL BUS
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
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* @{
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*/
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/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
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* @{
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*/
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#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
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#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
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#if defined(DMA2)
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#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
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#endif /*DMA2*/
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#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
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#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
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#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
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#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
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#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
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#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
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#if defined(GPIOD)
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#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
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#endif /*GPIOD*/
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#if defined(GPIOE)
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#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
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#endif /*GPIOE*/
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#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
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#if defined(TSC)
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#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
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#endif /*TSC*/
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
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* @{
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*/
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#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
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#if defined(TIM2)
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#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
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#endif /*TIM2*/
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#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
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#if defined(TIM6)
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#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
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#endif /*TIM6*/
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#if defined(TIM7)
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#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
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#endif /*TIM7*/
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#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
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#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
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#if defined(SPI2)
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#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
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#endif /*SPI2*/
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#if defined(USART2)
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#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
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#endif /* USART2 */
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#if defined(USART3)
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#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
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#endif /* USART3 */
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#if defined(USART4)
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#define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN
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#endif /* USART4 */
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#if defined(USART5)
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#define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN
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#endif /* USART5 */
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#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
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#if defined(I2C2)
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#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
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#endif /*I2C2*/
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#if defined(USB)
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#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
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#endif /* USB */
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#if defined(CAN)
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#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
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#endif /*CAN*/
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#if defined(CRS)
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#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN
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#endif /*CRS*/
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#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
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#if defined(DAC)
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#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
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#endif /*DAC*/
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#if defined(CEC)
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#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
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#endif /*CEC*/
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
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* @{
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*/
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#define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU
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#define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
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#define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
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#if defined(USART8)
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#define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN
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#endif /*USART8*/
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#if defined(USART7)
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#define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN
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#endif /*USART7*/
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#if defined(USART6)
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#define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN
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#endif /*USART6*/
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#define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
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#define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
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#define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN
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#if defined(TIM15)
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#define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
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#endif /*TIM15*/
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#define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
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#define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
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#define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
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* @{
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*/
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/** @defgroup BUS_LL_EF_AHB1 AHB1
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* @{
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*/
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/**
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* @brief Enable AHB1 peripherals clock.
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* @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
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* AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
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* AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n
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* AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
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* AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
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* AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
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* AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
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* AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
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* AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
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* AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
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* AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
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* AHBENR TSCEN LL_AHB1_GRP1_EnableClock
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
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* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
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* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
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*
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* (*) value not defined in all devices.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
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{
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__IO uint32_t tmpreg;
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SET_BIT(RCC->AHBENR, Periphs);
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->AHBENR, Periphs);
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(void)tmpreg;
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}
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/**
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* @brief Check if AHB1 peripheral clock is enabled or not
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* @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
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* AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
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* AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n
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* AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
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* AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
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* AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
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* AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
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* AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
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* AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
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* AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
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* AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
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* AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
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* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
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* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
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*
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* (*) value not defined in all devices.
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* @retval State of Periphs (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
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{
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return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
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}
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/**
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* @brief Disable AHB1 peripherals clock.
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* @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
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* AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
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* AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n
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* AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
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* AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
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* AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
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* AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
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* AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
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* AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
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* AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
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* AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
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* AHBENR TSCEN LL_AHB1_GRP1_DisableClock
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
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* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
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* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
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*
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* (*) value not defined in all devices.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
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{
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CLEAR_BIT(RCC->AHBENR, Periphs);
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}
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/**
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* @brief Force AHB1 peripherals reset.
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* @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
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* AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
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* AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
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* AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
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* AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
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* AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
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* AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
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* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
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*
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* (*) value not defined in all devices.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
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{
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SET_BIT(RCC->AHBRSTR, Periphs);
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}
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/**
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* @brief Release AHB1 peripherals reset.
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* @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
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* AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
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* AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
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* AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
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* AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
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* AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
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* AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
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* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
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*
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* (*) value not defined in all devices.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
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{
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CLEAR_BIT(RCC->AHBRSTR, Periphs);
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}
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1
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* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable APB1 peripherals clock (available in register 1).
|
||||
* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR CANEN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR CECEN LL_APB1_GRP1_EnableClock
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
|
||||
{
|
||||
__IO uint32_t tmpreg;
|
||||
SET_BIT(RCC->APB1ENR, Periphs);
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
|
||||
(void)tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if APB1 peripheral clock is enabled or not (available in register 1).
|
||||
* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval State of Periphs (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
|
||||
{
|
||||
return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable APB1 peripherals clock (available in register 1).
|
||||
* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR CANEN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR CECEN LL_APB1_GRP1_DisableClock
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
|
||||
{
|
||||
CLEAR_BIT(RCC->APB1ENR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Force APB1 peripherals reset (available in register 1).
|
||||
* @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR CECRST LL_APB1_GRP1_ForceReset
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
|
||||
{
|
||||
SET_BIT(RCC->APB1RSTR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Release APB1 peripherals reset (available in register 1).
|
||||
* @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
|
||||
{
|
||||
CLEAR_BIT(RCC->APB1RSTR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable APB1 peripherals clock (available in register 2).
|
||||
* @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR ADC1EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR USART8EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR USART7EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR USART6EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR TIM1EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR SPI1EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR USART1EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR TIM15EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR TIM16EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR TIM17EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR DBGMCUEN LL_APB1_GRP2_EnableClock
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
|
||||
{
|
||||
__IO uint32_t tmpreg;
|
||||
SET_BIT(RCC->APB2ENR, Periphs);
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
|
||||
(void)tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if APB1 peripheral clock is enabled or not (available in register 2).
|
||||
* @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR ADC1EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR USART8EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR USART7EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR USART6EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR TIM1EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR SPI1EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR USART1EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR TIM15EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR TIM16EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR TIM17EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR DBGMCUEN LL_APB1_GRP2_IsEnabledClock
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval State of Periphs (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
|
||||
{
|
||||
return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable APB1 peripherals clock (available in register 2).
|
||||
* @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR ADC1EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR USART8EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR USART7EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR USART6EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR TIM1EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR SPI1EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR USART1EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR TIM15EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR TIM16EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR TIM17EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR DBGMCUEN LL_APB1_GRP2_DisableClock
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
|
||||
{
|
||||
CLEAR_BIT(RCC->APB2ENR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Force APB1 peripherals reset (available in register 2).
|
||||
* @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR ADC1RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR USART8RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR USART7RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR USART6RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR TIM1RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR SPI1RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR USART1RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR TIM15RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR TIM16RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR TIM17RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR DBGMCURST LL_APB1_GRP2_ForceReset
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_ALL
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
|
||||
{
|
||||
SET_BIT(RCC->APB2RSTR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Release APB1 peripherals reset (available in register 2).
|
||||
* @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR ADC1RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR USART8RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR USART7RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR USART6RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR TIM1RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR SPI1RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR USART1RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR TIM15RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR TIM16RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR TIM17RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR DBGMCURST LL_APB1_GRP2_ReleaseReset
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_ALL
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
|
||||
{
|
||||
CLEAR_BIT(RCC->APB2RSTR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(RCC) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_LL_BUS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CORTEX LL module.
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The LL CORTEX driver contains a set of generic APIs that can be
|
||||
used by user:
|
||||
(+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
|
||||
functions
|
||||
(+) Low power mode configuration (SCB register of Cortex-MCU)
|
||||
(+) API to access to MCU info (CPUID register)
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_LL_CORTEX_H
|
||||
#define __STM32F0xx_LL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL CORTEX
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
|
||||
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function checks if the Systick counter flag is active or not.
|
||||
* @note It can be used in timeout function on application side.
|
||||
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
|
||||
{
|
||||
return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source
|
||||
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
|
||||
* @param Source This parameter can be one of the following values:
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
|
||||
{
|
||||
if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
|
||||
{
|
||||
SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the SysTick clock source
|
||||
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
|
||||
{
|
||||
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable SysTick exception request
|
||||
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
|
||||
{
|
||||
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SysTick exception request
|
||||
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
|
||||
{
|
||||
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if the SYSTICK interrupt is enabled or disabled.
|
||||
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
|
||||
{
|
||||
return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Processor uses sleep as its low power mode
|
||||
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableSleep(void)
|
||||
{
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Processor uses deep sleep as its low power mode
|
||||
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
|
||||
{
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
|
||||
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
|
||||
* empty main application.
|
||||
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
|
||||
{
|
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Do not sleep when returning to Thread mode.
|
||||
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
|
||||
{
|
||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
|
||||
* processor.
|
||||
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
|
||||
{
|
||||
/* Set SEVEONPEND bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
|
||||
* excluded
|
||||
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
|
||||
{
|
||||
/* Clear SEVEONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Implementer code
|
||||
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
|
||||
* @retval Value should be equal to 0x41 for ARM
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Variant number (The r value in the rnpn product revision identifier)
|
||||
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
|
||||
* @retval Value between 0 and 255 (0x0: revision 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Architecture number
|
||||
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
|
||||
* @retval Value should be equal to 0xC for Cortex-M0 devices
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Part number
|
||||
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
|
||||
* @retval Value should be equal to 0xC20 for Cortex-M0
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
|
||||
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
|
||||
* @retval Value between 0 and 255 (0x1: patch 1)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_LL_CORTEX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,783 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_crs.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRS LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_LL_CRS_H
|
||||
#define __STM32F0xx_LL_CRS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(CRS)
|
||||
|
||||
/** @defgroup CRS_LL CRS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
|
||||
* @brief Flags defines which can be used with LL_CRS_ReadReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
|
||||
#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
|
||||
#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
|
||||
#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
|
||||
#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
|
||||
#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
|
||||
#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_IT IT Defines
|
||||
* @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
|
||||
#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
|
||||
#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
|
||||
#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
|
||||
#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
|
||||
#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
|
||||
#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
|
||||
#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
|
||||
#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
|
||||
#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
|
||||
#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */
|
||||
#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
|
||||
#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
|
||||
#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
|
||||
#define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Reset value of the RELOAD field
|
||||
* @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
|
||||
* and a synchronization signal frequency of 1 kHz (SOF signal from USB)
|
||||
*/
|
||||
#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
|
||||
|
||||
/**
|
||||
* @brief Reset value of Frequency error limit.
|
||||
*/
|
||||
#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
|
||||
|
||||
/**
|
||||
* @brief Reset value of the HSI48 Calibration field
|
||||
* @note The default value is 32, which corresponds to the middle of the trimming interval.
|
||||
* The trimming step is around 67 kHz between two consecutive TRIM steps.
|
||||
* A higher TRIM value corresponds to a higher output frequency
|
||||
*/
|
||||
#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in CRS register
|
||||
* @param __INSTANCE__ CRS Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in CRS register
|
||||
* @param __INSTANCE__ CRS Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
|
||||
* @note The RELOAD value should be selected according to the ratio between
|
||||
* the target frequency and the frequency of the synchronization source after
|
||||
* prescaling. It is then decreased by one in order to reach the expected
|
||||
* synchronization on the zero value. The formula is the following:
|
||||
* RELOAD = (fTARGET / fSYNC) -1
|
||||
* @param __FTARGET__ Target frequency (value in Hz)
|
||||
* @param __FSYNC__ Synchronization signal frequency (value in Hz)
|
||||
* @retval Reload value (in Hz)
|
||||
*/
|
||||
#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EF_Configuration Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable Frequency error counter
|
||||
* @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
|
||||
* @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_CEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Frequency error counter
|
||||
* @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_CEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Frequency error counter is enabled or not
|
||||
* @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
|
||||
{
|
||||
return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Automatic trimming counter
|
||||
* @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Automatic trimming counter
|
||||
* @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Automatic trimming is enabled or not
|
||||
* @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
|
||||
{
|
||||
return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set HSI48 oscillator smooth trimming
|
||||
* @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
|
||||
* @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
|
||||
* @param Value a number between Min_Data = 0 and Max_Data = 63
|
||||
* @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
|
||||
{
|
||||
MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get HSI48 oscillator smooth trimming
|
||||
* @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
|
||||
* @retval a number between Min_Data = 0 and Max_Data = 63
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set counter reload value
|
||||
* @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
|
||||
* @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
|
||||
* @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
|
||||
* Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
|
||||
{
|
||||
MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get counter reload value
|
||||
* @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
|
||||
* @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set frequency error limit
|
||||
* @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
|
||||
* @param Value a number between Min_Data = 0 and Max_Data = 255
|
||||
* @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
|
||||
{
|
||||
MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get frequency error limit
|
||||
* @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
|
||||
* @retval A number between Min_Data = 0 and Max_Data = 255
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set division factor for SYNC signal
|
||||
* @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
|
||||
* @param Divider This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_DIV_1
|
||||
* @arg @ref LL_CRS_SYNC_DIV_2
|
||||
* @arg @ref LL_CRS_SYNC_DIV_4
|
||||
* @arg @ref LL_CRS_SYNC_DIV_8
|
||||
* @arg @ref LL_CRS_SYNC_DIV_16
|
||||
* @arg @ref LL_CRS_SYNC_DIV_32
|
||||
* @arg @ref LL_CRS_SYNC_DIV_64
|
||||
* @arg @ref LL_CRS_SYNC_DIV_128
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
|
||||
{
|
||||
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get division factor for SYNC signal
|
||||
* @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_DIV_1
|
||||
* @arg @ref LL_CRS_SYNC_DIV_2
|
||||
* @arg @ref LL_CRS_SYNC_DIV_4
|
||||
* @arg @ref LL_CRS_SYNC_DIV_8
|
||||
* @arg @ref LL_CRS_SYNC_DIV_16
|
||||
* @arg @ref LL_CRS_SYNC_DIV_32
|
||||
* @arg @ref LL_CRS_SYNC_DIV_64
|
||||
* @arg @ref LL_CRS_SYNC_DIV_128
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SYNC signal source
|
||||
* @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
|
||||
* @param Source This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_USB
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
|
||||
{
|
||||
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SYNC signal source
|
||||
* @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_USB
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set input polarity for the SYNC signal source
|
||||
* @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
|
||||
* @param Polarity This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
|
||||
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
|
||||
{
|
||||
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get input polarity for the SYNC signal source
|
||||
* @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
|
||||
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure CRS for the synchronization
|
||||
* @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
|
||||
* CFGR RELOAD LL_CRS_ConfigSynchronization\n
|
||||
* CFGR FELIM LL_CRS_ConfigSynchronization\n
|
||||
* CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
|
||||
* CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
|
||||
* CFGR SYNCPOL LL_CRS_ConfigSynchronization
|
||||
* @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
|
||||
* @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
|
||||
* @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
|
||||
* @param Settings This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
|
||||
* or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
|
||||
* @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
|
||||
{
|
||||
MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
|
||||
MODIFY_REG(CRS->CFGR,
|
||||
CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
|
||||
ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Generate software SYNC event
|
||||
* @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the frequency error direction latched in the time of the last
|
||||
* SYNC event
|
||||
* @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
|
||||
* @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the frequency error counter value latched in the time of the last SYNC event
|
||||
* @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
|
||||
* @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC event OK signal occurred or not
|
||||
* @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
|
||||
{
|
||||
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC warning signal occurred or not
|
||||
* @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
|
||||
{
|
||||
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Synchronization or trimming error signal occurred or not
|
||||
* @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
|
||||
{
|
||||
return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Expected SYNC signal occurred or not
|
||||
* @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
|
||||
{
|
||||
return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC error signal occurred or not
|
||||
* @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
|
||||
{
|
||||
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC missed error signal occurred or not
|
||||
* @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
|
||||
{
|
||||
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Trimming overflow or underflow occurred or not
|
||||
* @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
|
||||
{
|
||||
return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the SYNC event OK flag
|
||||
* @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
|
||||
{
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the SYNC warning flag
|
||||
* @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
|
||||
{
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
|
||||
* the ERR flag
|
||||
* @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
|
||||
{
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Expected SYNC flag
|
||||
* @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
|
||||
{
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EF_IT_Management IT_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable SYNC event OK interrupt
|
||||
* @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SYNC event OK interrupt
|
||||
* @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC event OK interrupt is enabled or not
|
||||
* @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
|
||||
{
|
||||
return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable SYNC warning interrupt
|
||||
* @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SYNC warning interrupt
|
||||
* @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC warning interrupt is enabled or not
|
||||
* @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
|
||||
{
|
||||
return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Synchronization or trimming error interrupt
|
||||
* @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_ERRIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Synchronization or trimming error interrupt
|
||||
* @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Synchronization or trimming error interrupt is enabled or not
|
||||
* @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
|
||||
{
|
||||
return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Expected SYNC interrupt
|
||||
* @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Expected SYNC interrupt
|
||||
* @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Expected SYNC interrupt is enabled or not
|
||||
* @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
|
||||
{
|
||||
return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_CRS_DeInit(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(CRS) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_LL_CRS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,940 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_LL_GPIO_H
|
||||
#define __STM32F0xx_LL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF)
|
||||
|
||||
/** @defgroup GPIO_LL GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief LL GPIO Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_LL_EC_PIN */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_MODE.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_SPEED.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
|
||||
|
||||
uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
|
||||
|
||||
uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_PULL.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
|
||||
|
||||
uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_AF.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
|
||||
} LL_GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_PIN PIN
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */
|
||||
#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */
|
||||
#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */
|
||||
#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */
|
||||
#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */
|
||||
#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */
|
||||
#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */
|
||||
#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */
|
||||
#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */
|
||||
#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */
|
||||
#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */
|
||||
#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */
|
||||
#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */
|
||||
#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */
|
||||
#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */
|
||||
#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */
|
||||
#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \
|
||||
GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \
|
||||
GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \
|
||||
GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
|
||||
GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
|
||||
GPIO_BSRR_BS_15) /*!< Select all pins */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_MODE Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
|
||||
#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */
|
||||
#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */
|
||||
#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_OUTPUT Output Type
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */
|
||||
#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_SPEED Output Speed
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */
|
||||
#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEEDR0_0 /*!< Select I/O medium output speed */
|
||||
#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEEDR0 /*!< Select I/O high output speed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
|
||||
#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
|
||||
#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_HIGH
|
||||
|
||||
/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
|
||||
#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
|
||||
#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_AF Alternate Function
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
|
||||
#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
|
||||
#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
|
||||
#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
|
||||
#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
|
||||
#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
|
||||
#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
|
||||
#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in GPIO register
|
||||
* @param __INSTANCE__ GPIO Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in GPIO register
|
||||
* @param __INSTANCE__ GPIO Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure gpio mode for a dedicated pin on dedicated port.
|
||||
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll MODER MODEy LL_GPIO_SetPinMode
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Mode This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_MODE_INPUT
|
||||
* @arg @ref LL_GPIO_MODE_OUTPUT
|
||||
* @arg @ref LL_GPIO_MODE_ALTERNATE
|
||||
* @arg @ref LL_GPIO_MODE_ANALOG
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
|
||||
{
|
||||
MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0), ((Pin * Pin) * Mode));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio mode for a dedicated pin on dedicated port.
|
||||
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll MODER MODEy LL_GPIO_GetPinMode
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_MODE_INPUT
|
||||
* @arg @ref LL_GPIO_MODE_OUTPUT
|
||||
* @arg @ref LL_GPIO_MODE_ALTERNATE
|
||||
* @arg @ref LL_GPIO_MODE_ANALOG
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio output type for several pins on dedicated port.
|
||||
* @note Output type as to be set when gpio pin is in output or
|
||||
* alternate modes. Possible type are Push-pull or Open-drain.
|
||||
* @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @param OutputType This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
|
||||
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
|
||||
{
|
||||
MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio output type for several pins on dedicated port.
|
||||
* @note Output type as to be set when gpio pin is in output or
|
||||
* alternate modes. Possible type are Push-pull or Open-drain.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
|
||||
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio speed for a dedicated pin on dedicated port.
|
||||
* @note I/O speed can be Low, Medium, Fast or High speed.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @note Refer to datasheet for frequency specifications and the power
|
||||
* supply and load conditions for each speed.
|
||||
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Speed This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
|
||||
{
|
||||
MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0), ((Pin * Pin) * Speed));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio speed for a dedicated pin on dedicated port.
|
||||
* @note I/O speed can be Low, Medium, Fast or High speed.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @note Refer to datasheet for frequency specifications and the power
|
||||
* supply and load conditions for each speed.
|
||||
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0)) / (Pin * Pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Pull This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PULL_NO
|
||||
* @arg @ref LL_GPIO_PULL_UP
|
||||
* @arg @ref LL_GPIO_PULL_DOWN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
|
||||
{
|
||||
MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0), ((Pin * Pin) * Pull));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PULL_NO
|
||||
* @arg @ref LL_GPIO_PULL_UP
|
||||
* @arg @ref LL_GPIO_PULL_DOWN
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0)) / (Pin * Pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
|
||||
* @note Possible values are from AF0 to AF7 depending on target.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @param Alternate This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
|
||||
{
|
||||
MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),
|
||||
((((Pin * Pin) * Pin) * Pin) * Alternate));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
|
||||
* @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->AFR[0],
|
||||
((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
|
||||
* @note Possible values are from AF0 to AF7 depending on target.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Alternate This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
|
||||
{
|
||||
MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),
|
||||
(((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
|
||||
* @note Possible values are from AF0 to AF7 depending on target.
|
||||
* @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->AFR[1],
|
||||
(((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) *
|
||||
(Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Lock configuration of several pins for a dedicated port.
|
||||
* @note When the lock sequence has been applied on a port bit, the
|
||||
* value of this port bit can no longer be modified until the
|
||||
* next reset.
|
||||
* @note Each lock bit freezes a specific configuration register
|
||||
* (control and alternate function registers).
|
||||
* @rmtoll LCKR LCKK LL_GPIO_LockPin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
__IO uint32_t temp;
|
||||
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
|
||||
WRITE_REG(GPIOx->LCKR, PinMask);
|
||||
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
|
||||
temp = READ_REG(GPIOx->LCKR);
|
||||
(void) temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
|
||||
* @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
|
||||
* @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EF_Data_Access Data Access
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return full input data register value for a dedicated port.
|
||||
* @rmtoll IDR IDy LL_GPIO_ReadInputPort
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval Input data register value of port
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(GPIOx->IDR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return if input data level for several pins of dedicated port is high or low.
|
||||
* @rmtoll IDR IDy LL_GPIO_IsInputPinSet
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write output data register for the port.
|
||||
* @rmtoll ODR ODy LL_GPIO_WriteOutputPort
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PortValue Level value for each pin of the port
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
|
||||
{
|
||||
WRITE_REG(GPIOx->ODR, PortValue);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return full output data register value for a dedicated port.
|
||||
* @rmtoll ODR ODy LL_GPIO_ReadOutputPort
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval Output data register value of port
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(GPIOx->ODR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return if input data level for several pins of dedicated port is high or low.
|
||||
* @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set several pins to high level on dedicated gpio port.
|
||||
* @rmtoll BSRR BSy LL_GPIO_SetOutputPin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
WRITE_REG(GPIOx->BSRR, PinMask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set several pins to low level on dedicated gpio port.
|
||||
* @rmtoll BRR BRy LL_GPIO_ResetOutputPin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
WRITE_REG(GPIOx->BRR, PinMask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggle data value for several pin of dedicated port.
|
||||
* @rmtoll ODR ODy LL_GPIO_TogglePin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
uint32_t odr = READ_REG(GPIOx->ODR);
|
||||
WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
|
||||
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
|
||||
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_LL_GPIO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,552 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_LL_PWR_H
|
||||
#define __STM32F0xx_LL_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(PWR)
|
||||
|
||||
/** @defgroup PWR_LL PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
|
||||
* @brief Flags defines which can be used with LL_PWR_WriteReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
|
||||
#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
|
||||
* @brief Flags defines which can be used with LL_PWR_ReadReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
|
||||
#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
|
||||
#if defined(PWR_PVD_SUPPORT)
|
||||
#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
#if defined(PWR_CSR_VREFINTRDYF)
|
||||
#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */
|
||||
#endif /* PWR_CSR_VREFINTRDYF */
|
||||
#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
|
||||
#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
|
||||
#if defined(PWR_CSR_EWUP3)
|
||||
#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
|
||||
#endif /* PWR_CSR_EWUP3 */
|
||||
#if defined(PWR_CSR_EWUP4)
|
||||
#define LL_PWR_CSR_EWUP4 PWR_CSR_EWUP4 /*!< Enable WKUP pin 4 */
|
||||
#endif /* PWR_CSR_EWUP4 */
|
||||
#if defined(PWR_CSR_EWUP5)
|
||||
#define LL_PWR_CSR_EWUP5 PWR_CSR_EWUP5 /*!< Enable WKUP pin 5 */
|
||||
#endif /* PWR_CSR_EWUP5 */
|
||||
#if defined(PWR_CSR_EWUP6)
|
||||
#define LL_PWR_CSR_EWUP6 PWR_CSR_EWUP6 /*!< Enable WKUP pin 6 */
|
||||
#endif /* PWR_CSR_EWUP6 */
|
||||
#if defined(PWR_CSR_EWUP7)
|
||||
#define LL_PWR_CSR_EWUP7 PWR_CSR_EWUP7 /*!< Enable WKUP pin 7 */
|
||||
#endif /* PWR_CSR_EWUP7 */
|
||||
#if defined(PWR_CSR_EWUP8)
|
||||
#define LL_PWR_CSR_EWUP8 PWR_CSR_EWUP8 /*!< Enable WKUP pin 8 */
|
||||
#endif /* PWR_CSR_EWUP8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
|
||||
#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
|
||||
#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(PWR_CR_LPDS)
|
||||
/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
|
||||
#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* PWR_CR_LPDS */
|
||||
|
||||
#if defined(PWR_PVD_SUPPORT)
|
||||
/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold 0 */
|
||||
#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold 1 */
|
||||
#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold 2 */
|
||||
#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold 3 */
|
||||
#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold 4 */
|
||||
#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold 5 */
|
||||
#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold 6 */
|
||||
#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold 7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
|
||||
#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */
|
||||
#if defined(PWR_CSR_EWUP3)
|
||||
#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */
|
||||
#endif /* PWR_CSR_EWUP3 */
|
||||
#if defined(PWR_CSR_EWUP4)
|
||||
#define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : LLG TBD */
|
||||
#endif /* PWR_CSR_EWUP4 */
|
||||
#if defined(PWR_CSR_EWUP5)
|
||||
#define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : LLG TBD */
|
||||
#endif /* PWR_CSR_EWUP5 */
|
||||
#if defined(PWR_CSR_EWUP6)
|
||||
#define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : LLG TBD */
|
||||
#endif /* PWR_CSR_EWUP6 */
|
||||
#if defined(PWR_CSR_EWUP7)
|
||||
#define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : LLG TBD */
|
||||
#endif /* PWR_CSR_EWUP7 */
|
||||
#if defined(PWR_CSR_EWUP8)
|
||||
#define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : LLG TBD */
|
||||
#endif /* PWR_CSR_EWUP8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in PWR register
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in PWR register
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EF_Configuration Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable access to the backup domain
|
||||
* @rmtoll CR DBP LL_PWR_EnableBkUpAccess
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable access to the backup domain
|
||||
* @rmtoll CR DBP LL_PWR_DisableBkUpAccess
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the backup domain is enabled
|
||||
* @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
|
||||
}
|
||||
|
||||
#if defined(PWR_CR_LPDS)
|
||||
/**
|
||||
* @brief Set voltage Regulator mode during deep sleep mode
|
||||
* @rmtoll CR LPDS LL_PWR_SetRegulModeDS
|
||||
* @param RegulMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
|
||||
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
|
||||
{
|
||||
MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get voltage Regulator mode during deep sleep mode
|
||||
* @rmtoll CR LPDS LL_PWR_GetRegulModeDS
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
|
||||
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
|
||||
}
|
||||
#endif /* PWR_CR_LPDS */
|
||||
|
||||
/**
|
||||
* @brief Set Power Down mode when CPU enters deepsleep
|
||||
* @rmtoll CR PDDS LL_PWR_SetPowerMode\n
|
||||
* @rmtoll CR LPDS LL_PWR_SetPowerMode
|
||||
* @param PDMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
|
||||
* @arg @ref LL_PWR_MODE_STOP_LPREGU
|
||||
* @arg @ref LL_PWR_MODE_STANDBY
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
|
||||
{
|
||||
MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Power Down mode when CPU enters deepsleep
|
||||
* @rmtoll CR PDDS LL_PWR_GetPowerMode\n
|
||||
* @rmtoll CR LPDS LL_PWR_GetPowerMode
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
|
||||
* @arg @ref LL_PWR_MODE_STOP_LPREGU
|
||||
* @arg @ref LL_PWR_MODE_STANDBY
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
|
||||
}
|
||||
|
||||
#if defined(PWR_PVD_SUPPORT)
|
||||
/**
|
||||
* @brief Configure the voltage threshold detected by the Power Voltage Detector
|
||||
* @rmtoll CR PLS LL_PWR_SetPVDLevel
|
||||
* @param PVDLevel This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_PVDLEVEL_0
|
||||
* @arg @ref LL_PWR_PVDLEVEL_1
|
||||
* @arg @ref LL_PWR_PVDLEVEL_2
|
||||
* @arg @ref LL_PWR_PVDLEVEL_3
|
||||
* @arg @ref LL_PWR_PVDLEVEL_4
|
||||
* @arg @ref LL_PWR_PVDLEVEL_5
|
||||
* @arg @ref LL_PWR_PVDLEVEL_6
|
||||
* @arg @ref LL_PWR_PVDLEVEL_7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
|
||||
{
|
||||
MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the voltage threshold detection
|
||||
* @rmtoll CR PLS LL_PWR_GetPVDLevel
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_PWR_PVDLEVEL_0
|
||||
* @arg @ref LL_PWR_PVDLEVEL_1
|
||||
* @arg @ref LL_PWR_PVDLEVEL_2
|
||||
* @arg @ref LL_PWR_PVDLEVEL_3
|
||||
* @arg @ref LL_PWR_PVDLEVEL_4
|
||||
* @arg @ref LL_PWR_PVDLEVEL_5
|
||||
* @arg @ref LL_PWR_PVDLEVEL_6
|
||||
* @arg @ref LL_PWR_PVDLEVEL_7
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Power Voltage Detector
|
||||
* @rmtoll CR PVDE LL_PWR_EnablePVD
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnablePVD(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_PVDE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Power Voltage Detector
|
||||
* @rmtoll CR PVDE LL_PWR_DisablePVD
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisablePVD(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Power Voltage Detector is enabled
|
||||
* @rmtoll CR PVDE LL_PWR_IsEnabledPVD
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
|
||||
}
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
|
||||
/**
|
||||
* @brief Enable the WakeUp PINx functionality
|
||||
* @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP4 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP5 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP6 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP7 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP8 LL_PWR_EnableWakeUpPin
|
||||
* @param WakeUpPin This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN1
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN2
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN4 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN6 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN7 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN8 (*)
|
||||
*
|
||||
* (*) not available on all devices
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
|
||||
{
|
||||
SET_BIT(PWR->CSR, WakeUpPin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the WakeUp PINx functionality
|
||||
* @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP4 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP5 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP6 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP7 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP8 LL_PWR_DisableWakeUpPin
|
||||
* @param WakeUpPin This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN1
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN2
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN4 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN6 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN7 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN8 (*)
|
||||
*
|
||||
* (*) not available on all devices
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
|
||||
{
|
||||
CLEAR_BIT(PWR->CSR, WakeUpPin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the WakeUp PINx functionality is enabled
|
||||
* @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP4 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP5 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP6 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP7 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP8 LL_PWR_IsEnabledWakeUpPin
|
||||
* @param WakeUpPin This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN1
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN2
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN4 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN6 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN7 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN8 (*)
|
||||
*
|
||||
* (*) not available on all devices
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Wake-up Flag
|
||||
* @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Standby Flag
|
||||
* @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
|
||||
}
|
||||
|
||||
#if defined(PWR_PVD_SUPPORT)
|
||||
/**
|
||||
* @brief Indicate whether VDD voltage is below the selected PVD threshold
|
||||
* @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
|
||||
}
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
|
||||
#if defined(PWR_CSR_VREFINTRDYF)
|
||||
/**
|
||||
* @brief Get Internal Reference VrefInt Flag
|
||||
* @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
|
||||
}
|
||||
#endif /* PWR_CSR_VREFINTRDYF */
|
||||
/**
|
||||
* @brief Clear Standby Flag
|
||||
* @rmtoll CR CSBF LL_PWR_ClearFlag_SB
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_CSBF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Wake-up Flags
|
||||
* @rmtoll CR CWUF LL_PWR_ClearFlag_WU
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_CWUF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup PWR_LL_EF_Init De-initialization function
|
||||
* @{
|
||||
*/
|
||||
ErrorStatus LL_PWR_DeInit(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(PWR) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_LL_PWR_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,274 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_utils.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of UTILS LL module.
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The LL UTILS driver contains a set of generic APIs that can be
|
||||
used by user:
|
||||
(+) Device electronic signature
|
||||
(+) Timing functions
|
||||
(+) PLL configuration functions
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_LL_UTILS_H
|
||||
#define __STM32F0xx_LL_UTILS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_LL UTILS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Max delay can be used in LL_mDelay */
|
||||
#define LL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* @brief Unique device ID register base address
|
||||
*/
|
||||
#define UID_BASE_ADDRESS UID_BASE
|
||||
|
||||
/**
|
||||
* @brief Flash size data register base address
|
||||
*/
|
||||
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief UTILS PLL structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
|
||||
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
|
||||
uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
#else
|
||||
uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
|
||||
} LL_UTILS_PLLInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief UTILS System, AHB and APB buses clock configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAHBPrescaler(). */
|
||||
|
||||
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAPB1Prescaler(). */
|
||||
} LL_UTILS_ClkInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
|
||||
* @{
|
||||
*/
|
||||
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
|
||||
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Flash memory size
|
||||
* @note This bitfield indicates the size of the device Flash memory expressed in
|
||||
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
|
||||
* @retval FLASH_SIZE[15:0]: Flash memory size
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
|
||||
{
|
||||
return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_LL_EF_DELAY DELAY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the Cortex-M SysTick source of the time base.
|
||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
|
||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||
* @param Ticks Number of ticks
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
||||
{
|
||||
/* Configure the SysTick to have interrupt in 1ms time base */
|
||||
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
|
||||
}
|
||||
|
||||
void LL_Init1msTick(uint32_t HCLKFrequency);
|
||||
void LL_mDelay(uint32_t Delay);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EF_SYSTEM SYSTEM
|
||||
* @{
|
||||
*/
|
||||
|
||||
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
ErrorStatus LL_SetFlashLatency(uint32_t Frequency);
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
#if defined(RCC_CFGR_SW_HSI48)
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
#endif /*RCC_CFGR_SW_HSI48*/
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
|
||||
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_LL_UTILS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
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Add table
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Reference in a new issue