813477aa8a
* custom delay * Update comment * add bus control status, add some missing include & fixed display output on sh1104 (#319) * add some missing include * Fixed display on SH1106 * Fix comment, add force sytem, rework flag, 16 bits data transfert * Update all library with new I2C API * custom delay * Update comment, add bus control status * fix i2c read + fix ds3231 temp + fix ssd1306 send
195 lines
4.8 KiB
C
195 lines
4.8 KiB
C
/*
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* Driver for ADS1113/ADS1114/ADS1115 I2C ADC
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*
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* Part of esp-open-rtos
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* Copyright (C) 2016 Ruslan V. Uss <unclerus@gmail.com>
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* BSD Licensed as described in the file LICENSE
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*/
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#include "ads111x.h"
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#include <i2c/i2c.h>
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#define ADS111X_DEBUG
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#ifdef ADS111X_DEBUG
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#include <stdio.h>
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#define debug(fmt, ...) printf("%s" fmt "\n", "ADS111x: ", ## __VA_ARGS__)
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#else
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#define debug(fmt, ...)
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#endif
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#define REG_CONVERSION 0
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#define REG_CONFIG 1
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#define REG_THRESH_L 2
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#define REG_THRESH_H 3
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#define COMP_QUE_OFFSET 1
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#define COMP_QUE_MASK 0x03
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#define COMP_LAT_OFFSET 2
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#define COMP_LAT_MASK 0x01
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#define COMP_POL_OFFSET 3
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#define COMP_POL_MASK 0x01
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#define COMP_MODE_OFFSET 4
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#define COMP_MODE_MASK 0x01
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#define DR_OFFSET 5
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#define DR_MASK 0x07
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#define MODE_OFFSET 8
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#define MODE_MASK 0x01
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#define PGA_OFFSET 9
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#define PGA_MASK 0x07
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#define MUX_OFFSET 12
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#define MUX_MASK 0x07
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#define OS_OFFSET 15
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#define OS_MASK 0x01
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const float ads111x_gain_values[] = {
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[ADS111X_GAIN_6V144] = 6.144,
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[ADS111X_GAIN_4V096] = 4.096,
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[ADS111X_GAIN_2V048] = 2.048,
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[ADS111X_GAIN_1V024] = 1.024,
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[ADS111X_GAIN_0V512] = 0.512,
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[ADS111X_GAIN_0V256] = 0.256,
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[ADS111X_GAIN_0V256_2] = 0.256,
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[ADS111X_GAIN_0V256_3] = 0.256
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};
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static uint16_t read_reg(uint8_t addr, uint8_t reg)
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{
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uint16_t res = 0;
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if (i2c_slave_read(addr, ®, (uint8_t *)&res, 2))
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debug("Could not read register %d", reg);
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//debug("Read %d: 0x%04x", reg, res);
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return res;
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}
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static void write_reg(uint8_t addr, uint8_t reg, uint16_t val)
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{
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//debug("Write %d: 0x%04x", reg, val);
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uint8_t buf[2] = { val >> 8, val};
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if (i2c_slave_write(addr, ®, buf, 2))
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debug("Could not write 0x%04x to register %d", val, reg);
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}
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static uint16_t read_conf_bits(uint8_t addr, uint8_t offs, uint16_t mask)
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{
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return (read_reg(addr, REG_CONFIG) >> offs) & mask;
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}
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static void write_conf_bits(uint8_t addr, uint16_t val, uint8_t offs, uint16_t mask)
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{
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write_reg(addr, REG_CONFIG, (read_reg(addr, REG_CONFIG) & ~(mask << offs)) | (val << offs));
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}
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bool ads111x_busy(uint8_t addr)
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{
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return read_conf_bits(addr, OS_OFFSET, OS_MASK);
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}
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void ads111x_start_conversion(uint8_t addr)
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{
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write_conf_bits(addr, 1, OS_OFFSET, OS_MASK);
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}
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int16_t ads111x_get_value(uint8_t addr)
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{
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return read_reg(addr, REG_CONVERSION);
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}
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ads111x_gain_t ads111x_get_gain(uint8_t addr)
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{
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return read_conf_bits(addr, PGA_OFFSET, PGA_MASK);
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}
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void ads111x_set_gain(uint8_t addr, ads111x_gain_t gain)
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{
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write_conf_bits(addr, gain, PGA_OFFSET, PGA_MASK);
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}
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ads111x_mux_t ads111x_get_input_mux(uint8_t addr)
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{
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return read_conf_bits(addr, MUX_OFFSET, MUX_MASK);
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}
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void ads111x_set_input_mux(uint8_t addr, ads111x_mux_t mux)
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{
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write_conf_bits(addr, mux, MUX_OFFSET, MUX_MASK);
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}
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ads111x_mode_t ads111x_get_mode(uint8_t addr)
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{
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return read_conf_bits(addr, MODE_OFFSET, MODE_MASK);
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}
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void ads111x_set_mode(uint8_t addr, ads111x_mode_t mode)
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{
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write_conf_bits(addr, mode, MODE_OFFSET, MODE_MASK);
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}
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ads111x_data_rate_t ads111x_get_data_rate(uint8_t addr)
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{
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return read_conf_bits(addr, DR_OFFSET, DR_MASK);
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}
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void ads111x_set_data_rate(uint8_t addr, ads111x_data_rate_t rate)
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{
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write_conf_bits(addr, rate, DR_OFFSET, DR_MASK);
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}
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ads111x_comp_mode_t ads111x_get_comp_mode(uint8_t addr)
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{
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return read_conf_bits(addr, COMP_MODE_OFFSET, COMP_MODE_MASK);
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}
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void ads111x_set_comp_mode(uint8_t addr, ads111x_comp_mode_t mode)
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{
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write_conf_bits(addr, mode, COMP_MODE_OFFSET, COMP_MODE_MASK);
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}
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ads111x_comp_polarity_t ads111x_get_comp_polarity(uint8_t addr)
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{
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return read_conf_bits(addr, COMP_POL_OFFSET, COMP_POL_MASK);
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}
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void ads111x_set_comp_polarity(uint8_t addr, ads111x_comp_polarity_t polarity)
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{
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write_conf_bits(addr, polarity, COMP_POL_OFFSET, COMP_POL_MASK);
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}
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ads111x_comp_latch_t ads111x_get_comp_latch(uint8_t addr)
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{
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return read_conf_bits(addr, COMP_LAT_OFFSET, COMP_LAT_MASK);
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}
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void ads111x_set_comp_latch(uint8_t addr, ads111x_comp_latch_t latch)
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{
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write_conf_bits(addr, latch, COMP_LAT_OFFSET, COMP_LAT_MASK);
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}
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ads111x_comp_queue_t ads111x_get_comp_queue(uint8_t addr)
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{
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return read_conf_bits(addr, COMP_QUE_OFFSET, COMP_QUE_MASK);
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}
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void ads111x_set_comp_queue(uint8_t addr, ads111x_comp_queue_t queue)
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{
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write_conf_bits(addr, queue, COMP_QUE_OFFSET, COMP_QUE_MASK);
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}
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int16_t ads111x_get_comp_low_thresh(uint8_t addr)
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{
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return read_reg(addr, REG_THRESH_L);
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}
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void ads111x_set_comp_low_thresh(uint8_t addr, int16_t thresh)
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{
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write_reg(addr, REG_THRESH_L, thresh);
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}
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int16_t ads111x_get_comp_high_thresh(uint8_t addr)
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{
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return read_reg(addr, REG_THRESH_H);
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}
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void ads111x_set_comp_high_thresh(uint8_t addr, int16_t thresh)
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{
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write_reg(addr, REG_THRESH_H, thresh);
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}
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