0aabbea16f
WDT is countdown timer. Current value is accessible via VAL register. At this time it's unclear if it's RO or RW (common sense says it shoul be RO). Source: looking at the WDT registers on a running chip.
51 lines
1.3 KiB
C
51 lines
1.3 KiB
C
/* esp/wdt_regs.h
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*
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* ESP8266 Watchdog Timer register definitions
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*
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* Not compatible with ESP SDK register access code.
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*/
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#ifndef _ESP_WDT_REGS_H
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#define _ESP_WDT_REGS_H
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#include "esp/types.h"
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#include "common_macros.h"
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#define WDT_BASE 0x60000900
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#define WDT (*(struct WDT_REGS *)(WDT_BASE))
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/* WDT register(s)
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Not fully understood yet. Writing 0 to CTRL disables WDT.
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See ROM functions esp_wdt_xxx
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*/
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struct WDT_REGS {
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uint32_t volatile CTRL; // 0x00
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uint32_t volatile REG1; // 0x04
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uint32_t volatile REG2; // 0x08
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// Current value, decrementing
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uint32_t volatile VAL; // 0x0c
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uint32_t volatile _unused[1]; // 0x10
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uint32_t volatile FEED; // 0x14
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};
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_Static_assert(sizeof(struct WDT_REGS) == 0x18, "WDT_REGS is the wrong size");
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/* Details for CTRL register */
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/* Note: these are currently just guesses based on interpretation of the startup code */
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#define WDT_CTRL_ENABLE BIT(0)
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#define WDT_CTRL_FIELD0_M 0x00000003
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#define WDT_CTRL_FIELD0_S 1
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#define WDT_CTRL_FLAG3 BIT(3)
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#define WDT_CTRL_FLAG4 BIT(4)
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#define WDT_CTRL_FLAG5 BIT(5)
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/* Writing WDT_FEED_MAGIC to WDT.FEED register "feeds the dog" and holds off
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* triggering for another cycle (unconfirmed) */
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#define WDT_FEED_MAGIC 0x73
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#endif /* _ESP_WDT_REGS_H */
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