125 lines
4.2 KiB
C
125 lines
4.2 KiB
C
/* esp/dport_regs.h
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*
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* ESP8266 DPORT0 register definitions
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*
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* Not compatible with ESP SDK register access code.
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*/
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#ifndef _ESP_DPORT_REGS_H
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#define _ESP_DPORT_REGS_H
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#include "esp/types.h"
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#include "common_macros.h"
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#define DPORT_BASE 0x3ff00000
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#define DPORT (*(struct DPORT_REGS *)(DPORT_BASE))
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/* DPORT registers
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Control various aspects of core/peripheral interaction... Not well
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documented or understood.
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*/
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struct DPORT_REGS {
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uint32_t volatile DPORT0; // 0x00 FIXME: need a better name for this
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uint32_t volatile INT_ENABLE; // 0x04
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uint32_t volatile _unknown08; // 0x08
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uint32_t volatile SPI_READY; // 0x0c
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uint32_t volatile _unknown10; // 0x10
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uint32_t volatile CPU_CLOCK; // 0x14
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uint32_t volatile CLOCKGATE_WATCHDOG; // 0x18
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uint32_t volatile _unknown1c; // 0x1c
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uint32_t volatile SPI_INT_STATUS; // 0x20
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uint32_t volatile SPI_CACHE_RAM; // 0x24
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uint32_t volatile PERI_IO; // 0x28
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uint32_t volatile SLC_TX_DESC_DEBUG; // 0x2c
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uint32_t volatile _unknown30; // 0x30
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uint32_t volatile _unknown34; // 0x34
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uint32_t volatile _unknown38; // 0x38
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uint32_t volatile _unknown3c; // 0x3c
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uint32_t volatile _unknown40; // 0x40
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uint32_t volatile _unknown44; // 0x44
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uint32_t volatile _unknown48; // 0x48
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uint32_t volatile _unknown4c; // 0x4c
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uint32_t volatile OTP_MAC0; // 0x50
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uint32_t volatile OTP_MAC1; // 0x54
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uint32_t volatile OTP_CHIPID; // 0x58
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uint32_t volatile OTP_MAC2; // 0x5c
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};
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_Static_assert(sizeof(struct DPORT_REGS) == 0x60, "DPORT_REGS is the wrong size");
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/* Details for DPORT0 register */
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/* Currently very little known about this register. The following is based on analysis of the startup code in the Espressif SDK: */
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#define DPORT_DPORT0_FIELD0_M 0x0000007f
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#define DPORT_DPORT0_FIELD0_S 0
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/* Details for INT_ENABLE register */
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/* Set flags to enable CPU interrupts from some peripherals. Read/write.
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bit 0 - INT_ENABLE_WDT (unclear exactly how this works. Set by RTOS SDK startup code)
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bit 1 - INT_ENABLE_TIMER0 allows TIMER 0 (FRC1) to trigger interrupt INUM_TIMER_FRC1.
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bit 2 - INT_ENABLE_TIMER1 allows TIMER 1 (FRC2) to trigger interrupt INUM_TIMER_FRC2.
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Espressif calls this register "EDGE_INT_ENABLE_REG". The "edge" in
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question is (I think) the interrupt line from the peripheral, as
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the interrupt status bit is set. There may be a similar register
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for enabling "level" interrupts instead of edge triggering
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- this is unknown.
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*/
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#define DPORT_INT_ENABLE_WDT BIT(0)
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#define DPORT_INT_ENABLE_TIMER0 BIT(1)
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#define DPORT_INT_ENABLE_TIMER1 BIT(2)
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/* Aliases for the Espressif way of referring to TIMER0 (FRC1) and TIMER1
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* (FRC2).. */
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#define DPORT_INT_ENABLE_FRC1 DPORT_INT_ENABLE_TIMER0
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#define DPORT_INT_ENABLE_FRC2 DPORT_INT_ENABLE_TIMER1
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/* Details for SPI_READY register */
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#define DPORT_SPI_READY_IDLE BIT(9)
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/* Details for CPU_CLOCK register */
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#define DPORT_CPU_CLOCK_X2 BIT(0)
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/* Details for CLOCKGATE_WATCHDOG register */
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/* Comment found in pvvx/mp3_decode headers: "use clockgate_watchdog(flg) { if(flg) 0x3FF00018 &= 0x77; else 0x3FF00018 |= 8; }". Not sure what this means or does. */
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#define DPORT_CLOCKGATE_WATCHDOG_DISABLE BIT(3)
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/* Details for SPI_INT_STATUS register */
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#define DPORT_SPI_INT_STATUS_SPI0 BIT(4)
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#define DPORT_SPI_INT_STATUS_SPI1 BIT(7)
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#define DPORT_SPI_INT_STATUS_I2S BIT(9)
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/* Details for SPI_CACHE_RAM register */
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#define DPORT_SPI_CACHE_RAM_BANK1 BIT(3)
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#define DPORT_SPI_CACHE_RAM_BANK0 BIT(4)
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/* Details for PERI_IO register */
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#define DPORT_PERI_IO_SWAP_UARTS BIT(0)
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#define DPORT_PERI_IO_SWAP_SPIS BIT(1)
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#define DPORT_PERI_IO_SWAP_UART0_PINS BIT(2)
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#define DPORT_PERI_IO_SWAP_UART1_PINS BIT(3)
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#define DPORT_PERI_IO_SPI1_PRIORITY BIT(5)
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#define DPORT_PERI_IO_SPI1_SHARED BIT(6)
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#define DPORT_PERI_IO_SPI0_SHARED BIT(7)
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/* Details for SLC_TX_DESC_DEBUG register */
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#define SLC_TX_DESC_DEBUG_VALUE_M 0x0000ffff
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#define SLC_TX_DESC_DEBUG_VALUE_S 0
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#define SLC_TX_DESC_DEBUG_VALUE_MAGIC 0xcccc
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#endif /* _ESP_DPORT_REGS_H */
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