6be0b6b20e
Rewrite to have the IRQ handler read the character and place it in a FreeRTOS queue.
176 lines
5.5 KiB
C
176 lines
5.5 KiB
C
/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2015 Johan Kanflo (github.com/kanflo)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <esp8266.h>
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#include <FreeRTOS.h>
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#include <semphr.h>
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#include <stdio.h>
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#if (configUSE_COUNTING_SEMAPHORES == 0)
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#error "You need to define configUSE_COUNTING_SEMAPHORES in a local FreeRTOSConfig.h, see examples/terminal/FreeRTOSConfig.h"
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#endif
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// IRQ driven UART RX driver for ESP8266 written for use with esp-open-rtos
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// TODO: Handle UART1
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#ifndef UART0
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#define UART0 (0)
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#endif
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#define UART0_RX_SIZE (128) // ESP8266 UART HW FIFO size
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static QueueHandle_t uart0_queue;
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static bool inited = false;
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static bool uart0_rx_init(void);
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static int uart0_nonblock;
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static TickType_t uart0_vtime = portMAX_DELAY;
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uint32_t uart0_parity_errors;
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uint32_t uart0_framing_errors;
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uint32_t uart0_breaks_detected;
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IRAM void uart0_rx_handler(void *arg)
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{
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// TODO: Handle UART1, see reg 0x3ff20020, bit2, bit0 represents uart1 and uart0 respectively
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// printf(" [%08x (%d)]\n", READ_PERI_REG(UART_INT_ST(UART0)), READ_PERI_REG(UART_STATUS(UART0)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S));
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BaseType_t xHigherPriorityTaskWoken = pdFALSE;
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do {
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// If new data arrives and the status changes after checking here, them
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// the interrupt will be re-triggered.
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uint32_t int_status = UART(UART0).INT_STATUS;
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if (int_status & UART_INT_STATUS_RXFIFO_FULL) {
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size_t count = UART(UART0).STATUS & (UART_STATUS_RXFIFO_COUNT_M << UART_STATUS_RXFIFO_COUNT_S);
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for (size_t i = 0; i < count; i++) {
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char ch = UART(UART0).FIFO & (UART_FIFO_DATA_M << UART_FIFO_DATA_S);
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xQueueSendToBackFromISR(uart0_queue, &ch, &xHigherPriorityTaskWoken);
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}
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UART(UART0).INT_CLEAR = UART_INT_CLEAR_RXFIFO_FULL;
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// If new data has arrived then the interrupt status will remain set.
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} else if (int_status & UART_INT_STATUS_PARITY_ERR) {
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uart0_parity_errors++;
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UART(UART0).INT_CLEAR = UART_INT_CLEAR_PARITY_ERR;
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} else if (int_status & UART_INT_STATUS_FRAMING_ERR) {
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uart0_framing_errors++;
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UART(UART0).INT_CLEAR = UART_INT_CLEAR_FRAMING_ERR;
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} else if (int_status & UART_INT_STATUS_BREAK_DETECTED) {
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uart0_breaks_detected++;
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UART(UART0).INT_CLEAR = UART_INT_CLEAR_BREAK_DETECTED;
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} else if (int_status & 0xff) {
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printf("Error: unexpected uart irq, INT_STATUS 0x%02x\n", int_status);
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} else {
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break;
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}
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} while (1);
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if(xHigherPriorityTaskWoken) {
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portYIELD();
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}
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}
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uint32_t uart0_num_char(void)
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{
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uint32_t count;
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if (!inited) uart0_rx_init();
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count = uxQueueMessagesWaiting(uart0_queue);
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return count;
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}
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int uart0_set_nonblock(int nonblock)
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{
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int current = uart0_nonblock;
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uart0_nonblock = nonblock;
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return current;
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}
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TickType_t uart0_set_vtime(TickType_t ticks)
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{
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TickType_t current = uart0_vtime;
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uart0_vtime = ticks;
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return current;
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}
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// _read_stdin_r in core/newlib_syscalls.c will be skipped by the linker in favour
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// of this function
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long _read_stdin_r(struct _reent *r, int fd, char *ptr, int len)
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{
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TickType_t vtime = uart0_vtime;
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int nonblock = uart0_nonblock;
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if (nonblock) {
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vtime = 0;
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}
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if (!inited) uart0_rx_init();
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for(size_t i = 0; i < len; i++, ptr++) {
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if (xQueueReceive(uart0_queue, (void*)ptr, vtime) == pdFALSE) {
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if (i > 0) {
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return i;
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}
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if (nonblock) {
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r->_errno = EAGAIN;
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return -1;
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}
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return 0;
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}
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}
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return len;
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}
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static bool uart0_rx_init(void)
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{
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uart0_queue = xQueueCreate(64, sizeof(char));
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if (!uart0_queue) {
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return false;
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}
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int trig_lvl = 1;
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_xt_isr_attach(INUM_UART, uart0_rx_handler, NULL);
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_xt_isr_unmask(1 << INUM_UART);
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// reset the rx fifo
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uint32_t conf = UART(UART0).CONF0;
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UART(UART0).CONF0 = conf | UART_CONF0_RXFIFO_RESET;
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UART(UART0).CONF0 = conf & ~UART_CONF0_RXFIFO_RESET;
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// set rx fifo trigger
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UART(UART0).CONF1 |= (trig_lvl & UART_CONF1_RXFIFO_FULL_THRESHOLD_M) << UART_CONF1_RXFIFO_FULL_THRESHOLD_S;
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// clear all interrupts
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UART(UART0).INT_CLEAR = 0x1ff;
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// enable rx_interrupt
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UART(UART0).INT_ENABLE = UART_INT_ENABLE_RXFIFO_FULL | UART_INT_ENABLE_PARITY_ERR |
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UART_INT_ENABLE_FRAMING_ERR | UART_INT_ENABLE_BREAK_DETECTED;
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inited = true;
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return true;
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}
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