c7a7dfdf82
The downside here is needing to use #include so the 'beq' in the exception vector can land on it directly, save an instruction. There might be a better way to do this, but it seems hard to "curate" the order that symbols appear in each section.
247 lines
6 KiB
ArmAsm
247 lines
6 KiB
ArmAsm
/* Xtensa Exception (ie interrupt) Vectors & low-level handler code
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Core exception handler code is placed in the .vecbase section,
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which gets picked up specially in the linker script and placed
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at beginning of IRAM.
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The actual VecBase symbol should be the first thing in .vecbase
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(this is not strictly important as it gets set by symbol lookup not
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by hardcoded address, but having it at 0x40100000 means that the
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exception vectors have memorable offsets, which match the default
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Boot ROM vector offsets. So convenient for human understanding.
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Part of esp-open-rtos
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Original vector contents Copyright (C) 2014-2015 Espressif Systems
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Additions Copyright (C) Superhouse Automation Pty Ltd and Angus Gratton
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BSD Licensed as described in the file LICENSE
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*/
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#include "led_debug.s"
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/* Some UserException causes, see table Table 4–64 in ISA reference */
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#define CAUSE_SYSCALL 1
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#define CAUSE_LOADSTORE 3
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#define CAUSE_LVL1INT 4
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.text
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.section .vecbase.text, "x"
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.global VecBase
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.type VecBase, @function /* it's not really a function, but treat it like one */
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.org 0
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VecBase:
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/* IMPORTANT: exception vector literals will go here, but we
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can't have more than 4 otherwise we push DebugExceptionVector past
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offset 0x10 relative to VecBase. There should be ways to avoid this,
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and also keep the VecBase offsets easy to read, but this works for now.
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*/
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.literal_position
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.org 0x10
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DebugExceptionVector:
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wsr.excsave2 a0
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call0 sdk_user_fatal_exception_handler
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rfi 2
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.org 0x20
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NMIExceptionVector:
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wsr.excsave3 a0
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call0 CallNMIExceptionHandler
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rfi 3 /* CallNMIExceptionHandler should call rfi itself */
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.org 0x30
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KernelExceptionVector:
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break 1, 0
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call0 sdk_user_fatal_exception_handler
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rfe
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.org 0x50
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UserExceptionVector:
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wsr.excsave1 a0
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rsr.exccause a0
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beqi a0, CAUSE_LOADSTORE, UserExceptionLoadStoreHandler
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j UserExceptionHandler
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.org 0x70
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DoubleExceptionVector:
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break 1, 4
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rsr.exccause a0
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beqi a0, CAUSE_LOADSTORE, DoubleExceptionLoadStoreHandler
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call0 sdk_user_fatal_exception_handler
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/* Reset vector would go here at offset 0x80 but should be unused,
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as vecbase goes back to mask ROM vectors on reset */
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/***** end of exception vectors *****/
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/* We include this here so UserExceptionLoadStoreHandler is within
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the range of a 'beq' instruction jump.
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*/
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#include "exception_unaligned_load.S.inc"
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.section .bss
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NMIHandlerStack: /* stack space for NMI handler */
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.skip 4*0x100
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.LNMIHandlerStackTop:
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NMIRegisterSaved: /* register space for saving NMI registers */
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.skip 4*(16 + 6)
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/* Save register relative to a0 */
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.macro SAVE_REG register, regnum
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s32i \register, a0, (0x20 + 4 * \regnum)
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.endm
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/* Load register relative to sp */
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.macro LOAD_REG register, regnum
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l32i \register, sp, (0x20 + 4 * \regnum)
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.endm
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.text
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.section .vecbase.text
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.literal_position
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.align 4
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.global call_user_start
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.type call_user_start, @function
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call_user_start:
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movi a2, VecBase
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wsr.vecbase a2
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call0 sdk_user_start
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.literal_position
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.align 16
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.type CallNMIExceptionHandler, @function
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CallNMIExceptionHandler:
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movi a0, NMIRegisterSaved
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SAVE_REG a2, 2
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SAVE_REG sp, 1
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SAVE_REG a3, 3
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rsr.excsave3 a2 /* a2 is now former a0 */
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SAVE_REG a4, 4
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SAVE_REG a2, 0
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rsr.epc1 a3
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rsr.exccause a4
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SAVE_REG a3, -5
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SAVE_REG a4, -4
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rsr.excvaddr a3
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SAVE_REG a3, -3
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rsr.excsave1 a3
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SAVE_REG a3, -2
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SAVE_REG a5, 5
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SAVE_REG a6, 6
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SAVE_REG a7, 7
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SAVE_REG a8, 8
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SAVE_REG a9, 9
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SAVE_REG a10, 10
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SAVE_REG a11, 11
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SAVE_REG a12, 12
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SAVE_REG a13, 13
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SAVE_REG a14, 14
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SAVE_REG a15, 15
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movi sp, .LNMIHandlerStackTop
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movi a0, 0
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movi a2, 0x23 /* argument for handler */
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wsr.ps a2
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rsync
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rsr.sar a14
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s32i a14, sp, 0 /* this is also NMIRegisterSaved+0 */
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call0 sdk_wDev_ProcessFiq
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l32i a15, sp, 0
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wsr.sar a15
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movi a2, 0x33
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wsr.ps a2
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rsync
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LOAD_REG a4, 4
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LOAD_REG a5, 5
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LOAD_REG a6, 6
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LOAD_REG a7, 7
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LOAD_REG a8, 8
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LOAD_REG a9, 9
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LOAD_REG a10, 10
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LOAD_REG a11, 11
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LOAD_REG a12, 12
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LOAD_REG a13, 13
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LOAD_REG a14, 14
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LOAD_REG a15, 15
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LOAD_REG a2, -5
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LOAD_REG a3, -4
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wsr.epc1 a2
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wsr.exccause a3
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LOAD_REG a2, -3
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LOAD_REG a3, -2
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wsr.excvaddr a2
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wsr.excsave1 a3
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LOAD_REG a0, 0
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/* set dport nmi status bit 0 (wDev_ProcessFiq clears & verifies this bit stays cleared,
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see http://esp8266-re.foogod.com/wiki/WDev_ProcessFiq_%28IoT_RTOS_SDK_0.9.9%29) */
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movi a2, 0x3ff00000
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movi a3, 0x1
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s32i a3, a2, 0
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LOAD_REG a2, 2
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LOAD_REG a3, 3
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LOAD_REG a1, 1
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rfi 0x3
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.type UserExceptionHandler, @function
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UserExceptionHandler:
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mov a0, sp /* a0 was saved in UserExceptionVector */
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addi sp, sp, -0x50
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s32i a0, sp, 0x10
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rsr.ps a0
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s32i a0, sp, 0x08
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rsr.epc1 a0
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s32i a0, sp, 0x04
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rsr.excsave1 a0
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s32i a0, sp, 0x0c
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movi a0, _xt_user_exit
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s32i a0, sp, 0x0
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call0 sdk__xt_int_enter
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movi a0, 0x23
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wsr.ps a0
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rsync
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rsr.exccause a2
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beqi a2, CAUSE_LVL1INT, UserHandleInterrupt
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/* Any UserException cause other than level 1 interrupt triggers a panic */
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UserFailOtherExceptionCause:
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break 1, 1
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call0 sdk_user_fatal_exception_handler
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UserHandleInterrupt:
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rsil a0, 1
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rsr.intenable a2
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rsr.interrupt a3
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movi a4, 0x3fff
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and a2, a2, a3
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and a2, a2, a4 /* a2 = 0x3FFF & INTENABLE & INTERRUPT */
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UserHandleTimer:
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movi a3, 0xffbf
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and a3, a2, a3 /* a3 = a2 & 0xFFBF, ie remove 0x40 from a2 if set */
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bnez a3, UserTimerDone /* bits other than 0x40 are set */
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movi a3, 0x40
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sub a12, a2, a3 /* a12 - a2 - 0x40 - I think a12 _must_ be zero here? */
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call0 sdk__xt_timer_int /* tick timer interrupt */
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mov a2, a12 /* restore a2 from a12, ie zero */
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beqz a2, UserIntDone
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UserTimerDone:
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call0 _xt_isr_handler
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bnez a2, UserHandleTimer
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UserIntDone:
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beqz a2, UserIntExit
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break 1, 1 /* non-zero remnant in a2 means fail */
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call0 sdk_user_fatal_exception_handler
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UserIntExit:
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call0 sdk__xt_int_exit /* calls rfi */
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/* _xt_user_exit is used to exit interrupt context.
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TODO: Find a better place for this to live.
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*/
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.text
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.section .text
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.global _xt_user_exit
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.type _xt_user_exit, @function
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_xt_user_exit:
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l32i a0, sp, 0x8
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wsr.ps a0
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l32i a0, sp, 0x4
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wsr.epc1 a0
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l32i a0, sp, 0xc
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l32i sp, sp, 0x10
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rsync
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rfe
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