c45e84d61d
Seems I got the functionality of this bit inverted when initially testing. In testing it also seems open drain mode is ignored on some pins, which still source current. Needs more investigation though (may be pullups internal to the ESP modules or set by default in software.) Relates to #45
128 lines
3.6 KiB
C
128 lines
3.6 KiB
C
/** esp_iomux.h
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*
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* GPIO functions.
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*
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* Part of esp-open-rtos
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* Copyright (C) 2015 Superhouse Automation Pty Ltd
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* BSD Licensed as described in the file LICENSE
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*/
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#ifndef _ESP_GPIO_H
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#define _ESP_GPIO_H
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#include <stdbool.h>
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#include "esp/gpio_regs.h"
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#include "esp/iomux.h"
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#include "esp/cpu.h"
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#include "xtensa_interrupts.h"
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typedef enum {
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GPIO_INPUT,
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GPIO_OUTPUT, /* "Standard" push-pull output */
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GPIO_OUT_OPEN_DRAIN, /* Open drain output */
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GPIO_INPUT_PULLUP,
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} gpio_direction_t;
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/* Enable GPIO on the specified pin, and set it to input/output/ with
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* pullup as needed
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*/
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INLINED void gpio_enable(const uint8_t gpio_num, const gpio_direction_t direction)
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{
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uint32_t iomux_flags;
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switch(direction) {
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case GPIO_INPUT:
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iomux_flags = 0;
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break;
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case GPIO_OUTPUT:
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iomux_flags = IOMUX_PIN_OUTPUT_ENABLE;
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break;
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case GPIO_OUT_OPEN_DRAIN:
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iomux_flags = IOMUX_PIN_OUTPUT_ENABLE;
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break;
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case GPIO_INPUT_PULLUP:
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iomux_flags = IOMUX_PIN_PULLUP;
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break;
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}
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iomux_set_gpio_function(gpio_num, iomux_flags);
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if(direction == GPIO_OUT_OPEN_DRAIN)
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GPIO.CONF[gpio_num] |= GPIO_CONF_OPEN_DRAIN;
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else
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GPIO.CONF[gpio_num] &= ~GPIO_CONF_OPEN_DRAIN;
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if (iomux_flags & IOMUX_PIN_OUTPUT_ENABLE)
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GPIO.ENABLE_OUT_SET = BIT(gpio_num);
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else
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GPIO.ENABLE_OUT_CLEAR = BIT(gpio_num);
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}
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/* Disable GPIO on the specified pin, and set it Hi-Z.
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*
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* If later muxing this pin to a different function, make sure to set
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* IOMUX_PIN_OUTPUT_ENABLE if necessary to enable the output buffer.
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*/
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INLINED void gpio_disable(const uint8_t gpio_num)
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{
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GPIO.ENABLE_OUT_CLEAR = BIT(gpio_num);
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*gpio_iomux_reg(gpio_num) &= ~IOMUX_PIN_OUTPUT_ENABLE;
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}
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/* Set output of a pin high or low.
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*
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* Only works if pin has been set to GPIO_OUTPUT via gpio_enable()
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*/
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INLINED void gpio_write(const uint8_t gpio_num, const bool set)
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{
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if(set)
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GPIO.OUT_SET = BIT(gpio_num);
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else
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GPIO.OUT_CLEAR = BIT(gpio_num);
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}
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/* Toggle output of a pin
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*
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* Only works if pin has been set to GPIO_OUTPUT via gpio_enable()
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*/
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INLINED void gpio_toggle(const uint8_t gpio_num)
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{
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/* Why implement like this instead of GPIO_OUT_REG ^= xxx?
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Concurrency. If an interrupt or higher priority task writes to
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GPIO_OUT between reading and writing, only the gpio_num pin can
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get an invalid value. Prevents one task from clobbering another
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task's pins, without needing to disable/enable interrupts.
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*/
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if(GPIO.OUT & BIT(gpio_num))
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GPIO.OUT_CLEAR = BIT(gpio_num);
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else
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GPIO.OUT_SET = BIT(gpio_num);
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}
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/* Read input value of a GPIO pin.
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*
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* If pin is set as an input, this reads the value on the pin.
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* If pin is set as an output, this reads the last value written to the pin.
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*/
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INLINED bool gpio_read(const uint8_t gpio_num)
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{
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return GPIO.IN & BIT(gpio_num);
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}
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extern void gpio_interrupt_handler(void);
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/* Set the interrupt type for a given pin
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*
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* If int_type is not GPIO_INTTYPE_NONE, the gpio_interrupt_handler will be attached and unmasked.
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*/
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INLINED void gpio_set_interrupt(const uint8_t gpio_num, const gpio_inttype_t int_type)
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{
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GPIO.CONF[gpio_num] = SET_FIELD(GPIO.CONF[gpio_num], GPIO_CONF_INTTYPE, int_type);
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if(int_type != GPIO_INTTYPE_NONE) {
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_xt_isr_attach(INUM_GPIO, gpio_interrupt_handler);
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_xt_isr_unmask(1<<INUM_GPIO);
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}
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}
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/* Return the interrupt type set for a pin */
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INLINED gpio_inttype_t gpio_get_interrupt(const uint8_t gpio_num)
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{
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return FIELD2VAL(GPIO_CONF_INTTYPE, GPIO.CONF[gpio_num]);
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}
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#endif
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