77813c8032
Seems I got the functionality of this bit inverted when initially testing. In testing it also seems open drain mode is ignored on some pins, which still source current. Needs more investigation though (may be pullups internal to the ESP modules or set by default in software.) Relates to #45
135 lines
4.3 KiB
C
135 lines
4.3 KiB
C
/* esp/gpio_regs.h
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*
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* ESP8266 GPIO register definitions
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*
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* Not compatible with ESP SDK register access code.
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*/
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#ifndef _ESP_GPIO_REGS_H
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#define _ESP_GPIO_REGS_H
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#include "esp/types.h"
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#include "common_macros.h"
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#define GPIO_BASE 0x60000300
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#define GPIO (*(struct GPIO_REGS *)(GPIO_BASE))
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/** GPIO output registers GPIO.OUT, GPIO.OUT_SET, GPIO.OUT_CLEAR:
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*
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* _SET and _CLEAR write-only registers set and clear bits in the main register,
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* respectively.
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*
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* i.e.
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* GPIO.OUT_SET = BIT(3);
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* and
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* GPIO.OUT |= BIT(3);
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*
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* ... are equivalent, but the former uses fewer CPU cycles.
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*
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* ENABLE_OUT / ENABLE_OUT_SET / ENABLE_OUT_CLEAR:
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*
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* Determine whether the corresponding GPIO has its output enabled or not.
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* When clear, GPIO can function as an input. When set, GPIO will drive its
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* output (and IN register will simply reflect the output state).
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*
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* (_SET/_CLEAR function similarly to OUT registers)
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*
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* STATUS / STATUS_SET / STATUS_CLEAR:
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*
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* Indicates which GPIOs have triggered an interrupt. Interrupt status should
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* be reset by writing to STATUS or STATUS_CLEAR.
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*
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* (_SET/_CLEAR function similarly to OUT registers)
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*/
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struct GPIO_REGS {
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uint32_t volatile OUT; // 0x00
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uint32_t volatile OUT_SET; // 0x04
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uint32_t volatile OUT_CLEAR; // 0x08
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uint32_t volatile ENABLE_OUT; // 0x0c
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uint32_t volatile ENABLE_OUT_SET; // 0x10
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uint32_t volatile ENABLE_OUT_CLEAR; // 0x14
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uint32_t volatile IN; // 0x18
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uint32_t volatile STATUS; // 0x1c
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uint32_t volatile STATUS_SET; // 0x20
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uint32_t volatile STATUS_CLEAR; // 0x24
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uint32_t volatile CONF[16]; // 0x28 - 0x64
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uint32_t volatile PWM; // 0x68
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uint32_t volatile RTC_CALIB; // 0x6c
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uint32_t volatile RTC_CALIB_RESULT; // 0x70
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};
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_Static_assert(sizeof(struct GPIO_REGS) == 0x74, "GPIO_REGS is the wrong size");
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/* Details for CONF[i] registers */
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/* GPIO.CONF[i] control the pin behavior for the corresponding GPIO in/output.
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*
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* GPIO_CONF_CONFIG (multi-value)
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* FIXME: Unclear what these do. Need to find a better name.
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*
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* GPIO_CONF_WAKEUP_ENABLE (boolean)
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* Can an interrupt contion on this pin wake the processor from a sleep
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* state?
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*
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* GPIO_CONF_INTTYPE (multi-value)
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* Under what conditions this GPIO input should generate an interrupt.
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* (see gpio_inttype_t enum below for values)
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*
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* GPIO_CONF_OPEN_DRAIN (boolean)
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* If this bit is set, the pin is in "open drain" mode - a high output state
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* will leave the pin floating but not source any current. If bit is cleared,
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* the pin is in push/pull mode so a high output state will drive the pin up
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* to +Vcc (3.3V). In either case, a low output state will pull the pin down
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* to ground.
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*
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* GPIO_CONF_OPEN_DRAIN does not appear to work on all pins.
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*
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*
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* GPIO_CONF_SOURCE_PWM (boolean)
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* When set, GPIO pin output will be connected to the sigma-delta PWM
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* generator (controlled by the GPIO.PWM register). When cleared, pin
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* output will function as a normal GPIO output (controlled by the
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* GPIO.OUT* registers).
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*/
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#define GPIO_CONF_CONFIG_M 0x00000003
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#define GPIO_CONF_CONFIG_S 11
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#define GPIO_CONF_WAKEUP_ENABLE BIT(10)
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#define GPIO_CONF_INTTYPE_M 0x00000007
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#define GPIO_CONF_INTTYPE_S 7
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#define GPIO_CONF_OPEN_DRAIN BIT(2)
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#define GPIO_CONF_SOURCE_PWM BIT(0)
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/* Valid values for the GPIO_CONF_INTTYPE field */
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typedef enum {
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GPIO_INTTYPE_NONE = 0,
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GPIO_INTTYPE_EDGE_POS = 1,
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GPIO_INTTYPE_EDGE_NEG = 2,
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GPIO_INTTYPE_EDGE_ANY = 3,
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GPIO_INTTYPE_LEVEL_LOW = 4,
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GPIO_INTTYPE_LEVEL_HIGH = 5,
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} gpio_inttype_t;
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/* Details for PWM register */
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#define GPIO_PWM_ENABLE BIT(16)
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#define GPIO_PWM_PRESCALER_M 0x000000ff
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#define GPIO_PWM_PRESCALER_S 8
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#define GPIO_PWM_TARGET_M 0x000000ff
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#define GPIO_PWM_TARGET_S 0
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/* Details for RTC_CALIB register */
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#define GPIO_RTC_CALIB_START BIT(31)
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#define GPIO_RTC_CALIB_PERIOD_M 0x000003ff
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#define GPIO_RTC_CALIB_PERIOD_S 0
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/* Details for RTC_CALIB_RESULT register */
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#define GPIO_RTC_CALIB_RESULT_READY BIT(31)
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#define GPIO_RTC_CALIB_RESULT_READY_REAL BIT(30)
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#define GPIO_RTC_CALIB_RESULT_VALUE_M 0x000fffff
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#define GPIO_RTC_CALIB_RESULT_VALUE_S 0
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#endif /* _ESP_GPIO_REGS_H */
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