100 lines
3.6 KiB
C
100 lines
3.6 KiB
C
/* esp/rtc_regs.h
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*
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* ESP8266 RTC register definitions
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*
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* Not compatible with ESP SDK register access code.
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*
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* RTC peripheral remains powered during deep sleep, and RTC clock
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* is used to wake from deep sleep when RTC.COUNTER == RTC.COUNTER_ALARM.
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*
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* "GPIO16" is a special GPIO pin connected to the RTC subsystem,
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* GPIO16 must be connected to reset to allow wake from deep sleep.
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*
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* The contents of scratch registers RTC.SCRATCH[] are preserved
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* across reset, including wake from sleep (unconfirmed). Contents of
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* RTCMEM are also preserved.
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*/
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#ifndef _ESP_RTC_REGS_H
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#define _ESP_RTC_REGS_H
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#include "esp/types.h"
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#include "common_macros.h"
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#define RTC_BASE 0x60000700
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#define RTC (*(struct RTC_REGS *)(RTC_BASE))
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//FIXME: need to understand/clarify distinction between GPIO_CONF and GPIO_CFG[]
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// Note: GPIO_CFG[3] is also known as PAD_XPD_DCDC_CONF in eagle_soc.h
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struct RTC_REGS {
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uint32_t volatile CTRL0; // 0x00
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uint32_t volatile COUNTER_ALARM; // 0x04
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uint32_t volatile RESET_REASON0; // 0x08 //FIXME: need better name
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uint32_t volatile _unknownc[2]; // 0x0c - 0x10
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uint32_t volatile RESET_REASON1; // 0x14 //FIXME: need better name
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uint32_t volatile RESET_REASON2; // 0x18 //FIXME: need better name
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uint32_t volatile COUNTER; // 0x1c
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uint32_t volatile INT_SET; // 0x20
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uint32_t volatile INT_CLEAR; // 0x24
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uint32_t volatile INT_ENABLE; // 0x28
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uint32_t volatile _unknown2c; // 0x2c
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uint32_t volatile SCRATCH[4]; // 0x30 - 3c
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uint32_t volatile _unknown40[10]; // 0x40 - 0x64
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uint32_t volatile GPIO_OUT; // 0x68
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uint32_t volatile _unknown6c[2]; // 0x6c - 0x70
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uint32_t volatile GPIO_ENABLE; // 0x74
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uint32_t volatile _unknown80[5]; // 0x78 - 0x88
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uint32_t volatile GPIO_IN; // 0x8c
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uint32_t volatile GPIO_CONF; // 0x90
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uint32_t volatile GPIO_CFG[6]; // 0x94 - 0xa8
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};
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_Static_assert(sizeof(struct RTC_REGS) == 0xac, "RTC_REGS is the wrong size");
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/* Details for CTRL0 register */
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/* Writing this bit causes a software reset but
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the device then fails in ets_main.c (needs other parameters set?) */
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#define RTC_CTRL0_BIT31 BIT(31)
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/* Details for RESET_REASONx registers */
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/* The following are used in sdk_rtc_get_reset_reason(). Details are still a
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* bit sketchy regarding exactly what they mean/do.. */
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#define RTC_RESET_REASON1_CODE_M 0x0000000f
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#define RTC_RESET_REASON1_CODE_S 0
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#define RTC_RESET_REASON2_CODE_M 0x0000003f
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#define RTC_RESET_REASON2_CODE_S 8
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/* Writing this bit causes the ESP to go into some kind of unrecoverable boot loop */
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#define RTC_RESET_REASON0_BIT20 BIT(20)
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/* Both bits 20 & 21 can be set & cleared from software,
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BIT21 appears to be checked inside sdk_rtc_get_reset_reason() */
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#define RTC_RESET_REASON0_BIT21 BIT(21)
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#define RTC_RESET_REASON0_BIT22 BIT(22)
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/* Details for GPIO_CONF register */
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#define RTC_GPIO_CONF_OUT_ENABLE BIT(0)
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/* Details for GPIO_CFG[3] register controlling GPIO16 (possibly others?) */
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#define RTC_GPIO_CFG3_PIN_PULLUP BIT(2)
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#define RTC_GPIO_CFG3_PIN_PULLDOWN BIT(3)
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#define RTC_GPIO_CFG3_PIN_PULLUP_SLEEP BIT(4)
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#define RTC_GPIO_CFG3_PIN_PULLDOWN_SLEEP BIT(5)
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/* The PIN_FUNC values here are probably similar to the
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values used to set the iomux registers...? */
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#define RTC_GPIO_CFG3_PIN_FUNC_M 0x00000043
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#define RTC_GPIO_CFG3_PIN_FUNC_S 0
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/* This should be the function value needed to have GPIO16 be the alarm
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output from the RTC. FIXME: Needs to be validated. */
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#define RTC_GPIO_CFG3_PIN_FUNC_RTC_GPIO0 BIT(0)
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#endif /* _ESP_RTC_REGS_H */
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