190 lines
5.2 KiB
PHP
190 lines
5.2 KiB
PHP
/* Xtensa Exception unaligned load handler
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Completes l8/l16 load instructions from Instruction address space,
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that the architecture require to be 4 byte aligned word reads.
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Called from either UserExceptionVector or DoubleExceptionVector
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depending on where the exception happened.
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Fast path (no branches) is for l8ui.
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Part of esp-open-rtos
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Copyright (C) Angus Gratton
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BSD Licensed as described in the file LICENSE
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*/
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.text
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.section .vecbase.text, "x"
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.literal_position
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/* "Fix" LoadStoreException exceptions that are l8/l16 from an Instruction region,
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normal exception variant. */
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UserExceptionLoadStoreHandler:
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addi sp, sp, -0x18
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s32i a2, sp, 0x08
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rsr.epc1 a2
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/* Inner UserLoadStoreExceptionHandler handlers. Works for both level1 & level 2 interrupt level.
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*
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* Called from level-specific handler above which sets up stack and loads epcX into a2.
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*/
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InnerLoadStoreExceptionHandler:
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s32i a3, sp, 0x0c
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s32i a4, sp, 0x10
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s32i a5, sp, 0x14
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rsr.sar a0 // save sar in a0
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/* Examine the instruction we failed to execute (in a2) */
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ssa8l a2 // sar is now correct shift for aligned read
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movi a3, ~3
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and a2, a2, a3 // a2 now 4-byte aligned address of instruction
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l32i a3, a2, 0
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l32i a4, a2, 4
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src a2, a4, a3 // a2 now instruction that failed
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/* check for l8ui opcode 0x000002, or branch to check l16 */
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movi a3, 0x00700F /* opcode mask for l8ui/l16si/l16ui */
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and a3, a2, a3
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bnei a3, 0x000002, .Lcheck_fix_16bit
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movi a5, 0xFF
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.Lcan_fix:
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/* verified an 8- or 16-bit read
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a2 holds instruction, a5 holds mask to apply to read value
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*/
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rsr.excvaddr a3 // read faulting address
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ssa8l a3 /* sar is now shift to extract a3's byte */
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movi a4, ~3
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and a3, a3, a4 /* a3 now word aligned read address */
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l32i a3, a3, 0 /* perform the actual read */
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srl a3, a3 /* shift right correct distance */
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and a4, a3, a5 /* mask off bits we need for an l8/l16 */
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bbsi a5, 14, .Lmaybe_extend_sign
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.Lafter_extend_sign:
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/* a2 holds instruction, a4 holds the correctly read value */
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extui a2, a2, 4, 4 /* a2 now destination register 0-15 */
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/* test if a4 needs to be written directly to a register (ie not a working register) */
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bgei a2, 6, .Lwrite_value_direct_reg
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/* test if a4 needs to be written to a0 */
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beqz a2, .Lwrite_value_a0_reg
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/* otherwise, a4 can be written to a saved working register 'slot' on the stack */
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addx4 a5, a2, sp
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s32i a4, a5, 0
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.Lafter_write_value:
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/* test PS.INTLEVEL (1=User, 2=Double) to see which interrupt level we restore from
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*/
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rsr.ps a2
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bbsi a2, 1, .Lincrement_PC_intlevel2
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.Lincrement_PC_intlevel1:
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rsr.epc1 a2
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addi a3, a2, 0x3
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wsr.epc1 a3
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wsr.sar a0 // restore saved sar
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rsr.excsave1 a0 // restore a0 saved in exception vector
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.Lafter_increment_PC:
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// Restore registers
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l32i a2, sp, 0x08
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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l32i a5, sp, 0x14
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addi sp, sp, 0x18
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rfe
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.literal_position
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/* "Fix" LoadStoreException exceptions that are l8/l16 from an Instruction region,
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DoubleException exception variant (ie load happened in a level1 exception handler). */
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DoubleExceptionLoadStoreHandler:
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addi sp, sp, -0x18
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s32i a2, sp, 0x08
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rsr.epc2 a2
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j InnerLoadStoreExceptionHandler
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/* Check the load instruction a2 for an l16si/16ui instruction
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First test for a signed vs unsigned load.
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a2 is the instruction, need to load a5 with the mask to use */
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.Lcheck_fix_16bit:
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movi a4, 0x001002 /* l16si or l16ui opcode after masking */
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bne a3, a4, .Lcant_fix
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bbsi a2, 15, .Lcan_fix_16bit_signed
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movi a5, 0xFFFF
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j .Lcan_fix
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.Lcan_fix_16bit_signed:
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movi a5, 0x7FFF
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j .Lcan_fix
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/* not an opcode we can try to fix, so bomb out
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TODO: the exception dump will have some wrong values in it */
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.Lcant_fix:
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call0 sdk_user_fatal_exception_handler
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/* increment PC for a DoubleException */
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.Lincrement_PC_intlevel2:
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rsr.epc2 a2
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addi a3, a2, 0x3
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wsr.epc2 a3
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wsr.sar a0 // restore saved sar
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rsr.excsave2 a0 // restore a0 saved in exception vector
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j .Lafter_increment_PC
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.Lmaybe_extend_sign: /* apply 16-bit sign extension if necessary
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a3 holds raw value, a4 holds masked */
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bbsi a5, 15, .Lafter_extend_sign /* 16-bit unsigned, no sign extension */
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bbci a3, 15, .Lafter_extend_sign /* sign bit not set, no sign extension */
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movi a3, 0xFFFF8000
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or a4, a3, a4 /* set 32-bit sign bits */
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j .Lafter_extend_sign
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.Lwrite_value_direct_reg:
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/* Directly update register index a2, in range 6-15, using value in a4 */
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addi a2, a2, -6
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slli a2, a2, 3 /* offset from a6, x8 */
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movi a3, .Ldirect_reg_jumptable
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add a2, a2, a3
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jx a2
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.align 8
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.Ldirect_reg_jumptable:
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mov a6, a4
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j .Lafter_write_value
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.align 8
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mov a7, a4
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j .Lafter_write_value
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.align 8
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mov a8, a4
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j .Lafter_write_value
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.align 8
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mov a9, a4
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j .Lafter_write_value
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.align 8
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mov a10, a4
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j .Lafter_write_value
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.align 8
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mov a11, a4
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j .Lafter_write_value
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.align 8
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mov a12, a4
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j .Lafter_write_value
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.align 8
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mov a13, a4
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j .Lafter_write_value
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.align 8
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mov a14, a4
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j .Lafter_write_value
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.align 8
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mov a15, a4
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j .Lafter_write_value
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.Lwrite_value_a0_reg:
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/* a0 is saved in excsave1,so just update this with value
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TODO: This won't work with interrupt level 2
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*/
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wsr.excsave1 a4
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j .Lafter_write_value
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/* End of InnerUserLoadStoreExceptionHandler */
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