124 lines
3.5 KiB
C
124 lines
3.5 KiB
C
/* ESP8266 Xtensa interrupt management functions
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*
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* Some (w/ sdk_ prefix) are implemented in binary libs, rest are
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* inlines replacing functions in the binary libraries.
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*
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* Part of esp-open-rtos
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* Copyright (C) 2015 Superhouse Automation Pty Ltd
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* BSD Licensed as described in the file LICENSE
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*/
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#ifndef _XTENSA_INTERRUPTS_H
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#define _XTENSA_INTERRUPTS_H
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#include <stdint.h>
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#include <stdbool.h>
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#include <xtruntime.h>
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#include <xtensa/hal.h>
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#include <common_macros.h>
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/* Interrupt numbers for level 1 exception handler. */
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typedef enum {
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INUM_WDEV_FIQ = 0,
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INUM_SLC = 1,
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INUM_SPI = 2,
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INUM_RTC = 3,
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INUM_GPIO = 4,
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INUM_UART = 5,
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INUM_TICK = 6, /* RTOS timer tick, possibly xtensa CPU CCOMPARE0(?) */
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INUM_SOFT = 7,
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INUM_WDT = 8,
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INUM_TIMER_FRC1 = 9,
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/* FRC2 default handler. Configured by sdk_ets_timer_init, which
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runs as part of default libmain.a startup code, assigns
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interrupt handler to sdk_vApplicationTickHook+0x68
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*/
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INUM_TIMER_FRC2 = 10,
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} xt_isr_num_t;
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void sdk__xt_int_exit(void);
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void _xt_user_exit(void);
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void sdk__xt_tick_timer_init(void);
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void sdk__xt_timer_int(void *);
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void sdk__xt_timer_int1(void);
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/* The normal running level is 0.
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* The system tick isr, timer frc2_isr, sv_isr etc run at level 1.
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* Debug exceptions run at level 2?
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* The wdev nmi runs at level 3.
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*/
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static inline uint32_t _xt_get_intlevel(void)
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{
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uint32_t level;
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__asm__ volatile("rsr %0, ps" : "=a"(level));
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return level & 0xf;
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}
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/*
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* There are conflicting definitions for XCHAL_EXCM_LEVEL. Newlib
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* defines it to be 1 and xtensa_rtos.h defines it to be 3. Don't want
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* 3 as that is for the NMI and might want to check that the OS apis
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* are not entered in level 3. Setting the interrupt level to 3 does
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* not disable the NMI anyway. So set the level to 2.
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*/
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#ifdef XCHAL_EXCM_LEVEL
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#undef XCHAL_EXCM_LEVEL
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#define XCHAL_EXCM_LEVEL 2
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#endif
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/* Disable interrupts and return the old ps value, to pass into
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_xt_restore_interrupts later.
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This is desirable to use in place of
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portDISABLE_INTERRUPTS/portENABLE_INTERRUPTS for
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non-FreeRTOS & non-portable code.
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*/
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static inline uint32_t _xt_disable_interrupts(void)
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{
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uint32_t old_level;
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__asm__ volatile ("rsil %0, " XTSTR(XCHAL_EXCM_LEVEL) : "=a" (old_level));
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return old_level;
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}
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/* Restore PS level. Intended to be used with _xt_disable_interrupts */
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static inline void _xt_restore_interrupts(uint32_t new_ps)
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{
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__asm__ volatile ("wsr %0, ps; rsync" :: "a" (new_ps));
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}
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static inline uint32_t _xt_isr_unmask(uint32_t unmask)
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{
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uint32_t old_level = _xt_disable_interrupts();
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uint32_t intenable;
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asm volatile ("rsr %0, intenable" : "=a" (intenable));
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asm volatile ("wsr %0, intenable;" :: "a" (intenable | unmask));
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_xt_restore_interrupts(old_level);
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return intenable;
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}
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static inline uint32_t _xt_isr_mask(uint32_t mask)
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{
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uint32_t old_level = _xt_disable_interrupts();
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uint32_t intenable;
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asm volatile ("rsr %0, intenable" : "=a" (intenable));
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asm volatile ("wsr %0, intenable;" :: "a" (intenable & ~mask));
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_xt_restore_interrupts(old_level);
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return intenable;
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}
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static inline uint32_t _xt_read_ints(void)
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{
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uint32_t interrupt;
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asm volatile ("rsr %0, interrupt" : "=a" (interrupt));
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return interrupt;
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}
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static inline void _xt_clear_ints(uint32_t mask)
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{
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asm volatile ("wsr %0, intclear; esync" :: "a" (mask));
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}
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typedef void (* _xt_isr)(void *arg);
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void _xt_isr_attach (uint8_t i, _xt_isr func, void *arg);
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#endif
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