23ea182e83
RTOS Timer tick handler is now the same as any other ISR. This causes a few subtle behaviour changes that seem OK but are worth noting: * RTOS tick handler sdk__xt_timer_int() is now called from one stack frame deeper (inside _xt_isr_handler()), whereas before it was called from the level above in UserHandleInterrupt. I can't see any way that the extra ~40 bytes of stack use here hurt, though. * sdk__xt_timer_int() was previous called after all other interrupts flagged in the handler, now it's called before the TIMER FRC1 & FRC2 handlers. The tick handler doesn't appear to do anything particularly timing intensive, though. * GPIO interrupt (value 3) is now lower priority than the SPI interrupt (value 2), whereas before it would have been called before SPI if both interrupts triggered at once.
103 lines
2.8 KiB
C
103 lines
2.8 KiB
C
/* ESP8266 Xtensa interrupt management functions
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*
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* Some (w/ sdk_ prefix) are implemented in binary libs, rest are
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* inlines replacing functions in the binary libraries.
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*
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* Part of esp-open-rtos
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* Copyright (C) 2015 Superhouse Automation Pty Ltd
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* BSD Licensed as described in the file LICENSE
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*/
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#ifndef _XTENSA_INTERRUPTS_H
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#define _XTENSA_INTERRUPTS_H
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#include <stdint.h>
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#include <stdbool.h>
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#include <xtruntime.h>
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#include <xtensa/hal.h>
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#include <common_macros.h>
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/* Interrupt numbers for level 1 exception handler. */
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typedef enum {
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INUM_SPI = 2,
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INUM_GPIO = 4,
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INUM_UART = 5,
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INUM_TICK = 6, /* RTOS timer tick, possibly xtensa CPU CCOMPARE0(?) */
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INUM_SOFT = 7,
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INUM_WDT = 8,
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INUM_TIMER_FRC1 = 9,
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/* FRC2 default handler. Configured by sdk_ets_timer_init, which
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runs as part of default libmain.a startup code, assigns
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interrupt handler to sdk_vApplicationTickHook+0x68
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*/
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INUM_TIMER_FRC2 = 10,
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} xt_isr_num_t;
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void sdk__xt_int_exit (void);
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void _xt_user_exit (void);
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void sdk__xt_tick_timer_init (void);
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void sdk__xt_timer_int(void);
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void sdk__xt_timer_int1(void);
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INLINED uint32_t _xt_get_intlevel(void)
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{
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uint32_t level;
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__asm__ volatile("rsr %0, intlevel" : "=a"(level));
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return level;
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}
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/* Disable interrupts and return the old ps value, to pass into
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_xt_restore_interrupts later.
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This is desirable to use in place of
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portDISABLE_INTERRUPTS/portENABLE_INTERRUPTS for
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non-FreeRTOS & non-portable code.
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*/
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INLINED uint32_t _xt_disable_interrupts(void)
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{
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uint32_t old_level;
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__asm__ volatile ("rsil %0, " XTSTR(XCHAL_EXCM_LEVEL) : "=a" (old_level));
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return old_level;
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}
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/* Restore PS level. Intended to be used with _xt_disable_interrupts */
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INLINED void _xt_restore_interrupts(uint32_t new_ps)
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{
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__asm__ volatile ("wsr %0, ps; rsync" :: "a" (new_ps));
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}
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/* ESPTODO: the mask/unmask functions aren't thread safe */
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INLINED void _xt_isr_unmask(uint32_t unmask)
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{
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uint32_t intenable;
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asm volatile ("rsr %0, intenable" : "=a" (intenable));
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intenable |= unmask;
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asm volatile ("wsr %0, intenable; esync" :: "a" (intenable));
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}
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INLINED void _xt_isr_mask (uint32_t mask)
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{
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uint32_t intenable;
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asm volatile ("rsr %0, intenable" : "=a" (intenable));
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intenable &= ~mask;
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asm volatile ("wsr %0, intenable; esync" :: "a" (intenable));
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}
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INLINED uint32_t _xt_read_ints (void)
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{
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uint32_t interrupt;
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asm volatile ("rsr %0, interrupt" : "=a" (interrupt));
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return interrupt;
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}
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INLINED void _xt_clear_ints(uint32_t mask)
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{
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asm volatile ("wsr %0, intclear; esync" :: "a" (mask));
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}
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typedef void (* _xt_isr)(void);
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/* This function is implemeneted in FreeRTOS port.c at the moment,
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should be moved or converted to an inline */
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void _xt_isr_attach (uint8_t i, _xt_isr func);
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#endif
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