1b0124cf05
Mostly determined from reverse engineering and poking around. Includes first "experiments" program with random bits and pieces for poking at registers, may be useful to keep in source control but not useful for writing actual programs.
306 lines
9.4 KiB
C
306 lines
9.4 KiB
C
/* esp/registers.h
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*
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* ESP8266 register addresses and bitmasks.
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*
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* Not compatible with ESP SDK register access code.
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*
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* Based on register map documentation:
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* https://github.com/esp8266/esp8266-wiki/wiki/Memory-Map
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*
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* Part of esp-open-rtos
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* Copyright (C) 2015 Superhouse Automation Pty Ltd
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* BSD Licensed as described in the file LICENSE
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*/
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#ifndef _ESP_REGISTERS
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#define _ESP_REGISTERS
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#include "common_macros.h"
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typedef volatile uint32_t *esp_reg_t;
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/* Internal macro, only defined in header body */
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#define _REG(BASE, OFFSET) (*(esp_reg_t)((BASE)+(OFFSET)))
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/* Register base addresses
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You shouldn't need to use these directly.
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*/
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#define MMIO_BASE 0x60000000
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#define DPORT_BASE 0x3ff00000
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#define UART0_BASE (MMIO_BASE + 0)
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#define SPI1_BASE (MMIO_BASE + 0x0100)
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#define SPI_BASE (MMIO_BASE + 0x0200)
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#define GPIO0_BASE (MMIO_BASE + 0x0300)
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#define TIMER_BASE (MMIO_BASE + 0x0600)
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#define RTC_BASE (MMIO_BASE + 0x0700)
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#define IOMUX_BASE (MMIO_BASE + 0x0800)
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#define WDT_BASE (MMIO_BASE + 0x0900)
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#define I2C_BASE (MMIO_BASE + 0x0d00)
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#define UART1_BASE (MMIO_BASE + 0x0F00)
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#define RTCB_BASE (MMIO_BASE + 0x1000)
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#define RTCS_BASE (MMIO_BASE + 0x1100)
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#define RTCU_BASE (MMIO_BASE + 0x1200)
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/*
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* iomux registers, apply to pin functions.
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*
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* Note that IOMUX register order is _not_ the same as GPIO order. See
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* esp_iomux.h for programmer-friendly IOMUX configuration options
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*/
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#define IOMUX_REG(X) _REG(IOMUX_BASE,0x04+4*X)
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#define IOMUX_OE BIT(0) /* iomux Output enable bit */
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#define IOMUX_OE_SLEEP BIT(1) /* iomux Output during sleep bit */
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#define IOMUX_PD BIT(6) /* iomux soft pulldown bit */
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#define IOMUX_PD_SLEEP BIT(2) /* iomux soft pulldown during sleep bit */
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#define IOMUX_PU BIT(7) /* iomux soft pullup bit */
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#define IOMUX_PU_SLEEP BIT(3) /* iomux soft pullup during sleep bit */
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#define IOMUX_FLAG_WAKE_MASK (IOMUX_OE|IOMUX_PD|IOMUX_PU)
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#define IOMUX_FLAG_SLEEP_MASK (IOMUX_OE_SLEEP|IOMUX_PD_SLEEP|IOMUX_PU_SLEEP)
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#define IOMUX_FLAG_MASK (IOMUX_FLAG_WAKE_MASK|IOMUX_FLAG_SLEEP_MASK)
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#define IOMUX_FUNC_MASK (BIT(4)|BIT(5)|BIT(12))
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/* All pins have FUNC_A on reset (unconfirmed) */
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#define IOMUX_FUNC_A (0)
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#define IOMUX_FUNC_B BIT(4)
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#define IOMUX_FUNC_C BIT(5)
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#define IOMUX_FUNC_D BIT(4)|BIT(5)
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#define IOMUX_FUNC_E BIT(12)
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/*
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* Based on descriptions by mamalala at https://github.com/esp8266/esp8266-wiki/wiki/gpio-registers
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*/
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/** GPIO OUTPUT registers GPIO_OUT_REG, GPIO_OUT_SET, GPIO_OUT_CLEAR
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*
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* Registers for pin outputs.
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*
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* _SET and _CLEAR write-only registers set and clear bits in _REG,
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* respectively.
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*
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* ie
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* GPIO_OUT_REG |= BIT(3);
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* and
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* GPIO_OUT_SET = BIT(3);
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*
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* ... are equivalent, but latter uses less CPU cycles.
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*/
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#define GPIO_OUT_REG _REG(GPIO0_BASE, 0x00)
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#define GPIO_OUT_SET _REG(GPIO0_BASE, 0x04)
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#define GPIO_OUT_CLEAR _REG(GPIO0_BASE, 0x08)
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/* GPIO DIR registers GPIO_DIR_REG, GPIO_DIR_SET, GPIO_DIR_CLEAR
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*
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* Set bit in DIR register for output pins. Writing to _SET and _CLEAR
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* registers set and clear bits in _REG, respectively.
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*/
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#define GPIO_DIR_REG _REG(GPIO0_BASE, 0x0C)
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#define GPIO_DIR_SET _REG(GPIO0_BASE, 0x10)
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#define GPIO_DIR_CLEAR _REG(GPIO0_BASE, 0x14)
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/* GPIO IN register GPIO_IN_REG
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*
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* Reads current input values.
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*/
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#define GPIO_IN_REG _REG(GPIO0_BASE, 0x18)
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/* GPIO interrupt 'status' flag
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Bit set if interrupt has fired (see below for interrupt config
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registers.
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Lower 16 bits only are used.
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*/
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#define GPIO_STATUS_REG _REG(GPIO0_BASE,0x1c)
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#define GPIO_STATUS_SET _REG(GPIO0_BASE,0x20)
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#define GPIO_STATUS_CLEAR _REG(GPIO0_BASE,0x24)
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#define GPIO_STATUS_MASK 0x0000FFFFL
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/* GPIO pin control registers for GPIOs 0-15
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*
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*/
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#define GPIO_CTRL_REG(GPNUM) _REG(GPIO0_BASE, 0x28+(GPNUM*4))
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#define GPIO_SOURCE_GPIO 0
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#define GPIO_SOURCE_DAC BIT(0) /* "Sigma-Delta" */
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#define GPIO_SOURCE_MASK BIT(0
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#define GPIO_DRIVE_PUSH_PULL 0
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#define GPIO_DRIVE_OPEN_DRAIN BIT(2)
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#define GPIO_DRIVE_MASK BIT(2)
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#define GPIO_INT_NONE 0
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#define GPIO_INT_RISING BIT(7)
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#define GPIO_INT_FALLING BIT(8)
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#define GPIO_INT_CHANGE (BIT(7)|BIT(8))
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#define GPIO_INT_LOW BIT(9)
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#define GPIO_INT_HIGH (BIT(7)|BIT(9))
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#define GPIO_INT_MASK (BIT(7)|BIT(8)|BIT(9))
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/* TIMER registers
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*
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* ESP8266 has two hardware(?) timer counters, FRC1 and FRC2.
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*
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* FRC1 is a 24-bit countdown timer, triggers interrupt when reaches zero.
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* FRC2 is a 32-bit countup timer, can set a variable match value to trigger an interrupt.
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*
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* FreeRTOS tick timer appears to come from XTensa core tick timer0,
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* not either of these. FRC2 is used in the FreeRTOS SDK however. It
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* is set to free-run, interrupting periodically via updates to the
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* MATCH register. sdk_ets_timer_init configures FRC2 and assigns FRC2
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* interrupt handler at sdk_vApplicationTickHook+0x68
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*/
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/* Load value for FRC1, read/write.
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When TIMER_CTRL_RELOAD is cleared in TIMER_FRC1_CTRL_REG, FRC1
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will reload to 0x7fffff once overflowed (unless the load value is
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rewritten in the interrupt handler.)
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When TIMER_CTRL_RELOAD is set in TIMER_FRC1_CTRL_REG, FRC1 will reload
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from the load register value once overflowed.
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*/
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#define TIMER_FRC1_LOAD_REG _REG(TIMER_BASE, 0x00)
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/* Current count value for FRC1, read only? */
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#define TIMER_FRC1_COUNT_REG _REG(TIMER_BASE, 0x04)
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/* Control register for FRC1, read/write.
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See the bit definitions TIMER_CTRL_xxx lower down.
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*/
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#define TIMER_FRC1_CTRL_REG _REG(TIMER_BASE, 0x08)
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/* Reading this register always returns the value in
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* TIMER_FRC1_LOAD_REG.
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*
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* Writing zero to this register clears the FRC1
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* interrupt status.
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*/
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#define TIMER_FRC1_CLEAR_INT_REG _REG(TIMER_BASE, 0x0c)
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/* FRC2 load register.
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*
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* If TIMER_CTRL_RELOAD is cleared in TIMER_FRC2_CTRL_REG, writing to
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* this register will update the FRC2 COUNT value.
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*
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* If TIMER_CTRL_RELOAD is set in TIMER_FRC2_CTRL_REG, the behaviour
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* appears to be the same except that writing 0 to the load register
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* both sets the COUNT register to 0 and disables the timer, even if
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* the TIMER_CTRL_RUN bit is set.
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*
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* Offsets 0x34, 0x38, 0x3c all seem to read back the LOAD_REG value
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* also (but have no known function.)
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*/
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#define TIMER_FRC2_LOAD_REG _REG(TIMER_BASE, 0x20)
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/* FRC2 current count value. Read only? */
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#define TIMER_FRC2_COUNT_REG _REG(TIMER_BASE, 0x24)
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/* Control register for FRC2. Read/write.
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See the bit definitions TIMER_CTRL_xxx lower down.
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*/
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#define TIMER_FRC2_CTRL_REG _REG(TIMER_BASE, 0x28)
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/* Reading this value returns the current value of
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* TIMER_FRC2_LOAD_REG.
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*
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* Writing zero to this value clears the FRC2 interrupt status.
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*/
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#define TIMER_FRC2_CLEAR_INT_REG _REG(TIMER_BASE, 0x2c)
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/* Interrupt match value for FRC2. When COUNT == MATCH,
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the interrupt fires.
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*/
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#define TIMER_FRC2_MATCH_REG _REG(TIMER_BASE, 0x30)
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/* Timer control bits to set clock divisor values.
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Divider from master 80MHz APB_CLK (unconfirmed, see esp/clocks.h).
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*/
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#define TIMER_CTRL_DIV_1 0
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#define TIMER_CTRL_DIV_16 BIT(2)
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#define TIMER_CTRL_DIV_256 BIT(3)
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#define TIMER_CTRL_DIV_MASK (BIT(2)|BIT(3))
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/* Set timer control bits to trigger interrupt on "edge" or "level"
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*
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* Observed behaviour is like this:
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*
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* * When TIMER_CTRL_INT_LEVEL is set, the interrupt status bit
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* TIMER_CTRL_INT_STATUS remains set when the timer interrupt
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* triggers, unless manually cleared by writing 0 to
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* TIMER_FRCx_CLEAR_INT. While the interrupt status bit stays set
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* the timer will continue to run normally, but the interrupt
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* (INUM_TIMER_FRC1 or INUM_TIMER_FRC2) won't trigger again.
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*
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* * When TIMER_CTRL_INT_EDGE (default) is set, there's no need to
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* manually write to TIMER_FRCx_CLEAR_INT. The interrupt status bit
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* TIMER_CTRL_INT_STATUS automatically clears after the interrupt
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* triggers, and the interrupt handler will run again
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* automatically.
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*
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*/
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#define TIMER_CTRL_INT_EDGE 0
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#define TIMER_CTRL_INT_LEVEL BIT(0)
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#define TIMER_CTRL_INT_MASK BIT(0)
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/* Timer auto-reload bit
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This bit interacts with TIMER_FCR1_LOAD_REG & TIMER_FCR2_LOAD_REG
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differently, see those registers for details.
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*/
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#define TIMER_CTRL_RELOAD BIT(6)
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/* Timer run bit */
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#define TIMER_CTRL_RUN BIT(7)
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/* Read-only timer interrupt status.
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This bit gets set on FRC1 when interrupt fires, and cleared on a
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write to TIMER_FRC1_CLEAR_INT (cleared automatically if
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TIMER_CTRL_INT_LEVEL is not set).
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*/
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#define TIMER_CTRL_INT_STATUS BIT(8)
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/* WDT register(s)
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Not fully understood yet. Writing 0 here disables wdt.
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See ROM functions esp_wdt_xxx
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*/
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#define WDT_CTRL _REG(WDT_BASE, 0x00)
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/* DPORT registers
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Control various aspects of core/peripheral interaction... Not well
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documented or understood.
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*/
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/* Set flags to enable CPU interrupts from some peripherals. Read/write.
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bit 0 - Is set by RTOS SDK startup code but function is unknown.
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bit 1 - INT_ENABLE_FRC1 allows TIMER FRC1 to trigger interrupt INUM_TIMER_FRC1.
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bit 2 - INT_ENABLE_FRC2 allows TIMER FRC2 to trigger interrupt INUM_TIMER_FRC2.
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Espressif calls this register "EDGE_INT_ENABLE_REG". The "edge" in
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question is (I think) the interrupt line from the peripheral, as
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the interrupt status bit is set. There may be a similar register
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for enabling "level" interrupts instead of edge triggering
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- this is unknown.
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*/
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#define DP_INT_ENABLE_REG _REG(DPORT_BASE, 0x04)
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/* Set to enable interrupts from TIMER FRC1 */
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#define INT_ENABLE_FRC1 BIT(1)
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/* Set to enable interrupts interrupts from TIMER FRC2 */
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#define INT_ENABLE_FRC2 BIT(2)
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#endif
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