1b0124cf05
Mostly determined from reverse engineering and poking around. Includes first "experiments" program with random bits and pieces for poking at registers, may be useful to keep in source control but not useful for writing actual programs.
32 lines
814 B
C
32 lines
814 B
C
/* esp/cpu.h
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*
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* Details relating to the ESP8266 Xtensa core.
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*
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*/
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#ifndef _ESP_CPU_H
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#define _ESP_CPU_H
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/* Interrupt numbers for level 1 exception handler.
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*
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* Currently the UserExceptionVector calls down to _xt_isr_handler,
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* defined in port.c, for at least some of these interrupts. Some are handled
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* on the SDK side, though.
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*/
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typedef enum {
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INUM_SPI = 2,
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INUM_GPIO = 4,
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INUM_UART = 5,
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INUM_MAX = 6, /* in some places this is documented as timer0 CCOMPARE0 interrupt */
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INUM_SOFT = 7,
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INUM_WDT = 8,
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INUM_TIMER_FRC1 = 9,
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/* FRC2 default handler. Configured by sdk_ets_timer_init, which
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runs as part of default libmain.a startup code, assigns
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interrupt handler to sdk_vApplicationTickHook+0x68
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*/
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INUM_TIMER_FRC2 = 10,
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} xt_isr_num_t;
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#endif
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